15th week of 2021 patent applcation highlights part 54 |
Patent application number | Title | Published |
20210111242 | LIQUID CRYSTAL DISPLAY DEVICE - A display device having a display region and a peripheral region in contact with the display region above a substrate is provided. The display region has a plurality of pixels each including a transistor, an insulating film above the transistor, a pixel electrode arranged above the insulating film and electrically connected to the transistor, and a common electrode above the insulating film, a video signal line and a gate signal line electrically connected to the transistor, and liquid crystal layer above the plurality of pixels. The peripheral region has a terminal electrically connected to the video signal line, a wiring arranged parallel to the gate wiring between the display region and the terminal, and a plurality of first electrodes above the wiring. The insulating film covers the wiring, and the wiring is electrically connected to the plurality of first electrodes via an opening in the insulating film. | 2021-04-15 |
20210111243 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device may include: a substrate; a protective region provided over the substrate; and a core structure enclosed by the protective region. The core structure may include a core material etchable by a chemical solution. The protective region may include a protective material resistant to etching by the chemical solution. The core structure may have a first side and a second side opposite to the first side, the first side being closer to the substrate than the second side. The core structure may be narrowest at the first side of the core structure. | 2021-04-15 |
20210111244 | COMPOSITION FOR DEPOSITING THIN FILM, MANUFACTURING METHOD FOR THIN FILM USING THE COMPOSITION, THIN FILM MANUFACTURED FROM THE COMPOSITION, AND SEMICONDUCTOR DEVICE INCLUDING THE THIN FILM - Disclosed are a composition for depositing a thin film including an organometallic compound including strontium, barium, or a combination thereof; and at least one unshared electron pair-containing compound represented by Chemical Formula 1, a method of manufacturing a thin film using the composition for depositing the thin film, and the thin film manufactured from the composition for depositing the thin film, and a semiconductor device including the thin film. | 2021-04-15 |
20210111245 | SEMICONDUCTOR DEVICE - A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region. | 2021-04-15 |
20210111246 | CONTACT SOURCE/DRAIN RESISTANCE - A nonplanar MOSFET device such as a FinFET or a sacked nanosheets/nanowires FET has a substrate, one or more nonplanar channels disposed on the substrate, and a gate stack enclosing the nonplanar channels. A first source/drain (S/D) region is disposed on the substrate on a source side of the nonplanar channel and second S/D region is disposed on the substrate on a drain side of the nonplanar channel. The first and second S/D regions made of silicon-germanium (SiGe). In some embodiments, both S/D regions are p-type doped. Contact trenches provide a metallic electrical connection to the first and the second source/drain (S/D) regions. The S/D regions have two parts, a first part with a first concentration of germanium (Ge) and a second part with a second, higher Ge concentration that is a surface layer having convex shape and aligned with one of the contact trenches. | 2021-04-15 |
20210111247 | DOUBLE MESA HETEROJUNCTION BIPOLAR TRANSISTOR - The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter. | 2021-04-15 |
20210111248 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device having a semiconductor substrate that includes a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and a plurality of trenches reaching a predetermined depth from a main surface of the semiconductor substrate to terminate in the first-conductivity-type epitaxial layer. The semiconductor substrate includes a hydrogen-donor introduced part, of which a concentration of a hydrogen donor is greatest at a depth position that is separate from bottoms of the trenches by a distance at least two times of the depth of the trenches. The impurity concentration of an impurity dopant of the first-conductivity-type substrate being lower than that of the first-conductivity-type epitaxial layer. A difference between a first resistivity, corresponding to a total impurity concentration of the impurity dopant and the hydrogen donor of the first-conductivity-type substrate, and a second resistivity, corresponding to the impurity concentration of the impurity dopant of the first-conductivity-type epitaxial layer, is at most 20%. | 2021-04-15 |
20210111249 | Semiconductor Structure Having Porous Semiconductor Segment for RF Devices and Bulk Semiconductor Region for Non-RF Devices - A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices. | 2021-04-15 |
20210111250 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device, including a semiconductor substrate having first and second semiconductor regions and a plurality of third semiconductor regions sequentially formed therein, a plurality of trenches penetrating the second and third semiconductor regions, a plurality of gate electrodes provided in the trenches via a gate insulating film, an interlayer insulating film covering the gate electrodes, a plurality of contact holes penetrating the interlayer insulating film, a first electrode provided in the contact holes and at the surface of the interlayer insulating film, and a second electrode electrically connected to the first semiconductor region. The interlayer insulating film has a plurality of recessed parts and protruding parts, to thereby form at least three recesses and protrusions repeatedly at a surface of the interlayer insulating film. The first electrode includes first to third electrode films, the second electrode film having a shape reflecting the surface of the interlayer insulating film. | 2021-04-15 |
20210111251 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide semiconductor device includes: a silicon carbide semiconductor substrate that has a front surface and a rear surface; and a plurality of ohmic electrodes that are in ohmic contact with a surface of silicon carbide on at least one of the front surface and the rear surface of the silicon carbide semiconductor substrate. The plurality of ohmic electrodes are scattered on the surface of the silicon carbide to provide a concavity and convexity. The concavity and convexity has a height due to the ohmic electrodes less than 1.0 μm. | 2021-04-15 |
20210111252 | COMPOUND SEMICONDUCTOR AND METHOD FOR PRODUCING THE SAME - Provided is a cadmium zinc telluride (CdZnTe) single crystal including a main surface that has a high mobility lifetime product (μτ product) in a wide range, wherein the main surface has an area of 100 mm | 2021-04-15 |
20210111253 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device, wherein: in a semiconductor substrate, a lifetime control region is provided from at least a part of a transistor portion to a diode portion; the transistor portion includes a main region, a boundary region located between the main region and the diode portion and overlapped with the lifetime control region, and a plurality of gate trench portions; the plurality of gate trench portions include a first gate trench portion provided in the main region and a second gate trench portion provided in the boundary region; and a gate resistance component of the first gate trench portion is different from a gate resistance component of the second gate trench portion. | 2021-04-15 |
20210111254 | STEPPED FIELD PLATES WITH PROXIMITY TO CONDUCTION CHANNEL AND RELATED FABRICATION METHODS - A transistor includes a semiconductor layer structure, a source electrode and a drain electrode on the semiconductor layer structure, a gate on a surface of the semiconductor layer structure between the source electrode and the drain electrode, and a field plate. The field plate includes a first portion adjacent the gate and a second portion adjacent the source or drain electrode. The second portion of the field plate is farther from the surface of the semiconductor layer structure than the first portion of the field plate, and is closer to the surface of the semiconductor layer structure than an extended portion of the gate. Related devices and fabrication methods are also discussed. | 2021-04-15 |
20210111255 | ASYMMETRIC THRESHOLD VOLTAGES IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. A gate stack is formed on the semiconductor fin, between the outer spacers. | 2021-04-15 |
20210111256 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - After the step of polishing, a part of each of each gate electrode is removed such that the upper surface of each gate electrode is located closer than the damaged region formed in the gate insulating film located between the gate electrodes to the main surface of the semiconductor substrate in cross-section view. Thus, it is possible to suppress the occurrence of a short-circuit defect during the operation of the semiconductor device. | 2021-04-15 |
20210111257 | VERTICAL FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACT STRUCTURE AND LAYOUT - Provided is a structure of a vertical field effect transistor (VFET) device which includes: a fin structure protruding from a substrate, and having an H-shape in a plan view; a gate including a fin sidewall portion formed on sidewalls of the fin structure, and a field gate portion extended from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a position inside the lower half of the fin structure; a bottom epitaxial layer comprising a bottom source/drain (S/D) region, and formed below the fin structure; a power contact landing on the bottom epitaxial layer, and configured to receive a power signal; a top S/D region formed above the fin structure; and a top S/D contact landing on the top S/D region. | 2021-04-15 |
20210111258 | DEVICE AND METHOD OF FORMING WITH THREE-DIMENSIONAL MEMORY AND THREE-DIMENSIONAL LOGIC - In a method for forming a semiconductor device, a layer of logic devices is formed on a substrate. The layer of logic devices includes a stack of gate-all-around field-effect transistors (GAA-FETs) positioned over the substrate, where the stack of GAA-FETs includes a first layer of GAA-FETs stacked over a second layer of GAA-FETs. A first wiring layer is formed over the layer of logic devices, where the first wiring layer includes one or more metal routing levels. A memory stack is formed over the first wiring layer. The memory stack includes wordline layers and insulating layers that alternatingly arranged over the first wiring layer. A three-dimensional (3D) NAND memory device is formed in the memory stack. The 3D NAND memory device includes a channel structure that extends into the memory stack and further is coupled to the wordline layers of the memory stack. | 2021-04-15 |
20210111259 | SEMICONDUCTOR DEVICES HAVING VARIOUSLY-SHAPED SOURCE/DRAIN PATTERNS - A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment. | 2021-04-15 |
20210111260 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns. | 2021-04-15 |
20210111261 | SEMICONDUCTOR STRUCTURES IN A WIDE GATE PITCH REGION OF SEMICONDUCTOR DEVICES - A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures. | 2021-04-15 |
20210111262 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL STRUCTURE - According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure. | 2021-04-15 |
20210111263 | OHMIC ALLOY CONTACT REGION SEALING LAYER - Forming an ohmic contact sealing layer disposed at an intersection between a sidewall of an ohmic contact and a surface of a semiconductor; forming an ohmic contact sealing layer on the intersection between a sidewall of the ohmic contact and the surface of the semiconductor; and subjecting the semiconductor with the ohmic contact to a chemical etchant. | 2021-04-15 |
20210111264 | GATE STRUCTURES - The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure. | 2021-04-15 |
20210111265 | Integrated Circuit with Sidewall Spacers for Gate Spacers - Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack. | 2021-04-15 |
20210111266 | SEMICONDUCTOR DEVICE - A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features. | 2021-04-15 |
20210111267 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer. | 2021-04-15 |
20210111268 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device is disclosed. The semiconductor device is formed by a process that first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film. | 2021-04-15 |
20210111269 | VERTICAL FIELD-EFFECT TRANSISTOR (VFET) DEVICES AND METHODS OF FORMING THE SAME - Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity. | 2021-04-15 |
20210111270 | INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND METHODS OF FORMING THE SAME - Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region. | 2021-04-15 |
20210111271 | SYMMETRICAL TWO-DIMENSIONAL FIN STRUCTURE FOR VERTICAL FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure. | 2021-04-15 |
20210111272 | FINFET DEVICE AND METHOD - A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin. | 2021-04-15 |
20210111273 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND CAPABLE OF CONTROLLING THICKNESSES OF OXIDE LAYERS - A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer. | 2021-04-15 |
20210111274 | Systems and Methods of Fabricating Gate Electrode on Trenched Bottom Electrode based Molecular Spintronics Device - A system and method comprising the steps of: depositing a first electrode metal on an insulating substrate or layer; creating a trench component, in which said trench component comprises a section of said first electrode metal or both first electrode metal and insulating substrate or layer with a depth based on at least one of, a molecular device element, a trenched bottom electrode, and a liftoff molecular device (TBELMD) to be produced; insulating said first electrode metal from a predetermined material deposited in said trench component; and depositing a second electrode metal on said predetermined material deposited in said trench component. | 2021-04-15 |
20210111275 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, an insulating film disposed above the semiconductor substrate, a temperature detecting element disposed on the insulating film, and an anode side region and a cathode side region respectively located on an anode side and a cathode side of the temperature detecting element. The anode side region or the cathode side region includes one or more capacitance elements, and a sum of capacitance values of the capacitance elements is larger than a capacitance value of the temperature detecting element. | 2021-04-15 |
20210111276 | Narrow Semiconductor Mesa Device - First and second trenches are provided in a semiconductor body. A mesa dividing structure is provided between the first and second trenches and comprises non-semiconductor material. A first semiconductor mesa is provided between the first trench and the non-semiconductor material of the mesa dividing structure. The first semiconductor mesa includes emitter, body and drift regions. The first and second trenches are formed by a masked etching technique with a minimum trench separation distance, and the first semiconductor mesa is provided to have a lateral width that is less than the minimum trench separation distance. | 2021-04-15 |
20210111277 | SWITCHING TRANSISTOR AND SEMICONDUCTOR MODULE - [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×10 | 2021-04-15 |
20210111278 | HIGH ELECTRON MOBILITY TRANSISTOR WITH REVERSE ARRANGEMENT OF CHANNEL LAYER AND BARRIER LAYER - A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer. | 2021-04-15 |
20210111279 | SEMICONDUCTOR DEVICE WITH IMPROVED SHORT CIRCUIT WITHSTAND TIME AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a drift layer, a well region, and a source region. The substrate has a first conductivity type. The drift layer has the first conductivity type and is on the substrate. The well region has a second conductivity type opposite the first conductivity type and provides a channel region. The source region is in the well region and has the first conductivity type. A doping concentration of the well region along a surface of the drift layer opposite the substrate is variable such that the well region includes a region of increased doping concentration at a distance from a junction between the source region and the well region. | 2021-04-15 |
20210111280 | METAL GATE STRUCTURE AND METHODS OF FABRICATING THEREOF - A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer. | 2021-04-15 |
20210111281 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction. | 2021-04-15 |
20210111282 | Source/Drain Structure and Manufacturing the Same - A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region. | 2021-04-15 |
20210111283 | MULTI-NEGATIVE DIFFERENTIAL TRANSCONDUCTANCE DEVICE AND METHOD OF PRODUCING THE SAME - A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip. Therefore, effects of low power consumption, a reduced size, and high speed of a chip may be achieved. | 2021-04-15 |
20210111284 | Magnetic Field Sensor Integrated Circuit with an Integrated Coil - A magnetic field sensor includes a lead frame, a semiconductor die having a first surface in which a magnetic field sensing element is disposed and a second surface attached to the lead frame, and a non-conductive mold material enclosing the die and at least a portion of the lead frame. The sensor may include a ferromagnetic mold material secured to a portion of the non-conductive mold material. Features include a multi-sloped taper to an inner surface of a non-contiguous central region of the ferromagnetic mold material, a separately formed element disposed in the non-contiguous central region, one or more slots in the lead frame, a molded ferromagnetic suppression device spaced from the non-conductive mold material and enclosing a portion of a lead, a passive device spaced from the non-conductive mold material and coupled to a plurality of leads, and a ferromagnetic bead coupled to a lead. Also described is a coil secured to the non-conductive mold material and a lead having at least two separated portions with a passive component coupled across the two portions. | 2021-04-15 |
20210111285 | Package Structure for Semiconductor Device, and Semiconductor Device - A package structure comprises a metal plate ( | 2021-04-15 |
20210111286 | MULTI-WELL SELENIUM DEVICE AND METHOD FOR FABRICATION THEREOF - Provided is a field shaping multi-well detector and method of fabrication thereof. The detector is configured by depositing a pixel electrode on a substrate, depositing a first dielectric layer, depositing a first conductive grid electrode layer on the first dielectric layer, depositing a second dielectric layer on the first conductive grid electrode layer, depositing a second conductive grid electrode layer on the second dielectric layer, depositing a third dielectric layer on the second conductive grid electrode layer, depositing an etch mask on the third dielectric layer. Two pillars are formed by etching the third dielectric layer, the second conductive grid electrode layer, the second dielectric layer, the first conductive grid electrode layer, and the first dielectric layer. A well between the two pillars is formed by etching to the pixel electrode, without etching the pixel electrode, and the well is filled with a-Se. | 2021-04-15 |
20210111287 | PHOTOVOLTAIC DEVICE AND METHOD FOR MANUFACTURING PHOTOVOLTAIC DEVICE - A photovoltaic device according to the present disclosure includes: a first-conductivity-type semiconductor film provided on a back side of a semiconductor substrate; a second-conductivity-type semiconductor film in which at least a part thereof is provided in a position different, in plan view, from a position of the first-conductivity-type semiconductor film on the back side of the semiconductor substrate; a protective film, which is formed on a back side of the first-conductivity-type semiconductor film and a back side of the second-conductivity-type semiconductor film, and which includes a conductive portion and a non-conductive transformed portion; and an electrode film formed on a back side of the conductive portion. The transformed portion of the protective film is provided along a conduction path between a back surface of the first-conductivity-type semiconductor film and a back surface of the second-conductivity-type semiconductor film. | 2021-04-15 |
20210111288 | BACK PANEL OF SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A back panel of a solar cell and a method for manufacturing the same are provided. The back panel includes a polyolefin laminate structure and a protective layer disposed on the polyolefin laminate structure. The polyolefin laminate structure includes a reflective layer and a transparent layer disposed on the reflective layer. The transparent layer includes a continuous phase and a dispersed phase dispersed in the continuous phase. The continuous phase is formed from polyolefin. The dispersed phase is formed from a rubber elastomer. Based on the total weight of the transparent layer, an amount of the dispersed phase ranges from 10 wt % to 25 wt %. | 2021-04-15 |
20210111289 | WAVEGUIDE PHOTOELECTRIC DETECTOR - A waveguide photoelectric detector, comprising: a substrate comprising a silicon layer, the silicon layer having a silicon waveguide formed thereon; an active layer dispose on the silicon waveguide, the active layer having a first doped region formed thereon; a horizontal PIN junction formed at an area of the silicon layer below the active layer, the horizontal PIN junction comprising a second doped region, an intrinsic region, and a third doped region. A doping type of the second doped region is the same as that of the first doped region. One end of the second doped region near the intrinsic region is connected to the first doped region. The third doped region and the first doped region form a vertical PIN junction. | 2021-04-15 |
20210111290 | SEMICONDUCTOR SUITABLE FOR USE IN PHOTOANODE - A composition of matter includes an n-type semiconductor. At least a portion of the semiconductor has the crystal structure of the chemical compound represented by FeWO | 2021-04-15 |
20210111291 | PHOTOELECTRIC CONVERSION ELEMENT - The present disclosure is a photoelectric conversion element including: a photoelectric conversion layer | 2021-04-15 |
20210111292 | SOLAR PANEL, ELECTRONIC DEVICE, AND ELECTRONIC TIMEPIECE - Disclosed is a solar panel being divided into a plurality of cells and including: a light transmissive power generation region which is a central region in a diameter direction of a ring-shaped member and in which extending thin line power generators are arranged in parallel in a direction substantially orthogonal to the extending direction; and a periphery power generation region which is a periphery region of the light transmissive power generation region and in which a part of the cells is arranged along a circumferential direction. The cells include a composite cell including at least a part of the periphery power generation region and at least a part of the light transmissive power generation region. A first cell and a second cell different from the first cell are respectively arranged on one end side and on the other end side in the diameter direction of the ring-shaped member. | 2021-04-15 |
20210111293 | METHOD FOR BLACKENING A METALLIC ARTICLE - A method includes providing an electrically conductive mandrel having an outer surface layer comprising a preformed pattern. The metallic article is electroformed. The metallic article includes a plurality of electroformed elements formed in the preformed pattern on the outer surface layer of the mandrel. The plurality of electroformed elements have a first side adjacent to the outer surface layer of the mandrel and a second side. The metallic article is separated from the mandrel. The plurality of electroformed elements are interconnected such that the metallic article forms a unitary, free-standing piece. A solution is applied to create a blackening of the first side of the plurality of electroformed elements. | 2021-04-15 |
20210111294 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell includes a substrate, an emitter layer, a first thin oxide layer, a first doped silicon layer, a second thin oxide layer, and a second doped silicon layer. The substrate has a first side and a second side opposite to each other. The emitter layer is disposed on the first side of the substrate and includes a first conductivity type of dopant. The first thin oxide layer is disposed on the emitter layer. The first doped silicon layer is disposed on the first thin oxide layer and includes the first conductivity type of dopant. The second thin oxide layer is disposed on the second side of the substrate. The second doped silicon layer is disposed on the second thin oxide layer and includes a second conductivity type of dopant. A method for manufacturing a solar cell is also provided herein. | 2021-04-15 |
20210111295 | TUBULAR PECVD DEVICE FOR BIFACIAL PERC SOLAR CELL - The present invention discloses a tubular PECVD device for bifacial PERC solar cell. The present invention bifacial PERC solar cell has high photoelectric conversion efficiency, high appearance quality, and high EL yield, and could solve the problems of both scratching and undesirable deposition. | 2021-04-15 |
20210111296 | AVALANCHE DIODE ALONG WITH VERTICAL PN JUNCTION AND METHOD FOR MANUFACTURING THE SAME FIELD - An embodiment method of manufacturing an avalanche diode includes forming a first trench in a substrate material, filling the first trench with a first material that comprises a dopant, and causing the dopant to diffuse from the first trench to form part of a PN junction. An avalanche diode array can be formed to include a number of the avalanche diodes. | 2021-04-15 |
20210111297 | METHOD OF CREATING CIGS PHOTODIODE FOR IMAGE SENSOR APPLICATIONS - Embodiments disclosed herein include photodiodes and methods of forming such photodiodes. In an embodiment, a method of creating a photodiode, comprises disposing an absorber layer over a first contact, wherein the absorber layer comprises a first conductivity type, and disposing a semiconductor layer over the absorber, wherein the semiconductor layer has a second conductivity type that is opposite from the first conductivity type. In an embodiment, the method further comprises disposing a hole blocking layer over the semiconductor layer, wherein the hole blocking layer is formed with a reactive sputtering process with a processing gas that comprises oxygen, and disposing a second contact over the hole blocking layer. | 2021-04-15 |
20210111298 | Photodetectors - The subject matter of this specification can be embodied in, among other things, a photodetector that includes a semiconductor substrate, a semiconductor annulus on a planar face the semiconductor substrate, and a metal layer on the semiconductor substrate, wherein the metal layer comprises a first region surrounding the semiconductor annulus and comprises a second region filling an interior region to the semiconductor annulus, and the metal layer in the first region forms a Schottky junction with the semiconductor ring. | 2021-04-15 |
20210111299 | SOLID-STATE NEUTRON DETECTOR - A method for fabricating a neutron detector includes providing an epilayer wafer of Boron-10 enriched hexagonal boron nitride (h- | 2021-04-15 |
20210111300 | THIN FILM DEPOSITION SYSTEMS AND DEPOSITION METHODS FOR FORMING PHOTOVOLTAIC CELLS - A thin film deposition system and method for forming photovoltaic cells, the system including a first deposition module including a titanium sputtering target and configured to deposit a titanium precursor layer of a diffusion barrier on the substrate, as the substrate moves through the first deposition module; a second deposition module configured to deposit a first electrode onto the diffusion barrier, as the substrate moves through the second deposition module; and a first connection unit configured to nitride at least a portion of the titanium precursor layer of the diffusion barrier, while the substrate moves though the first connection unit from the first deposition module to the second deposition module. | 2021-04-15 |
20210111301 | III-V/SI HYBRID OPTOELECTRONIC DEVICE AND METHOD OF MANUFACTURE - A method of manufacturing an electro-optically active device. The method comprising the steps of: etching a cavity on a silicon-on-insulator wafer; providing a sacrificial layer adjacent to a substrate of a lll-V semiconductor wafer; epitaxially growing an electro-optically active structure on the lll-V semiconductor wafer; etching the epitaxially grown optically active structure into an electro-optically active mesa; disposing the electro-optically active mesa in the cavity of the silicon-on-insulator wafer and bonding a surface of the electro-optically active mesa, which is distal to the sacrificial layer, to a bed of the cavity; and removing the sacrificial layer between the substrate of the lll-V semiconductor wafer and the electro-optically active mesa. | 2021-04-15 |
20210111302 | INTEGRATED ACTIVE-MATRIX LIGHT EMITTING PIXEL ARRAYS BASED DEVICES - Integrated active-matrix light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. One of the methods includes: forming a plurality of light emitting elements on a substrate, each of the light emitting elements including multiple semiconductor layers epitaxially grown on the substrate and being configured to emit light with a single color, integrating the light emitting elements formed on the substrate with a backplane device, such that each of the light emitting elements is bonded and conductively coupled to a respective pixel circuit in the backplane device, and then removing the substrate from the light emitting elements that remain integrated with the backplane device. Active-matrix multi-color pixel arrays can be formed by sequentially integrating different color light emitting element arrays on the backplane device or depositing different color phosphor or quantum dot materials on single color light emitting element arrays integrated on the backplane device. | 2021-04-15 |
20210111303 | METHOD OF MANUFACTURING DISPLAY DEVICE AND DISPLAY DEVICE - A method of manufacturing a display device includes: forming a first electrode on a substrate; forming an insulating layer on the substrate and on the first electrode; | 2021-04-15 |
20210111304 | SURFACE MODIFICATION METHOD OF ALUMINUM NITRIDE CERAMIC SUBSTRATE - A surface modification method of an aluminum nitride ceramic substrate uses a sputtering deposition and a metal organic chemical vapor deposition (MOCVD) to perform a surface modification of the polycrystalline aluminum nitride ceramic substrate. Accordingly, an aluminum nitride layer is epitaxially grown in two stages of temperature by MOCVD, such that a crystallization phase of monocrystalline aluminum nitride material may be formed on the surface of the polycrystalline aluminum nitride ceramic substrate, so as to decrease a surface roughness of the polycrystalline aluminum nitride ceramic substrate. | 2021-04-15 |
20210111305 | LIGHT-EMITTING DEVICE - The present application relates to a light-emitting device, comprising an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and a cathode, which are stacked in sequence, wherein the light-emitting layer comprises N stacked light-emitting units; each light-emitting unit comprises a thermal activation delayed fluorescent material layer and a quantum dot material layer; the light emitted from the thermal activation delayed fluorescent material layer and the light emitted from the quantum dot material layer are synthesized into white light. | 2021-04-15 |
20210111306 | PIXEL FOR MICRO DISPLAY AND METHOD OF MANUFACTURING THE SAME - Disclosed are a unit pixel of a microdisplay and a method of manufacturing the same. In the unit pixel, each of the sub-pixels forming blue, green, and red light is vertically stacked on the growth substrate. As a result, the area of a unit pixel may be reduced, and transfer processes may be facilitated. | 2021-04-15 |
20210111307 | LIGHT EMITTING ELEMENT - A light emitting element includes: a substrate including a first surface including a first region and a second region; a first semiconductor layered body on the first region, the first semiconductor layered body comprising a first light emitting layer and including: a first lateral surface, and a second lateral surface opposite to the first lateral surface; and a second semiconductor layered body on the second region, the second semiconductor layered body comprising a second light emitting layer and including: a first lateral surface facing the second lateral surface and located on a first semiconductor layered body side of the second semiconductor layered body, and a second lateral surface opposite to the first lateral surface and located on a side opposite the first semiconductor layered body side of the second semiconductor layered body. | 2021-04-15 |
20210111308 | ULTRA-WIDEBAND, FREE SPACE OPTICAL COMMUNICATION APPARATUS - Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a free space optical (FSO) communication apparatus includes a digital data port, an array of light-emitting diodes (LEDs) each configured to have a transient response time of less than 500 picoseconds (ps), and current drive circuitry coupled between the digital data port and the array of LEDs. | 2021-04-15 |
20210111309 | DISPLAY WITH NANO-PYRAMID LIGHT EMITTING DIODES - Particular embodiments described herein provide for an electronic device that can be configured to include a direct view light emitting diode (LED) display. The display can include a plurality of microLEDs and a backplane. Each microLED is comprised of a plurality of nano-pyramid LEDs and the backplane is coupled to each of the microLEDs and can drive each of the microLEDs Each of the plurality of microLEDs includes an array at least two nano-pyramid LEDs connected together. The display can include a plurality of blue microLEDs, a plurality of green microLEDs, and a plurality of red microLEDs | 2021-04-15 |
20210111310 | LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE - A light emitting chip and associated package structure are provided. The light emitting chip includes a substrate, a first type layer, an active layer, a second type layer, a first type electrode and a second type electrode. A second portion of the first type layer is located over the substrate. A first portion of the first type layer is located over the second portion of the first type layer. The active layer is located over the first portion of the first type layer. The second type layer is located over the active layer. The first type electrode is contacted with a top surface and a sidewall of the second portion of the first type layer and contacted with a portion of a sidewall of the substrate. The second type electrode is contacted with the second type layer. | 2021-04-15 |
20210111311 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A light emitting element includes: a semiconductor structure including: a first semiconductor, an active layer, and a second semiconductor layer; a first electrode; a first insulating layer; a first internal electrode; a second internal electrode; a second insulating layer; a first external electrode; and a second external electrode. | 2021-04-15 |
20210111312 | DISPLAY DEVICE REFLECTOR HAVING IMPROVED REFLECTIVITY - Various embodiments of the present disclosure are directed towards a display device. The display device includes an isolation structure disposed over a semiconductor substrate. An electrode is disposed at least partially over the isolation structure. A light-emitting structure is disposed over the electrode. A conductive reflector is disposed below the isolation structure and electrically coupled to the electrode. The conductive reflector is disposed at least partially between sidewalls of the light-emitting structure. The conductive reflector comprises a non-metal-doped aluminum material. | 2021-04-15 |
20210111313 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package includes a substrate, at least one micro LED chip, a black material layer, and a transparent material layer. The substrate has a width ranging from 100 micrometers to 1000 micrometers. The at least one micro LED chip is electrically mounted on a top surface of the substrate and has a width ranging from 1 micrometer to 100 micrometers. The black material layer covers the top surface of the substrate to expose the at least one micro LED chip. The transparent material layer covers the at least one micro LED chip and the black material layer. | 2021-04-15 |
20210111314 | LED WHITE LIGHT DEVICE AND BACKLIGHT MODULE - A light emitting diode (LED) white light device and a backlight module. The LED white light device includes a white light source and a purified film disposed on the white light source. The purified film is evenly distributed with a first rhodamine dye configured to transfer cyan light into green light and a second rhodamine dye configured to transfer orange light into red light. | 2021-04-15 |
20210111315 | FORMING A MULTICOLOR PHOSPHOR-CONVERTED LED ARRAY - A phosphor carrier assembly includes a substrate, a thermal or UV activated release adhesive, a layer containing a pixelated phosphor array, and a partially cured or highly viscous adhesive. The phosphor pixels on the carrier are typically all of the same color. In formation of a phosphor converted LED array the phosphor pixels on the carrier assembly are aligned with and placed in contact with corresponding LED pixels in an array of pixelated LED dice. Selected phosphor pixels on the carrier assembly may then be attached to corresponding LED pixels, and released from the substrate, by powering (activating) the corresponding LED pixels to heat the selected phosphor pixel to a temperature that releases the thermal release adhesive and that cures or partially cures the adhesive on the selected phosphor pixels in contact with the corresponding LED pixels. | 2021-04-15 |
20210111316 | OPTICAL COUPLING LAYER TO IMPROVE OUTPUT FLUX IN LEDS - An optical coupling structure is disposed on a light output surface of a semiconductor LED to facilitate coupling of light emitted by the semiconductor LED through the light output surface. The optical coupling structures comprise light scattering particles and/or air voids embedded in or coated with a thin layer of a material that has an index of refraction close to or matching the index of refraction of the material forming the light output surface of the semiconductor LED. | 2021-04-15 |
20210111317 | PHOTON EXTRACTION FROM ULTRAVIOLET LIGHT-EMITTING DEVICES - In various embodiments, a layer of organic encapsulant is provided over a surface of an ultraviolet (UV) light-emitting semiconductor die, and at least a portion of the encapsulant is exposed to UV light to convert at least some of said portion of the encapsulant into non-stoichiometric silica material. The non-stoichiometric silica material includes silicon, oxygen, and carbon, and a carbon content of the non-stoichiometric silica material is greater than 1 ppm and less than 40 atomic percent. | 2021-04-15 |
20210111318 | UV LED PACKAGE - A UV LED package includes a substrate having a dam, a LED die on the substrate, a lens bonded to the substrate, an extraction layer covering a light emitting surface of the LED die, and a lens sealing layer between the lens and the dam. The extraction layer can be formed to provide a precise gap G between the lens and the light emitting diode (LED). In addition, the materials for the lens and the extraction layer can be selected, and the gap G can be precisely dimensioned, to reduce refraction and reflection, to improve radiation extraction, to reduce power radiance, and to improve the efficiency of the UV LED package. | 2021-04-15 |
20210111319 | MICRO-LED DESIGN FOR CHIEF RAY WALK-OFF COMPENSATION - Techniques disclosed herein relate to micro light emitting diodes (micro-LEDs) for a display system. A display system includes an array of micro light emitting diodes (micro-LEDs), an array of output couplers optically coupled to the array of micro-LEDs and configured to extract light emitted by respective micro-LEDs in the array of micro-LEDs, a waveguide display, and display optics configured to couple the light emitted by the array of micro-LEDs and extracted by the array of output couplers into the waveguide display. Each output coupler in the array of output couplers is configured to direct a chief ray of the light emitted by a respective micro-LED in the array of micro-LEDs to a different respective direction. | 2021-04-15 |
20210111320 | OPTICAL COUPLING LAYER TO IMPROVE OUTPUT FLUX IN LEDS - An optical coupling structures are disposed on light output surfaces of semiconductor LEDs of a miniLED or microLED array to facilitate coupling of light emitted by the semiconductor LEDs through the light output surfaces. The optical coupling structures comprise light scattering particles and/or air voids embedded in or coated with a thin layer of a material that has an index of refraction close to or matching the index of refraction of the material forming the light output surface of the semiconductor LEDs. | 2021-04-15 |
20210111321 | PASSIVATION FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE - In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure. | 2021-04-15 |
20210111322 | LIGHT-EMITTING DEVICE - A light-emitting device includes a carrier, a light-emitting unit disposed on the carrier, a reflective element arranged on the light-emitting unit, and an optical element arranged on the carrier and surrounding the light-emitting unit. | 2021-04-15 |
20210111323 | DISPLAY DEVICE - A display device includes a substrate including a display area and a non-display area, a pixel located in the display area, a pad unit on one side of the non-display area, and a driver connected to the pixel. The pixel includes a first insulating layer, a first light emitting element on the first insulating layer, a second insulating layer on the first light emitting element and exposing one end portion and another end portion of the first light emitting element, a first contact electrode on the second insulating layer and connected to the one end portion of the first light emitting element, and a second contact electrode on the second insulating layer and connected to the other end portion of the first light emitting element. The pad unit includes a pad metal layer, a first pad insulating layer, a second pad insulating layer, and a pad electrode. | 2021-04-15 |
20210111324 | DISPLAY MODULE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a display module includes forming a driving circuit layer on a substrate, the driving circuit layer including a plurality of driving circuits and a plurality of electrode pads electronically connected with the plurality of driving circuits; forming an adhesive layer on the driving circuit layer; transferring each of a plurality of light emitting diodes (LEDs) onto a respective area of the adhesive layer corresponding to a respective one of the plurality of electrode pads; and forming a black matrix layer on the adhesive layer, between the plurality of LEDs. | 2021-04-15 |
20210111325 | DISPLAY MODULE AND MANUFACTURING METHOD THEREOF - A display module and a manufacturing method thereof are provided. The manufacturing method may include forming an epitaxial film comprising a light emitting layer, a first type semiconductor layer, and a second type semiconductor layer, attaching the epitaxial film to an intermediate substrate comprising a conductive material, patterning the epitaxial film to form a light emitting diode (LED) and coupling the LED to a driving circuit layer through the conductive material. | 2021-04-15 |
20210111326 | UPPER SUBSTRATE FOR MINIATURE LED COMPONENT, MINIATURE LED COMPONENT, AND MINIATURE LED DISPLAY DEVICE - Provided is an upper substrate for a miniature LED component, a miniature LED component, and a miniature LED display device, wherein the upper substrate for the miniature LED component comprises: a bottom substrate; a metal layer formed on the bottom substrate and having a pattern capable of covering a non-opening region of the lower substrate for the miniature LED component; a graphene layer formed on the bottom substrate; a transparent adhesive layer formed on the bottom substrate to cover the metal layer and the graphene layer. | 2021-04-15 |
20210111327 | THERMOELECTRIC CONVERSION MODULE AND METHOD FOR PRODUCING THERMOELECTRIC CONVERSION MODULE - A thermoelectric conversion module includes thermoelectric conversion elements, and a first insulating circuit board provided with a first insulating layer and a first electrode part formed on one surface of the first insulating layer is disposed on one end side of the thermoelectric conversion elements. The first electrode part includes a first aluminum layer made of aluminum or an aluminum alloy, and a first sintered silver layer which is formed on a surface of the first aluminum layer on a side opposite to the first insulating layer and is formed of a sintered body of silver. The first aluminum layer has a thickness in a range of 50 μm or more and 2000 μm or less. The first sintered silver layer has a thickness of 5 μm or more and a porosity of less than 10% at least in a region where the thermoelectric conversion element is disposed. | 2021-04-15 |
20210111328 | STABILIZED COPPER SELENIDE THERMOELECTRIC MATERIALS AND METHODS OF FABRICATION THEREOF - A thermoelectric composition is provided that includes a nanocomposite comprising a copper selenide (Cu | 2021-04-15 |
20210111329 | FABRICATING TRANSMON QUBIT FLIP-CHIP STRUCTURES FOR QUANTUM COMPUTING DEVICES - A quantum computing device is formed using a first chip and a second chip, the first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The second chip has a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits. | 2021-04-15 |
20210111330 | PACKAGE FOR ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE PACKAGE - A package for an electric device is proposed based on a substrate (SU, SU | 2021-04-15 |
20210111331 | DEVICE HAVING AN ELECTRO-CERAMIC COMPONENT | 2021-04-15 |
20210111332 | BONDED BODY AND ELASTIC WAVE ELEMENT - A bonded body includes a piezoelectric single crystal substrate; a supporting substrate composed of a polycrystalline ceramic material or a single crystal material; a bonding layer provided on the piezoelectric single crystal substrate and having a composition of Si | 2021-04-15 |
20210111333 | SIDEWALL SPACER STRUCTURE FOR MEMORY CELL - Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material. | 2021-04-15 |
20210111334 | MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer. | 2021-04-15 |
20210111335 | STACKED DIE ASSEMBLY - A sensor device comprising: a lead frame; a first/second semiconductor die having a first/second sensor structure at a first/second sensor location, and a plurality of first/second bond pads electrically connected to the lead frame; the semiconductor dies having a square or rectangular shape with a geometric center; the sensor locations are offset from the geometrical centers; the second die is stacked on top of the first die, and is rotated by a non-zero angle and optionally also offset or shifted with respect to the first die, such that a perpendicular projection of the first and second sensor location coincide. | 2021-04-15 |
20210111336 | HALL DEVICE - A Hall effect device includes a semiconductor region and at least three contacts to the semiconductor region, which are arranged in the semiconductor region substantially along a line or curve. The line or curve functionally separates the semiconductor region in a first region and a second region. The Hall effect device further including a first electrode that is electrically isolated against the first region and a second electrode that is electrically isolated against the second region. Two of the at least three contacts supply electric energy to the first region and to the second region, and the remaining at least one contact taps an output signal of the first region and/or the second region that responds to a magnetic field component. | 2021-04-15 |
20210111337 | HYBRID PERPENDICULAR AND IN-PLANE STT-MRAM - A memory device, comprising a first magnetic anisotropy magnetic tunnel junction (ma-MTJ) having a first free layer disposed at one end thereof and a second ma-MTJ having a second free layer disposed at one end thereof. The first and second ma-MTJs are stacked with each other with the first free layer facing the second free layer. A tunneling barrier is sandwiched between the first and second free layer. A magnetic anisotropy direction of the first ma-MTJ is perpendicular to a magnetic anisotropy direction of the second ma-MTJ, and a magnetisation direction of the first free layer is perpendicular to a magnetisation direction of the second free layer. | 2021-04-15 |
20210111338 | MAGNETIC TUNNEL JUNCTIONS WITH PROTECTION LAYERS - A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer. | 2021-04-15 |
20210111339 | RRAM STRUCTURE - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode. | 2021-04-15 |
20210111340 | MULTI-BIT RESISTIVE RANDOM ACCESS MEMORY CELL AND FORMING METHOD THEREOF - A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell. | 2021-04-15 |
20210111341 | THREE-DIMENSIONAL PHASE-CHANGE MEMORY DEVICES - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes parallel lower and upper bit lines, parallel word lines, lower and upper memory cells, a lower bit line contact in contact with the lower bit line, and an upper bit line contact in contact with the upper bit line. The parallel word lines are in a same plane between the lower and the upper bit lines. Each word line is perpendicular to the lower and upper bit lines. Each lower memory cell is disposed at an intersection of the lower bit line and a respective word line. Each upper memory cell is disposed at an intersection of the upper bit line and a respective word line. Each lower or upper memory cell includes stacked a phase-change memory (PCM) element, a selector, and electrodes. At least one of the lower and upper bit line contacts is disposed inclusively between the lower and upper memory cells in a plan view. | 2021-04-15 |