15th week of 2016 patent applcation highlights part 43 |
Patent application number | Title | Published |
20160104727 | ARRAY SUBSTRATE AND MANUFACTURE METHOD THEREOF - Embodiments of the disclosure provide an array substrate and a manufacture method thereof. The array substrate comprises a display region and a non-display region, the display region comprises a transistor, the transistor comprises a source electrode, a drain electrode and an active layer, the source electrode and the drain electrode are provided on the active layer and are respectively provided at two ends of the active layer. The non-display region is provided with an alignment mark, the alignment mark is provided in a same layer as the active layer and is configured for aligning the source electrode and the drain electrode with the active layer in the case of re-fabricating the source electrode and the drain electrode. | 2016-04-14 |
20160104728 | SOLID-STATE IMAGE PICKUP APPARATUS - Provided is a back-illuminated solid-state image pickup apparatus having an improved color separation characteristic. A photo detector includes a first photo detector unit and a second photo detector unit disposed deeper than the first photo detector unit with respect to a back surface of a semiconductor substrate, wherein the first photo detector unit includes a first-conductivity-type first semiconductor region where carriers generated through photo-electric conversion are collected as signal carriers. A readout portion includes a first-conductivity-type second semiconductor region extending in a depth direction such that the carriers collected in the first semiconductor region are read out to a front surface of the semiconductor substrate. A unit that reduces the amount of light incident on the second semiconductor region is provided. | 2016-04-14 |
20160104729 | PINNED PHOTODIODE WITH A LOW DARK CURRENT - A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer. | 2016-04-14 |
20160104730 | PHOTODIODE INSULATION STRUCTURE - A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer. | 2016-04-14 |
20160104731 | Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region - A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias. | 2016-04-14 |
20160104732 | IMAGE PICKUP APPARATUS, IMAGE PICKUP SYSTEM, AND IMAGE PICKUP APPARATUS DRIVING METHOD - Each of multiple pixels includes a photoelectric conversion unit. A first holding unit is configured to hold a charge generated by the photoelectric conversion unit, at a location different from location of the photoelectric conversion unit. A second holding unit is configured to hold a charge held by the first holding unit at a location different from locations of both of the first holding unit and the photoelectric conversion unit. An amplifying unit includes an input node different from the second holding unit and is configured to output a signal based on a charge transferred to the input node from the second holding unit. A first discharge unit includes a charge draining node which is electrically connected to a line where a predetermined voltage is supplied. The first discharge unit discharges a charge held by the first holding unit to the charge draining node. | 2016-04-14 |
20160104733 | IMAGE PICKUP APPARATUS AND RADIATION IMAGE PICKUP SYSTEM - An image pickup apparatus includes a pixel array including a plurality of pixels arranged in a two-dimensional pattern, each of which includes a conversion unit, an amplification unit, a first holding unit configured to hold a first signal obtained by the amplification unit amplifying an electric charge converted by the conversion unit having a first sensitivity, a second holding unit configured to hold a second signal obtained by the amplification unit amplifying the electric charge converted by the conversion unit having a second sensitivity different from the first sensitivity, and a third holding unit configured to hold an offset signal of the amplification unit, and a correction unit configured to correct the first signal using a second output signal output from the second holding unit or a first output signal output from the first holding unit, and a third output signal output from the third holding unit. | 2016-04-14 |
20160104734 | IMAGING DEVICE - To provide an imaging device in which incident light can be converted into an appropriate electric signal. The imaging device includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, and a fourth transistor. One of a source electrode and a drain electrode of the first transistor and one electrode of the photoelectric conversion element have an electrical connection portion in a first opening provided in an insulating layer positioned between the one of the source electrode and the drain electrode of the first transistor and the one electrode of the photoelectric conversion element. The number of the first opening is one in a region where the one of the source electrode and the drain electrode of the first transistor overlaps with the one electrode of the photoelectric conversion element. | 2016-04-14 |
20160104735 | Dual-Mode Image Sensor With A Signal-Separating Color Filter Array, And Method For Same - A dual-mode image sensor with a signal-separating CFA includes a substrate including a plurality of photodiode regions and a plurality of tall spectral filters having a uniform first height and for transmitting a first electromagnetic wavelength range. Each of the tall spectral filters is disposed on the substrate and aligned with a respective photodiode region. The image sensor also includes a plurality of short spectral filters for transmitting one or more spectral bands within a second electromagnetic wavelength range. Each of the short spectral filters is disposed on the substrate and aligned with a respective photodiode region. The image sensor also includes a plurality of single-layer blocking filters for blocking the first electromagnetic wavelength range. Each single-layer blocking filter is disposed on a respective short spectral filter. Each single-layer blocking filter and its respective short spectral filter have a combined height substantially equal to the first height. | 2016-04-14 |
20160104736 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD OF THE SAME, ELECTRONIC EQUIPMENT, AND SEMICONDUCTOR DEVICE - A solid-state imaging device includes: a photodiode formed to be segmented with respect to each pixel in a pixel area in which plural pixels are integrated on a light receiving surface of a semiconductor substrate; an insulator film formed on the semiconductor substrate to cover the photodiode; a recessed part formed with respect to each of the pixels in the insulator film in an upper part of the photodiode; a first light transmission layer of a siloxane resin formed to fill the recessed part and configure an optical waveguide in the pixel area; a second light transmission layer formed to configure an on-chip lens with respect to each of the pixels in the pixel area; and a guard ring formed to surround an outer circumference of the pixel area to partition an inner area containing the pixel area and an outer dicing area. | 2016-04-14 |
20160104737 | IMAGE SENSOR DEVICE WITH FLEXIBLE INTERCONNECT LAYER AND RELATED METHODS - An image sensor device may include an interconnect layer having an opening extending therethrough, an image sensor IC within the opening and having an image sensing surface, and an IR filter aligned with the image sensing surface. The image sensor device may include an encapsulation material laterally surrounding the image sensor IC and filling the opening, and a flexible interconnect layer coupled to the interconnect layer opposite the image sensing surface. | 2016-04-14 |
20160104738 | IMAGE SENSING DEVICE WITH INTERCONNECT LAYER GAP AND RELATED METHODS - An image sensing device may include an interconnect layer, an image sensor IC coupled to the interconnect layer and having an image sensing surface, and an IR filter aligned with the image sensing surface opposite the interconnect layer. The image sensing device may include a flexible interconnect layer aligned with the interconnect layer and having a flexible substrate extending laterally outwardly from the interconnect layer, and electrically conductive traces on the flexible substrate. The image sensing device may also include solder bodies coupling the interconnect layer and the flexible interconnect layer and also defining a gap between the interconnect layer and the flexible interconnect layer. | 2016-04-14 |
20160104739 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line. | 2016-04-14 |
20160104740 | IMAGE SENSOR AND METHODS OF MANUFACTURING THE SAME - An image sensor includes a first substrate, a photodiode array, a first wiring structure, a second wiring structure, a third wiring structure and a light blocking layer pattern. The photodiode array is disposed in the first substrate. The photodiode array includes first photodiodes in a first region, second photodiodes in a second region and third photodiodes in a third region. The first wiring structure is disposed in the first region. The first wiring structure is electrically connected to the first photodiodes. The second wiring structure is disposed in the second region. The second wiring structure includes power supply wiring. The third wiring structure is disposed in the third region. The third wiring structure is electrically connected to the third photodiodes. The light blocking layer pattern is disposed on the first substrate. The light blocking layer pattern covers the third region and the fourth region. | 2016-04-14 |
20160104741 | INTEGRATED IMAGING DEVICE FOR INFRARED RADIATION AND METHOD OF PRODUCTION - The integrated imaging device comprises a substrate ( | 2016-04-14 |
20160104742 | METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP APPARATUS - One or more methods of manufacturing a solid-state image pickup apparatus and one or more methods of manufacturing a light reflection member are provided herein, and one or more embodiments thereof may include forming a first insulating film and forming a photoresist pattern on the first insulating film. Furthermore, one or more embodiments of such methods may include forming an opening portion by removing the first insulating film while having the photoresist pattern serve as a mask and forming a light reflection member on a sidewall of the opening portion formed in the first insulating film. | 2016-04-14 |
20160104743 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME - The invention relates to an optoelectronic device ( | 2016-04-14 |
20160104744 | LED ARRAY - An LED array having N light-emitting diode units (N≧3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer. | 2016-04-14 |
20160104745 | SEMICONDUCTOR DEVICE - A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer. | 2016-04-14 |
20160104746 | METHODS OF FABRICATING A VARIABLE RESISTANCE MEMORY DEVICE USING MASKING AND SELECTIVE REMOVAL - A semiconductor device is fabricated by forming a semiconductor layer on a substrate, patterning the semiconductor layer in a first direction parallel to a top surface of the substrate to form semiconductor patterns extending parallel to the first direction, forming sacrificial patterns in gap regions between the semiconductor patterns, forming mask patterns on the semiconductor patterns and the sacrificial patterns extending parallel to a second direction crossing the first direction, removing the sacrificial patterns, and patterning the semiconductor patterns using the mask patterns as an etch mask to form an array of selection devices for a variable resistance memory device on the substrate. | 2016-04-14 |
20160104747 | APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY - Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described. | 2016-04-14 |
20160104748 | MEMORY CELL ARRAY STRUCTURES AND METHODS OF FORMING THE SAME - The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure. | 2016-04-14 |
20160104749 | ORGANIC ELECTROLUMINESCENT ELEMENT - The objective is to provide an organic electroluminescent element with an improved luminous efficiency. The organic electroluminescent element has a structure in which a first light-emitting unit containing a phosphorescent red light-emitting material, a second light-emitting unit containing a phosphorescent yellow light-emitting material, and a third light-emitting unit containing a fluorescent blue light-emitting material are stacked with interlayers in-between. A peak emission wavelength of the phosphorescent yellow light-emitting material is in a range of 530 nm to 570 nm. A peak emission wavelength of the fluorescent blue light-emitting material is in a range of 440 nm to 480 nm. The organic electroluminescent element has a ratio of a yellow emission intensity to a blue emission intensity in a range of 1.0 to 2.0. The organic electroluminescent element further has a ratio of a red emission intensity to the blue emission intensity in a range of 1.5 to 3.0. | 2016-04-14 |
20160104750 | DISPLAY UNIT AND ELECTRONIC APPARATUS - There is included a pixel including a plurality of sub-pixels, each of the sub-pixels including a single first electrode, a single second electrode provided along a laminating direction of the first electrode, and a light-emitting layer inserted between the first electrode and the second electrode. One or more of the plurality of sub-pixels have a plurality of light emission regions including two or more light emission regions different in one or more of shape, size, and orientation from one another. | 2016-04-14 |
20160104751 | HYBRID DISPLAY ASSEMBLY INCLUDING A SOLAR CELL - A display assembly for a portable object includes a first, at least partially transparent, emissive display device located on the side of an observer, a second reflective display device and a solar cell being arranged, in that order, underneath the first emissive display device. The second reflective display device is capable of switching between a transparent state, in which the device does not display any information, and a reflective state, when activated. | 2016-04-14 |
20160104752 | TRANSPARENT ORGANIC LIGHT EMITTING DISPLAY DEVICE - A transparent organic light emitting display device having a pixel region on which an image is displayed and a transparent region through which external light passes. The transparent organic light emitting display device includes a first substrate, a second substrate opposing the first substrate, a display unit disposed between the first substrate and the second substrate, the display unit including an organic light emitting diode. A sealing unit is disposed between the first substrate and the second substrate to surround the display unit and to bond the first substrate to the second substrate. A filling unit is disposed in an inner side of the sealing unit to cover the display unit, the filling unit including a silicon filling material and a photochromic material. | 2016-04-14 |
20160104753 | PIXEL STRUCTURE - A pixel structure, including a data line, a scan line, at least one active device, a first auxiliary electrode, and a light emitting device, is provided. The at least one active device is electrically connected with the data line and the scan line, and each active device includes a gate, a channel layer, a source, and a drain. The first auxiliary electrode is electrically insulated from the active device. The light emitting device is disposed above the first auxiliary electrode, wherein the light emitting device includes a first electrode layer, a light emitting layer, and a second electrode layer. The first electrode layer is electrically connected with the first auxiliary electrode. The light emitting layer is disposed on the first electrode layer. The second electrode layer is disposed on the light emitting layer, wherein the second electrode layer is electrically connected with the active device. | 2016-04-14 |
20160104754 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a substrate; a thin film transistor (TFT) on the substrate; a first interlayer insulating layer between a gate electrode and the source electrode and between a drain electrode and the source electrode of the TFT and including an inorganic material; a second interlayer insulating layer between the first interlayer insulating layer and the source electrode and between the first interlayer insulating layer and the drain electrode and including an organic material; a first organic layer on the source electrode and the drain electrode; a capacitor, a second electrode, and the first interlayer insulating layer between the first electrode and the second electrode; a pixel electrode in an aperture in the second interlayer insulating layer adjacent to the thin film transistor and the capacitor and coupled to the source electrode or the drain electrode; an organic emission layer ; and an opposite electrode. | 2016-04-14 |
20160104755 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes: a substrate; a first thin film transistor including a first active region on the substrate; a second thin film transistor connected to the first thin film transistor and including a second active region spaced from the first active region; and a silicon layer on the substrate and including a plurality of polysilicon lines spaced from each other and extending in a first direction and a plurality of amorphous silicon lines between the adjacent polysilicon lines and extending in the first direction, wherein the first active region and the second active region are in different polysilicon lines of the plurality of polysilicon lines. | 2016-04-14 |
20160104756 | DISPLAY APPARATUS - Provided is a display apparatus, including a substrate; a plurality of pixels that are on the substrate and include at least one display device; a separation area that is on the substrate and between two adjacent pixels from among the plurality of pixels; and a penetrating portion that is in the separation area and penetrates the substrate. | 2016-04-14 |
20160104757 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - Provided is an organic light emitting diode display device, including a pixel substrate including a pixel unit displaying an image and a peripheral unit surrounding the pixel unit; a first insulating layer covering the pixel substrate; a fanout line on the first insulating layer of the peripheral unit; a second insulating layer covering the first insulating layer and the fanout line; an etching prevention member on the second insulating layer of the peripheral unit and preventing overetching of the second insulating layer; a third insulating layer covering the second insulating layer; a peripheral potential voltage line on the third insulating layer of the peripheral unit and transferring a potential voltage; a passivation layer covering the third insulating layer; and an organic light emitting diode on the passivation layer of the pixel unit, in which the etching prevention member overlaps with the fanout line and the peripheral potential voltage line. | 2016-04-14 |
20160104758 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting device includes: a substrate; a first thin film transistor including a first active pattern positioned on the substrate and a first gate electrode positioned on the first active pattern; an organic light emitting element connected to the first active pattern; and a capacitor electrode overlapping the first gate electrode on the first gate electrode and having the same edge as the first gate electrode. | 2016-04-14 |
20160104759 | DISPLAY UNIT AND ELECTRONIC APPARATUS - A display unit includes: a drive substrate including a thin film transistor; a pixel section provided on the drive substrate and including a plurality of pixels, each of the pixels including a first electrode, an organic layer including a light-emitting layer, and a second electrode in this order; and a connection section provided in a peripheral region around the pixel section in the drive substrate and configured to be electrically connected to the second electrode, in which the connection section includes an oxide semiconductor layer including, in at least a portion on a surface side thereof, a low-resistance region with lower electrical resistance than that in a portion other than the low-resistance region. | 2016-04-14 |
20160104760 | DISPLAY DEVICE AND MANUFACTURING METHOD OF THE DISPLAY DEVICE - A display device includes a plurality of pixels arranged on a substrate, a plurality of pixel electrodes, wherein each pixel electrode of the plurality of pixel electrodes corresponds to a pixel of the plurality of pixels, a bank between adjacent pixel electrodes of the plurality of pixel electrodes, wherein the bank exposes a part of the pixel electrodes, an electroluminescent layer on each of the plurality of pixel electrodes, a common electrode above the bank and the electroluminescent layer, a plurality of insulators on the exposed regions of the pixel electrodes, wherein the common electrode is between the insulators and the pixel electrodes, and an auxiliary wiring on the common electrode between adjacent insulators of the plurality of insulators, wherein a top surface of each insulator of the plurality of insulators is farther from the substrate than a top surface of the common electrode. | 2016-04-14 |
20160104761 | DISPLAY DEVICE - A display device includes a display region comprising a plurality of pixels, each pixel of the plurality of pixels comprises a light emitting element which includes a pixel electrode, a conductive layer below the pixel electrode and configured to receive a specified electric voltage, and a thin film transistor below the pixel electrode and the conductive layer, wherein the thin film transistor comprises a semiconductor layer which includes a channel region, a gate electrode which is overlapping the channel region, a first electrode electrically connected to the semiconductor layer and the pixel electrode, and a second electrode electrically connectable to a power supply line, wherein the conductive layer includes an overlapped region which overlaps with the channel region, and the first electrode extends so as to cover the gate electrode at the overlapped region. | 2016-04-14 |
20160104762 | METHOD OF FABRICATING A MIM CAPACITOR WITH MINIMAL VOLTAGE COEFFICIENT AND A DECOUPLING MIM CAPACITOR AND ANALOG/RF MIM CAPACITOR ON THE SAME CHIP WITH HIGH-K DIELECTRICS - Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient α; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient α′ opposite in polarity but substantially equal in magnitude to α; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line. | 2016-04-14 |
20160104763 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode. | 2016-04-14 |
20160104764 | METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE - A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings. | 2016-04-14 |
20160104765 | SEMICONDUCTOR DEVICES WITH HORIZONTAL GATE ALL AROUND STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device having a horizontal gate all around structure is provided. The semiconductor device includes a substrate and a fin. The fin is disposed on the substrate, and includes an anti-punch through (APT) layer formed of a material at a dose of about 1E18 atoms/cm | 2016-04-14 |
20160104766 | Power Semiconductor Device with Source Trench and Termination Trench Implants - A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench. | 2016-04-14 |
20160104767 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration layer formed on the high-concentration layer and containing first conductivity type impurities; a first electrode and a second electrode formed on the low-concentration layer; a vertical semiconductor element that allows current to flow between the second electrode and the high-concentration layer; and a first trench unit that realizes electric connection between the first electrode and the high-concentration layer. The first trench unit consists of first polysilicon containing first conductivity type impurities, and a diffusion layer configured to surround the first polysilicon in a plan view and to contain first conductivity type impurities. The first polysilicon is configured to reach the high-concentration layer by penetrating the low-concentration layer. Respective concentrations of the first conductivity type impurities contained in the first polysilicon and in the diffusion layer are kept constant in a direction from the low-concentration layer to the high-concentration layer. | 2016-04-14 |
20160104768 | Method of Forming a Super Junction Semiconductor Device Having Stripe-Shaped Regions of the Opposite Conductivity Types - A super junction semiconductor device is formed by forming at least a portion of a drift layer on a doped layer of a first conductivity type, implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type and stripe-shaped second implant regions of the second conductivity type in alternating order, and performing a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions of the first conductivity type and stripe-shaped second regions of the second conductivity type. | 2016-04-14 |
20160104769 | LAYERED STRUCTURE OF A P-TFET - A p-type Tunnel Field-Effect Transistor comprises a drain p-type semiconductor region, a source n-type semiconductor region, and at least one gate stack. The source n-type semiconductor region comprises a lowly doped section with a length of at least 10 nm and with a doping level of n-type dopant elements below 5×10 | 2016-04-14 |
20160104770 | PROFILE CONTROL OVER A COLLECTOR OF A BIPOLAR JUNCTION TRANSISTOR - Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench. | 2016-04-14 |
20160104771 | COMMON CONTACT OF N++ AND P++ TRANSISTOR DRAIN REGIONS IN CMOS - Implementations of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one implementation, an integrated circuit is provided. The integrated circuit comprises a first transistor having a first conductivity type, the first transistor comprising a first gate, an first source region and a first drain region disposed on opposite sides of the first gate, and a second transistor having a second conductivity type opposite from the first conductivity type of the first transistor, the second transistor comprising a second gate, a second source region and a second drain region disposed on opposite sides of the second gate, wherein the second drain region of the second transistor is abutted against the first drain region of the first transistor. | 2016-04-14 |
20160104772 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE - A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins. | 2016-04-14 |
20160104773 | Semiconductor Structure Having Integrated Snubber Resistance and Related Method - A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions. | 2016-04-14 |
20160104774 | NON-PLANAR VERTICAL DUAL SOURCE DRIFT METAL-OXIDE SEMICONDUCTOR (VDSMOS) - A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure allow for two channels and a dual current with mirrored flows, each traveling into and downward through a center region of a connecting well that connects the substrate with the drain areas and shallow wells containing the source areas, the current then traveling in opposite directions within the substrate region of the connecting well toward the two drains. The source and drain areas may be separate raised structures or isolated areas of a continuous raised structure. | 2016-04-14 |
20160104775 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a buffer layer on a semiconductor substrate including first and second regions, a first channel layer on the buffer layer of the first region, a second channel layer on the buffer layer of the second region, and a spacer layer between the second channel layer and the buffer layer. The buffer layer, the first and second channel layers, and the spacer layer are formed of semiconductor materials including germanium. A germanium concentration difference between the first and second channel layers is greater than a germanium concentration difference between the buffer layer and the second channel layer. The spacer layer has a germanium concentration gradient. | 2016-04-14 |
20160104776 | High Mobility Devices with Anti-Punch Through Layer and Methods of Forming Same - An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having APT dopants and a channel region over the APT layer. The channel region is substantially free of APT dopants. The semiconductor device further includes a conductive gate stack on a sidewall and a top surface of the channel region. | 2016-04-14 |
20160104777 | Zero-Dimensional Electron Devices and Methods of Fabricating the Same - A semiconductor device comprises a substrate and quantum dots, wherein a peak emission of the quantum dots has a FWHM of less than 20 meV when the semiconductor is measured at a temperature of 4 Kelvin. | 2016-04-14 |
20160104778 | GRAPHENE BASE TRANSISTOR AND METHOD FOR MAKING THE SAME - A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other. | 2016-04-14 |
20160104779 | SILICON CARBIDE DEVICE AND A METHOD FOR FORMING A SILICON CARBIDE DEVICE - A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation layer structure laterally covers at least partly a main surface of the silicon carbide substrate and the molding material layer is arranged adjacent to the inorganic passivation layer structure. | 2016-04-14 |
20160104780 | Semiconductor Devices and Methods of Manufacturing Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer. | 2016-04-14 |
20160104781 | INTEGRATED FLOATING DIODE STRUCTURE AND METHOD THEREFOR - In one embodiment, a floating diode structure includes a p-type semiconductor substrate. An n-type doped region is disposed between the semiconductor substrate and a p-type doped region of the first conductivity type adjacent the first doped region. An n-type cathode region is disposed within the p-type doped region and a p-type anode region is disposed within the cathode region. An anode electrode is connected to the anode region and a cathode electrode is connected to the cathode region. In one embodiment, the cathode electrode is further connected to the p-type doped region. The n-type doped region is configured as a floating region that facilitates the diode operating in both a forward and reverse bias mode and both below ground and above ground with respect to the p-type semiconductor substrate. | 2016-04-14 |
20160104782 | TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a transistor structure includes a step of implanting a light dosage into a substrate at a bit line junction and two cell side junctions, and a step of implanting a light dosage into the bit line junction an additional time. A uniform region having a substantially uniform dopant concentration is formed at the bit line junction. The dopant concentration of the uniform region is higher than that of the cell side junctions and higher than that of the region of the bit line junction under the uniform region. | 2016-04-14 |
20160104783 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction. | 2016-04-14 |
20160104784 | Ohmic Contact to Semiconductor - A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged. | 2016-04-14 |
20160104785 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first dielectric layer thereon, and a shallow trench isolation (STI) in the substrate and surrounding the first gate layer and the first dielectric layer; removing the first dielectric layer; forming a first spacer on the sidewall of the STI above the first gate layer; and using the first spacer as mask to remove part of the first gate layer and part of the substrate for forming a first opening while defining a first gate structure and a second gate structure. | 2016-04-14 |
20160104786 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess. | 2016-04-14 |
20160104787 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE CONTACTS ON SOURCE/DRAINS - Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer. | 2016-04-14 |
20160104788 | Methods of Fabricating Semiconductor Devices - Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask. | 2016-04-14 |
20160104789 | SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same - A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma nitridation process. The method includes forming. subsequent to the etching, a charge-trapping layer on the first oxide layer. | 2016-04-14 |
20160104790 | SILICENE MATERIAL LAYER AND ELECTRONIC DEVICE HAVING THE SAME - Provided are silicene material layers and electronic devices having a silicene material layer. The silicene material layer contains silicon atoms in a 2-dimensional honeycomb structure formed as one of a monolayer and a double layer. The silicene material layer includes a doping region doped with at least one material from the group of Group 1, Group 2, Group 16 and Group 17 and at least one of a p-type dopant or an n-type dopant. | 2016-04-14 |
20160104791 | METHOD FOR FORMING AN IMPLANTED AREA FOR A HETEROJUNCTION TRANSISTOR THAT IS NORMALLY BLOCKED - The invention relates to a method for manufacturing a heterojunction transistor ( | 2016-04-14 |
20160104792 | HIGH VOLTAGE MOSFET DEVICES AND METHODS OF MAKING THE DEVICES - A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described. | 2016-04-14 |
20160104793 | Structure and Method for FinFET Device - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a fin structure disposed over a substrate. The fin structure includes a semiconductor oxide layer disposed over the substrate, which has a top surface facing away from the substrate, a first semiconductor material layer disposed over and spaced apart from the semiconductor oxide layer, which has a top surface facing away from the substrate and an opposing bottom surface facing the substrate, and a dielectric sidewall spacer disposed along a sidewall of the semiconductor oxide layer and extending to the first semiconductor material layer. The device also includes a gate dielectric layer disposed over the fin structure and a gate electrode layer disposed over the gate dielectric layer. The gate electrode extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer. | 2016-04-14 |
20160104794 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide semiconductor device includes: a vertical MOSFET having: a semiconductor substrate including a high-concentration impurity layer and a drift layer; a base region; a source region; a trench gate structure; a source electrode; and a drain electrode. The base region has a high-concentration base region and a low-concentration base region having a second conductivity type with an impurity concentration lower than the high-concentration base region, which are stacked each other. Each of the high-concentration base region and the low-concentration base region contacts a side surface of the trench. | 2016-04-14 |
20160104795 | SEMICONDUCTOR DEVICE - A semiconductor device includes a second conductivity type back gate electrode formed within a body area, and electrically connected with the body area, and performs bidirectional current control in a direction from a drain area to a source area and in a direction from the source area to the drain area. A sheet resistance of the back gate electrode is lower than a sheet resistance of the body area. The source area and the back gate electrode are disposed apart from each other with a clearance sufficient for preventing a breakdown phenomenon caused between the source area and the back gate electrode when a maximum operation voltage is applied between the source area and the drain area. | 2016-04-14 |
20160104796 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - In one embodiment, a method of forming a semiconductor device may include forming a buried region within a semiconductor region, including forming an opening in the buried region. The method may also include forming a drift region of a second conductivity type in the semiconductor region with at least a portion of the drift region overlying a first portion of the buried region. Another portion of the method may include forming a first drain region of the second conductivity type in the drift region wherein the first drain region does not overlie the buried region. | 2016-04-14 |
20160104797 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along an extension direction of the trench, the gate segments being connected to neighboring gate segments by means of connection elements. A distance between adjacent gate segments is equal to or smaller than 0.5*L, wherein L denotes a length of each of the gate segments, the length being measured along the extension direction of the trench. | 2016-04-14 |
20160104798 | VERTICAL-CHANNEL SEMICONDUCTOR DEVICE - A vertical-channel semiconductor device having a buried bit line is disclosed. The vertical-channel semiconductor device enables an active pillar including a vertical channel region to be separate from a substrate, couples the active pillar to the substrate using a body-tied structure, and prevents a floating body effect from occurring therein. In addition, the vertical-channel semiconductor device includes an air gap between buried bit lines to reduce parasitic capacitance between the bit lines. | 2016-04-14 |
20160104799 | DUAL-STRAINED NANOWIRE AND FINFET DEVICES WITH DIELECTRIC ISOLATION - A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions. | 2016-04-14 |
20160104800 | Body-Tied, Strained-Channel Multi-Gate Device and Methods of Manufacturing Same - A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials. | 2016-04-14 |
20160104801 | MEMORY DEVICES, METHODS OF MANUFACTURING THE SAME, AND METHODS OF ACCESSING THE SAME - Memory devices, methods of manufacturing the same, and methods of accessing the same are provided. In one embodiment, the memory device may include a substrate, a back gate formed on the substrate, and a transistor. The transistor may include fins formed on opposite sides of the back gate on the substrate and a gate stack formed on the substrate and intersecting the fins. The memory device may further include a back gate dielectric layer formed on side and bottom surfaces of the back gate. The back gate dielectric layer may have a thickness reduced portion at a region facing the fins on one side of the gate stack. | 2016-04-14 |
20160104802 | NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT - According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film. | 2016-04-14 |
20160104803 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a base substrate, a gate pattern, an active pattern and a data metal pattern. The gate pattern includes a gate electrode on the base substrate. The active pattern overlaps the gate electrode and includes a first active layer, a second active layer and a third active layer. The first active layer includes first amorphous silicon (a-Si:H). The second active layer is disposed on the first active layer and includes second amorphous silicon of which a concentration of hydrogen is higher than that of the first amorphous silicon. The third active layer is disposed on the second active layer and includes third amorphous silicon of which a concentration of hydrogen is substantially the same as that of the first amorphous silicon. The data metal pattern is disposed on the active pattern and includes source and drain electrodes spaced apart from each other. | 2016-04-14 |
20160104804 | SELF-ALIGNED THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF - Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern. | 2016-04-14 |
20160104805 | OPTICAL SEMICONDUCTOR DEVICE INCLUDING BLACKENED TARNISHABLE BOND WIRES AND RELATED METHODS - A method for making an optical semiconductor device may include forming an integrated circuit (IC) including an optical sensing area and a bond pads outside the optical sensing area, and coupling proximal ends of respective bond wires to corresponding bond pads. The method may further include performing a blackening treatment on the bond wires. | 2016-04-14 |
20160104806 | HEATED IMAGE SENSOR WINDOW - An image sensor assembly having a sensor window positioned in front of an image sensor, having structure and/or characteristics to prevent the formation of condensation on the sensor window. Structure to prevent the formation of condensation includes thin films which can have anti-condensation, anti-reflective, electrically conductive, and/or thermally conductive properties. The sensor window can further have a textured surface to displace water so as to avoid condensation formation on the window surface. The sensor window, and in some embodiments a frame, can be maintained at an elevated temperature proximate to the image sensor during operation to prevent the formation of condensation. | 2016-04-14 |
20160104807 | SOLAR CELL - A solar cell includes a support substrate; a back electrode layer on the a support substrate; a light absorbing layer on the back electrode layer; a buffer layer on the light absorbing layer; a front electrode layer on the buffer layer; and a fourth through hole formed through the back electrode layer, the light absorbing layer, the buffer layer and the front electrode layer, wherein at least a portion of the fourth through hole is inclined with respect to a top surface of the support substrate. | 2016-04-14 |
20160104808 | METHOD FOR PRODUCING THE P-N JUNCTION OF A THIN-FILM PHOTOVOLTAIC CELL AND CORRESPONDING METHOD FOR PRODUCING A PHOTOVOLTAIC CELL - A method for producing a P-N junction in a thin film photovoltaic cell comprising a deposition step in which are carried out successively: a layer of precursors of a photovoltaic material of type P or N, a barrier layer and a layer of precursors of a semiconducting material of type N or P, this deposition step being followed by an annealing step carried out with a supply of S and/or Se, this annealing step leading to the formation of an absorbing layer of the type P or N and of a buffer layer of type N or P and of a P-N junction at the interface between said layers. | 2016-04-14 |
20160104809 | A BACKSHEET FOR PHOTOVOLTAIC MODULES - A backsheet for a photovoltaic module includes a support and a weather resistant layer, the weather resistant layer including a crosslinking agent, a first binder, and a second binder, each of the first and second binders including a crosslinkable group, wherein the first binder is a fluoropolymer and the second binder is an acrylic resin and the weight ratio of fluoropolymer to acrylic resin is less than 4.0. | 2016-04-14 |
20160104810 | SOLAR CELL MODULE AND METHOD FOR PRODUCING SAME - A solar cell module having low resistance loss between a collector electrode and a connection wiring line, and a method for producing the solar cell module. A solar cell includes a finger electrode portion extending in a predetermined direction, the finger electrode portion being a region in which a collector electrode is disposed, in plan view of a photoelectric conversion section. The finger electrode portion has a stacked structure in which a first conductive layer and a second conductive layer having a lower resistance than the first conductive layer are stacked on the photoelectric conversion section. A wiring member is arranged on the collector electrode in a manner to intersect the finger electrode portion. An intersecting region between the finger electrode portion | 2016-04-14 |
20160104811 | SOLAR CELL AND METHOD OF FABRICATING THE SAME - A solar cell is provided. The solar cell includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer, an anti-reflection layer on the second semiconductor layer, and a negative charge layer between the anti-reflection layer and the second semiconductor layer. | 2016-04-14 |
20160104812 | INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES - A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light-transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light-transparent region, to a circuit on the semiconductor substrate. | 2016-04-14 |
20160104813 | METHOD FOR PROCESSING DEVICES INCLUDING QUANTUM DOTS AND DEVICES - A method of processing quantum dots is disclosed. The method comprises applying energy to excite the quantum dots to emit light and placing the quantum dots under vacuum after excitation of the quantum dots. Also disclosed is a method of processing a component including quantum dots comprising applying energy to the component including quantum dots to excite the quantum dots to emit light; and placing the component including quantum dots under vacuum after excitation. A method for processing a device is further disclosed, the method comprising applying energy to the device to excite the quantum dots to emit light; and placing the device under vacuum after excitation of the quantum dots. A method for preparing a device is also disclosed. Quantum dots, component, and devices of the methods are also disclosed. | 2016-04-14 |
20160104814 | VERTICAL-TYPE SEMICONDUCTOR LIGHT-EMMITTING DEVICE AND METHOD OF FABRICATING THE VERTICAL-TYPE LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes an active layer and a first semiconductor layer sequentially stacked on a second semiconductor layer and including a plurality of contact holes exposing portions of the first semiconductor layer, a plurality of first electrodes on the exposed portions of the first semiconductor layer, a second electrode on the second semiconductor layer adjacent to the contact holes, a first insulating layer on the second electrode in the first region defining at least a portion of the contact holes and insulating the plurality of first electrodes from the active layer and the second semiconductor layer, a first bonding layer on the first insulating layer, filling the contact holes and connected to the first electrodes, a second bonding layer on the second electrode, and a conductive layer including first and second portions contacting a lower surface of the first bonding layer and the second bonding layer, respectively. | 2016-04-14 |
20160104815 | THIN-FILM FLIP-CHIP LIGHT EMITTING DIODE HAVING ROUGHENING SURFACE AND METHOD FOR MANUFACTURING THE SAME - A thin-film flip-chip light emitting diode (LED) having a roughened surface and a method for manufacturing the same are provided. First, a substrate having a patterned structure on a surface of the substrate is provided, and the surface is roughened. A first semiconductor layer is then formed on the surface; a light emitting structure layer is then formed on the first semiconductor layer; a second semiconductor layer is then formed on the light emitting structure layer. The first and second semiconductor layers possess opposite electrical characteristics. A first contact electrode and a second contact electrode are then formed on the first semiconductor layer and the second semiconductor layer, respectively. Finally, a sub-mount is formed on the first and second contact electrodes, and the substrate is removed to form the thin-film flip-chip LED having the roughened surface. Here, the light emitting efficiency of the thin-film flip-chip LED is improved. | 2016-04-14 |
20160104816 | LIGHT EMITTING DEVICE AND METHOD FOR PREPARING THE SAME - Provided are a light-emitting element and a method for preparing same. The method includes a method for growing a p-type semiconductor layer having a low-concentration doping layer, an undoped layer and a high-concentration doping layer. During the growth of the low-concentration doping layer and the high-concentration doping layer, both N | 2016-04-14 |
20160104817 | LED PACKAGE - The present disclosure provides a light emitting diode die which includes a substrate; an N type semiconductor layer, an active layer, and a P type semiconductor layer formed on the substrate in sequence; at least one recess, and a pair of electrodes. The recess extends to the N type semiconductor layer. The insulating layer covers the all of side surfaces of the N type semiconductor layer, the active layer, the P type semiconductor layer, and covers top of the P type semiconductor layer except an opening on the P semiconductor layer. One of the electrodes is filled in the recess and electrically connected to the N type semiconductor layer, and the other one of the electrodes is connected to the P type semiconductor layer in the opening. The present disclosure further provides an LED package having the LED die and a method for manufacturing the same. | 2016-04-14 |
20160104818 | MICRO-LIGHT-EMITTING DIODE - A micro-light-emitting diode (micro-LED) includes a first type semiconductor layer, a second type semiconductor layer, a dielectric layer, and electrodes. The second type semiconductor layer is disposed on or above the first type semiconductor layer. The dielectric layer is disposed on the second type semiconductor layer. The dielectric layer includes openings therein to expose parts of the second type semiconductor layer. The electrodes partially are disposed on the dielectric layer and respectively electrically coupled with the exposed parts of the second type semiconductor layer through the openings of the dielectric layer, in which the electrodes are separated from each other. | 2016-04-14 |
20160104819 | METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP - A method for producing an optoelectronic semiconductor chip comprises the following steps: providing a substrate, depositing a sacrificial layer, depositing a functional semiconductor layer sequence, laterally patterning the functional semiconductor layer sequence, and oxidizing the sacrificial layer in a wet thermal oxidation process. | 2016-04-14 |
20160104820 | LIGHTING EMITTING DEVICE - A light emitting device is disclosed. The light emitting device includes: a light emitting diode emitting light having a peak wavelength in the range of 415 nm to 435 nm; and a wavelength conversion unit disposed on the light emitting diode, wherein the wavelength conversion unit includes cyan phosphors emitting light having a peak wavelength in a cyan light wavelength band and red phosphors emitting light having a peak wavelength in a red light wavelength band, and a ratio of an output of light having a wavelength in the range of 435 nm to 465 nm to a total output of light emitted from the light emitting device is approximately equal to or less than 3%. | 2016-04-14 |
20160104821 | IMAGE DISPLAY MODULE AND IMAGE DISPLAY DEVICE INCLUDING THE SAME - An image display module includes a light emitting device including a nitride semiconductor light-emitting element, as a light source, having an emission peak wavelength in a wavelength range of 240 nm to 560 nm, an Mn | 2016-04-14 |
20160104822 | METHOD FOR THE PRODUCTION OF A WAVELENGTH CONVERSION ELEMENT, WAVELENGTH CONVERSION ELEMENT, AND COMPONENT COMPRISING THE WAVELENGTH CONVERSION ELEMENT - Disclosed is a method for producing a wavelength conversion element ( | 2016-04-14 |
20160104823 | ENGINEERED-PHOSPHOR LED PACKAGES AND RELATED METHODS - In accordance with certain embodiments, a phosphor element at least partially surrounding a light-emitting die is shaped to influence color-temperature divergence. | 2016-04-14 |
20160104824 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a light emitting element, a fluorescent material layer, and an inorganic material layer. The light emitting element has an asperity surface. The fluorescent material layer is provided on the asperity surface. The fluorescent material layer has a glass member and a fluorescent material dispersed in the glass member. The inorganic material layer is provided between the asperity surface and the fluorescent material layer. The inorganic material layer is in contact with the asperity surface and the fluorescent material layer, and transmissive to light emitted from the light emitting element. | 2016-04-14 |
20160104825 | LED PACKAGE, BACKLIGHT UNIT AND LIQUID CRYSTAL DISPLAY DEVICE - Disclosed is a light emitting diode package that includes: a frame having a light emitting diode (LED) thereon; and a glass cell over the LED, the glass cell including a quantum dot dispersed in one of a resin and an organic solvent. | 2016-04-14 |
20160104826 | LIGHT EMITTING PACKAGE HAVING A GUIDING MEMBER GUIDING AN OPTICAL MEMBER - A light emitting package, includes a base; a light emitting device on the base; an electrical circuit layer electrically connected to the light emitting device; an optical member formed of a light transmissive material; and a guiding member guiding the optical member, the guiding member including an opening, a first portion disposed on the uppermost surface of the base, and a second portion connected to an edge portion of the optical member. The first portion of the guiding member is positioned higher than a bottom surface of the optical member, an uppermost surface of the base is closer to the first portion of the guiding member than the second portion of the guiding member, and the edge portion of the optical member is closer to the second portion of the guiding member than the first portion of the guiding member. | 2016-04-14 |