| 15th week of 2011 patent applcation highlights part 10 |
| Patent application number | Title | Published |
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| 20110084698 | STEERABLE MAGNETIC DIPOLE ANTENNA FOR MEASUREMENT WHILE DRILLING APPLICATIONS - A steerable, magnetic dipole antenna for Measurement-While-Drilling (MWD) or Logging-While-Drilling (LWD) applications. The antenna elements use a hole arrangement in addition to grooves in a steel tool body, which is typically a drill collar. This antenna embodiment is extremely robust, meaning that does not significantly reduce the structural integrity of the tool body in which it is disposed. The antenna embodiment is also relatively wear resistant. The resultant magnetic dipole generated by this antenna is also electrically steerable in inclination angle from a common origin. A variable dipole moment inclination angle combined with independently measured tool rotation orientation during normal drilling allows the antenna to generate a magnetic dipole moment that may be directed at any three dimensional angle and from a common origin point at the centroid of the antenna. The antenna can also be embodied to be more sensitive to resitivity in a particular azimuthal direction. | 2011-04-14 |
| 20110084699 | STEERABLE MAGNETIC DIPOLE ANTENNA FOR MEASUREMENT-WHILE-DRILLING APPLICATIONS - A steerable or non-steerable, magnetic dipole antenna for Measurement-While-Drilling (MWD) or Logging-While-Drilling (LWD) applications. The antenna elements use a hole arrangement in addition to grooves in a steel tool body, which is typically a drill collar. This antenna embodiment is extremely robust, meaning that does not significantly reduce the structural integrity of the tool body in which it is disposed. The antenna embodiment is also relatively wear resistant. The resultant magnetic dipole generated by this antenna is also electrically steerable in inclination angle from a common origin. A variable dipole moment inclination angle combined with independently measured tool rotation orientation during normal drilling allows the antenna to generate a magnetic dipole moment that may be directed at any three dimensional angle and from a common origin point at the centroid of the antenna. The antenna can also be embodied to be more sensitive to resistivity in a particular azimuthal direction. | 2011-04-14 |
| 20110084700 | ONE-SHEET TEST DEVICE AND TEST METHOD THEREOF - A one-sheet test device for testing panels on a one-sheet substrate and a test method thereof, wherein the test device and method are capable of performing a one-sheet test regardless of the number of panels formed on the one-sheet substrate. The one-sheet test device includes a signal supplier and a connection board. The signal supplier is for generating a plurality of signal groups and a plurality of dummy signals for testing the panels. The connection board is for transmitting a first signal group of the signal groups to a first panel of the panels corresponding to the first signal group, and for transmitting a signal of at least one signal group of the plurality of signal groups to at least two of the panels when the number of panels is larger than the number signal groups. The one-sheet test device may include a connection controller for controlling the connection board. | 2011-04-14 |
| 20110084701 | TESTING OF LEDS - A method of determining the ageing characteristics of an LED comprises applying a current stress pulse to the LED. The LED is monitored to determine when the thermal heating induced by the current stress pulse has been dissipated to a desired level. The operational characteristics of the LED are then measured before applying the next stressing pulse. | 2011-04-14 |
| 20110084702 | BATTERY PACK AND METHOD FOR DETECTING DEGRADATION OF BATTERY - A buttery pack includes: one or two or more secondary batteries; a charge control switch that turns on/off a charging current to the secondary battery; a discharge control switch that turns on/off a discharging current from the secondary battery; a current-detecting element for detecting the charging current and the discharging current; a voltage measuring part that measures the voltage of the secondary battery; a control unit that controls the charge control switch and the discharge control unit; and a storage unit that stores an initial internal resistance of the secondary battery. The control unit measures a closed circuit voltage and a charging current during charging, and a first closed circuit voltage after a first waiting time and a second closed circuit voltage after a second waiting time. The second waiting time is longer than the first waiting time. | 2011-04-14 |
| 20110084703 | Frequency Extension Methods and Apparatus for Low-Frequency Electronic Instrumentation - An electronic measuring system for extending the effective measurement input frequency range of an electronic measuring instrument includes an electronic measuring instrument and a frequency downconverting subsystem, separate from the electronic measuring instrument, having one or more cascaded (i.e., series-connected) downconverting frequency extending units (FEU-Ds). Each FEU-D of the frequency downconverting subsystem includes a downconverting circuit (e.g., a block downconverter) enclosed within a housing. The frequency downconverting subsystem operates to downconvert a test signal from a device under test (DUT) to a downconverted test signal having a frequency within the permissible input frequency range of the measuring instrument, thereby extending the effective measurement input frequency range of the electronic measuring instrument. | 2011-04-14 |
| 20110084704 | POWER SUPPLY DEVICE AND METHOD FOR MAKING DECISION AS TO CONTACTOR WELD OF POWER SUPPLY DEVICE - A power supply device includes: a power supply; a first contactor and a second contactor that are connected between the power supply and a load; a voltage detection circuit that detects a voltage between a load side of the first contactor and a power supply side of the second contactor; and a control unit that sets the contactors to an open/closed state. In a state in which electrical power has not been supplied to the load, a voltage which is greater than zero and less than a voltage at the power supply is applied between a positive electrode and a negative electrode on the load side; and after controlling the contactors to an open state, the control unit makes a decision as to whether or not one of the contactors is welded based upon detection results of the voltage detection circuit. | 2011-04-14 |
| 20110084705 | INSULATION MEASURING APPARATUS - An insulation measuring apparatus, comprises: a measuring circuit including a first capacitor; a control unit that reads a voltage set on the first capacitor to decide an insulation state of a power supply, and control a path configuration of the measuring circuit; a switching section provided in a path located between the measuring circuit and the control unit; and a second capacitor provided between a ground and a path located between the switching section and the control unit. The control unit controls the path configuration of the measuring circuit, by turning ON the switching section to set a voltage corresponding to the voltage that is set on the first capacitor on the second capacitor, and then by turning OFF the switching section to read the voltage set on the second capacitor and to discharge an electric charge corresponding to the voltage being set on the first capacitor. | 2011-04-14 |
| 20110084706 | ELIMINATING INLINE POSITIONAL ERRORS FOR FOUR-POINT RESISTANCE MEASUREMENT - Calculating resistance correction factors includes contacting the arms of a four-arm probe with a test sample; selecting a first set of first and second arms and a second set of third and fourth arms; applying a first current from the first arm to the second arm of the first set; detecting a first voltage between the third and fourth arms of the second set; calculating a first resistance using the first voltage and current; selecting a third set of first and second arms including no more than one arm of the first set, and a fourth set of third and fourth arms including no more than one arm of the second set; applying a second current from the first arm to the second arm of the third set; detecting a second voltage between the third and fourth arms of the fourth set; calculating a second resistance using the second voltage and current; and calculating a correction factor using the first and second resistances. | 2011-04-14 |
| 20110084707 | OPERATOR IDENTIFYING APPARATUS, OPERATOR IDENTIFYING METHOD AND VEHICLE-MOUNTED APPARATUS - An operator identifying apparatus, operator identifying method, and a vehicle-mounted apparatus. | 2011-04-14 |
| 20110084708 | APPARATUS, DEVICES, SYSTEMS, KITS, AND METHODS OF MONITORING FOOD TREATING MEDIA - An apparatus, system, and method regarding the monitoring of a fluid parameter are disclosed. More particularly, it relates to apparatus, systems, and methods of efficiently and economically monitoring the quality of a fluid, such as food treating media. An improved portable testing device may be in the form of a cartridge that is usable with a separate testing apparatus used to measure a parameter of the fluid carried on the sensing device. Included is a system and method that include a portable handheld device having a sensing device and a filter for protecting the sensing device from the fluid to be tested. | 2011-04-14 |
| 20110084709 | CAPACITIVE PROXIMITY DEVICE AND ELECTRONIC DEVICE COMPRISING THE CAPACITIVE PROXIMITY DEVICE - The invention relates to a capacitive proximity device ( | 2011-04-14 |
| 20110084710 | ENVELOPE MOISTENING DETECTOR - A mailing system includes a mailing machine having an envelope feed path, a sealing system configured to apply a liquid to an envelope in the envelope feed path, a capacitive sensor located in the envelope feed path downstream from the sealing system, and a controller connected to the capacitive sensor. The sealing system may include a liquid reservoir and a liquid applicator. The capacitive sensor is configured to measure a quantity of liquid on a portion of the envelope applied by the sealing system and to generate a signal based on the measured quantity. The controller is configured to perform an operation based on the measured quantity signal from the capacitive sensor. | 2011-04-14 |
| 20110084711 | CAPACITANCE SENSING CIRCUIT WITH ANTI-ELECTROMAGNETIC INTERFERENCE CAPABILITY - The present invention relates to a capacitance sensing circuit with anti-EMI capability. A filter is coupled to a capacitor under test; receives a plurality of reference signals; and produces a first filter signal and a second filter signal. A difference circuit receives the first and second filter signals; eliminates the common-mode noise in the first and second filter signals; and produces a difference signal. The amplitude of the difference signal is related to the capacitance value of the capacitor under test. Thereby, the purpose of sensing capacitance can be achieved. In addition, by eliminating common-mode noise using the difference circuit, the anti-EMI capability can be achieved. Because the difference circuit can adjust the dynamic range of the output of the filter, the capacitance sensing circuit with anti-EMI capability can achieve capacitance sensing in few clock cycles. | 2011-04-14 |
| 20110084712 | CURRENT DIVIDER RESISTANCE IMAGING OF AN ELECTRICAL DEVICE USING AN ATOMIC FORCE PROBE - A method of analyzing an electronic device includes grounding a first end of an electrical structure, grounding a second end of the electrical structure, contacting an atomic force probe (AFP) to the electrical structure between the first and second ends, shifting the AFP across the electrical structure between the first and second ends, measuring an electrical property of the electrical structure at one of the first and second ends, and creating an image of the electrical structure based on the electrical property. | 2011-04-14 |
| 20110084713 | CHLORIDE DETECTION - A high electron mobility transistor (HEMT) capable of performing as a chlorine sensor is disclosed. In one implementation, a silver chloride layer can be provided on a gate region of the HEMT. In one application, the HEMTs can be used for the measurement and detection of chloride in bio-sensing applications. In another application, the HEMTs can be used for the detection of chloride in water for environmental and health applications. | 2011-04-14 |
| 20110084714 | Induced Current Measurement Systems And Methods - In an embodiment, the invention includes a measurement system for measuring induced currents within an implantable medical device undergoing magnetic resonance imaging. The measurement system can include a resistor connected in series with a conductive loop and electronic circuitry configured to generate a signal representative of a voltage differential across the resistor. In some embodiments, the measurement system includes a fiber optic cable configured to transmit the signal away from the area subject to magnetic resonance imaging. In some embodiments, the measurement system includes a transmitter to wirelessly transmit the signal away from the area subject to magnetic resonance imaging. In an embodiment, the invention can include an implantable medical device including a measurement system for measuring induced currents. In an embodiment, the invention can include a method of measuring an induced current in an implantable medical device undergoing magnetic resonance imaging. Other embodiments are described herein. | 2011-04-14 |
| 20110084715 | Resistance Measurement in High Power Apparatus Environments - A measuring device for measuring the resistance of high power apparatuses comprises a current source connect-able to a test object, and means for measuring, wherein the current source is a capacitor. By providing the current source as a capacitor, a light weight device is obtained which can be used essentially continuously without periods of non-use during recharging. | 2011-04-14 |
| 20110084716 | DIAGNOSTIC METHOD FOR OIL-FILLED ELECTRICAL DEVICE, DIAGNOSTIC DEVICE FOR IMPLEMENTING THE DIAGNOSTIC METHOD, AND OIL-FILLED ELECTRICAL DEVICE PROVIDED WITH THE DIAGNOSTIC DEVICE - An object of the invention is to provide a diagnostic method for an oil-filled electrical device that considers a temperature distribution in the oil-filled electrical device and enables accurate diagnosis to be conducted even when the method is applied to diagnosis of an actually operating device, and further provide a method with which such diagnosis of an oil-filled electrical device can be conducted from a component analysis value of an insulating oil in the oil-filled electrical device. The invention is a diagnostic method for an oil-filled electrical device including in an insulating oil a metal part wrapped with insulating paper, and determines that a time when a surface resistivity of a maximum precipitation site where metal sulfide is most precipitated on the insulating paper reaches a preset surface resistivity management value is a time of occurrence of an abnormality. | 2011-04-14 |
| 20110084717 | CORRECTED OPTICAL SPECTRAL RESPONSES FOR PHOTOELECTRIC DEVICES - A system for measuring an optical spectral response of a photoelectric device under test (DUT) includes a spectrally programmable light source including in optically coupled sequence a broadband light source for emitting light, a dispersive element for dispersing light, and a spatial light modulator for controlling an intensity and a spectra of the light to provide a spectrally programmable light beam. A light distributing device having at least one input portion is coupled to receive the spectrally programmable light beam and includes a light distributing structure for distributing the spectrally programmable light beam in a known ratio to a first area and at least a second area. A reference detector having a reference output positioned at the first area, and the DUT is positioned at the second area. Data acquisition electronics and a processor can receive simultaneously generated output signals from the DUT and the reference detector to correct for intensity variation in the spectrally programmable light beam in determining the optical spectral response of the DUT. | 2011-04-14 |
| 20110084718 | Burn-In Testing System - The present invention discloses a burn-in testing system including a burn-in board and a burn-in testing apparatus, the burn-in board including: a first interface component, adapted to connect with the burn-in testing apparatus for signal input and/or output between the burn-in board and the burn-in testing apparatus; and a second interface component, adapted to connect with a device under test for signal input and/or output between the burn-in board and the device, wherein the burn-in testing system further includes a pin matching unit flexibly connected with the burn-in board and adapted to adjust signal connection relationship between the first interface component and the second interface component according to a pin description of the device. By using the invention, burn-in tests of various devices having the same number of pins and different pin descriptions can be performed using the same burn-in board, which is compatible with existing burn-in boards, thereby improving production efficiency and reducing production costs. | 2011-04-14 |
| 20110084719 | TEST FIXTURE FOR PRINTED CIRCUIT BOARD - There is provided a printed circuit board (“PCB”) test fixture comprising a support, an electrical tester, and a pusher. The support is for supporting a PCB being tested in a PCB test position, The electrical tester is positioned with respect to the PCB test position such that, when a PCB is supported by the support in the PCB test position, the electrical tester is disposed in electrical contact with a circuit on the PCB supported by the support in the PCB test position during PCB testing. The pusher is configured for releasable coupling to a plurality of pusher members, such that each one of the plurality of pusher members is configured to co-operate with the pusher so as to become releasably coupled to and uncoupled from the pusher independently of the releasable coupling and uncoupling of at least another one of the plurality of pusher members, and such that an operative plurality of pusher members is provided when each one of the plurality of pusher members is releasably coupled to the pusher, wherein the operative plurality of pusher members is configured for translating, to a PCB which is supported by the PCB support and is disposed in the PCB test position, a force being applied by the pusher so as to effect pressing of a circuit of the PCB against the electrical tester when the PCB is supported on the PCB support and disposed in the PCB test position. | 2011-04-14 |
| 20110084720 | TEST APPARATUS FOR ELECTRONIC DEVICE PACKAGE AND METHOD FOR TESTING ELECTRONIC DEVICE PACKAGE - A test apparatus for an electronic device package is provided, which includes a test socket having a first portion with a recess for receiving an electronic device package having external terminals arranged in a terminal configuration and a second portion. An interchangeable insert board is disposed between the first portion and the second portion and extended on the recess, which includes first contact pads arranged in a first pad configuration compatible with the terminal configuration and facing the recess and second contact pads arranged in a second pad configuration and disposed between the first and the second portions. Trace layers each electrically connects one of the first contact pads to one of the second contact pads. The contact pins each penetrates through the second portion and electrically connects to one of the second pads, wherein the contact pins are arranged in a pin configuration compatible with the second pad configuration. | 2011-04-14 |
| 20110084721 | MANUFACTURING METHOD AND WAFER UNIT FOR TESTING - A manufacturing method of manufacturing a wafer unit for testing includes forming a plurality of test circuits on a circuit wafer, forming a plurality of circuit pads on a predetermined surface of a connecting wafer, forming a plurality of wafer pads on a rear surface of the connection wafer opposing the predetermined surface, forming a plurality of long via holes to electrically connect the plurality of circuit pads and the plurality of wafer pads, and forming the wafer unit for testing, by overlapping the circuit wafer and the connection wafer to electrically connect the plurality of test circuits and the plurality of circuit pads. | 2011-04-14 |
| 20110084722 | Semiconductor device and test method thereof - A semiconductor device includes a plurality of memory chips arranged in a layered manner, each including a substrate and a memory cell array, and a plurality of current paths provided while penetrating through the memory chips. Each of the memory chips includes a test circuit that reads test data from a corresponding one of the memory cell array and outputs a layer test result signal responding to the test data to a different current path for each of the memory chips. | 2011-04-14 |
| 20110084723 | Built-in Line Test Method - A method for testing a line including an input/output pin of a programmable logic circuit, said line including at least one individual line extending from the input/output pin to a peripheral element, said input/output pin being able to be either at a high logic level or at a low logic level opposite to the high logic level. The method includes, between an initial driving instant and a final driving instant, a step for driving the input/output pin in which a driving voltage is applied to the terminals of the input/output pin. The method also includes: from the final driving instant, a step for measuring the level of the input/output pin during which the pin is no longer driven and during which the measured logic level is recorded for the input/output pin at least one measuring instant, and the measured logic level(s) is/are compared, at the (respective) measuring instant(s), with the theoretical logic level(s) at which the input/output pin should be at the (respective) measuring instant(s) in the absence of any line failure, and, when at least one logic level measured at a measuring instant differs from the theoretical logic level at said measuring instant, a line failure is detected. | 2011-04-14 |
| 20110084724 | UNIVERSAL PINOUT FOR BOTH RECEIVER AND TRANSCEIVER WITH LOOPBACK - An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output. | 2011-04-14 |
| 20110084725 | HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL - An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode. | 2011-04-14 |
| 20110084726 | ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS - A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value. | 2011-04-14 |
| 20110084727 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 2011-04-14 |
| 20110084728 | PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS - In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc. | 2011-04-14 |
| 20110084729 | Semiconductor device - One interface chip and a plurality of core chips are electrically connected via a plurality of through silicon vias. A data signal of a driver circuit is input into the core chip via any one of the through silicon vias. An output switching circuit activates any one of tri-state inverters and selects one of the through silicon vias. The tri-state inverters amplify the data signal and transmit it to the through silicon via. Similarly, an input switching circuit activates any one of tri-state inverters. These tri-state inverters also amplify the data signal transmitted from the through silicon via and supply it to the receiver circuit. | 2011-04-14 |
| 20110084730 | TRANSMISSION APPARATUS FOR DIFFERENTIAL COMMUNICATION - A transmission apparatus for differential communication includes a driver bridge circuit and a pair of noise protection circuits. The driver bridge circuit includes four output devices that are independently connected between each of a pair of transmission lines and a power line or a ground line. Each noise protection circuit is provided to a corresponding transmission lines. Each noise protection circuit includes a ground potential detector and an impedance controller. The ground potential detector detects a potential of the corresponding transmission line with respect to the ground line. The impedance controller causes an impedance of the corresponding transmission line with respect to the ground line to become equal to an impedance of the other transmission line with respect to the ground line, when the detected potential becomes outside a predetermined potential range. | 2011-04-14 |
| 20110084731 | LOGIC CIRCUIT AND DISPLAY DEVICE HAVING THE SAME - It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided. | 2011-04-14 |
| 20110084732 | UNIVERSAL CMOS CURRENT-MODE ANALOG FUNCTION SYNTHESIZER - The universal CMOS current-mode analog function synthesizer is based on approximating the required function using its sixth-order Taylor series expansion. These approximations can be implemented by adding the weighted output currents of a number of basic building blocks built around a basic current squarer, and a constant current. The circuit can simultaneously realize thirty-two different mathematical functions and can be easily expanded to accommodate many others. | 2011-04-14 |
| 20110084733 | DRIVING CIRCUIT WITH SLEW-RATE ENHANCEMENT CIRCUIT - A driving auxiliary circuit receiving an input voltage to control an output voltage of an operational amplifier via a first switch and a second switch is provided. A pull-low circuit turns on the first switch, including a first input terminal coupled to a high voltage source providing a high voltage and a first output terminal for controlling the voltage level of the output voltage. The output voltage is charged to be equal to the input voltage when the input voltage exceeds the output voltage. A pull-high circuit turns on the second switch, including a second input terminal coupled to the high voltage source providing the high voltage and a second output terminal for controlling the voltage level of the output voltage. The output voltage is discharged to be equal to the input voltage when the output voltage exceeds the input voltage. | 2011-04-14 |
| 20110084734 | CIRCUIT HAVING SAMPLE AND HOLD FEEDBACK CONTROL AND METHOD - A drive circuit and a method for maintaining an operating state of the drive circuit. The drive circuit includes a capacitor connected to an inverting input terminal of an operational amplifier and to a terminal of a current sensitive load through a switch. The output of the operational amplifier is connected to a switching regulator which has an output terminal connected to another terminal of the current sensitive load. An energy storage element is connected to the inverting input terminal of the operational amplifier. Energy is stored in the energy storage element during a first portion of a PWM pulse which is used during a second portion of the PWM pulse to generate the error signal. A drive signal is generated from the error signal where the drive signal is used to generate a voltage that biases the current source during the second portion of the PWM pulse. | 2011-04-14 |
| 20110084735 | SCART INTERFACE CONTROL CIRCUIT AND VIDEO DEVICE USING THE SAME - A SCART interface control circuit outputs a mode switch signal to a switch signal pin of the SCART interface according to standby, widescreen and normal modes of video signals. The SCART interface control circuit comprises a first voltage circuit, a second voltage circuit, a voltage combination circuit and an amplifier circuit. The first and second voltage circuits output first and second voltage signals according to the video signal modes, respectively. The voltage combination circuit combines the first and second voltage signals into a combination voltage signal. The amplifier circuit amplifies the combination voltage signal so as to output the mode switch signal for indicating the video signal modes. | 2011-04-14 |
| 20110084736 | ARCHITECTURE FOR CONTROLLING CLOCK CHARACTERISTICS - An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. | 2011-04-14 |
| 20110084737 | FREQUENCY RESPONSIVE BUS CODING - A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a measure of a number of logic level transitions relative to a prior signal (“DBI_AC”) provides a measure of control that may be used to compensate for both main and predriver switching noise. | 2011-04-14 |
| 20110084738 | LOW-POWER FREQUENCY DIVIDER AND LOW-POWER PHASE-LOCKED LOOP EQUIPPED THEREWITH - A low power frequency divider and a low power phase locked loop, which consume the least power. The low power frequency divider generates a frequency dividing signal by dividing a frequency of an input signal in a uniform ratio, and includes a phase to voltage converter, a comparator, a phase synchronization circuit, and a reset circuit. The phase to voltage converter generates a phase voltage signal corresponding to phase change of the input signal in response to a reset signal. The comparator generates a comparator signal by comparing the phase voltage signal and a reference phase voltage signal. The phase synchronization circuit generates the frequency dividing signal by matching phases of the input signal and the comparator signal. The reset circuit generates the reset signal in response to the comparator signal or the frequency dividing signal. | 2011-04-14 |
| 20110084739 | Methods and Devices for Generating Trapezoidal Fire Pulses - The present application discloses trapezoidal fire pulse generating methods and devices. According to the devices and methods of the present application, the voltage value of the positive DC control voltage signal, the voltage value of the negative DC control voltage signal, the voltage value of the rise-time DC control voltage signal and a fall-time DC control voltage signal can be determined according to the parameter values of a trapezoidal fire pulse required to be output. Thus, corresponding DC control voltage signals can be generated. Further, the positive DC control voltage signal and the negative DC control voltage signal can be modulated to a square-wave pulse. Then, the rise-time DC control voltage signal, the fall-time DC control voltage signal and the square-wave pulse can be input to a inverse integrator so as to generate a trapezoidal fire pulse. Since there are specific quantitative relations between the rise time and fall time of the trapezoidal fire pulse and the voltage values of the rise-time and fall-time DC control voltage signals, the corresponding rise time and fall time of the trapezoidal fire pulses can be accurately controlled and adjusted so that the output trapezoidal fire pulses can be more stable and accurate. | 2011-04-14 |
| 20110084740 | POWER-ON RESET CIRCUIT - A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases. | 2011-04-14 |
| 20110084741 | FAST-LOCKING BANG-BANG PLL WITH LOW OUPUT JITTER - The present invention relates to a gigitaol phaselocked loop DPLL ( | 2011-04-14 |
| 20110084742 | DYNAMIC CURRENT SUPPLYING PUMP - A pump system that can dynamically increase its current capability includes: a pump circuit, for producing an output voltage; an oscillator, for driving the pump circuit to pump at a particular frequency according to a pump enable signal; a limiter, coupled to both the oscillator and the output voltage fed back from the pump circuit, for generating the pump enable signal to the oscillator according to the output voltage feedback signal; and an edge timer, coupled to both the oscillator and the pump enable signal, for driving the oscillator to operate at an increased frequency according to a threshold parameter of the pump enable signal. | 2011-04-14 |
| 20110084743 | PHASE LOCKED LOOP AND VOLTAGE CONTROLLED OSCILLATOR THEREOF - A phase locked loop (PLL) and a voltage controlled oscillator (VCO) thereof are provided. The VCO includes a ring oscillator circuit and a control circuit. The ring oscillator circuit is used for providing an output clock signal; and the control circuit is coupled to the ring oscillator circuit, and used for receiving an output voltage to respectively provide a first voltage-frequency gain and a second voltage-frequency gain so as to control a frequency of the output clock signal provided by the ring oscillator circuit, wherein the first voltage-frequency gain is larger than the second voltage-frequency gain. | 2011-04-14 |
| 20110084744 | Semiconductor device, adjustment method thereof and data processing system - Read data that are output from core chips are accurately captured into an interface chip. Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that adjusts the period of time required from the reception of the read command to the outputting of the read data from the data output circuit. The interface chip includes a data input circuit that captures read data, and an input timing adjustment circuit that adjusts the timing for the data input circuit to allow the capturing of the read data after issuing the read command. In this manner, a sufficient latch margin for read data on the interface chip side can be secured. | 2011-04-14 |
| 20110084745 | OUTPUT BUFFER WITH SLEW-RATE ENHANCEMENT OUTPUT STAGE - An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage. | 2011-04-14 |
| 20110084746 | EDGE RATE CONTROL - This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal. | 2011-04-14 |
| 20110084747 | VOLTAGE CONVERTING CIRCUIT AND METHOD - A voltage converting circuit for converting an input voltage into an output voltage is disclosed. The voltage converting circuit includes a modulation signal generator, a comparator and a logic unit. The modulation signal generator is configured for generating a pulse width modulation (PWM) signal responsive to a feedback signal corresponding to the output voltage and a load coupled thereto. The comparator is configured for comparing the feedback signal with a reference signal to output a comparing signal. The logic unit is configured for performing a logical conjunction of the PWM signal and the comparing signal to generate a control signal for adjusting an input current corresponding to the input voltage to regulate the output voltage. A method for converting an input voltage into an output voltage is also disclosed herein. | 2011-04-14 |
| 20110084748 | FLIP-FLOP WITH SINGLE CLOCK PHASE AND WITH REDUCED DYNAMIC POWER - A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase. | 2011-04-14 |
| 20110084749 | METHOD AND APPARATUS FOR GENERATING A MODULATED WAVEFORM SIGNAL - A semiconductor device comprising timer logic for generating a first modulated waveform signal, and delay logic, operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic; and provide a second delay in a falling edge of the first modulated waveform generated by the timer logic. The first delay and second delay of the first modulated waveform forms a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal. | 2011-04-14 |
| 20110084750 | MODULATION APPARATUS AND TEST APPARATUS - Provided is a modulation apparatus that outputs an output signal having a designated amplitude and a designated phase, comprising a first variable delay section that outputs a first delayed signal obtained by delaying a periodic signal by a set delay time; a second variable delay section that outputs a second delayed signal obtained by delaying the periodic signal by a set delay time; an adding section that adds together the first delayed signal and the second delayed signal, and outputs the result as the output signal; and a setting section that sets the delay times for the first variable delay section and the second variable delay section according to the designated amplitude and the designated phase. | 2011-04-14 |
| 20110084751 | MULTICHANNEL INTERFACING DEVICE HAVING A BALANCING CIRCUIT - The invention relates to an interfacing device for transmission through interconnections used for sending a plurality of electrical signals. | 2011-04-14 |
| 20110084752 | Systems and Methods for Maintaining a Drive Signal to a Resonant Circuit at a Resonant Frequency - Systems and methods for maintaining a drive signal to a resonant circuit at a resonant frequency are provided. A system for maintaining a drive signal to a resonant circuit at a resonant frequency can include: an oscillator configured to provide an output to a phase comparator and a drive circuit, the drive circuit configured to provide a drive signal to a resonant circuit; a phase detector configured to receive a filtered version of the drive signal from the resonant circuit and provide a phase-indicating signal to the phase comparator; and the phase comparator, wherein the phase comparator is configured to provide a signal based on the phase difference between the oscillator output and the phase-indicating signal, wherein the signal from the phase comparator is used to control the frequency of the oscillator such that the phase difference converges to a fixed value. | 2011-04-14 |
| 20110084753 | ELECTRICAL, CONTROL METHOD, SYSTEM AND APPARATUS - A system for addressing electrical signals is disclosed, comprising an electromagnetically conductive control element, at least one control signal, at least one electromagnetic pulse modulator associated with the control element, and a threshold element positioned proximate to the control element, having an electromagnetic resistance that is conditional and changes as a result of fluctuations in the electromagnetic field of the control element. | 2011-04-14 |
| 20110084754 | CLOCK SIGNAL AMPLIFICATION CIRCUIT, CONTROL METHOD THEREOF, AND CLOCK SIGNAL DISTRIBUTION CIRCUIT - In an exemplary aspect of the invention, a clock signal amplifier circuit includes an amplifier circuit, a first switch part, and a second switch part. The amplifier circuit amplifies a clock signal. The first switch part controls ON/OFF of the amplifier circuit according to a select signal. The second switch part opens and closes complementarily to the first switch part according to the select signal. The amplifier circuit receives a test clock signal used in a test mode operation state through the second switch part. Further, the amplifier circuit outputs a signal generated by amplifying an input signal serving as the clock signal, or the test clock signal, according to the select signal. | 2011-04-14 |
| 20110084755 | ANALOG SWITCH - An analog switch ( | 2011-04-14 |
| 20110084756 | Reduced capacitor charge-pump - Systems and methods to achieve a charge pump for generating from single supply voltage energy efficient supply voltages that are symmetrical around ground voltage have been disclosed. The charge pump requires two flying capacitors only. The charge pump generates positive and negative supply voltages following a 1/N ratio of Vdd voltage, i.e. +−Vdd/N, and can be generalized to generate +/−Vdd/2 | 2011-04-14 |
| 20110084757 | VDD/5 or VDD/6 charge-pump - Systems and methods to achieve a charge pump for generating from single supply voltage energy efficient supply voltages having a value of ±1/6 Vdd, ±1/5 Vdd, ±1/4 Vdd, ±1/3 Vdd, ±1/2 Vdd or ±1 Vdd that are symmetrical around ground voltage have been disclosed. The charge pump requires two flying capacitors only. The charge pump generates positive and negative supply voltages following a 1/N ratio of Vdd voltage, i.e. +−Vdd/N, and can be generalized to generate +/−Vdd/2 | 2011-04-14 |
| 20110084758 | Semiconductor device - To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced. | 2011-04-14 |
| 20110084759 | HIGH IMPEDANCE BIAS NETWORK - This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair. | 2011-04-14 |
| 20110084760 | HIGHLY EFFICIENT CLASS-G AMPLIFIER AND CONTROL METHOD THEREOF - A highly efficient class-G amplifier includes an amplifier circuit coupled between a positive power rail and a negative power rail to amplify an audio input signal of the class-G amplifier, and a boost inverting power converter to convert a supply voltage to a positive rail voltage and a negative rail voltage on the positive and negative power rails. The boost inverting power converter includes a boost inverting power stage coupled to the positive and negative power rails, and a controller to switch the boost inverting power stage between a boost mode and an inverting mode. An audio level detector detects the audio input signal for the controller to adjust the positive and negative rail voltages. The class-G amplifier has higher efficiency and requires lower cost because it does not need a charge pump. | 2011-04-14 |
| 20110084761 | Output Amplifier of Source Driver - An output amplifier includes an amplifier circuit, a driving stage circuit, an output stage circuit, a first unity gain buffer, and a second unity gain buffer. The amplifier circuit provides an inverted signal and a non-inverted signal, in which the amplifier circuit amplifies an input pixel signal to generate the inverted signal and the non-inverted signal. The output stage circuit passes a supply voltage or a ground voltage to the pixel circuit according to the inverted signal and the non-inverted signal. The driving stage circuit passes the supply voltage or the ground voltage to the pixel circuit. The first unity gain buffer enhances and passes the inverted signal from the amplifier circuit to the driving stage circuit. The second unity gain buffer passes and enhances the non-inverted signal from the amplifier circuit to the driving stage circuit. | 2011-04-14 |
| 20110084762 | Envelope Detector for High Speed Applications - An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit. | 2011-04-14 |
| 20110084763 | DB-LINEAR PROCESS-INDEPENDENT VARIABLE GAIN AMPLIFIER - An amplifier is provided with continuously-variable analog control that exhibits a highly linear gain control curve in db/volts, while preserving high dynamic range, low third order distortion, and low noise. This amplifier has a control mechanism that preserves a varied linear or log linear curve over a wide range and is inherently insensitive to process variations thereby allowing more accurate gain control and higher signal fidelity for amplifying high dynamic range signals. | 2011-04-14 |
| 20110084764 | AMPLIFIER AND SIGNAL FILTER - A signal filter circuit, an amplifier circuit, combinations thereof and methods for configuring and using the same are provided. Embodiments of the amplifier circuit may provide precise reproduction and amplification of input signals. The amplifier may be built entirely with discrete components or an integrated circuit may be configured to provide some or all of the modules included in the amplifier. | 2011-04-14 |
| 20110084765 | Three Dimensional Inductor and Transformer - A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip. | 2011-04-14 |
| 20110084766 | WIDEBAND ACTIVE CIRCUIT WITH FEEDBACK STRUCTURE - A broadband active circuit with a feedback structure includes: an active load unit providing a load varied according to a control voltage; an active circuit unit connected between the active load unit and a ground and outputting a signal corresponding to a pre-set bandwidth, among input signals; and a feedback circuit unit formed between an output terminal of the active circuit unit and the active load unit and providing a signal from the output terminal of the active circuit unit to the active load unit. | 2011-04-14 |
| 20110084767 | Active bias control circuit for an amplifier and method of power up sequencing the same - An active bias control circuit for an amplifier includes a low dropout regulator for providing a regulated voltage to provide an input current to the amplifier, and a current sense circuit responsive to the low dropout regulator for sensing a scaled down replica of the input current to the amplifier. An amplifier control circuit adjusts a control voltage to the amplifier in response to the sensed, scaled down replica of the input current to regulate the input current to the amplifier. A method for power up sequencing an amplifier for an active bias control circuit for the amplifier is also disclosed. | 2011-04-14 |
| 20110084768 | Dual reference oscillator phase-lock loop - A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error. | 2011-04-14 |
| 20110084769 | Estimation and Compensation of Oscillator Nonlinearities - A device comprises an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit comprises a frequency control input and is configured to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input. The processor circuit is configured to calculate, on the basis of the first input signal value, the second input signal value, the third input signal value, the first frequency value, the second frequency value, and the third frequency value, a second order coefficient of a polynomial oscillator characteristic relating values of the frequency of the oscillator signal to values of the input signal. | 2011-04-14 |
| 20110084770 | Oscillator - An oscillator is provided. The oscillator comprises a flip-flop module, a first and a second setting module. The first setting module comprises: a first switch device to generates a first switch signal according to a first oscillating signal, an NMOS and an inverter. The NMOS comprises a drain to receive a first charging current and a gate to receive the first switch signal, wherein the drain is charged or discharged according to the first switch signal. The inverter is connected to the drain to generate a first setting signal. The second setting module comprises a second switch device to generate a second switch signal according to a second oscillating signal and a comparator to generate a second setting signal according to the second switch signal and a reference voltage. The flip-flop module generates the first and the second oscillating signal according to the first and the second setting signal. | 2011-04-14 |
| 20110084771 | Low Phase Noise Frequency Synthesizer - Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs. | 2011-04-14 |
| 20110084772 | METHOD FOR SELECTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTION NETWORKS WITH NO INDUCTOR OVERHEAD - An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels. | 2011-04-14 |
| 20110084773 | ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NETWORKS - A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. | 2011-04-14 |
| 20110084774 | ARCHITECTURE FOR OPERATING RESONANT CLOCK NETWORK IN CONVENTIONAL MODE - An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels. | 2011-04-14 |
| 20110084775 | RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE FOR TRACKING PARAMETER VARIATIONS IN CONVENTIONAL CLOCK DISTRIBUTION NETWORKS - A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. | 2011-04-14 |
| 20110084776 | VIBRATING REED, VIBRATOR, OSCILLATOR, AND ELECTRONIC DEVICE - A vibrating reed includes: a base; and a vibrating arm which is extended from one end portion of the base, the vibrating arm having an arm portion which is disposed on the base side, a weight portion which is disposed on a tip side of the arm portion and has a larger width than the arm portion, main surfaces which are respectively disposed on front and back sides of the vibrating arm, side surfaces each of which extends in a longitudinal direction of the vibrating arm to connect the main surfaces on the front and back sides and which are formed so as to face each other, a first groove portion which is a bottomed groove formed at least one of the main surfaces along the longitudinal direction of the vibrating arm, a first excitation electrode which is formed on groove side surfaces each connecting a bottom of the first groove portion with the one main surface, a second excitation electrode which is formed on the both side surfaces, and a projection-in-groove which is disposed on the tip side of a bisector bisecting the vibrating arm in the longitudinal direction and is formed so as to be along the groove side surface with a part of the first groove portion interposed between the projection-in-groove and the groove side surface. | 2011-04-14 |
| 20110084777 | Jumpless Phase Modulation In A Polar Modulation Environment - A circuit includes a phase shifter configured to selectively shift a phase of a baseband phase signal in accordance with a zero crossing signal to output a selectively phase-shifted signal, a phase modulator configured to provide a phase modulated carrier signal in accordance with the selectively phase-shifted signal, and an inverter configured to selectively invert the phase modulated carrier signal in accordance with the zero crossing signal. | 2011-04-14 |
| 20110084778 | ELECTRICAL CIRCUIT SIGNAL CONNECTION SYSTEM - A termination block for connecting a first signal device and a second signal device. The termination block includes a housing, first and second connectors, and an electrical circuit having passive elements that connect the first and second connectors and provide impedance matching. | 2011-04-14 |
| 20110084779 | BULK ACOUSTIC WAVE RESONATOR AND METHOD OF FABRICATING SAME - An acoustic resonator with improved quality factor and electro-mechanical coupling is disclosed. In one embodiment, the acoustic resonator includes an acoustic mirror formed on the top surface of a substrate or in the substrate, a first electrode having a end portion, formed on the acoustic mirror, a piezoelectric layer formed on the first electrode; and a second electrode formed on the piezoelectric layer, where at least one of the first electrode and the second electrode and the piezoelectric layer define an air gap in a region that overlaps the end portion of the first electrode. In one embodiment, a dielectric film is deposited on the surface of the end portion of the first electrode to form completely planarized surface before the piezoelectric layer deposition. In another embodiment, an air gap between the second electrode and the piezoelectric layer, so that the piezoelectric coupling in the end portion area of the first electrode is minimally contributed into the whole resonator. | 2011-04-14 |
| 20110084780 | Transversal Filter - The filter includes at least one acoustic track formed on a piezoelectric substrate. At least one SAW input transducer and at least one SAW output transducer are arranged in each track. Each track has a RSPUDT structure and thus a distributed excitation. The excitation function includes sources arranged in a main lobe and a tail function including at least one tail lobe. A fine and precise approximation to the desired continuous excitation function is obtained by decreasing the excitation strength in the tail function by a factor of at least 2. | 2011-04-14 |
| 20110084781 | Method For Temperature Compensation In MEMS Resonators With Isolated Regions Of Distinct Material - MEMS resonators containing a first material and a second material to tailor the resonator's temperature coefficient of frequency (TCF). The first material has a different Young's modulus temperature coefficient than the second material. In one embodiment, the first material has a negative Young's modulus temperature coefficient and the second material has a positive Young's modulus temperature coefficient. In one such embodiment, the first material is a semiconductor and the second material is a dielectric. In a further embodiment, the quantity and location of the second material in the resonator is tailored to meet the resonator TCF specifications for a particular application. In an embodiment, the second material is isolated to a region of the resonator proximate to a point of maximum stress within the resonator. In a particular embodiment, the resonator includes a first material with a trench containing the second material. | 2011-04-14 |
| 20110084782 | ELECTROMAGNETIC FILTER AND ELECTRONIC DEVICE HAVING SAME - The electromagnetic filter according to the present invention includes a shield opening | 2011-04-14 |
| 20110084783 | WAVEGUIDE FILTER - A waveguide filter comprises a dielectric board on at least one of the two E-planes of a rectangular waveguide. The dielectric board comprises a conductive pattern formed on one surface thereof and having a slit extending in a signal propagation direction, and a ground pattern formed on the other surface. | 2011-04-14 |
| 20110084784 | MULTIPLE TAP ATTENUATOR MICROCHIP DEVICE - A multiple tap attenuator microchip device is disclosed. The device includes a substrate having two or more attenuator taps formed on a surface of the substrate. One or more ground contacts are also formed on the substrate surface and operatively connected to the attenuator taps. The attenuator taps each include a resistive network that is configured to provide a level of attenuation of an rf signal applied to the attenuator tap that is different from the attenuation level provided by the other attenuator tap(s). | 2011-04-14 |
| 20110084785 | CIRCUIT INTERRUPTING DEVICE WITH REVERSE WIRING PROTECTION - Resettable circuit interrupting devices, such as GFCI devices, that include reverse wiring protection, and optionally an independent trip portions and/or a reset lockout portion are provided. The reverse wiring protection operates at both the line and load sides of the device so that in the event line side wiring to the device is improperly connected to the load side, fault protection for the device remains. The trip portion operates independently of a circuit interrupting portion used to break the electrical continuity in one or more conductive paths in the device. The reset lockout portion prevents the reestablishing of electrical continuity in open conductive paths if the circuit interrupting portion is non-operational or if an open neutral condition exists. | 2011-04-14 |
| 20110084786 | ELECTROMAGNETIC SWITCHING DEVICE - A first coil constitutes a first coil unit by placing an iron core plate between the first coil and an auxiliary yokes and engaging stopping parts provided in two holding members to an end surface in an axial direction of the auxiliary yoke. A second coil constitutes a second coil unit by forming magnetic path members by insertion to a resin member provided in a second bobbin unitarily, and fixing two terminals to the resin member. The first and the second coil units are united by connecting one terminal lead line of the first coil taken out from holding members to the first terminal, and connecting another terminal lead line to a surface of the magnetic path member. | 2011-04-14 |
| 20110084787 | PHOTOSENSITIVE RESIN COMPOSITION, METAL-BASE-CONTAINING CIRCUIT BOARD PRODUCTION METHOD EMPLOYING THE PHOTOSENSITIVE RESIN COMPOSITION, AND METAL-BASE-CONTAINING CIRCUIT BOARD - A photosensitive resin composition which is capable of reducing stress occurring due to thermal history, such as a heat treatment, a metal-base-containing circuit board production method which suppresses the warpage of a circuit board by employing the photosensitive resin composition and a metal-base-containing circuit board. The photosensitive resin composition comprises a polyamide acid, a 1,4-dihydropyridine derivative and an amide compound. | 2011-04-14 |
| 20110084788 | Radial and linear magnetic axial alignemt chamber - The invention is a processing component used in electrophoresic conversion of coal fired flue gas carbon dioxide and nitrogen emissions into useful products in lieu of the more costly geosequestration of pollutant by-products produced in the electrical generating and transportation sectors of the economy. Carbon dioxide and facility stack nitrogen imbalance of coal-fired furnace emissions are chemically reacted with electric vehicle fuel cell spent electrolyte in the commercial production of plastic carbon polymers and nitrogen fertilizers. | 2011-04-14 |
| 20110084789 | TRANSFORMER AND TRANSFORMER ASSEMBLY - A transformer includes: a bobbin on which a coil is wound; a core coupled with the bobbin to provide a magnetic flux and installed on the PCB in a penetrating manner; and a base plate electrically connected to the coil and having a lead frame connected to the PCB, wherein the lead frame is formed such that the base plate is separated from an upper surface of the PCB. | 2011-04-14 |
| 20110084790 | NEUTRAL-GROUNDED STRUCTURE FOR DELTA-CONNECTED WINDINGS AND METHOD THEREOF - A neutral-grounded structure and a method for delta-connected windings are provided. The delta-connected windings include a first phase winding, a second phase winding, and a third phase winding. A grounding winding is disposed on at least one of the phase windings. The first end of the grounding winding is connected to a grounded point which is utilized as a neutral point. The second end of the grounding winding is connected to a tap of one of the other two phase windings. The voltage phase displacement between the grounding winding and the phase winding corresponding to the grounding winding is 180 degrees. According to the above-mentioned neutral-grounded structure, all the three phase-to-ground voltages are the same when the three phase voltages are balanced. Accordingly, the present invention can solve correlated problems due to differences of the three phase-to-ground voltages of delta-connected windings with conventional grounding methods. | 2011-04-14 |
| 20110084791 | MULTI-BAND LOW NOISE AMPLIFIER AND MULTI-BAND RADIO FREQUENCY RECEIVER INCLUDING THE SAME - An integrated circuit (IC) includes multiple circuits isolated with respect to one another. Each circuit of the multiple circuits includes an inductor pair formed in a loop pattern on a same layer as at least one other inductor pair from another circuit of the multiple circuits, such that the inductor pair surrounds and is isolated from the at least one other inductor pair. | 2011-04-14 |
| 20110084792 | SIP (Symmetrical-in-Parallel) Induction Coils for Electromagnetic Devices - A SIP (Symmetrical-in-Parallel) induction coil is made of winding two conductive wires symmetrically around a magnetic core and connecting them in parallel (refer to four figures in four pages). Such SIP induction coils can be applied to construct electromagnetic devices which have unique outstanding features of reduced magnetization current, reduced cupper loss, higher power efficiency, lower temperature-rise and reduced size (volume) of the electromagnetic devices. | 2011-04-14 |
| 20110084793 | Tri-Mode Over-Voltage Protection and Disconnect Circuit Apparatus and Method - A single-phase apparatus and method for protecting for all AC power wires/lines and combinations thereof. The present invention prevents (1) the hazardous condition occurring at the wall receptacle, arising from accidental reversal of the line wire with the neutral wire, from adversely affecting at least one peripheral device in the line, and (2) the overheating and destruction of components in an over-voltage protection circuit by providing an efficient circuit configuration which assures a rapid simultaneous disconnect of both the hot line and neutral power lines. | 2011-04-14 |
| 20110084794 | IMMERSION WELL ASSEMBLY - An immersion well assembly may include a thermistor housing defining a first axial passage and a thermistor wire collar axially secured to the thermistor housing and defining a second axial passage. The second axial passage may receive a thermistor wire and may axially fix the thermistor wire relative to the thermistor housing. | 2011-04-14 |
| 20110084795 | Systems and Methods for Dynamically Changing Alerts of Portable Devices Using Brainwave Signals - A method for dynamically adjusting alerts of a portable electronic device is provided. The method may include steps for receiving, from a threshold value associated with an attention level of a user. The method may also include receiving one or more numeric values corresponding to a current mental state of a user from a brainwave sensor. Next, the method may compare the one or more numeric values from the brainwave sensor and the received threshold, and based at least on the comparison, the method may automatically adjust at least one alert of the portable electronic device. | 2011-04-14 |
| 20110084796 | METHOD AND SYSTEM FOR SECURE RFID COMMUNICATION BETWEEN A NOISY READER AND A COMMUNICATING OBJECT - A method for communication between a RFID noisy reader ( | 2011-04-14 |
| 20110084797 | Activity Based Management System - The present invention is directed to management of activities by the operation of keys for performing said activities that are monitored for timing of any activity itself, its duration and frequency in predefined intervals and more particularly to an activity based key monitoring and management system. The present system provides a safe and secured manner of management of activities involving key operation whereby it would be possible to value add to the required authentication and performance of key operative activities in variety of applications and end uses. | 2011-04-14 |
