15th week of 2012 patent applcation highlights part 12 |
Patent application number | Title | Published |
20120085998 | TRANSISTORS AND ELECTRONIC DEVICES INCLUDING THE SAME - Example embodiments disclose transistors and electronic devices including the transistors. A transistor may include a charge blocking layer between a gate insulating layer and a gate. An energy barrier between the gate insulating layer and the gate may be increased by the charge blocking layer. The transistor may be an oxide transistor including a channel layer formed of an oxide semiconductor. | 2012-04-12 |
20120085999 | Transistors, Methods Of Manufacturing The Same, And Electronic Devices Including Transistors - Example embodiments disclose transistors, methods of manufacturing the same, and electronic devices including transistors. An active layer of a transistor may include a plurality of material layers (oxide layers) with different energy band gaps. The active layer may include a channel layer and a photo sensing layer. The photo sensing layer may have a single-layered or multi-layered structure. When the photo sensing layer has a multi-layered structure, the photo sensing layer may include a first material layer and a second material layer that are sequentially stacked on a surface of the channel layer. The first layer and the second layer may be alternately stacked one or more times. | 2012-04-12 |
20120086000 | THIN FILM ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film. | 2012-04-12 |
20120086001 | METHOD FOR PRODUCTION OF ZINC OXIDE SINGLE CRYSTALS - The disclosed subject matter includes a method of producing zinc oxide (ZnO) single crystals in an enclosure. The ZnO single crystals have a low concentration of lithium and hydrogen impurities. | 2012-04-12 |
20120086002 | THERMALLY LABILE PRECURSOR COMPOUNDS FOR IMPROVING THE INTERPARTICULATE CONTACT SITES AND FOR FILLING THE INTERSTICES IN SEMICONDUCTIVE METAL OXIDE PARTICLE LAYERS - The present invention relates to a process for producing a layer comprising at least one semiconductive metal oxide on a substrate, comprising at least the steps of: | 2012-04-12 |
20120086003 | SEMICONDUCTOR DEVICE AND TEST SYSTEM FOR THE SEMICONDUCTOR DEVICE - A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member. | 2012-04-12 |
20120086004 | ELASTIC ENCAPSULATED CARBON NANOTUBE BASED ELECTRICAL CONTACTS - Contacts of an electrical device can be made of carbon nanotube columns. Contact tips can be disposed at ends of the columns. The contact tips can be made of an electrically conductive paste applied to the ends of the columns and cured (e.g., hardened). The paste can be applied, cured, and/or otherwise treated to make the contact tips in desired shapes. The carbon nanotube columns can be encapsulated in an elastic material that can impart the dominant mechanical characteristics, such as spring characteristics, to the contacts. The contacts can be electrically conductive and can be utilized to make pressure-based electrical connections with electrical terminals or other contact structures of another device. | 2012-04-12 |
20120086005 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF - A photoelectric conversion device including a single crystal silicon substrate; a first amorphous silicon layer in contact with a surface (a light-receiving surface) of the single crystal silicon substrate; a first polarity (p-type) impurity diffusion layer in contact with the first amorphous silicon layer; a second amorphous silicon layer in contact with a back surface of the single crystal silicon substrate; and a second polarity (n-type) impurity diffusion layer in contact with the second amorphous silicon layer, in which the first and second polarity impurity diffusion layers are microcrystalline silicon layers formed under a deposition condition where a pressure in a reaction chamber is adjusted to be greater than or equal to 450 Pa and less than or equal to 10000 Pa is provided. | 2012-04-12 |
20120086006 | SEMICONDUCTOR DEVICE - Techniques are provided for obtaining a photoelectric conversion device having a favorable spectral sensitivity characteristic and reduced variation in output current without a contamination substance mixed into a photoelectric conversion layer or a transistor, and for obtaining a highly reliable semiconductor device including a photoelectric conversion device. A semiconductor device may include, over an insulating surface, a first electrode; a second electrode; a color filter between the first electrode and the second electrode; an overcoat layer covering the color filter; and a photoelectric conversion layer over the overcoat layer, where one end portion of the photoelectric conversion layer is in contact with the first electrode, and where an end portion of the color filter lies inside the other end portion of the photoelectric conversion layer. | 2012-04-12 |
20120086007 | PIN STRUCTURES INCLUDING INTRINSIC GALLIUM ARSENIDE, DEVICES INCORPORATING THE SAME, AND RELATED METHODS - Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices. | 2012-04-12 |
20120086008 | FIELD-EFFECT TRANSISTOR, PROCESSES FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE USING THE SAME - Provided is a field-effect transistor which has a high mobility and a low variation of mobility. | 2012-04-12 |
20120086009 | Array Substrate for Fringe Field Switching Mode Liquid Crystal Display Device and Method of Manufacturing the Same - A method of manufacturing an array substrate for an FFS mode LCD device includes forming a gate line and a gate electrode on a substrate, forming a pixel electrode in the pixel region, forming a gate insulating layer on the gate line, the gate electrode and the pixel electrode, forming a data line, a source electrode, a drain electrode, and a semiconductor layer on the gate insulating layer, the data line crossing the gate line to define the pixel region, the semiconductor layer disposed over the gate electrode, the source electrode and the drain electrode spaced apart from each other over the semiconductor layer, the drain electrode overlapping the pixel electrode, forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer including a drain contact hole and a pixel contact hole, and forming a connection pattern and a common electrode on the passivation layer, wherein the common electrode includes bar-shaped first openings in the pixel region, and the connection pattern contacts the drain electrode and the pixel electrode through the drain contact hole and the pixel contact hole, respectively. | 2012-04-12 |
20120086010 | ELECTRONIC IMAGE DETECTION DEVICE - The instant disclosure relates to an electronic image detection device comprising: a plurality of metal electrodes on a first face of an insulating layer; and amorphous silicon regions extending over the insulating layer between the metal electrodes. | 2012-04-12 |
20120086011 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A display panel includes a substrate having a display area and a blank area. The blank area includes at least one of a non-metal line region and a metal-line region. The non-metal line region includes a plurality of insulating patterns and a first conductive pattern layer formed on the substrate. The insulating patterns are isolated from each other by the first conductive pattern layer. The metal-line region includes an insulating multilayer formed on the substrate and a conductive pattern layer formed on the insulating multilayer. Several isolated zones are formed by the conductive pattern layer on the surface of the insulating multilayer. | 2012-04-12 |
20120086012 | LIQUID CRYSTAL DISPLAY DEVICE - A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions. | 2012-04-12 |
20120086013 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor is provided, which comprises at least an active layer, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on the active layer and spaced apart from each other; a channel is defined in the active layer between the source electrode and the drain electrode; edges of the active layer are aligned with outer edges of the source electrode and the drain electrode, the outer edge of the source electrode is an edge of the source electrode opposite to the drain electrode, and the outer edge of the drain electrode is an edge of the drain electrode opposite to the source electrode. Also, a method of manufacturing a thin film transistor is provided. | 2012-04-12 |
20120086014 | Semiconductor Device Having Glue Layer And Supporter - A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials. | 2012-04-12 |
20120086015 | GROUP III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device includes a group III nitride semiconductor supporting base, a GaN based semiconductor region, an active layer, and a GaN semiconductor region. The primary surface of the group III nitride semiconductor supporting base is not any polar plane, and forms a finite angle with a reference plane that is orthogonal to a reference axis extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region, grown on the semipolar primary surface, includes a semiconductor layer of, for example, an n-type GaN based semiconductor doped with silicon. A GaN based semiconductor layer of an oxygen concentration of 5×10 | 2012-04-12 |
20120086016 | GROUP III NITRIDE SEMICONDUCTOR AND GROUP III NITRIDE SEMICONDUCTOR STRUCTURE - There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity. | 2012-04-12 |
20120086017 | HETEROGENEOUS SUBSTRATE, NITRIDE-BASED SEMICONDUCTOR DEVICE USING SAME, AND MANUFACTURING METHOD THEREOF - Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer. | 2012-04-12 |
20120086018 | PACKAGE-ON-PACKAGE PROXIMITY SENSOR MODULE - A package-on-package proximity sensor module including a infrared transmitter package and a infrared receiver package is presented. The proximity sensor module may include a fully-assembled infrared transmitter package and a fully-assembled infrared receiver package disposed on a quad flat pack no-lead (QFN) lead frame molded with an IR cut compound housing. A bottom surface of the QFN lead frame may be etched and covered with the IR cut compound to provide a locking feature between the QFN lead frame and the IR cut compound housing. | 2012-04-12 |
20120086019 | SUBSTRATE FOR DISPLAY PANEL, AND DISPLAY DEVICE - Disclosed is a substrate for display panel that includes, in a pixel, a PIN diode | 2012-04-12 |
20120086020 | Integrated photodetecting device - This invention relates to an integrated photodetecting device. The integrated photodetecting device includes a substrate, a light source layer and a photodetector layer. The photodetector layer and light source layer are epitaxied in a stacked structure. The whole device in this invention is fabricated by epitaxy method during a single process. Therefore, the production cost can be reduced by the omission of alignment process. Besides, the integrated photodetecting device of the invention integrates the light source and photodetector into one chip, hence has the ability of minimization, resulting in the reduction of consumption of samples and test time. The distance between the photodetector layer and targets to be tested can also be largely reduced, making the accuracy and sensitivity largely improved, and the kinds of detectable targets largely increased. Furthermore, the integrated photodetecting device of the invention is a portable device so as to increase the possibility of preventive medicine. | 2012-04-12 |
20120086021 | MULTI-LAYER VARIABLE MICRO STRUCTURE FOR SENSING SUBSTANCE - An optical sensor includes a substrate having an upper surface, a plurality of protrusions on the substrate, wherein each of the plurality of protrusions is defined by a base at the upper surface of the substrate and by one or more sloped surfaces oriented at oblique angles relative to the upper surface, and two or more structural layers in the sloped surfaces. The surfaces of the two or more structural layers can adsorb molecules of a chemical or biological substance. | 2012-04-12 |
20120086022 | Light source with light scattering features, device including light source with light scattering features, and/or methods of making the same - Certain example embodiments of this invention relate to techniques for improving the performance of Lambertian and non-Lambertian light sources. In certain example embodiments, this is accomplished by (1) providing an organic-inorganic hybrid material on LEDs (which in certain example embodiments may be a high index of refraction material), (2) enhancing the light scattering ability of the LEDs (e.g., by fractal embossing, patterning, or the like, and/or by providing randomly dispersed elements thereon), and/or (3) improving performance through advanced cooling techniques. In certain example instances, performance enhancements may include, for example, better color production (e.g., in terms of a high CRI), better light production (e.g., in terms of lumens and non-Lambertian lighting), higher internal and/or external efficiency, etc. | 2012-04-12 |
20120086023 | Insulating glass (IG) or vacuum insulating glass (VIG) unit including light source, and/or methods of making the same - Certain example embodiments of this invention relate to techniques for improving the performance of Lambertian and non-Lambertian light sources. In certain example embodiments, this is accomplished by (1) providing an organic-inorganic hybrid material on LEDs (which in certain example embodiments may be a high index of refraction material), (2) enhancing the light scattering ability of the LEDs (e.g., by fractal embossing, patterning, or the like, and/or by providing randomly dispersed elements thereon), and/or (3) improving performance through advanced cooling techniques. In certain example instances, performance enhancements may include, for example, better color production (e.g., in terms of a high CRI), better light production (e.g., in terms of lumens and non-Lambertian lighting), higher internal and/or external efficiency, etc. | 2012-04-12 |
20120086024 | MULTIPLE CONFIGURATION LIGHT EMITTING DEVICES AND METHODS - Multiple configuration light emitting diode (LED) devices and methods are disclosed wherein LEDs within the device can be selectively configured for use in higher voltage, or variable voltage, applications. Variable arrangements of LEDs can be configured. Arrangements can include one or more LEDs connected in series, parallel, and/or a combination thereof. A surface over which one or more LEDs may be mounted can comprise one or more electrically and/or thermally isolated portions. | 2012-04-12 |
20120086025 | ORGANIC LIGHT-EMITTING DIODE MODULE - An organic light-emitting diode (OLED) module includes a substrate, a bus line, an organic light-emitting device layer, a plurality of conductive elements, and at least one conductive wire. The bus line is configured on the substrate. The organic light-emitting device layer is configured on the substrate and electrically connected to the bus line. The conductive elements are configured on the substrate and electrically connected to the bus line. The conductive wire is configured next to the conductive elements and electrically connected to the conductive elements. | 2012-04-12 |
20120086026 | Optoelectronic Semiconductor Body and Method for the Production Thereof - An optoelectronic semiconductor body comprises a substantially planar semiconductor layer sequence having a first and a second main side, which has an active layer suitable for generating electromagnetic radiation. Furthermore, the semiconductor body comprises at least one trench that severs the active layer of the semiconductor layer sequence and serves for subdividing the active of the semiconductor layer sequence into at least two electrically insulated active partial layers. A first and second connection layer arranged on a second main side serve for making contact with the active partial layers. In this case, the first and second connection layers for making contact with the at least two active partial layers are electrically conductively connected to one another in such a way that the active partial layers form a series circuit. | 2012-04-12 |
20120086027 | GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - A group-III nitride compound semiconductor light-emitting device, a method of manufacturing the group-III nitride compound semiconductor light-emitting device, and a lamp. The method includes the steps of: forming an intermediate layer ( | 2012-04-12 |
20120086028 | Wavelength conversion chip for use with light emitting diodes and method for making same - A wavelength conversion chip is formed by depositing a wavelength conversion material on a substrate to form a layer, removing the resulting wavelength conversion layer from the substrate and then segmenting the wavelength conversion layer into a plurality of wavelength conversion chips. The wavelength conversion material can be annealed by thermal annealing or radiation annealing to increase the wavelength conversion efficiency of the chips or to sinter the wavelength conversion material to form a ceramic material. Optical coatings, vias, light extraction elements, electrical connections or electrical bond pads can be fabricated on the wavelength conversion chips. | 2012-04-12 |
20120086029 | LIGHT-EMITTING DIODE DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) device includes a substrate and an epitaxial layer which is disposed on a surface of the substrate. A depression is disposed to a sidewall of the LED device, and a reflective layer is disposed to on least one portion of the depression. By the reflective layer disposed to the depression of the sidewall of the LED device, the light loss caused by the interface of the substrate and the epitaxial layer can be reduced, the light absorbed by the substrate can be decreased, and the angle of the light exiting from the LED device can be adjusted. A manufacturing method of the LED device is also disclosed. | 2012-04-12 |
20120086030 | Light-emitting element - A light-emitting element includes a semiconductor substrate, a light emitting portion including an active layer, a reflective portion between the semiconductor substrate and the light emitting portion, and a current dispersion layer on the light emitting portion. The reflective portion includes a plurality of pair layers each including a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a thickness T | 2012-04-12 |
20120086031 | LED PACKAGE, AND MOLD AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a light emitting diode (LED) package, which includes a first substrate with electrodes disposed on a top thereof and a second substrate with an LED chip disposed on a top thereof. The LED chip is connected with the electrodes via wires. A first package layer is disposed on the top of the first substrate to cover the wires and electrodes. A fluorescent layer is disposed on the top of the second substrate to cover the LED chip. The present disclosure also provides a mold and a method of manufacturing the LED package. | 2012-04-12 |
20120086032 | SEMICONDUCTOR LIGHT-EMITTING STRUCTURE HAVING LOW THERMAL STRESS - A semiconductor light-emitting structure includes a silicon substrate, a distributed Bragg reflector, a semiconductor structures layer and an epitaxy connecting layer. The silicon substrate has a top surface. The distributed Bragg reflector is formed on the top surface of the silicon substrate. The semiconductor structures layer is configured for emitting light. The epitaxy connecting layer is placed between the distributed Bragg reflector and the semiconductor structures layer. Grooves extend from the semiconductor structures layer through the epitaxy connecting layer and the distributed Bragg reflector to reach the semiconductor structures layer. | 2012-04-12 |
20120086033 | LIGHT EMITTING DEVICE - A lighting emitting device includes a conductive substrate; a first conductive layer formed on the conductive substrate; a second conductive layer formed on the first conductive layer; a second semiconductor layer formed on the second conductive layer; an active layer formed on the second semiconductor layer; a first semiconductor layer being formed on the active layer and including a charge distribution layer; and an insulation layer. | 2012-04-12 |
20120086034 | SOLID-STATE LIGHT EMITTING DEVICES AND SIGNAGE WITH PHOTOLUMINESCENCE WAVELENGTH CONVERSION - A solid-state light emitting device having a solid-state light emitter (LED) operable to generate excitation light and a wavelength conversion component including a mixture of particles of a photoluminescence material and particles of a light reflective material. In operation the phosphor absorbs at least a portion of the excitation light and emits light of a different color. The emission product of the device comprises the combined light generated by the LED and the phosphor. The wavelength conversion component can be light transmissive and comprise a light transmissive substrate on which the mixture of phosphor and reflective materials is provided as a layer or homogeneously distributed throughout the volume of the substrate. Alternatively the wavelength conversion component can be light reflective with the mixture of phosphor and light reflective materials being provided as a layer on the light reflective surface. | 2012-04-12 |
20120086035 | LED Device With A Light Extracting Rough Structure And Manufacturing Methods Thereof - A light emitting diode device includes a substrate, one or more light emitting diode chips on the substrate configured to emit electromagnetic radiation, and a lens configured to encapsulate the light emitting diode chips having a surface with a micro-roughness structure. The micro-roughness structure functions to improve the light extraction of the electromagnetic radiation and to direct the electromagnetic radiation outward from the lens. | 2012-04-12 |
20120086036 | LIGHT EMITTING DEVICE AND LIGTH EMITTING DEVICE PACKAGE - Disclosed are a light emitting device, a method of manufacturing the same and a light emitting device package. The light emitting device of the embodiment includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first and second conductive semiconductor layers; a fluorescent layer on the light emitting structure; and a light extracting structure on the fluorescent layer. The light extracting structure extracts light, which is generated in the light emitting structure and incident into an interfacial surface between the fluorescent layer and the light extracting structure, to an outside of the light emitting structure. | 2012-04-12 |
20120086037 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a substrate; a light-emitting layer formed on the substrate; a transparent electrode layer formed on the light-emitting layer, the transparent electrode layer having a curved surface; and a reflective layer formed on and along the curved surface of the transparent electrode layer such that the curved surface of the transparent electrode layer is transferred so as to reflect the light generated from the light-emitting layer toward the light-emitting layer. | 2012-04-12 |
20120086038 | LIGHT EMITTING DEVICE HAVING A DIELECTRIC LAYER AND A CONDUCTIVE LAYER IN A CAVITY - Disclosed are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure including a second conductive semiconductor layer, an active layer over the second conductive semiconductor layer, and a first conductive semiconductor layer over the active layer, a dielectric layer in a cavity defined by removing a portion of the light emitting structure, and a second electrode layer over the dielectric layer. | 2012-04-12 |
20120086039 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material. | 2012-04-12 |
20120086040 | LIGHT-EMITTING DIODE HAVING A WAVELENGTH CONVERSION MATERIAL LAYER, AND METHOD FOR FABRICATING SAME - Provided is a light-emitting diode having a wavelength conversion material and a method for fabricating the same. The light-emitting diode comprises: a base structure; a light-emitting diode chip arranged on the base structure; and a wavelength conversion material layer arranged on the light-emitting diode chip, such that the area adjacent the upper surface of the light-emitting diode chip is thicker than the area adjacent to the side surface of the light-emitting diode chip. In addition, the method for fabricating a light-emitting diode comprises: a step of arranging the light-emitting diode chip on the base structure; and a step of arranging a wavelength conversion material layer containing a light-transmitting photocurable material on the light-emitting diode chip, such that the area thereof adjacent to the upper surface of the light-emitting diode chip is thicker than the area thereof adjacent to the side surface of the light-emitting diode chip. | 2012-04-12 |
20120086041 | LED PACKAGE - According to one embodiment, an LED package includes a first leadframe, a second leadframe, an anisotropic conductive film, an LED chip, and a resin body. The first leadframe and the second leadframe are mutually separated. The anisotropic conductive film is provided on the first leadframe and the second leadframe. The LED chip is provided on the anisotropic conductive film. The LED chip includes a first terminal and a second terminal provided on a face of the LED chip on the anisotropic conductive film side. The resin body is provided on the anisotropic conductive film to cover the LED chip. The first terminal is connected to the first leadframe via the anisotropic conductive film. The second terminal is connected to the second leadframe via the anisotropic conductive film. | 2012-04-12 |
20120086042 | Light Emitting Device and Method of Manufacturing the Same - A light-emitting device structured so as to increase the amount of light taken out in a certain direction is provided as well as a method of manufacturing this light emitting device. As a result of etching treatment, an upper edge portion of an insulator ( | 2012-04-12 |
20120086043 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM - A light emitting device may be provided that includes a conductive support member; a first conductive layer disposed on the conductive support member; a second conductive layer disposed on the first conductive layer; a light emitting structure including a second semiconductor layer formed on the second conductive layer, an active layer formed on the second semiconductor layer, a first semiconductor layer formed on the active layer and an insulation layer. The first conductive layer includes at least one via penetrating the second conductive layer, the second semiconductor layer and the active layer and projecting into a certain area of the first semiconductor layer. The first semiconductor layer includes an ohmic contact layer formed on or above the conductive via. The insulation layer is formed between the first conductive layer and the second conductive layer and is formed on the side wall of the via. | 2012-04-12 |
20120086044 | LIGHT EMITTING DEVICE AND METHOD OF PRODUCING LIGHT EMITTING DEVICE - There is provided a light emitting device that includes a base wafer that contains silicon, a plurality of seed bodies provided in contact with the base wafer, and a plurality of Group 3-5 compound semiconductors that are each lattice-matched or pseudo-lattice-matched to corresponding seed bodies. In the device, a light emitting element that emits light in response to current supplied thereto is formed in at least one of the plurality of the Group 3-5 compound semiconductors, and a current limiting element that limits the current supplied to the light emitting element is formed in at least one of the plurality of the Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor in which the light emitting element is formed. | 2012-04-12 |
20120086045 | Vertical Semiconductor Device with Thinned Substrate - A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region. | 2012-04-12 |
20120086046 | SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE - A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer. | 2012-04-12 |
20120086047 | Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. | 2012-04-12 |
20120086048 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode. | 2012-04-12 |
20120086049 | E-Mode High Electron Mobility Transistor And Method Of Manufacturing The Same - According to an example embodiment, a high electron mobility transistor (HEMT) includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier structure on the channel layer. The buffer layer includes a 2-dimensional electron gas (2DEG). A polarization of the barrier structure varies in a region corresponding to a gate electrode. The HEMT further includes and the gate electrode, a source electrode, and a drain electrode on the barrier structure. | 2012-04-12 |
20120086050 | Massively Parallel Interconnect Fabric for Complex Semiconductor Devices - An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. | 2012-04-12 |
20120086051 | SEMICONDUCTOR DEVICE WITH (110)-ORIENTED SILICON - A vertical semiconductor device includes a bottom metal layer and a first P-type semiconductor layer overlying the bottom metal layer. The first P-type semiconductor layer is characterized by a surface crystal orientation of (110) and a first conductivity. The first P-type semiconductor layer is heavily doped. The vertical semiconductor device also includes a second P-type semiconductor layer overlying the first P-type semiconductor layer. The second semiconductor layer has a surface crystal orientation of (110) and is characterized by a lower conductivity than the first conductivity. The vertical semiconductor device also has a top metal layer overlying the second P-type semiconductor layer. A current conduction from the top metal layer to the bottom metal layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane. | 2012-04-12 |
20120086052 | HIGH VOLTAGE MOS DEVICE AND METHOD FOR MAKING THE SAME - A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided. | 2012-04-12 |
20120086053 | TRANSISTOR HAVING NOTCHED FIN STRUCTURE AND METHOD OF MAKING THE SAME - A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). | 2012-04-12 |
20120086054 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties. | 2012-04-12 |
20120086055 | DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE - Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of trenches in a pad film to form raised portions. The method further includes depositing a hard mask in the trenches and over the upper pad film. The method further includes forming a plurality of fins including the raised portions and a second plurality of fins including the hard mask deposited in the trenches, each of which are separated by a deep trench. The method further includes removing the hard mask on the plurality of fins including the raised portions and the second plurality of fins resulting in a dual height fin array. The method further includes forming gate electrodes within each deep trench between each fin of the dual height fin array, burying the second plurality of fins and abutting sides of the plurality of fins including the raised portions. The plurality of fins including the raised portions electrically and physically isolate adjacent gate electrode of the gate electrodes. | 2012-04-12 |
20120086056 | Superior Integrity of a High-K Gate Stack by Forming a Controlled Undercut on the Basis of a Wet Chemistry - In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior. | 2012-04-12 |
20120086057 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a gate insulating layer formed over a semiconductor substrate; a first conductive layer pattern for select transistors and memory cells formed on the gate insulating layer; a dielectric layer formed on the first conductive layer pattern; a second conductive layer pattern formed on the dielectric layer on the first conductive layer pattern for the memory cells; and select lines made of material having lower resistance than the second conductive layer pattern and coupled to the first conductive layer pattern for the select transistors. | 2012-04-12 |
20120086058 | TUNNEL FIELD EFFECT TRANSISTOR - A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source. | 2012-04-12 |
20120086059 | ENGINEERING MULTIPLE THRESHOLD VOLTAGES IN AN INTEGRATED CIRCUIT - An integrated circuit and method for forming an integrated circuit. There are at least three field-effect transistors with at least two of the field-effect transistors having the same electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. It is optional for the third field-effect transistor to have an electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. The at least three field-effect transistors are strained to varying amounts so that each of the three field-effect transistors has a threshold voltage, Vt, which is different from the Vt of the two other field-effect transistors. | 2012-04-12 |
20120086060 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region. | 2012-04-12 |
20120086061 | Semiconductor Device - A semiconductor device with a transistor for supplying a current to a pixel comprising an EL element, that can supply an accurate current without the influence of variations even when a small signal current, is provided. A precharge voltage is supplied in advance for the current supply to a pixel and subsequently, the signal writing is completed quickly. The precharge voltage is outputted from a circuit for supplying voltage and current that supplies a current to a current source circuit for supplying a current to the pixel. As the precharge voltage, a gate voltage of a transistor for supplying a current to the current source circuit is supplied to the pixel. Optimum precharge voltage can be supplied in the case where W/L of a transistor in the pixel and W/L of a transistor for supplying current in the circuit for supplying voltage and current are approximately equivalent to each other. | 2012-04-12 |
20120086062 | SWITCHING POWER SUPPLY DEVICE AND A SEMICONDUCTOR INTEGRATED CIRCUIT - In a switching power source which controls a current which flows in an inductor through a switching element which performs a switching operation in response to a PWM signal, and forms an output voltage by a capacitor which is provided in series in the inductor, a booster circuit which is constituted of a bootstrap capacity and a MOSFET is provided between an output node of the switching element and a predetermined voltage terminal. The boosted voltage is used as an operational voltage of a driving circuit of the switching element, another source/drain region and a substrate gate are connected with each other such that when the MOSFET is made to assume an OFF state, and a junction diode between one source/drain region and the substrate gate is inversely directed with respect to the boosted voltage which is formed by the bootstrap capacity. | 2012-04-12 |
20120086063 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a memory cell region and a peripheral circuit region; a bit line extending over the memory cell region and the peripheral circuit region, the bit line including a first portion in the peripheral circuit region; and a sense amplifier in the peripheral circuit region. The sense amplifier includes a transistor having a gate electrode which includes the first portion of the bit line. | 2012-04-12 |
20120086064 | METHOD OF FORMING ENHANCED CAPACITANCE TRENCH CAPACITOR - A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example. | 2012-04-12 |
20120086065 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device having a vertical channel transistor and method of fabricating the same. The semiconductor device includes first and second field effect transistors, wherein a channel region of the first field effect transistor serves as source/drain electrodes of the second field effect transistor, and a channel region of the second field effect transistor serves as source/drain electrodes of the first field effect transistor. | 2012-04-12 |
20120086066 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern. | 2012-04-12 |
20120086067 | SEMICONDUCTOR DEVICE AND STRUCTURE - A device, comprising: a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline, wherein said first layer comprises first transistors, wherein said second layer comprises second transistors, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said first transistors and said second transistors are processed following the same lithography step. | 2012-04-12 |
20120086068 | METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES - A method for forming a semiconductor device and a corresponding device are provided. The method includes forming a floating gate device in a process with dual strain layers, and an etch stop layer. An oxide is formed between the floating gate device and a nitride layer above the floating gate. | 2012-04-12 |
20120086069 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In one embodiment, a nonvolatile semiconductor memory device includes a substrate; a tunnel insulating film on the substrate; a charge storage layer on the tunnel insulating film; a block insulating film on the charge storage layer; a first element isolation insulating film in an element isolation trench in the substrate, having a bottom surface lower than an interface between the substrate and the tunnel insulating film, and having a top surface lower than an interface between the charge storage layer and the block insulating film; a second element isolation insulating film on the first element isolation insulating film, protruding to a top surface of the block insulating film, in contact with a side surface of the block insulating film, and having a higher Si concentration than the block insulating film; and a control gate electrode on the block insulating film and on the second element isolation insulating film. | 2012-04-12 |
20120086070 | FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other. | 2012-04-12 |
20120086071 | STRESS MEMORIZATION PROCESS IMPROVEMENT FOR IMPROVED TECHNOLOGY PERFORMANCE - Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions. | 2012-04-12 |
20120086072 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF MANUFACTURE - A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent. | 2012-04-12 |
20120086073 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant. | 2012-04-12 |
20120086074 | Semiconductor Devices And Methods of Forming The Same - Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench. | 2012-04-12 |
20120086075 | DEVICE WITH ALUMINUM SURFACE PROTECTION - A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer. | 2012-04-12 |
20120086076 | SUPER-JUNCTION SEMICONDUCTOR DEVICE - Provision of a super-junction semiconductor device capable of reducing rises in transient on-resistance at the time of repeated switching operation. A super-junction structure is provided that has a striped parallel surface pattern, where a super-junction stripe and a MOS cell | 2012-04-12 |
20120086077 | FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE - An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage. | 2012-04-12 |
20120086078 | DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE - Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes. | 2012-04-12 |
20120086079 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of a first conductivity type; an insulation layer on the first semiconductor layer; a second semiconductor layer in the insulation layer; an active element in the second semiconductor layer; a first semiconductor region on the first semiconductor layer and of a second conductivity type; a second semiconductor region in the first semiconductor region and of the second conductivity type with a higher impurity concentration than the first semiconductor region; a first conductor in a through hole in the insulation layer and connected to the second semiconductor region; a second conductor above or within the insulation layer, the second conductor surrounding the first conductor such that an outside edge thereof is outside the second semiconductor region; a third conductor connecting the first and second conductors; and a fourth conductor connected to the first semiconductor layer. | 2012-04-12 |
20120086080 | LOW-VOLTAGE STRUCTURE FOR HIGH-VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION - An electrostatic discharge (ESD) protected device may include a substrate, an N+ doped buried layer, an N-type well region and a P-type well region. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may be disposed proximate to a portion of the N+ doped buried layer to form a collector region. The P-type well region may be disposed proximate to remaining portions of the N+ doped buried layer and having at least a P+ doped plate corresponding to a base region and distributed segments of N+ doped plates corresponding to an emitter region. | 2012-04-12 |
20120086081 | SEMICONDUCTOR DEVICE - A semiconductor device includes a thin-film diode ( | 2012-04-12 |
20120086082 | DUAL PORT STATIC RANDOM ACCESS MEMORY CELL LAYOUT - A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions. | 2012-04-12 |
20120086083 | DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE - Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in a pad film and an underlying substrate. The method further includes protecting at least one of the plurality of isolation structures in order to preserve its height. The method further includes removing portions of unprotected isolation structures such that the unprotected isolation structures are of a different height than the at least one of the plurality isolation structures. The method further includes removing the pad film and protection over the at least one of the plurality isolation structures, wherein the at least one of the plurality of isolation structures extends above the underlying substrate. The method further includes forming at least one gate electrode on the substrate, over the remaining isolation structures and abutting sides of the at least one of the plurality of isolation structures. | 2012-04-12 |
20120086084 | SEMICONDUCTOR DEVICE - A semiconductor device comprise a memory cell region and a peripheral circuit region on a semiconductor substrate, and a metal laminating wiring extending over the memory cell region and the peripheral circuit region. The metal laminating wiring is a bit line in the memory cell region, and is a portion of a wiring for the peripheral circuit region connected to the bit line and a portion of a gate electrode connected to the wiring for the peripheral circuit region, in the peripheral circuit region. A height of a bottom surface of the metal laminating wiring disposed in the memory cell region, from an upper surface of the semiconductor substrate is substantially the same as the height of the bottom surface of the metal laminating wiring disposed in the peripheral circuit region, from the upper surface of the semiconductor substrate. | 2012-04-12 |
20120086085 | METHOD OF FABRICATING DUAL HIGH-K METAL GATE FOR MOS DEVICES - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack. | 2012-04-12 |
20120086086 | MEMS DEVICE AND COMPOSITE SUBSTRATE FOR AN MEMS DEVICE - An MEMS device and a composite substrate for an MEMS device are provided. The MEMS device comprises a first silicon structure layer and a second silicon structure layer fixedly connecting to the first silicon structure layer. The first silicon structure layer has a twistable rod and a first plane. The first silicon structure layer has a first crystal direction with a miller index of <100> and a second crystal direction with a miller index of <110>. The first crystal direction and the second crystal direction are both parallel to the first plane. The rod has an axis direction, which is parallel to the first plane and intersected by the second crystal direction. In this manner, the torsional stiffness of the rod can be improved. | 2012-04-12 |
20120086087 | SOI-BASED CMUT DEVICE WITH BURIED ELECTRODES - A muli-layer stacked micro-electro-mechanical (MEMS) device that acts as a capacitive micromachined ultrasonic transducer (CMUT) with a hermetically sealed device cavity formed by a wafer bonding process with semiconductor and insulator layers. The CMUT design uses a doped Si SOI and wafer bonding fabrication method, and is composed of semiconductor layers, insulator layers, and metal layers. Conventional doped silicon may be used for electrode layers. Other suitable semi-conductor materials such as silicon carbide may be used for the electrode layers. The insulator may be silicon oxide, silicon nitride or other suitable dielectric. | 2012-04-12 |
20120086088 | ELECTRONIC COMPONENT - An electronic component includes: a first substrate having a through-hole; a second substrate opposite the first substrate; a sealing member surrounding a sealing space formed between the first substrate and the second substrate; a functional element having at least a part thereof disposed in the sealing space, and a through-electrode filling the through-hole, the through-hole penetrating the first substrate. The sealing member includes an elastic core part on the first substrate. A metal film is on a surface of the core part and is bonded to the second substrate. | 2012-04-12 |
20120086089 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. A particular embodiment includes a magnetic tunnel junction structure above a bottom electrode. The particular embodiment further includes a portion of a diffusion barrier layer adjacent to the magnetic tunnel junction structure. A top of the magnetic tunnel junction structure is connected to a conductive layer. | 2012-04-12 |
20120086090 | METHODS AND APPARATUS FOR PASSIVE ATTACHMENT OF COMPONENTS FOR INTEGRATED CIRCUITS - Methods and apparatus provide a sensor including a component coupled to the leadframe such that the component is an integrated part of the IC package. | 2012-04-12 |
20120086091 | BACKSIDE IMAGE SENSOR - A backside image sensor including an assembly of pixels, each pixel including, in a vertical stack, a photosensitive area and a filtering element topping the photosensitive area on the back surface side, wherein at least two adjacent filtering elements of adjacent pixels are separated by a vertical metal wall extending over at least eighty percent of the height of the filtering elements or over a greater height. | 2012-04-12 |
20120086092 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a substrate in which a plurality of pixels including photoelectric converters are formed, a wiring layer that includes wirings in a plurality of layers formed via an interlayer insulating film in a front surface side of the substrate, a base electrode pad portion that includes a portion of the wirings formed in the wiring layer, an opening that penetrates the substrate from a rear surface side of the substrate and reaches the base electrode pad portion, and an embedded electrode pad layer that is formed so as to be embedded in the opening by electroless plating. | 2012-04-12 |
20120086093 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of pixels formed on a semiconductor substrate and include a photoelectric conversion unit; a color filter on the pixels; an on-chip microlens made of an organic film on the color filter, corresponding to each of the pixels; a first inorganic film formed on a surface of the on-chip microlens and having a higher refraction index than the on-chip microlens; and a second inorganic film formed on a surface of the first inorganic film and having a lower refraction index than the on-chip microlens and the first inorganic film, in which at least the second inorganic film includes a non-lens area at an interface of an adjacent second inorganic film. | 2012-04-12 |
20120086094 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC EQUIPMENT - A solid-state imaging device includes: a substrate; a wiring layer formed on a front side of the substrate in which pixels are formed; a surface electrode pad section formed in the wiring layer; a light-shielding film formed on a rear side of the substrate; a pad section base layer formed in the same layer as the light-shielding film; an on-chip lens layer formed over the light-shielding film and the pad section base layer in a side opposite from the substrate side; a back electrode pad section formed above the on-chip lens layer; a through-hole formed to penetrate the on-chip lens layer, the pad section base layer, and the substrate so as to expose the surface electrode pad section; and a through-electrode layer which is formed in the through-hole and connects the surface electrode pad section and the back electrode pad section. | 2012-04-12 |
20120086095 | Photoelectric Conversion Device and Image Pick-Up Device - A photoelectric conversion device includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, an electrode provided on the insulating layer, a photoelectric conversion film provided on the electrode for converting received light to charges, a line connected between the electrode and the semiconductor substrate, a first planar electrode provided in the insulating layer and connected to the electrode, and a second planar electrode provided in the insulating layer between the first planar electrode and the semiconductor substrate. | 2012-04-12 |
20120086096 | CONDENSER LENS-COUPLED PHOTOCONDUCTIVE ANTENNA DEVICE FOR TERAHERTZ WAVE GENERATION AND DETECTION AND FABRICATING METHOD THEREOF - Provided are a condenser lens-coupled photoconductive antenna device for terahertz wave generation and detection and a fabricating method thereof. A condenser lens-coupled photoconductive antenna device for terahertz wave generation and detection includes a condenser lens, a photoconductive thin film deposited on the condenser lens, and a metal electrode formed on the photoconductive thin film for a photoconductive antenna. In the antenna device, the condenser lens and the photoconductive thin film are coupled to each other. | 2012-04-12 |
20120086097 | FRONT-SIDE ILLUMINATED, BACK-SIDE CONTACT DOUBLE-SIDED PN-JUNCTION PHOTODIODE ARRAYS - The present application is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present application is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate wafers. More specifically the photodiode array of the present application is fabricated such that the PN junctions are located on both the front side and back side surfaces of the array, and wherein the front side PN-junction is in electrical communication with the back side PN-junction. Still more specifically, the present application is a photodiode array aving PN junctions that are electrically connected from the front to back surfaces and which can be operated in a fully depleted mode at low reverse bias. | 2012-04-12 |