15th week of 2014 patent applcation highlights part 35 |
Patent application number | Title | Published |
20140099707 | ANTIBODY POLYPEPTIDES THAT ANTAGONIZE CD40L - Antibody polypeptides that specifically bind human CD40L are provided. The antibody polypeptides do not activate platelets. The antibody polypeptides are useful in the treatment of diseases involving CD40L activation, such as graft-related diseases and autoimmune diseases. The antibody polypeptides may be domain antibodies (dAbs) comprising a single V | 2014-04-10 |
20140099708 | Anti-IL12Rbeta1 Antibodies And Their Use In Treating Autoimmune And Inflammatory Disorders - The present invention relates to antibodies that specifically bind to IL12Rβ1, the non-signal transducing chain of both the heterodimeric IL12 and IL23 receptors. The invention more specifically relates to specific antibodies that are IL12 and IL23 receptor antagonists capable of inhibiting IL12/IL18 induced IFNγ production of blood cells and compositions and methods of use for said antibodies to treat pathological disorders that can be treated by inhibiting IFNγ production, IL12 and/IL23 signaling, such as rheumatoid arthritis, psoriasis or inflammatory bowel diseases or other autoimmune and inflammatory disorders. | 2014-04-10 |
20140099709 | ENGINEERED THREE-DIMENSIONAL CONNECTIVE TISSUE CONSTRUCTS AND METHODS OF MAKING THE SAME - Disclosed are engineered, living, three-dimensional connective tissue constructs comprising connective tissue cells. In some embodiments, the connective tissue cells are derived from multi-potent cells such as mesenchymal stem/stromal cells. In some embodiments, the cells are cohered to one another. In some embodiments, the multi-potent cells have been exposed to one or more differentiation signals to provide a living, three-dimensional connective tissue construct. In some embodiments, the constructs are substantially free of pre-formed scaffold at the time of use. Also disclosed are implants for engraftment, arrays of connective tissue constructs for in vitro experimentation, as well as methods of making the same. | 2014-04-10 |
20140099710 | COMPOSITIONS FOR THE IN VITRO DERIVATION AND CULTURE OF EMBRYONIC STEM (ES) CELL LINES WITH GERMLINE TRANSMISSION CAPABILITY AND FOR THE CULTURE OF ADULT STEM CELLS - The present invention is directed to a method of deriving pluripotent embryonic stem cells from mouse blastocysts or from primordial germ cells from a post-implantation mouse embryo, or of maintaining or growing pluripotent embryonic stem cells from a mouse, or of expanding human hematopoietic stem cells or human hematopoietic precursor cells. The methods include the step of cultivating the stem cells or precursor cells for at least one passage in a culture medium preconditioned by the rabbit fibroblast cell line Rab9 (ATCC catalogue CRL1414) and containing less than 0.1 ng/ml Leukemia Inhibitory Factor (LIF). | 2014-04-10 |
20140099711 | METHODS AND SYSTEMS FOR OPTIMIZING PERFUSION CELL CULTURE SYSTEM - Methods and perfusion culture systems are disclosed. The systems and methods relate to decreasing the starting perfusion rate, resulting in increased residence time of the cells in the bioreactor and the cell retention device, and/or concomitantly increasing the starting bioreactor volume or decreasing the starting cell retention device volume, or both. Other method embodiments include increasing the concentrations of individual components of the tissue culture fluid, and adding a stabilizer of the degradation of the recombinant protein. | 2014-04-10 |
20140099712 | Methods and Compositions for Targeting Progenitor Cell Lines - The invention provides methods, compositions and kits for the identification and enrichment of progenitor cell lines obtained from pluripotent stem cells. | 2014-04-10 |
20140099713 | METHODS AND COMPOSITIONS FOR FEEDER-FREE PLURIPOTENT STEM CELL MEDIA CONTAINING HUMAN SERUM - The present invention provides compositions and methods for the culture and maintenance of pluripotent stem cells. More particularly, the present invention provides for compositions and methods for culturing, maintaining, growing and stabilizing primate pluripotent stem cells in a feeder-free defined media further comprising human serum, or a soluble attachment component of the human serum, for promoting cell attachment. | 2014-04-10 |
20140099714 | NATURAL KILLER CELL LINES AND METHODS OF USE - This invention relates to a natural killer cell line termed NK-92. The invention provides a vector for transfecting a mammalian cell which includes a nucleic acid sequence encoding a cytokine that promotes the growth of NK-92. Additionally, the invention provides an NK-92 cell, or an NK-92 cell modified by transfection with a vector conferring advantageous properties, which is unable to proliferate and which preserves effective cytotoxic activity. The invention further provides a modified NK-92 cell that is transfected with a vector encoding a cytokine that promotes the growth of NK-92 cells. The cell secretes the cytokine upon being cultured under conditions that promote cytokine secretion, and furthermore secretes the cytokine in vivo upon being introduced into a mammal. In a significant embodiment, the cytokine is interleukin 2. The present invention also provides methods of purging cancer cells from a biological sample, of treating a cancer ex vivo in a mammal, and of treating a cancer in vivo in a mammal employing a natural killer cell, such as NK-92 itself, an NK-92 cell which is unable to proliferate and which preserves effective cytotoxic activity, or natural killer cells transfected with a vector encoding a cytokine. | 2014-04-10 |
20140099715 | HIGH POTENCY SIRNAS FOR REDUCING THE EXPRESSION OF TARGET GENES - The present invention provides improved methods of attenuating gene expression through the phenomenon of RNA interference. The invention provides methods of synthesis of double stranded RNAs (dsRNAs) of increased potency for use as small interfering RNA (siRNA). Surprisingly and unexpectedly, siRNAs made by the methods of the invention are significantly more potent than previously available siRNAs. | 2014-04-10 |
20140099716 | MONOCLONAL ANTIBODY CAPABLE OF BINDING INTEGRIN ALPHA 10 BETA 1 - The present invention provides a monoclonal antibody or a fragment thereof binding to the extracellular I-domain of integrin alpha10beta1 and a hybridoma cell line deposited at the Deutsche Sammlung von Microorganismen and Zellkulturen GmbH under the accession number DSM ACC2583. Furthermore, the present invention also provides a monoclonal antibody or a fragment thereof binding to the extracellular I-domain of integrin alpha10beta1 produced by the hybridoma cell line deposited. Methods and uses of said antibody or a fragment thereof in identifying and selecting cells of a chondrogenic nature for treatment purposes, in particular for the identification and isolation of chondrocytes, mesenchymal progenitor cells and embryonic stem cells for tissue engineering of cartilage, or for identifying diagnostic and therapeutic tools in studying the biological role and the structural/functional relationships of the integrin alpha10beta1 with its various extracellular matrix ligands are also included. | 2014-04-10 |
20140099717 | ENHANCED OXYGEN CELL CULTURE PLATFORMS - Provided is a cell culture apparatus for culturing cells, that provides enhanced oxygen delivery and supply to cells without the need for stirring or sparging. Oxygen diffusion occurs on both sides of the culture vessel, top and bottom. A gas-permeable membrane that includes perfluorocarbons or fluorocarbon derivatives (e.g., fluorinated silane, partially fluorinated silane) in its composition allows for the rapid, enhanced and uniform transfer of oxygen between the environment of cells or tissues contained in the cell culture container apparatus and the atmosphere of the incubator in which the cell culture apparatus is incubated. | 2014-04-10 |
20140099718 | SINGLE-CRYSTAL APATITE NANOWIRES SHEATHED IN GRAPHITIC SHELLS AND SYNTHESIS METHOD THEREOF - Heterogeneous nanowires having a core-shell structure consisting of single-crystal apatite as the core and graphitic layers as the shell and a synthesis method thereof are provided. More specifically, provided is a method capable of producing large amounts of heterogeneous nanowires, composed of graphitic shells and apatite cores, in a reproducible manner, by preparing a substrate including an element corresponding to X of X | 2014-04-10 |
20140099719 | METHOD FOR PRODUCING YEAST EXPRESSED HPV TYPES 6 AND 16 CAPSID PROTEINS - Mosaic VLPs of viral capsid proteins from different virus types are described, as are methods of making the same. Specifically, a diploid yeast strain that coexpresses the L1 and L2 capsid proteins of both HPV-6 and HPV-16 as mosaic VLPs is described. The mosaic VLPs induced the production of conformational antibodies against both L1 proteins upon administration to mice. | 2014-04-10 |
20140099720 | MICROORGANISM EXPRESSING XYLOSE ISOMERASE - The present invention relates to a transformed microorganism capable of (a) a higher xylose isomerase activity than the equivalent microorganism prior to transformation; and/or (b) a higher growth rate in or on a growth medium comprising xylose than the equivalent microorganism prior to transformation; and/or (c) a faster metabolism of xylose than the equivalent microorganism prior to transformation; and/or (d) a higher production of ethanol when grown anaerobically on xylose as the carbon source than the equivalent microorganism prior to transformation. | 2014-04-10 |
20140099721 | FILAMENTOUS FUNGI HAVING AN ALTERED VISCOSITY PHENOTYPE - Described are compositions and methods relating to variant filamentous fungi having altered growth characteristics. Such variants are well-suited for growth in submerged cultures, e.g., for the large-scale production of enzymes and other proteins for commercial applications. | 2014-04-10 |
20140099722 | FLOW-RATE CONTROL IN A MICROFLUIDIC DEVICE - A method for controlling a flow-rate of fluid flowing in a microfluidic network comprising a microchannel and a plurality of inlet/outlet interface ports is disclosed. The method includes: successively applying a plurality of pressures on at least one inlet/outlet interface port, measuring a time series of flow-rate values of the fluid generated in response to the plurality of applied pressures, estimating parameters of a model of the microfluidic network response to input pressure values based on the applied pressure values and the measured time series of output flow-rate values, computing a target pressure value at each of the inlet/outlet interface ports corresponding to a predetermined flow-rate value at the flow-rate measuring point, wherein the predetermined flow-rate value corresponds to an output value of the model of the microfluidic network response to the target pressure value, and applying the computed target pressure value on the at least one inlet/outlet interface port. | 2014-04-10 |
20140099723 | DETERIORATION ANALYSIS METHOD AND CHEMICAL STATE MEASUREMENT METHOD - The present invention provides a deterioration analysis method capable of analyzing in detail deterioration of a polymer material, and in particular deterioration in the surface condition of a polymer material with low conductivity. The present invention relates to a deterioration analysis method including irradiating a polymer material with a metal coating having a thickness of 100 Å or less formed thereon, with high intensity X-rays, and measuring X-ray absorption while varying the energy of the X-rays, to analyze deterioration of the polymer. | 2014-04-10 |
20140099724 | FLUORESCENT DETECTION OF IN VITRO TRANSLATED PROTEIN ON A SOLID SURFACE - Disclosed herein are methods and kits useful in the detection of protein folding and in the identification of compounds that promote proper protein folding. In one example approach, fluorophores and a protein tag are incorporated into a nascent polypeptide within a ribosome-nascent-chain complex during cell free translation and the resulting labeled ribosome-nascent-chain complex is conjugated to a solid surface via the tag. Fluorescence imaging via FRET is then preformed to assess the folding state of the ribosome-nascent-chain complex under a variety of conditions. | 2014-04-10 |
20140099725 | METHODS FOR THE ANALYSIS OF GLYCOPROTEINS OR GLYCOPEPTIDES BY MASS SPECTROMETRY - A method for the analysis of samples including one or more glycopeptides including the steps of separating one or more glycopeptides using a chromatography system to produce a chromatographic eluent, adding a supercharging reagent to the chromatographic eluent, providing the chromatographic eluent and supercharging reagent to a mass spectrometer, ionizing said chromatographic eluent and supercharging reagent in an ion source to produce glycopeptide ions, performing at least one ion ion reaction on at least some of the glycopeptide ions to produce fragment ions, mass analyzing the fragment ions to produce ion ion reaction mass spectral data, and interpreting the ion ion reaction data mass spectral data to provide structural information relating to the glycopeptide. | 2014-04-10 |
20140099726 | DEVICE FOR CHARACTERIZING POLYMERS - Provided is a device comprising (a) a plurality of chambers, each chamber in communication with an adjacent chamber through at least one pore wherein the device contains at least two pores defined as a first and a second pores, (b) means to move at least a portion of the polymer out of the first pore and into the second pore and (c) at least one sensor capable of identifying individual components of the polymer during movement of the polymer through the first and second pores, provided that when only a single sensor is employed, the single sensor does not include two electrodes placed at both ends of a pore to measure an ionic current across the pore. Methods of using the device are also provided. | 2014-04-10 |
20140099727 | Method and apparatus for determination of haloacetic acid ("HAA") presence in aqueous solution - Techniques related to printing using a metal-surface charging element. A printing system includes a metal-surface charging element and a power supply. The charging element is disposed to deposit electric charge on an imaging surface. The power supply may provide electric power with an alternating current (AC) component and a direct current (DC) component to the charging element. | 2014-04-10 |
20140099728 | Oil life measurement - Rotatable bomb device having a stationary hollow housing and a rotatable component inside the housing provides for very good temperature calibration, temperature recording and, when desired, sample control. The device can have at least one of an insulating lower disc or washer; a plurality of staggered heating bands encompassing a stationary housing; a dry scan port; a rear upper and/or lower port; and an extraction/injection fitting for access to the interior of the stationary housing. The device may be used to react or attempt to react substance(s), for example, generally as in ASTM Method D2272 testing of turbine oil. | 2014-04-10 |
20140099729 | Methods and Apparatus for Artificial Olfaction - In exemplary implementations of this invention, an electronic olfactor determines whether a scent being tested matches the scent of a positive control. The electronic olfactor can perform this scent matching even in a changing olfactory environment, and even if the positive control scent is a combination of hundreds or thousands of different odorants. No prior training is needed, and no attempt is made to identify a single odorant that is unambiguously responsible for a scent. Instead, a computer compares the total scent pattern of a positive control sample with the total scent pattern of a test sample, across a sweep of many permutations of electrical inputs to scent sensors, to try to find any condition under which the total scent patterns do not match. If such a condition cannot be found, then the computer declares a match between the test and target scents. | 2014-04-10 |
20140099730 | MAGIC ANGLE SPINNING NUCLEAR MAGNETIC RESONANCE APPARATUS AND PROCESS FOR HIGH-RESOLUTION IN SITU INVESTIGATIONS - A continuous-flow (CF) magic angle sample spinning (CF-MAS) NMR rotor and probe are described for investigating reaction dynamics, stable intermediates/transition states, and mechanisms of catalytic reactions in situ. The rotor includes a sample chamber of a flow-through design with a large sample volume that delivers a flow of reactants through a catalyst bed contained within the sample cell allowing in-situ investigations of reactants and products. Flow through the sample chamber improves diffusion of reactants and products through the catalyst. The large volume of the sample chamber enhances sensitivity permitting in situ | 2014-04-10 |
20140099731 | Assays - A method for assaying a sample for each of multiple analytes is described. The method includes contacting an array of spaced-apart test zones with a liquid sample (e.g., whole blood). The test zones disposed within a channel of a microfluidic device. The channel is defined by at least one flexible wall and a second wall which may or may not be flexible. Each test zone comprising a probe compound specific for a respective target analyte. The microfluidic device is compressed to reduce the thickness of the channel, which is the distance between the inner surfaces of the walls within the channel. The presence of each analyte is determined by optically detecting an interaction at each of multiple test zones for which the distance between the inner surfaces at the corresponding location is reduced. The interaction at each test zone is indicative of the presence in the sample of a target analyte. | 2014-04-10 |
20140099732 | OPTICAL SENSOR FOR ANALYTE DETECTION - Devices, systems, and methods for detection of an analyte in a sample are disclosed. In some embodiments, an optical sensor can include a metallic layer and a plurality of dielectric pillars extending through the metallic layer. A plurality of regions of concentrated light can be supported in proximity to the ends of the plurality of dielectric pillars when a surface of the metallic layer is illuminated. Concentrated light within one or more of these regions can interact with an analyte molecule, allowing for detection of the analyte. | 2014-04-10 |
20140099733 | Methods of Detecting Antibodies Specific for Denatured HLA Antigents - The invention is directed to methods of screening for HLA antibodies comprising detecting antibodies specific for native HLA antigens and denatured HLA antigens. The invention also provides for methods of removing antibodies specific for denatured HLA antigens or antibodies specific for native HLA antigens from a serum sample. In addition, the invention also provides for method of predicting whether a transplant recipient has an increased risk for rejecting the transplanted organ. | 2014-04-10 |
20140099734 | DEPOSITION METHOD AND DEPOSITION APPARATUS - Disclosed is a method for depositing an insulating film with a high coverage through a low temperature process. The deposition method deposits an insulating film on a substrate using a deposition apparatus which includes a processing container that defines a processing space in which plasma is generated, a gas supply unit configured to supply a gas into the processing space, and a plasma generating unit configured to generate plasma by supplying microwave into the processing container. The deposition method includes depositing an insulating film that includes SiN on the substrate by supplying into a gas formed by adding H | 2014-04-10 |
20140099735 | Structure and Method to Fabricate High Performance MTJ Devices for Spin-Transfer Torque (STT)-RAM Application - A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation and containing an oxygen surfactant layer to form a more uniform MgO layer and lower breakdown distribution percent. A CoFeB/NCC/CoFeB composite free layer with a middle nanocurrent channel layer minimizes Jc | 2014-04-10 |
20140099736 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display device includes an array substrate and a color filter substrate, a plurality of gate lines and a plurality of data lines formed on the array substrate such that the gate lines and the data lines intersect each other to define a plurality of pixel regions, a plurality of thin film transistors formed at respective intersections of the gate lines and the data lines, a liquid crystal layer interposed between the array and color filter substrates, and a plurality of repair patterns formed on the first substrate. Each of the plurality of the repair patterns crosses a corresponding one of the data lines, and is along and adjacent to a corresponding one of the gate lines, such that the repair pattern includes protruding ends that protrude from the corresponding data line to repair a defect on the pixel regions. | 2014-04-10 |
20140099737 | Method for Monitoring Contact Hole Etching Process of TFT Substrate - The present invention provides a method for monitoring a contact hole etching process of a TFT substrate, which includes: ( | 2014-04-10 |
20140099738 | LASER IRRADIATION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS USING THE SAME - A laser irradiation apparatus including a chamber configured to receive a panel including an organic layer on a substrate, a laser oscillator outside the chamber, and configured to irradiate a laser beam onto the panel in the chamber, and a transparent window at a side of the chamber, and configured to allow the laser beam to pass therethrough, wherein the laser beam is configured to remove at least a portion of the organic layer on the substrate. | 2014-04-10 |
20140099739 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE CHIP WITH ELECTRODES HAVING SMOOTH SURFACES - A method for manufacturing a light emitting diode chip includes the following steps: providing an epitaxial structure having an epitaxial layer; forming a first electrode and a second electrode on the epitaxial layer; coating an inert layer on the epitaxial structure, the first electrode and the second electrode continuously; annealing the first electrode and the second electrode; and removing the inert layer coated on the first electrode and the second electrode to expose the first electrode and the second electrode. | 2014-04-10 |
20140099740 | DEPOSITING APPARATUS AND METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY USING THE SAME - A deposition apparatus includes a deposition source that receives a deposition material, and a plurality of spray nozzles arranged in a first direction at one side of the deposition source to spray the deposition material to a facing substrate. The deposition source includes a center area and outer areas, the outer areas being at respective ends of the center area with reference to the first direction. The spray nozzles include first spray nozzles arranged in each outer area and extending outwardly from the deposition source, a surface forming an end of the first spray nozzles forming a first inclination angle with a substrate surface in the first direction. | 2014-04-10 |
20140099741 | Insulating Pattern, Method of Forming the Insulating Pattern, Light-Emitting Device, Method of Manufacturing the Light-Emitting Device, and Lighting Device - A simple formation method of an insulating pattern having an eaves portion using one light-exposure mask is provided. As the formation method of an insulating pattern having an eaves portion, first, a first photosensitive organic layer is formed over a substrate, and then a first region is exposed to light with the use of a light-exposure mask, so that a leg portion is formed. After that, a second photosensitive organic layer is formed, the light-exposure mask is moved in the direction parallel to the substrate, and then a second region partly overlapping with the first region is exposed to light plural times, so that a stage portion is formed. The insulating pattern formed by this method may be applied to the light-emitting device or the lighting device. | 2014-04-10 |
20140099742 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed. | 2014-04-10 |
20140099743 | FLEXIBLE DISPLAY DEVICE MANUFACTURING METHOD - A flexible display device manufacturing method includes preparing a substrate assembly in which a flexible substrate is formed on a carrier substrate; piling up a plurality of the prepared substrate assemblies in a heating furnace in multi-stages; performing heat treatment by providing hot blast onto each of the piled substrate assemblies in a horizontal direction; forming a display unit on the flexible substrate of the heat-treated substrate assembly; and separating the flexible substrate and the carrier substrate from each other. According to the above-described manufacturing method, since warpage of a flexible substrate after a carrier substrate and the flexible substrate are separated from each other may be suppressed, a subsequent process may be appropriately performed, productivity may be improved, and damage of products caused while the flexible substrate is handled may be reduced. | 2014-04-10 |
20140099744 | INTERCONNECTION METHOD FOR A MICRO-IMAGING DEVICE - A method for producing an opto-microelectronic micro-imaging device includes a step of forming a first functional part on the base of a first substrate, a base layer, and first electric connection pad. The first functional part is transferred onto a second substrate. The first substrate is thinned until the base layer is reached. A second functional part is formed on the base layer. One via is connected to the first electric connection pad and through the first functional part. The step of forming the second functional part includes connecting the via with the second electric connection pad. | 2014-04-10 |
20140099745 | SILICON-BASED VISIBLE AND NEAR-INFRARED OPTOELECTRIC DEVICES - In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1. A/W for longer wavelengths, e.g., up to about 3.5 microns. | 2014-04-10 |
20140099746 | METHOD OF MANUFACTURING SOLAR CELL MODULE - A method of manufacturing a solar cell module includes pressing a first silicone gel sheet provided on a sunlight receiving surface and a second silicone gel sheet provided on an opposite side sunlight non-receiving surface in vacuum to encapsulate the solar cell string with the first and second silicone gel sheets; disposing the sunlight receiving side of the first silicone gel sheet on one surface of a transparent light receiving panel and disposing butyl rubber in a picture frame-like shape along an outer peripheral portion of the first silicone gel sheet and laying the light receiving panel and the light non-receiving panel or back sheet over each other with the silicone gel sheet-encapsulated solar cell string on the inside, and pressing them at 100 to 150° C. in vacuum to press bond the light receiving panel and the non-receiving panel to each other through the butyl rubber. | 2014-04-10 |
20140099747 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate and a first insulating layer. The first insulating layer includes a first lower layer and a first upper layer on the first lower layer. The first insulating layer has a first opening through the first lower layer and the first upper layer. A maximum width of the first opening at the first lower layer is different from a maximum width of the first opening at the first upper layer. | 2014-04-10 |
20140099748 | HYBRID MULTI-JUNCTION PHOTOVOLTAIC CELLS AND ASSOCIATED METHODS - A multi-junction photovoltaic cell includes a substrate and a back contact layer formed on the substrate. A low bandgap Group IB-IIIB-VIB | 2014-04-10 |
20140099749 | METHOD FOR MANUFACTURING ABSORBER LAYER OF THIN FILM SOLAR CELL - A method for manufacturing an absorber layer of thin film solar cells is revealed. Firstly vapors of different metal-organic sources are generated in a plurality of containers used for mounting different metal-organic sources. Then the vapors of the metal-organic sources are mixed with a carrier gas and are filled into a reaction together with a reaction gas chamber through pipelines. Next the metals and the compounds are deposited on a substrate in the reaction chamber to form an absorber layer of a thin film solar cell. A flow rate of each metalorganic vapors filled into the reaction chamber is controlled by a mass flow controller respectively. | 2014-04-10 |
20140099750 | SOLUTION CONTAINMENT DURING BUFFER LAYER DEPOSITION - Improved methods and apparatus for forming thin-film layers of chalcogenide on a substrate web. Solutions containing the reactants for the chalcogenide layer may be contained substantially to the front surface of the web, controlling the boundaries of the reaction and avoiding undesired deposition of chalcogenide upon the back side of the web. | 2014-04-10 |
20140099751 | METHOD FOR FORMING DOPING REGION AND METHOD FOR FORMING MOS - The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS. | 2014-04-10 |
20140099752 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer. By fourth heat treatment, hydrogen is supplied at least to an interface between the second oxide semiconductor layer and the oxide insulating layer. | 2014-04-10 |
20140099753 | TECHNIQUES FOR PACKAGING MULTIPLE DEVICE COMPONENTS - Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dice coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package. | 2014-04-10 |
20140099754 | COMPLIANT INTERCONNECTS IN WAFERS - A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit. | 2014-04-10 |
20140099755 | FABRICATION METHOD OF STACKED PACKAGE STRUCTURE - A fabrication method of a stacked package structure is provided, which includes the steps of: providing a substrate having at least a semiconductor device disposed thereon; and disposing a semiconductor package on the substrate through a plurality of conductive elements such that the semiconductor device is located between the substrate and the semiconductor package, and forming an encapsulant between the substrate and the semiconductor package to encapsulate the semiconductor device. The encapsulant can be formed on the semiconductor package first and then laminated on the substrate to encapsulate the semiconductor device, or alternatively the encapsulant can be filled between the substrate and the semiconductor package driven by a capillary force after the semiconductor package is disposed on the substrate. Therefore, the present invention alleviates pressure and temperature effects on the package to prevent warpage of the substrate and facilitate fabrication of multi-layer stacked package structures. | 2014-04-10 |
20140099756 | THIN FILM TRANSISTOR AND FABRICATING METHOD - A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed. | 2014-04-10 |
20140099757 | III-N Device Structures and Methods - A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive. | 2014-04-10 |
20140099758 | SRAM Devices Utilizing Strained-Channel Transistors and Methods of Manufacture - A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow. | 2014-04-10 |
20140099759 | APPARATUS AND METHODS FOR FORMING A MODULATION DOPED NON-PLANAR TRANSISTOR - Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed. | 2014-04-10 |
20140099760 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed. | 2014-04-10 |
20140099761 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon. | 2014-04-10 |
20140099762 | MANUFACTURING METHOD OF TRENCH TYPE POWER TRANSISTOR DEVICE WITH SUPER JUNCTION - The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate. | 2014-04-10 |
20140099763 | FORMING SILICON-CARBON EMBEDDED SOURCE/DRAIN JUNCTIONS WITH HIGH SUBSTITUTIONAL CARBON LEVEL - Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top of the semiconductor substrate; amorphizing the silicon-carbon layer; covering the amorphized silicon-carbon layer with a stress liner; and subjecting the amorphized silicon-carbon layer to a solid phase epitaxy (SPE) process to form a highly substitutional silicon-carbon film. In one embodiment, the highly substitutional silicon-carbon film is formed to be embedded stressors in the source/drain regions of an nFET transistor, and provides tensile stress to a channel region of the nFET transistor for performance enhancement. | 2014-04-10 |
20140099764 | GRAPHENE DEVICE INCLUDING A PVA LAYER OR FORMED USING A PVA LAYER - An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a dielectric layer upon the PVA layer. In an example, the PVA layer can be activated and the dielectric layer can be deposited on an activated portion of the PVA layer. In an example, an electronic device can include such apparatus, such as included as a portion of graphene field-effect transistor (GFET), or one or more other devices. | 2014-04-10 |
20140099765 | TRANSISTOR STRUCTURE WITH FEED-THROUGH SOURCE-TO-SUBSTRATE CONTACT - An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer. | 2014-04-10 |
20140099766 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A resist layer ( | 2014-04-10 |
20140099767 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes. | 2014-04-10 |
20140099768 | SEMICONDUCTOR DEVICES HAVING PASSIVE ELEMENT IN RECESSED PORTION OF DEVICE ISOLATION PATTERN AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern. | 2014-04-10 |
20140099769 | METHOD TO PROTECT AGAINST CONTACT RELATED SHORTS ON UTBB - Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches. | 2014-04-10 |
20140099770 | Semiconductor Device and a Method of Manufacturing the Same and Designing the Same - There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP | 2014-04-10 |
20140099771 | Reverse Tone STI Formation - A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. | 2014-04-10 |
20140099772 | METHOD OF FORMING A BACKSIDE CONTACT STRUCTURE HAVING SELECTIVE SIDE-WALL ISOLATION - A backside contact structure is created using the following sequence of steps: etching a deep tench from the front surface of the semiconductor wafer to the buried layer to be contacted; depositing an isolation layer into the trench which covers the surfaces of the trench; performing an ion beam anisotropic etch in order to selectively etch the isolation layer at the bottom of the trench; filling the trench with a conductive material in order to create an electrical connection to the backside layer. The process can either be performed at a front-end stage of wafer processing following the formation of shallow trench isolation structures, or at a back-end stage after device transistors are formed. The backside contact structure so fabricated is used to electrically isolate circuit structures constructed on the wafer's upper surface, so that the various components of an integrated circuit can operate at different reference voltages. | 2014-04-10 |
20140099773 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 2014-04-10 |
20140099774 | Method for Producing Strained Ge Fin Structures - Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer. | 2014-04-10 |
20140099775 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH MINI SONOS CELL - A method for fabricating a semiconductor device with mini-SONOS cell is disclosed. The method includes: providing a semiconductor substrate having a first MOS region and a second MOS region; forming a first trench in the semiconductor substrate between the first MOS region and the second MOS region; depositing a oxide liner and a nitride liner in the first trench; forming a STI in the first trench; removing a portion of the nitride liner for forming a second trench between the first MOS region of the semiconductor substrate and the STI and a third trench between the STI and the second MOS region of the semiconductor substrate; and forming a first conductive type nitride layer in the second trench. | 2014-04-10 |
20140099776 | COMPRESSIVELY STRAINED SOI SUBSTRATE - A method of forming a strained silicon-on-insulator includes forming a first wafer having a compressively strained active semiconductor layer, forming a second wafer having an insulation layer formed above a bulk semiconductor layer, and bonding the compressively strained active semiconductor layer of the first wafer to the insulation layer of the second wafer. | 2014-04-10 |
20140099777 | Singulation Processes - In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer. | 2014-04-10 |
20140099778 | INDEXED INLINE SUBSTRATE PROCESSING TOOL - In some embodiments, an indexed inline substrate processing tool may include a substrate carrier having a base and pair of opposing substrate supports having respective substrate support surfaces that extend upwardly and outwardly from the base; and a plurality of modules coupled to one another in a linear arrangement, wherein each module of the plurality of modules comprises an enclosure having a first end, a second end, and a lower surface to support the substrate carrier and to provide a path for the substrate carrier to move linearly through the plurality of modules, and wherein at least one module of the plurality of modules comprises: a window disposed in a side of the enclosure; a heating lamp coupled to the side of the enclosure; a gas inlet disposed proximate a top of the enclosure; and an exhaust disposed opposite the gas inlet. | 2014-04-10 |
20140099779 | Reverse Tone STI Formation - A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. | 2014-04-10 |
20140099780 | Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack For Dopant Source and Passivation - Techniques and structures for laser doping of crystalline semiconductors using a dopant-containing amorphous silicon stack for dopant source and passivation. A method includes forming a dopant-containing amorphous silicon layer stack on at least one portion of a surface of a crystalline semiconductor layer, and irradiating a selected area of the dopant-containing amorphous silicon layer stack, wherein the selected area of the dopant-containing amorphous silicon layer stack interacts with an upper portion of the underlying crystalline semiconductor layer to form a doped, conductive crystalline region, and each non-selected area of the dopant-containing amorphous silicon layer stack remains intact on the at least one portion of the surface of the crystalline semiconductor layer. | 2014-04-10 |
20140099781 | BEAM HOMOGENIZER, LASER IRRADIATION APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The energy distribution of the beam spot on the irradiated surface changes due to the change in the oscillation condition of the laser or before and after the maintenance. The present invention provides an optical system for forming a rectangular beam spot on an irradiated surface including a beam homogenizer for homogenizing the energy distribution of the rectangular beam spot on the irradiated surface in a direction of its long or short side. The beam homogenizer includes an optical element having a pair of reflection planes provided oppositely for reflecting the laser beam in the direction where the energy distribution is homogenized and having a curved shape in its entrance surface. The entrance surface of the optical element means a surface of the optical element where the laser beam is incident first. | 2014-04-10 |
20140099782 | METHOD AND APPARATUS FOR THERMAL CONTROL OF ION SOURCES AND SPUTTERING TARGETS - A method and apparatus are disclosed for controlling a semiconductor process temperature. In one embodiment a thermal control device includes a heat source and a housing comprising a vapor chamber coupled to the heat source. The vapor chamber includes an evaporator section and a condenser section. The evaporator section has a first wall associated with the heat source, the first wall having a wick for drawing a working fluid from a lower portion of the vapor chamber to the evaporator section. The condenser section coupled to a cooling element. The vapor chamber is configured to transfer heat from the heat source to the cooling element via continuous evaporation of the working fluid at the evaporator section and condensation of the working fluid at the condenser section. Other embodiments are disclosed and claimed. | 2014-04-10 |
20140099783 | METHOD OF ADDING AN ADDITIONAL MASK IN THE ION-IMPLANTATION PROCESS - The present invention discloses a method of adding an additional mask in the ion-implantation process. It relates to technical field of ion implantation. This invention comprises: a mask plate is added upon the said MPW and the nitrogen element is implanted in the said MPW; the implanted nitrogen element is used for amorphizing the upper surface of the MPW. The advantageous effects of the above technical solution are as follows: the steps of the production process are simplified; the ion implantation mask will achieve 4 different doping concentrations of the ion implantation when the wafer is implanted. It means that it is possible to form 4 different gate oxide layers of different in thickness. However, it is essential to apply the photomask three times to achieve the same effect in the process of prior art. Consequently, the method of the present invention can reduce both the cost and the term of production process. | 2014-04-10 |
20140099784 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern. | 2014-04-10 |
20140099785 | Sacrificial Low Work Function Cap Layer - A method includes forming an interlayer on a substrate, depositing a dielectric on the interlayer to form a dielectric stack, forming a sacrificial cap layer over the dielectric stack, processing the substrate to alter properties of the dielectric stack, and removing the sacrificial cap layer. | 2014-04-10 |
20140099786 | Methods Of Forming Through Substrate Interconnects - A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material. | 2014-04-10 |
20140099787 | SEMICONDUCTOR DEVICE PROCESSING WITH REDUCED WIRING PUDDLE FORMATION - A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer. | 2014-04-10 |
20140099788 | METHOD FOR APPLYING AN IMAGE OF AN ELECTRICALLY CONDUCTIVE MATERIAL ONTO A RECORDING MEDIUM AND DEVICE FOR EJECTING DROPLETS OF AN ELECTRICALLY CONDUCTIVE FLUID - The invention relates to a method for applying an image of an electrically conductive material onto a recording medium. In the method, the recording medium is heated and the electrically conductive material is jetted onto the recording medium. The invention further relates to a device for ejecting droplets of an electrically conductive fluid onto a recording medium. | 2014-04-10 |
20140099789 | METHOD OF MAKING AN INTERCONNECT DEVICE - A semiconductor system includes: providing a dielectric layer; providing a conductor in the dielectric layer, the conductor exposed at the top of the dielectric layer; capping the exposed conductor; and modifying the surface of the dielectric layer, modifying the surface of the dielectric layer, wherein modifying the surface includes cleaning conductor ions from the dielectric layer by dissolving the conductor in a low pH solution, dissolving the dielectric layer under the conductor ions, mechanically enhanced cleaning, or chemisorbing a hydrophobic layer on the dielectric layer. | 2014-04-10 |
20140099790 | Chemical Mechanical Polishing Composition Having Chemical Additives and Methods for Using Same - Chemical-mechanical polishing (CMP) compositions containing chemical additives and methods of using the CMP compositions are disclosed. The CMP composition comprises abrasive; chemical additive; liquid carrier; optionally an oxidizing agent; a pH buffering agent and salt; a surfactant and a biocide. The CMP compositions and the methods provide enhanced removing rate for “SiC”, SiN” and “SiC | 2014-04-10 |
20140099791 | COMPOSITION FOR FORMING RESIST UNDERLAYER FILM FOR EUV LITHOGRAPHY - A method for producing a semiconductor device includes the steps of: applying a composition for forming a resist underlayer film for EUV lithography including a novolac resin containing a halogen atom onto a substrate having a film to be fabricated for forming a transferring pattern and baking the composition so as to form a resist underlayer film for EUV lithography; and applying a resist for EUV lithography onto the resist underlayer film for EUV lithography, irradiating, with EUV through a mask, the resist underlayer film for EUV lithography and a film of the resist for EUV lithography on the resist underlayer film, developing the film of the resist for EUV lithography, and transferring an image formed in the mask onto the substrate by dry etching so as to form an integrated circuit device. | 2014-04-10 |
20140099792 | SINGLE FIN CUT EMPLOYING ANGLED PROCESSING METHODS - Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the overlay tolerance increases by a pitch of fin-defining spacers due to the mask material portions. Alternately, a conformal silicon oxide layer can be deposited on fin-defining spacers and structure-damaging ion implantation is performed only on fin-defining spacers located on one side of each mandrel structure. A photoresist layer is subsequently applied and patterned to form an opening, from which a damaged silicon oxide portion and an underlying fin-defining spacer are removed, while undamaged silicon oxide portions are not removed. An array of semiconductor fins including a vacancy can be formed by transferring the pattern into a semiconductor layer. | 2014-04-10 |
20140099793 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask. | 2014-04-10 |
20140099794 | RADICAL CHEMISTRY MODULATION AND CONTROL USING MULTIPLE FLOW PATHWAYS - Systems and methods are described relating to semiconductor processing chambers. An exemplary chamber may include a first remote plasma system fluidly coupled with a first access of the chamber, and a second remote plasma system fluidly coupled with a second access of the chamber. The system may also include a gas distribution assembly in the chamber that may be configured to deliver both the first and second precursors into a processing region of the chamber, while maintaining the first and second precursors fluidly isolated from one another until they are delivered into the processing region of the chamber. | 2014-04-10 |
20140099795 | METHODS AND APPARATUS FOR PROCESSING SUBSTRATES USING AN ION SHIELD - Methods and apparatus for processing a substrate are provided. In some embodiments, a method of processing a substrate having a first layer may include disposing a substrate atop a substrate support in a lower processing volume of a process chamber beneath an ion shield having a bias power applied thereto, the ion shield comprising a substantially flat member supported parallel to the substrate support, and a plurality of apertures formed through the flat member, wherein the ratio of the aperture diameter to the thickness flat member ranges from about 10:1-1:10; flowing a process gas into an upper processing volume above the ion shield; forming a plasma from the process gas within the upper processing volume; treating the first layer with neutral radicals that pass through the ion shield; and heating the substrate to a temperature of up to about 550 degrees Celsius while treating the first layer. | 2014-04-10 |
20140099796 | METHOD FOR DEVELOPING LOW DIELECTRIC CONSTANT FILM AND DEVICES OBTAINED THEREOF - A method for porogen removal of porous SiOCH film is provided, as well as devices obtained thereof. The devices and associated methods are in the field of advanced semiconductor interconnect technology, and more in particular in the development of dielectric films with low-k value. | 2014-04-10 |
20140099797 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A silicon oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a silicon-containing layer on the substrate by supplying a source gas containing silicon, to the substrate housed in a processing chamber and heated to a first temperature; and oxidizing and changing the silicon-containing layer formed on the substrate, to a silicon oxide layer by supplying reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure atmosphere of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure atmosphere of less than atmospheric pressure and heated to a second temperature equal to the first temperature or higher than the first temperature. | 2014-04-10 |
20140099798 | UV-Curing Apparatus Provided With Wavelength-Tuned Excimer Lamp and Method of Processing Semiconductor Substrate Using Same - A UV irradiation apparatus for processing a semiconductor substrate includes: a UV lamp unit having at least one dielectric barrier discharge excimer lamp which is constituted by a luminous tube containing a rare gas wherein an inner surface of the luminous tube is coated with a fluorescent substance having a peak emission spectrum in a wavelength range of 190 nm to 350 nm; and a reaction chamber disposed under the UV lamp unit and connected thereto via a transmission window. | 2014-04-10 |
20140099799 | Lithography Masks, Systems, and Manufacturing Methods - Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position. | 2014-04-10 |
20140099800 | Oscillation Proof Brushblock for Sliprings - A slip ring assembly for the electrical connection of two rotating parts has at least a sliding track with V-grooves. At least two brushes of electrically conductive material are contacting the sliding track within the V-groove. The brushes are connected electrically with each other and mounted at different levels resulting in a different distance to the rotation axis of the sliding track. This results in an improved resistance against shock and vibrations. | 2014-04-10 |
20140099801 | MAGNETIC LIGHT SOURCE ADAPTOR AND LIGHT SOURCE THEREFOR - A magnetic light source adaptor includes a main body, a control module and a magnetic unit. The main body has a male portion and a female portion. A first conducting set is disposed within the female portion, whereas a second conducting set is arranged on the male portion. The control module is arranged on the main body and electrically connecting the first and second conducting sets. The magnetic unit attaches to the main body to facilitate positioning of the magnetic light source adaptor. The magnetic light source adaptor and a light source are detachably assembled for easier access under maintenance and replacement. | 2014-04-10 |
20140099802 | GROUNDING DEVICE FOR WELDERS - A magnetic grounding clamp for portable yet secure connection of a welder grounding lead to any grounding body including irregular-shaped objects such as pipes and metal cylinders. The grounding electrode generally comprises conductive body having a protruding elongate neck, opposing-protruding legs, and a pivoting foot assembly having a disk-like magnet attached distally at the end of each leg. A length-adjustable tungsten grounding electrode protrudes downward from the end of the elongate neck. The body has a tail section with an adjustable spacer protruding therefrom. The spacer see-saws the body about the foot assemblies to maintain the grounding electrode in direct contact with whatever earth structure the cupped magnets are affixed to, thereby ensuring a firm ground contact and reliable ground path for the welder grounding lead. | 2014-04-10 |
20140099803 | ELECTRICAL CONTACT ASSEMBLY - An electrical contact assembly includes a first electrical contact having a first mating element, and a second electrical contact having a second mating element. The first and second electrical contacts being configured to mate together at the first and second mating elements such that the first and second mating elements engage each other at a contact interface. A distribution of contact pressure across the contact interface at least partially coincides with a distribution of electrical current flow across the contact interface. | 2014-04-10 |
20140099804 | CONNECTOR - A connector is mountable on a circuit board and mateable with a mating connector along a mating direction. The connector comprises a contact, a housing, an enclosing portion and a coupling portion. The housing holds the contact. The enclosing portion encloses an outer circumference of the housing in a plane perpendicular to the mating direction. The coupling portion directly or indirectly couples the enclosing portion with the housing so as to allow the enclosing portion to move along the mating direction relative to the housing. | 2014-04-10 |
20140099805 | ELECTRONIC CONNECTOR CAPABLE OF ACCEPTING A SINGLE SUBSCRIBER IDENTITY MOPDULE OR A MEMORY CARD - An electronic communications device | 2014-04-10 |
20140099806 | FLOATING BUS BAR CONNECTOR - A floating bus bar connector connects a computing asset to bus bars using a connecting clip and a conducting terminal that is coupled to the connecting clip and to an electronic component inside the computing asset. To simplify connection to the bus bars, the floating bus bar connector is mounted to a chassis of the computing asset so that the entire connector is movable, relative to the chassis, in a direction perpendicular to the bus bar. Thus, if the floating bus bar connector and bus bars become misaligned when the computing asset is being connected to the bus bars, the floating bus bar connector may move to realign with the bus bars. | 2014-04-10 |