| 15th week of 2009 patent applcation highlights part 21 |
| Patent application number | Title | Published |
|---|
| 20090091915 | Illumination device with mechanically adjustable color conversion system - A mechanically adjustable color conversion system for illumination devices comprised of light sources oriented linearly or in an array located under a fluorescent dyed clear or defused plastic element which has holes that carefully align with the light sources, dyed element which can be moved thru some simple mechanical fashion in such a way that there can be careful control of the light that goes directly thru the hole in one extreme or that progressively goes less thru the hole and more thru the fluorescent dyed element until all the light goes thru the dyed element at the other extreme thus allowing for the simple mechanical adjustment of the color or hue of light from the light source. | 2009-04-09 |
| 20090091916 | MANUFACTURING METHOD OF SUBSTRATE, MANUFACTURING METHOD OF WIRING BOARD, WIRING BOARD, ELECTRONIC DEVICE, ELECTRON SOURCE, AND IMAGE DISPLAY APPARATUS - To provide a method for simply manufacturing a substrate provided with a flat surface shape. Specifically, a method for manufacturing a substrate according to the present invention includes the steps of preparing a structure including a glass layer and a precious metal particle having a diameter not less than 1 μm and not more than 10 μm disposed on the glass layer while contacting thereto; and putting the precious metal particle in the glass layer by heating the structure at a temperature which is lower than a softening point of the glass layer. | 2009-04-09 |
| 20090091917 | Switch attachment for visual enhancement - A switch attachment for visual enhancement utilizing photoluminescent material. The invention incorporates photoluminescent material into devices for locating switches in low light conditions. The invention is embodied by attachments to switch assemblies, which utilize existing structures for attachment, or by the use of adhesives. The photoluminescent material is incorporated directly into the invention or is painted on or dyed. | 2009-04-09 |
| 20090091918 | ORGANIC ELECTRO-LUMINESCENCE ELEMENT, PRODUCTION METHOD AND USE THEREOF - Disclosed is an organic electro-luminescence element including an anode layer, an organic electro-luminescence compound layer containing a high molecular weight light-emitting compound, and a cathode layer, laminated in this order, wherein said cathode layer includes: (i) a metal-doped electron injection layer in contact with the organic electro-luminescence compound layer and (ii) a transparent, non-metallic electron-injecting material in contact with the metal-doped electron injection layer; and wherein said metal-doped electron injection layer is selected from the group consisting of a material functioning as a hole-blocking material, a material functioning as an exciton-blocking material and a material functioning as a blocking material for both holes and excitons. | 2009-04-09 |
| 20090091919 | SURFACE LIGHT SOURCE SYSTEM AND LIGHT SOURCE UNIT - A surface light source system | 2009-04-09 |
| 20090091920 | LIGHT GUIDE MEMBER, FLAT LIGHT SOURCE DEVICE, AND DISPLAY DEVICE - A light guide member, a flat light source device and a display device using the light guide member, by which a white light having a high color rendering property can be obtained without using luminescent devices of a plurality of colors are provided. | 2009-04-09 |
| 20090091921 | Decorative object connectable to a connected object - In a decorative object connectable to a connected object, a connecting member includes a fixing portion at an end of the connecting member, and the fixing portion is connected and fixed to a stylish decorative object with a specific shape, and another end of the connecting member is a stop portion, and a connecting portion is disposed between both ends, and a stop portion of the connecting member is passed through a connecting hole of the connected object, and stopped by both ends and positioned onto the connected object, and the stylish decorative object includes a light emitting element. | 2009-04-09 |
| 20090091922 | Decorative object connectable to a connected object - In a decorative object connectable to a connected object, the decorative object includes a connecting member having a fixing portion at an end of the connecting member, and the fixing portion is connected and fixed to a stylish decorative object with a specific shape, and another end of the connecting member is a positioning portion, and a passage is penetrated through the positioning portion and provided for passing and fixing the connected object, and the stylish decorative object includes a light emitting element. | 2009-04-09 |
| 20090091923 | LAMP STRUCTURE - The present invention relates to a lamp structure. The lamp structure is mainly installed inside a cabinet, and by opening the cabinet door will enable the electrical circuit of the lamp structure to be a close circuit; vise versa, closing the cabinet door will result in the open circuit of the electrical circuit of the lamp structure. When the electrical circuit is a close circuit, the light emitting part of the lamp structure will generate light to illuminate the internal space of the cabinet so as clearly view the objects location in the cabinet. | 2009-04-09 |
| 20090091924 | ILLUMINATING BRICK - An illuminating brick includes a block and at least one light-emitting element mounted in the brick. The brick has a top face, a bottom face and a plurality of lateral side surfaces interconnecting the top and bottom faces. The at least one light-emitting element is engaged in and optically coupled to at least one of the bottom face and lateral side surfaces. The lateral side surfaces and the bottom face are configured for reflecting and directing light emitted from the at least a light-emitting element to exit through the top face. | 2009-04-09 |
| 20090091925 | LIGHT-EMITTING PRODUCT - A light-emitting product (for example, a flashlight) includes a first housing includes a light source for emitting light and a lens system that is adjustable in position relative to the light source. The second housing can be attached to the first housing and includes a power source for the light source. When the first housing and the second housing are attached, the first housing and the second housing can be moved relative to each other to adjust the position of the lens system relative to the position of the light source to focus the light from the light source. | 2009-04-09 |
| 20090091926 | Illumination apparatus for bag toss game - A light array for illuminating the circular opening in the platform of a bag toss game includes a circular frame and mating cover that define a hole, at least equal in area to the opening. A plurality of lights (LEDs) is positioned in the annular enclosure formed by the frame and cover. The cover includes a transparent wall through which light is projected to the opening in the platform. An annular printed circuit board is supported in the annular enclosure and mechanically supports and electrically connects the LEDs to a switched battery source. Different embodiments for blinking and sequencing the LEDs are shown. A laser diode arrangement for producing a cross hair pattern of beams in the platform hole is also described. | 2009-04-09 |
| 20090091927 | PLANAR LIGHTING DEVICE - The planar lighting device includes linear light sources, a light guide plate having a flat light exit surface, a rear surface and parallel grooves formed in the rear surface for accommodating the light sources, respectively, and a support member for supporting the light guide plate with the rear surface. A cross-section of the light guide plate has a rear surface profile including convex portions having the respective grooves and concave portions formed between adjacent grooves, and a thickness in each concave portion decreases from each groove toward either midpoint between adjacent grooves and is thinnest at the midpoint. A cross-section of the support member has a first surface profile of a first surface including a profile identical to a profile of each concave portion of the rear surface profile and a second surface of the support member is a flat surface. | 2009-04-09 |
| 20090091928 | IMAGE DISPLAY APPARATUS THAT REDUCES ILLUMINANCE IRREGULARITY, PROJECTION-TYPE IMAGE DISPLAY APPARATUS USING THE IMAGE DISPLAY APPARATUS AND REAR-PROJECTION TELEVISION - An illumination apparatus includes: a light source including at least one light-emitting element, the light-emitting element being configured to emit light and having an uneven light distribution characteristic; a coupling optical system disposed corresponding to the light source and configured to convert the light emitted from the light source into substantially parallel light; a light condensing optical system configured to condense the light from the light source, converted into the substantially parallel light by the coupling optical system, at a predetermined focal position; an illuminated surface as an object to be illuminated by the light from the light source condensed by the light condensing optical system; and an optical element disposed between the coupling optical system and the light condensing optical system, and configured to reduce irregular distribution of an amount of light on the illuminated surface caused by the light distribution characteristic of the light-emitting element. | 2009-04-09 |
| 20090091929 | DIRECTIONAL L.E.D. LIGHTING UNIT FOR RETROFIT APPLICATIONS - An adjustable light emitting diode (LED) lighting unit adapted for installation in a light fixture is disclosed. In one example, the lighting unit includes first and second end assemblies adapted to interfit with first and second portions, respectively, of the light fixture. A substrate is mounted between the first and second end assemblies and includes electrically conductive paths that are electrically coupled to the light fixture via at least one of the first and second end assemblies. A plurality of LED units are positioned on the substrate and coupled to the electrically conductive paths of the substrate. The first and second end assemblies are configured to allow rotation of the substrate relative to the first and second portions, respectively, of the light fixture. | 2009-04-09 |
| 20090091930 | Light fixture - A light fixture comprises a housing configured to store a plurality of light bulbs therein, wherein at least one of the light bulbs is located in a non-illumination position within the housing. The light fixture may also comprise an openable door such that at least one light bulb is coupled to the door. The light fixture may also comprise an actuatable mechanism that releases the light fixture from a fixed position when actuated to enable variable positioning of the light fixture. | 2009-04-09 |
| 20090091931 | Illumination device with side aimed light source and two step light dispersion - A two step process of light manipulation to obtain an even toned linear light from point sources of light. This process obtained by taking evenly space particular point sources of light (element A) delivering essentially 100% of their light into the side of an adjacent clear rod (element B). The light turns 90 degrees and travels down the clear rod (element B) in what is called a “waveguide” effect. Adjacent and parallel to A and 90 degrees turned from B is element C, a diffusing rod like member. A, B and C form a triad with A and C in separate contact with B. A and C oriented more or less 90 degrees to each other with B as the pivot point. The triad of A, B and C are contained in a channel where only C sticks out half way. Light from B illuminates C which finishes evening out the light and delivers the final bright even tone of light beyond the containing channel thru the exposed portion of element C. | 2009-04-09 |
| 20090091932 | LED ARRAY GRID, METHOD AND DEVICE FOR MANUFACTURING SAID GRID AND LED COMPONENT FOR USE IN THE SAME - Disclosed herein is a method for producing an LED array grid including the steps of (i) arranging N electrically conducting parallel wires, where N is an integer >1, thus creating an array of wires having a width D perpendicular to a direction of the wires, (ii) arranging LED components to the array of wires such that each LED component is electrically coupled to at least two adjacent wires, (iii) stretching the array of wires such that the width D increases, and arranging the stretched LED array grid onto a plate or between two plates | 2009-04-09 |
| 20090091933 | KEYPAD ASSEMBLY AND PORTABLE ELECTRONIC DEVICE USING THE SAME - A keypad assembly ( | 2009-04-09 |
| 20090091934 | High power LED module - A high power LED module includes a substrate formed of a metal bottom thermal transfer plate coated with an insulative layer and having a plurality of electric contacts formed on the metal bottom thermal transfer plate and exposed to the outside of the insulative layer and a plurality of bonding holes cut through the top and bottom sides, epitaxial chips installed in a center area of the substrate and electrically connected to the electric contacts, and a frame injection-molded on the substrate around the at least one epitaxial chip and having a plurality of bonding legs bonded to the bottom bonding holes of the substrate. | 2009-04-09 |
| 20090091935 | LIGHT FIXTURE WITH AN EFFICIENCY-OPTIMIZED OPTICAL REFLECTION STRUCTURE - A light fixture with an optical reflection structure, comprising a lamp housing having at least one open accommodating space for light beam to be emitted outward therefrom; a plurality of connectors for coupling a light tube to the light fixture, the connectors being located at both opposite ends in a longitudinal direction of the accommodating space; a reflector having a curved surface affixed with a composite mirror film for light reflection, the reflector being located in the accommodating space and substantially covering at least a part of a surface of the accommodating space, wherein the curved surface is determined based on law of reflection by optimizing a luminous flux of primary reflection light reflected off the reflector to the extent of 90% or more compared with a naked light source from the light tube. The light fixture of the invention provides sufficient illumination and prolongs the lifespan of the light tube in a cost-economic way, thus directly saving energy and reducing the production of carbon. | 2009-04-09 |
| 20090091936 | Focal point projection light signal comprising a beam concentrator - An improved focal point projection light signal device having a single point light source, a Fresnel lens, and a reflective beam concentrator having a spherical reflective surface located to the rear of the light source. The single point light source is positioned at the focal point of the Fresnel lens such that light emitted toward the Fresnel lens is refracted into a concentrated beam pattern that is projected from the front of the lens. The reflective surface of the beam concentrator is spherically concave and is positioned such that light emitted to the rear of the light bulb is reflected back through the lens focal point and out through the Fresnel lens. The overall diameter of the reflective beam concentrator is significantly smaller than the diameter of the Fresnel lens such that reflection of extraneous light sources that may produce phantom signal indications is minimized. | 2009-04-09 |
| 20090091937 | LIGHT CONTROL DEVICE HAVING IRREGULAR PRISM SURFACE - The light control device has an array of prism elements, thereby forming a series of interleaving peaks and valleys along a major surface of the light control device, where the surface of the prism elements has bulging bumps and/or the bottoms of the valleys are raised. The bumps are randomly distributed; and the height of the valley bottoms can be randomly distributed, or patterned in accordance with a planar light intensity distribution along a plane. In addition, the light control device can have integrated color correcting and/or diffusing function by dispersing appropriate additives uniformly in the prism elements and/or in the substrate of the light control device. The light control device can have diffusing elements on the other major surface so that the degree of haze/surface roughness is either uniform or patterned. | 2009-04-09 |
| 20090091938 | LAMP AND METHOD FOR SUPPORTING A LIGHT SOURCE - A lamp is provided. Generally, the lamp comprises light source means for providing illumination in a frontward direction, retainer means for applying a frontward-directed load to the light source, and housing means for mechanically supporting the light source means and the retainer means. | 2009-04-09 |
| 20090091939 | LAMP STRUCTURE - The present invention relates to a lamp structure characterized in which the lamp structure is installed inside a cabinet where the opening of the cabinet door turns on the electrical loop of the lamp structure and the closing of the cabinet door shuts off its electrical loop; when the electrical loop is charged, the illuminating part of the lamp structure produces light rays to illuminate the inside of the cabinet that allows clear viewing of the positions of objects inside. | 2009-04-09 |
| 20090091940 | Portable lightbox assembly - A portable lightbox assembly comprises a housing and a lift mechanism having at least one light fixture coupled thereto, the lift mechanism coupled to the housing and movable from a retracted position enclosable within the housing to an extended position protruding beyond the housing. | 2009-04-09 |
| 20090091941 | PANEL COMPONENT HOLDER - The invention relates to a panel component holder arranged to be attached to a panel element. The panel component holder comprises at least one supporting means and a casing including a brim and at least one retainer. The at least one supporting means comprises an attached end being attached to the casing, an elastic means and a free end. Said at least one retainer is arranged to prevent outwardly movement of the at least one supporting means from said casing in a plane coinciding with the centre axis of the casing, wherein the outwardly movement of the supporting means is induced by the elastic means. | 2009-04-09 |
| 20090091942 | Lighting system for tow truck - The lighting system for tow truck includes a housing having lights disposed on a front and sides thereof to illuminate a work area. The lighting system may be disposed on a tow truck accessory frame situated behind a cab of the tow truck. The lights disposed on the housing may be a combination of spotlights and work lights, and are directed to illuminate work areas in the vicinity of the tow truck. This configuration of lights provides greater illumination in work areas to the rear and sides for better control and efficiency of load recovery operations. | 2009-04-09 |
| 20090091943 | Ambient Lighting Display - An ambient lighting display is obtained directly on a portion of an interior panel. The portion of the panel is covered with a paint or ink which reacts to ultraviolet light by emitting visible light of a predetermined color. To obtain a lighting display, a portion of the panel is illuminated with ultraviolet light of an appropriate wavelength to cause the paint or ink to fluoresce with the predetermined color. | 2009-04-09 |
| 20090091944 | LIGHTING OR SIGNALLING DEVICE FOR A MOTOR VEHICLE - A lighting or signalling device for a motor vehicle, having an optical axis and comprising at least one light source and at least one guide for the light rays between the source and an exit face, the guide having an entry edge associated with the source. The guide for the light rays is formed by a sheet and the sheet comprises a curved rear edge convex towards the rear, able to provide reflection of the light rays towards the exit face. A curved shape of the rear edge being associated with the profile of the exit faced so that the emerging light rays have a direction contained in a substantially horizontal plane containing the optical axis of the device. | 2009-04-09 |
| 20090091945 | Coloured Polyurethane Light Guides - An optical illumination device ( | 2009-04-09 |
| 20090091946 | Light-guiding structure - A light-guiding structure includes a light-guiding plate, and an LED set matched with the light-guiding plate. The characteristic is that the light-guiding plate has a light-entering surface, and there are a plurality of ditches on the light-entering surface. A light-entering interface is formed between two adjacent ditches. The LED set corresponds to the light-entering surface of the light-guiding plate, and each of the LEDs of the LED set corresponds to one light-entering interface. By utilizing the light-entering interface and the ditches, the light is uniformly spread. The light is uniformly spread at the light-entering surface of the light-guiding plate so that the bright point does not occur. The light is uniformly emitted from the light-emitting surface and the illumination is enhanced. | 2009-04-09 |
| 20090091947 | Surface light source structure of backlight module in a flat panel display - A surface light source structure having a circuit board, a first light emitting diode (LED) array, and a second LED array is provided. The first and second LED arrays are assembled on the circuit board. Each LED rows of the two LED arrays has a plurality of LED units connected in series. The LED rows of the first LED array are connected in parallel. The LED rows of the second LED array are connected in parallel. The LED rows of the second LED array are intersected between the LED rows of the first LED array. Positive-to-negative directions of the LED units of the first and second LED array are arranged in opposite directions. | 2009-04-09 |
| 20090091948 | LIGHT SOURCE MODULE - An exemplary light source module includes a plurality of light emitting units and a light pervious paste. Each light emitting unit includes a light guide plate and a light source optically coupled to the light guide plate. The light guide plate includes a bottom surface, a light emitting surface opposite to the bottom surface, and a plurality of side surfaces interconnected between the bottom surface and the light emitting surface. The light pervious paste is interconnected between two adjacent side surfaces of two neighboring light guide plates. | 2009-04-09 |
| 20090091949 | ALL-IN-ONE TYPE LIGHT GUIDE PLATE AND BACKLIGHT APPARATUS EMPLOYING THE SAME - An all-in-one light guide plate, a backlight apparatus employing the same, and a method of manufacturing the all-in-one light guide plate are provided. The all-in-one light guide plate has a structure in which a plurality of protrusion type refractive elements for outputting light are integrated into the light guide member. It is possible to improve optical properties by more densely arranging the refractive elements with distance from the light source. | 2009-04-09 |
| 20090091950 | POWER CONVERTING CIRCUIT WITH OPEN LOAD PROTECTION FUNCTION - A power converting circuit with an open load protection function is electrically connected to a power supply providing a first voltage level, and outputs a second voltage level to drive a load. The power converting circuit includes a DC/DC converter and a rectifying element disposed between an output node and an input node of the DC/DC converter that forms a discharging loop with the DC/DC converter. The DC/DC converter receives the power, converts the first voltage level into the second voltage level and outputs the second voltage level to the load. The rectifying element is utilized to release a surge voltage produced by the DC/DC converter in an open load condition. | 2009-04-09 |
| 20090091951 | CONTROL CIRCUIT FOR SYNCHRONOUS RECTIFYING AND SOFT SWITCHING OF POWER CONVERTERS - A control circuit for soft switching and synchronous rectifying is provided for power converter. A switching-signal circuit is used for generating drive signals and a pulse signal in response to a leading edge and a trailing edge of a switching signal. The switching signal is developed for regulating the power converter. Drive signals are coupled to switch the power transformer. A propagation delay is developed between drive signals to achieve soft switching of the power converter. An isolation device is coupled to transfer the pulse signal from a primary side of a power transformer to a secondary side of the power transformer. A controller of the integrated synchronous rectifier is coupled to the secondary side of the power transformer for the rectifying operation. The controller is operated to receive the pulse signal for switching on/off the power transistor. The pulse signal is to set or reset a latch circuit of the controller for controlling the power transistor. | 2009-04-09 |
| 20090091952 | DC-DC CONVERTER - Disclosed is a DC-DC converter for suitably converting the voltage of a solar panel into a desired output voltage to be supplied to various observation equipment installed in an artificial satellite. The DC-DC converter | 2009-04-09 |
| 20090091953 | Compensating for inductance variation in a power converter using a dual-purpose feedback pin - A comparing circuit and a control loop are used to maintain the peak level of current flowing through an inductor of a flyback converter. An inductor switch control signal controls an inductor switch through which the inductor current flows. The inductor current increases at a ramp-up rate during a ramp time and stops increasing at the end of the ramp time. The comparing circuit generates a timing signal that indicates a target time at which the inductor current would reach a predetermined current limit if the inductor current continued to increase at the ramp-up rate. The control loop then receives the timing signal and compares the target time to the end of the ramp time. The pulse width of the inductor switch control signal is increased when the target time occurs after the end of the ramp time. Adjusting the pulse width controls the peak of the inductor current. | 2009-04-09 |
| 20090091954 | POWER CONVERTER AND POWER CONVERSION METHOD - This invention provides a power converter and a power conversion method that can reduce distortions of an output voltage and an output current, can simply a calculation processing, and is inexpensive and has a high performance even when a PWM pulse gets narrow. In a power converter for connecting each phase of an AC power supply to each phase on an output side through a bidirectional switch and converting an AC source voltage by PWM, the power converter includes a one-phase fixing switching mode and a full phase switching mode, and a mode switching section for switching from the full phase switching mode to the one-phase fixing switching mode. Moreover, the power converter includes a vector component calculator ( | 2009-04-09 |
| 20090091955 | Quasi resonant switching mode power supply - A switching mode power supply (SMPS) and a driving method thereof are provided. The SMPS includes a power supply block that includes a first switch coupled to a first coil of a primary side of a transformer for converting an input voltage, wherein the power supply block supplies power to a second coil and a third coil of a secondary side of the transformer according to operation of the first switch; and a PWM signal generator determines a turn-on time of the first switch according to the input voltage, and the turn-on time is determined regardless of a power magnitude of an output terminal connected to the second coil. Accordingly, screen noise due to a ripple can be eliminated and stress on the switch breakdown due to excessive power input can be reduced to enable an SMPS with stable driving. | 2009-04-09 |
| 20090091956 | SYSTEM FOR PRODUCING ELECTRIC POWER FROM RENEWABLE SOURCES AND A CONTROL METHOD THEREOF - Described herein is a system for generating electric power, comprising: an electric-power source ( | 2009-04-09 |
| 20090091957 | CASCADED PFC AND RESONANT MODE POWER CONVERTERS - A control unit controls cascaded PFC and LLC converters, the LLC converter having an input coupled to an output, of the PFC converter and providing an output voltage that decreases with increasing switching frequency. The control unit produces a sawtooth waveform with a linear ramp for controlling the LLC converter switching frequency, and hence its output voltage, in dependence upon a feedback signal. It also produces for the PFC converter a PWM signal with a frequency that is the same as or an integer fraction of the LLC converter switching frequency, by comparing two thresholds with the linear ramp in respective different cycles of the sawtooth waveform to turn on and off a switch of the PFC converter during these different cycles. Logic circuits prevent PFC converter switch transitions from occurring simultaneously with switching transitions of the LLC converter. | 2009-04-09 |
| 20090091958 | DEVICE FOR SIMULATING RECTIFIED CONSTANT IMPEDANCE LOAD AND METHOD THEREOF - The device for simulating a rectified constant impedance load provide by the present invention is to test a power product and comprises an analog-digital converter, a digital signal processor, a digital-analog converter, and an active electrical load module in order to replacing the passive components of a traditional rectified passive load. method for simulating a rectified constant impedance load being applied to test a power product and comprising the steps of: (S1) replacing the plurality of passive components of the rectified constant impedance load with a digital control module and an active electrical load module; (S2) establishing a passive load model function in order to represent the application relationships of the plurality of the passive components; (S3) executing the operation of the passive load model function by the digital control module in order to gain a load current value, and transferring the load current value to an analog control signal via the digital control module; and (S4) controlling the active electrical load module via the analog control signal so as to draw currents from the power product. | 2009-04-09 |
| 20090091959 | POWER SUPPLY UNIT, IMAGE FORMING APPARATUS, AND METHOD FOR CONTROLLING POWER SUPPLY - In an image forming apparatus, a monitoring unit monitors whether a returning factor required to switch an operational state of the apparatus from a power-saving mode to an operating mode is generated, an antenna unit receives external electrical wave, a power generation unit generates electricity from the received electrical wave and supplies the electricity to the monitoring unit, and a controlling unit switches the operational state of the apparatus from the power-saving mode to the operating mode when the monitoring unit detects generation of a returning factor. | 2009-04-09 |
| 20090091960 | METHOD AND APPARATUS FOR SYNCHRONOUS RECTIFYING OF SOFT SWITCHING POWER CONVERTERS - An apparatus for synchronous rectifying of a soft switching power converter is provided. An integrated synchronous rectifier includes a power transistor coupled between a transformer and the output of the soft switching power converter, and a controller receiving a pulse signal to switch on/off the power transistor. A switching control circuit generates the pulse signal in response to a current signal, and generates drive signals to switch the transformer in response to a switching signal. An isolation device is coupled to transfer the pulse signal between the switching control circuit and the integrated synchronous rectifier. The switching signal is used for regulating the power converter and the current signal is correlated to the switching current of the transformer. | 2009-04-09 |
| 20090091961 | Single-Stage Power Factor Correction Circuit - A single-stage power factor correction circuit includes a first rectifier, a second rectifier, a full bridge rectifier, a capacitor, a fly back transformer, and a switch. Unlike conventional single-stage power factor correction circuits, the present invention just needs to pass through two rectifiers at positive and negative half cycles, so as to reduce the conduction loss, lower the temperature of the power supply, and control the voltage of the control energy storage capacitor, and stabilize voltage output. | 2009-04-09 |
| 20090091962 | MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY - A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips. | 2009-04-09 |
| 20090091963 | MEMORY DEVICE - A first DRAM device comprises a first input connected to a first trace line to receive an address signal and a second input is connected to receive an operating voltage, such as Vdd. A second DRAM device comprises a first input connected to the first trace line to receive the address signal and a second input to receive the operating voltage. A first signal termination structure is connected to the first trace line, wherein the first signal termination structure is to terminate the first trace line to the operating voltage. | 2009-04-09 |
| 20090091964 | Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region - A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a location where the first well region is formed, and a third well region of a second conductivity type, which is located between the first well region and the second well region. The memory cell further includes a first tap diffused layer of the first conductivity type for supplying a potential to the first well region, a second tap diffused layer of the first conductivity type for supplying the potential to the second well region, the first and second tap diffused layers being arranged substantially on a diagonal line in the layout of the SRAM cell, and a metal interconnection connected to the first and second tap diffused layers, the metal interconnection passing on the third well region in the SRAM cell. | 2009-04-09 |
| 20090091965 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 2009-04-09 |
| 20090091966 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 2009-04-09 |
| 20090091967 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 2009-04-09 |
| 20090091968 | INTEGRATED CIRCUIT INCLUDING A MEMORY HAVING A DATA INVERSION CIRCUIT - An integrated circuit includes an array of resistivity changing memory cells. The integrated circuit includes a circuit configured to invert a data word to be written to the array in response to determining that writing the inverted data word would use less power than writing the non-inverted data word. | 2009-04-09 |
| 20090091969 | RESISTANCE CHANGE MEMORY - A resistance change memory includes a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state, a first replica cell which is connected to a second node, generates a write voltage for programming from the first resistance state to the second resistance state, and is fixed in the first resistance state, and a first constant-current source connected to the second node, wherein when writing the second resistance state in the memory cell, a voltage of the first node is held equal to that of the second node. | 2009-04-09 |
| 20090091970 | SEMICONDUCTOR MEMORY DEVICE - Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell. | 2009-04-09 |
| 20090091971 | Semiconductor phase change memory using multiple phase change layers - In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized. | 2009-04-09 |
| 20090091972 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - The disclosure concerns a memory including a floating body provided in a semiconductor layer between a source and a drain and storing data; a first gate dielectric provided on a first surface of the body; a first gate electrode provided on the first surface via the first gate dielectric; a second gate dielectric provided on a second surface of the body different from the first surface; a second gate electrode provided on the second surface via the second gate dielectric; a driver driving the first gate electrode and the second gate electrode; and a sense amplifier writing into the memory cells first data showing a sate of a small charge amount in a state that a voltage of the second gate electrode at a data writing time is brought closer to a potential of the source layer than a voltage of the second gate electrode at a data holding time. | 2009-04-09 |
| 20090091973 | REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE - The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative voltage followed by a positive V | 2009-04-09 |
| 20090091974 | Methods of programming non-volatile memory cells - A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit. | 2009-04-09 |
| 20090091975 | Non-volatile memory device and operation method of the same - Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. | 2009-04-09 |
| 20090091976 | Integrated Circuit with Switching Unit for Memory Cell Coupling, and Method for Producing an Integrated Circuit for Memory Cell Coupling - An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element. | 2009-04-09 |
| 20090091977 | METHOD AND SYSTEM FOR UPDATING A STORED DATA VALUE IN A NON-VOLATILE MEMORY - The invention provides a method of updating a stored data value in a non-volatile memory. The method includes reading the stored data value from the non-volatile memory; reading a stored differential value from a volatile memory; receiving an updated data value; calculating a calculated differential value from the difference between the updated data value and the sum of the stored data value and the stored differential value; comparing the calculated differential value with a threshold differential value; and writing the updated data value to the non-volatile memory if the calculated differential value exceeds the threshold differential value. The invention further provides a related memory system. | 2009-04-09 |
| 20090091978 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method under limited system resources is provided, the wear levelling method is suitable for a non-volatile memory, the non-volatile memory is substantially divided into a plurality of blocks, and the blocks are at least grouped into a data area, a spare area and a substitution-transient area. The blocks within the data area may be divided into a plurality of lately-used blocks and a plurality of lately-unused blocks. The method includes only recording erase times of the lately-used blocks and blocks within the spare area and selecting a block used for the substitution-transient area is selected from the spare area according to a judgment condition of erase times of another block within the spare area plus a first threshold value. The method also includes performing a wear leveling procedure. Wherein, the selected block and the other block are selected in a random mode or a sequential mode. | 2009-04-09 |
| 20090091979 | RELIABLE DATA STORAGE IN ANALOG MEMORY CELLS IN THE PRESENCE OF TEMPERATURE VARIATIONS - A method for data storage includes programming a first group of analog memory cells at a first time at a known first temperature, so as to cause the analog memory cells in the first group to assume respective first analog storage values. Respective second analog storage values are read from the analog memory cells in the first group at a second time at which the analog memory cells are at a second temperature. A shift is estimated between the first analog storage values and the second analog storage values, and a memory access parameter is adjusted responsively to the estimated shift. A second group of the analog memory cells is accessed at the second temperature using the adjusted memory access parameter. | 2009-04-09 |
| 20090091980 | SEMICONDUCTOR INTEGRATED CIRCUIT - In the semiconductor integrated circuit incorporating non-volatile memory that is not electrically rewritable, updating stored data and reusing the non-volatile memory are made possible. The data stored in the non-volatile memory can be updated and the non-volatile memory can be reused by dividing the non-volatile memory into a plurality of blocks and replacing a used block with an unused block. When data “1” is set in the first flag of a certain block, a block selection circuit judges that data is already written in the block and rewriting new data into the block is not possible. To update the stored data, the updated data is written into a block that is selected by the block selection circuit out of the rest of the blocks. At that time, the first flag of the block is set to data “1”. Stored data is updated one after another as described above. When data of final update is written into a certain block, the second flag of the block is set to data “1”. | 2009-04-09 |
| 20090091981 | NONVOLATILE MEMORY DEVICE WITH MULTIPLE PAGE REGIONS, AND METHODS OF READING AND PRECHARGING THE SAME - A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line. The nonvolatile memory devices also includes a first common source line connecting with the memory cells of the first page region, and a second common source line connecting with the memory cells of the second page region. The first and second common source lines are controlled independently. | 2009-04-09 |
| 20090091982 | EXTERNAL CLOCK TRACKING PIPELINED LATCH SCHEME - A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second command latch input, and a command latch output, the first command latch input to couple to the command decoder output, and the second command latch input to couple to a write command output of an internal clock control generator; and a command register including a first command register input and a second command register input, the first command register input to couple to the command latch output, and the second command register input to couple to an internal latch command output of the internal clock control generator. Additional apparatus, systems, and methods are disclosed. | 2009-04-09 |
| 20090091983 | NON-VOLATILE MEMORY STRUCTURE AND ARRAY THEREOF - A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively. | 2009-04-09 |
| 20090091984 | MEMORY CONFIGURATION OF A COMPOSITE MEMORY DEVICE - The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of other flash memory array is enable when the plural sector flash memory array is gained access. | 2009-04-09 |
| 20090091985 | INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND CONTROL METHOD OF THE SAME - An input circuit of a semiconductor memory apparatus includes a first frequency control unit which receives a first signal and a second frequency control unit which receives a second signal. The first frequency control unit outputs the first signal to the second frequency control unit in response to a test mode signal and generates a third signal which has a frequency higher than the frequencies of the first and second signals by using the first and second signals. Also, the second frequency control unit outputs the second signal to the first frequency control unit in response to the test mode signal and generates a fourth signal which has a frequency higher than the frequencies of the first and second signals by using the first and second signals. | 2009-04-09 |
| 20090091986 | CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR A LINEAR OUTPUT DRIVER - Embodiments are described for an output driver circuit capable of maintaining a substantially constant output impedance across a wide range of output voltages. The driver circuit includes a pull-up circuit and a pull-down circuit, each having two or more current paths that either source currents to or sink currents from the output node. The addition of the third current path provides additional current such that the sum of the total currents have a magnitude that changes linearly as the output voltage at the output node is being driven. | 2009-04-09 |
| 20090091987 | Multiple memory standard physical layer macro function - A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers. | 2009-04-09 |
| 20090091988 | Writing bit alterable memories - A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply voltage and then mirrored using a pump voltage. In some embodiments, the mirroring may be ratioed at the partition level and multiplied at the plane level. A delay may be provided before applying the currents to the cell to accommodate for transients. | 2009-04-09 |
| 20090091989 | SEMICONDUCTOR MEMORY DEVICE AND BIASING METHOD THEREOF - The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device which controls the voltage supplied to a dummy bit line and a biasing method thereof. The semiconductor memory device includes: a dummy bit line disposed in a cell array; and a switching unit which switches the supply of a bias voltage to the dummy bit line by a control signal related to an operation of the cell array. | 2009-04-09 |
| 20090091990 | Apparatus and method of multi-bit programming - Disclosed are a multi-bit programming apparatus and a multi-bit programming method. The multi-bit programming apparatus may include a first control unit that may generates 2 | 2009-04-09 |
| 20090091991 | Apparatuses and methods for multi-bit programming - Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus includes a page buffer configured to store first data of the page programming operation, an input control unit configured to determine whether to invert the first data based on a number of bits having a first value and a number of bits having a second value. The input control unit is further configured to invert the first data to generate second data if the number of bits having a first value is greater than the number of bits having a second value and store the second data in the page buffer. The multi-bit programming apparatus further includes a page programming unit configured to program the second data stored in the page buffer in at least one multi-bit cell. | 2009-04-09 |
| 20090091992 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus include an internal tuning unit that can tune a generation timing of a data input strobe signal according to input timings of an input data and a data strobe clock signal, and a data input sense amplifier that can transmit data bits to a global line in response to the data input strobe signal. | 2009-04-09 |
| 20090091993 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY CELL TEST METHOD - A semiconductor storage device includes: a memory section including memory cell groups; a redundancy circuit which stops to access the memory section when the redundancy circuit section is activated, and to activate one of the redundancy memory cell groups corresponding to an address signal when the redundancy circuit section is activated; a redundancy decoder which accesses one of the redundancy memory cell groups corresponding to an input selection signal; and a decoder which accesses one of the memory cell groups corresponding to an input address signal, and stops to access the memory cell groups in response to a selection signal. In a normal mode, an access to the redundancy memory section is permitted. In a redundancy circuit inactivation mode, an access to the redundancy memory section is prohibited. Memory tests of a storage device under various conditions can be performed in a short time. | 2009-04-09 |
| 20090091994 | SYSTEM AND METHOD FOR INITIATING A BAD BLOCK DISABLE PROCESS IN A NON-VOLATILE MEMORY - A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid command, a process for disabling access to the defective portions of the array of non-volatile memory is initiated in addition to executing the initial valid command. One implementation provides receiving a memory command and determining whether an indicator has been set. In response to the indicator not being set, access to defective regions of the array of non-volatile memory is disabled in addition to executing the memory command. The indicator is also set to prevent the disabling process from being performed in response to receipt of subsequent memory commands. | 2009-04-09 |
| 20090091995 | SENSE AMPLIFIER CIRCUIT HAVING CURRENT MIRROR ARCHITECTURE - A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit. | 2009-04-09 |
| 20090091996 | Solid state semiconductor storage device with temperature control function, application system thereof and control element thereof - A solid state semiconductor storage device with temperature control function comprises a non-volatile memory unit, a temperature sensing element, and a control unit. The temperature sensing element is used for sensing the operation temperature of the solid state semiconductor storage device so as to provide a temperature sensing signal to the control unit. According to the temperature sensing signal, the control unit controls the operation mode of the solid state semiconductor storage device for achieving the function of temperature control. | 2009-04-09 |
| 20090091997 | SEMICONDUCTOR MEMORY DEVICE SUITABLE FOR MOUNTING ON PORTABLE TERMINAL - A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register. | 2009-04-09 |
| 20090091998 | POWER SAVING METHOD AND CIRCUIT THEREOF FOR A SEMICONDUCTOR MEMORY - A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated. | 2009-04-09 |
| 20090091999 | LEAKAGE OPTIMIZED MEMORY - A method of power optimization in a memory is disclosed. The method generally includes the steps of (A) dividing a plurality of bit cells in a design of the memory into (i) a plurality of first rows storing programmed data and (ii) at least one second row storing only padding data, (B) adjusting the design such that a second power consumption in each of the second rows is lower than a first power consumption in each of the first rows and (C) generating a file defining the design as adjusted. | 2009-04-09 |
| 20090092000 | SEMICONDUCTOR MEMORY DEVICE WITH REDUCED CURRENT CONSUMPTION - A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal. | 2009-04-09 |
| 20090092001 | SOLUTION MAKING SYSTEM AND METHOD - A solution making system and apparatus are described. The solution maker mixes a chemical or slurry with a solvent to a desired concentration. The concentration of the solution is monitored by one or more methods. Based upon this measurement, the concentration of the solution may be adjusted. | 2009-04-09 |
| 20090092002 | ACOUSTIC COMMUNICATION AND CONTROL FOR SEISMIC SENSORS - A method for wireless communication in a seismic sensor network is disclosed. The method comprises providing a first acoustic device having at least one seismic sensor with communication and control data to communicate over an acoustic energy wave on a first communications channel. The first acoustic device generates the acoustic energy wave with a first wave intensity. The first acoustic device is configured to receive a reflection of the generated wave at a prescribed signal sensitivity level based on a network configuration. If the first wave intensity is below the prescribed signal sensitivity level, the first wave intensity of the acoustic energy wave is tuned to the prescribed signal sensitivity level to interpret the communication and control data provided by the first communications channel. | 2009-04-09 |
| 20090092003 | CONTROLLING A SEISMIC SURVEY TO REDUCE THE EFFECTS OF VIBRATION NOISE - A technique includes towing a particle motion sensor in connection with a seismic survey and controlling the survey to cause a notch in a frequency response of the particle motion sensor to substantially coincide with a frequency band at which aliased vibration noise appears in a seismic signal acquisition space of the particle motion sensor. | 2009-04-09 |
| 20090092004 | MARINE SEISMIC STREAMER STEERING APPARATUS - Marine seismic streamer steering apparatus are described having an elongate body, at least a portion of which is positioned eccentric of a marine seismic streamer, the apparatus having stability features selected from: one or more lateral steering control surfaces providing a center of lift approximately through a vertical streamer axis; one or more buoyancy elements providing a center of buoyancy through the same or a different vertical axis approximately through the center of the streamer; and combinations thereof. The apparatus have improved stability and avoid heeling during use. | 2009-04-09 |
| 20090092005 | CONTROLLING SEISMIC SOURCE ELEMENTS BASED ON DETERMINING A THREE-DIMENSIONAL GEOMETRY OF THE SEISMIC SOURCE ELEMENTS - To control a seismic source having plural seismic source elements, a three-dimensional geometric shape of the plural seismic source elements is determined. Timings of activation of the plural seismic source elements is adjusted according to the determined three-dimensional geometric shape. | 2009-04-09 |
| 20090092006 | SEISMIC STREAMER PLATFORM - A technique includes designing a streamer, which includes a cable and seismic sensors based at least in part on a relationship between vibration noise and a bending stiffness of the cable. | 2009-04-09 |
| 20090092007 | IDENTIFYING AN INTERNAL MULTIPLE GENERATOR IN A SUBTERRANEAN STRUCTURE - A technique is provided for identifying an internal multiple generator in a subterranean structure. The technique includes injecting wavefields at different levels in the subterranean structure, where the different levels are proximate a predicted location of the internal multiple generator. Wavefields induced by the injected wavefields are recorded and the effect of the internal multiple generator based on the recorded wavefields is determined. | 2009-04-09 |
| 20090092008 | APPARATUS FOR DIARIZING JANITORIAL SERVICE - The invention provides an apparatus for diarizing the performance of janitorial services that includes an electronic display unit for indicating when a service was last completed and an input device for signalling when the display is to be updated. The apparatus can include a chassis mountable on a wall of a facility being maintained by a janitorial service, and at least one electronic display framed by a window on said chassis, said chassis for displaying a time when said facility was last maintained. The apparatus can also include a central processing unit connected to said display and for updating the display based on a user-input received from an input device that is mounted to said chassis and connected to the central processing unit. The input device is actuated at a time that is substantially coterminous when said facility was last maintained. | 2009-04-09 |
| 20090092009 | Runout detection method - A method for determining runout disc is disclosed. The method comprises: focusing on a focal point on a disc; driving the disc to spin the disc; generating a crossover signal according to a track of the disc crossing the focal point; and determining that the disc is a runout disc when the frequency of the crossover signal exceeds a pre-determine value. | 2009-04-09 |
| 20090092010 | METHOD AND APPARATUS FOR DETERMINING WRITE STRATEGY PARAMETER VALUES FOR WRITING DATA ON AN OPTICAL DISK - The invention relates to a method for determining write strategy parameter values for writing data on an optical disk from a group of optical disks of different types using an optical disk drive, in particular to different types of BD disks. The method includes identifying the type of optical disk, the type of optical disk being associated with a standard write strategy with standard write strategy parameters; determining a cluster write strategy with cluster write strategy parameters, the number of cluster write strategy parameters being smaller than the number of standard write strategy parameters; initializing the cluster write strategy parameters with initial cluster write strategy parameter values; and optimizing cluster write strategy parameter values for at least a subset of the cluster write strategy parameters. The optimizing is preferably performed on optimization sets of cluster write strategy parameters in a pre-determined optimization order. | 2009-04-09 |
| 20090092011 | RECORDING AND REPRODUCING DEVICE - A recording and reproducing device ( | 2009-04-09 |
| 20090092012 | DEVICE AND METHOD OF RECORDING/REPRODUCING INFORMATION INTO/FROM A MEDIUM - A method for recording/reproducing data to/from a medium by which a table is formed for assigning physical addresses of spare areas of the medium to make the physical addresses be continuous with the last address of logical addresses of a user data recording area, and recording/reproducing is performed by using the table. The physical address of an unused spare area is assigned to make the physical address be continuous with the last address of the logical addresses of the user data recording area. It is therefore possible to use the unused spare area as the user data recording area and to effectively utilize the unused spare area. | 2009-04-09 |
| 20090092013 | OPTICAL DISC APPARATUS, INFORMATION RECORDING METHOD AND INFORMATION RECORDING MEDIUM - When executing an replacement process on a multi-layer recording optical disc, alternate recording regions are successively used starting at the nearest spare area from an objective lens regardless of the layer where the replacement process is generated. Alternatively, in the spare area of each layer, a priority spare area is provided for executing an alternation with a higher priority by shifting the radial position from the other layer. Alternatively, arrangement is performed so that the radial position or the alternative recording start radial position of the spare area of each layer is not superposed on the upper or the lower layer spare area. | 2009-04-09 |
| 20090092014 | Recording device and recording method - A recording device for performing recording supporting an optical disk-shaped recording medium having a laminated structure includes a first recording layer and a second recording layer. The recording device includes: a recording section configured to record data in the first recording layer and the second recording layer by irradiating the optical disk-shaped recording medium with laser light; a recording control section configured to control the recording section so as to perform recording in the first recording layer first and next perform recording in the second recording layer when the recording is performed sequentially on the optical disk-shaped recording medium; a pseudo defect area setting section configured to set a pseudo defect area in the second recording layer; and a defect registering section configured to register the real defect area and the pseudo defect area as a defect area. | 2009-04-09 |
