| 15th week of 2009 patent applcation highlights part 11 |
| Patent application number | Title | Published |
|---|
| 20090090913 | DUAL-GATE MEMORY DEVICE WITH CHANNEL CRYSTALLIZATION FOR MULTIPLE LEVELS PER CELL (MLC) - A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an amorphous semiconductor material. The amorphous semiconductor material may include, for example, silicon. Mobility enhancement may be achieved by: (a) Excimer laser annealing; (b) lateral crystallization; (c) metal-induced lateral crystallization; (d) a combination of laser annealing and metal-induced laterally crystallization steps; or (e) solid-phase, epitaxially growth. | 2009-04-09 |
| 20090090914 | SEMICONDUCTOR THIN FILM, METHOD FOR PRODUCING THE SAME, AND THIN FILM TRANSISTOR - A transparent semiconductor thin film | 2009-04-09 |
| 20090090915 | THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and methods for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a pair of buffer layers formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the pair of buffer layers, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes the impurity element which serves as a donor. | 2009-04-09 |
| 20090090916 | THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor. | 2009-04-09 |
| 20090090917 | GaN single-crystal substrate and method for producing GaN single crystal - A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm | 2009-04-09 |
| 20090090918 | TRANSPARENT NANOCRYSTALLINE DIAMOND CONTACTS TO WIDE BANDGAP SEMICONDUCTOR DEVICES - A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n− and p− SiC epilayers. I-V measurements on p+ NCD/n− SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film. | 2009-04-09 |
| 20090090919 | Semiconductor device and method of producing the same - A semiconductor device includes a silicon carbide substrate having a channel region formed on a surface thereof; a silicon layer formed on the channel region; a gate insulation film formed on the silicon layer; and a gate electrode formed on the gate insulation film. A method of producing a semiconductor device includes the steps of: forming a silicon layer on a surface of a silicon carbide substrate; forming a gate insulation film on the silicon layer to form a laminated structure of the silicon layer and the gate insulation film; and forming a gate electrode on the gate insulation film. | 2009-04-09 |
| 20090090920 | Silicon carbide semiconductor device - A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second conductivity type, and located in a surface portion of the drift layer; and a first conductivity type region located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration higher than the drift layer. | 2009-04-09 |
| 20090090921 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE - A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting layer; and a p-type nitride semiconductor layer formed on the active layer. | 2009-04-09 |
| 20090090922 | METHOD OF MANUFACTURING GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - Provided are a method of manufacturing a gallium nitride-based compound semiconductor light-emitting device with a low driving voltage (Vf) and high light outcoupling efficiency, a gallium nitride-based compound semiconductor light-emitting device, and a lamp. In the method of manufacturing the gallium nitride-based compound semiconductor light-emitting device, a transparent conductive oxide film | 2009-04-09 |
| 20090090923 | METHOD FOR MANUFACTURING A SEMICONDUCTOR LIGHT-EMITTING DEVICE AND SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device and method for manufacturing the semiconductor light-emitting device includes a mask layer etching process on first and second mask layers provided on a Group-III nitride-based compound semiconductor substrate, the mask layer with a higher etching rate being closer to the p-type semiconductor layer; a semiconductor layer etching process; a side-etching process that selectively etches the side of the mask layer with the high etching rate to define a groove portion with a portion of the p-type semiconductor layer exposed; a ZrO | 2009-04-09 |
| 20090090924 | INTERMEDIATE OPTICAL PACKAGES AND SYSTEMS COMPRISING THE SAME, AND THEIR USES - Methods and apparatuses for forming optical packages, and intermediate structures resulting from the same are disclosed, which provide an optical element over a device. The optical element is formed by applying a force to lateral portions of a liquid material layer formed below an elastomeric material layer such that the liquid material layer has a radius of curvature sufficient to direct light to a light sensitive portion of the device, after which the liquid material layer is exposed to conditions which maintain the radius of curvature after the lateral force is removed. | 2009-04-09 |
| 20090090925 | SEMICONDUCTOR DEVICE - There are a silicon laser device having a IV-group semiconductor such as silicon or germanium equivalent to the silicon as a basic constituent element on a substrate made of the silicon, and the like by a method capable of easily forming the silicon laser device by using a general silicon process, and a manufacturing method thereof. The silicon laser device is an ultrathin silicon laser that includes a first electrode unit injecting electrons, a second electrode unit injecting holes, a light emitting unit electrically connected to the first electrode unit and the second electrode unit, wherein the light emitting unit is made of single-crystal silicon and has a first surface (top surface) and a second surface (bottom surface) opposed to the first surface, a waveguide made of a first dielectric, which is disposed in the vicinity of the light emitting unit, by setting surface directions of the first and second surfaces as a surface (100) and thinning a thickness of the light emitting unit in a direction perpendicular to the first and second surfaces, and a mirror formed by alternately adjoining the first dielectric and a second dielectric. | 2009-04-09 |
| 20090090926 | SOLID STATE LIGHT EMITTING DEVICE - A solid state light emitting device includes a laminated substrate structure ( | 2009-04-09 |
| 20090090927 | Structure of light emitted diode package - A structure of light emitted diode package including a lead frame, a holder coupled on an end of the lead frame, a LED chip disposed on the holder, a lower sealing portion made by injection molding a first resin material to grab one end of lead frame with the LED chip in order to hold the lead frame and an upper sealing portion made by casting by a second resin material to dispose on the top of the lower sealing portion. | 2009-04-09 |
| 20090090928 | LIGHT EMITTING MODULE AND METHOD FOR MANUFACTURING THE SAME - Provided are: a light emitting module capable of ensuring a high heat-dissipating property and mountable in any of sets in various shapes; and a method for manufacturing the light emitting module. The light emitting module mainly includes: a metal substrate; an insulating layer covering the upper surface of the metal substrate; a conductive pattern formed on the upper surface of the insulating layer; and a light emitting element fixedly attached to the upper surface of the metal substrate and electrically connected to the conductive pattern. Furthermore, a groove is formed in the metal substrate, and then the metal substrate is bent. Thus, a bent portion is formed in the metal substrate. | 2009-04-09 |
| 20090090929 | LIGHT-EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) chip includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer and a groove. The first semiconductor layer, active layer and second semiconductor layer are formed on the substrate in sequence. The groove is formed in the first semiconductor layer, the active layer and the second semiconductor layer. | 2009-04-09 |
| 20090090930 | EPITAXIAL SUBSTRATE AND MANUFACTURING METHOD THEREOF AND MANUFACTURING METHOD OF LIGHT EMITTING DIODE APPARATUS - A manufacturing method of an epitaxial substrate includes the steps of: forming a sacrificial layer, which has a first micro/nano structure, on a substrate; and forming a buffer layer on the sacrificial layer. The sacrificial layer comprises a plurality of micro/nano particles, and the first micro/nano structure is formed after the plurality of micro/nano particles are removed. An epitaxial substrate and a manufacturing method of a light emitting diode (LED) apparatus are also disclosed. | 2009-04-09 |
| 20090090931 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a buffer layer, a corrosion-resistant film, a multi-layer structure, and an ohmic electrode structure. The buffer layer is grown on an upper surface of the substrate. The corrosion-resistant film is deposited to overlay the buffer layer The multi-layer structure is grown on the corrosion-resistant film and includes a light-emitting region. The buffer layer assists the epitaxial growth of a bottom-most layer of the multi-layer structure. The corrosion-resistant film prevents the buffer layer from being corroded by a gas during the epitaxial growth of the bottom-most layer. The ohmic electrode structure is deposited on the multi-layer structure. | 2009-04-09 |
| 20090090932 | NITRIDE SEMICONDUCTOR ULTRAVIOLET LEDS WITH TUNNEL JUNCTIONS AND REFLECTIVE CONTACT - A structure and method for improving UV LED efficiency is described. The structure utilizes a tunnel junction to separate a P-doped layer of the LED from a n-doped contact layer. The n-doped contact layer allows the use of a highly reflective, low work function metal, such as aluminum, for the p-side contact. The reflectivity at the contact can be further improved by including a phase matching layer in some areas between the contact metal (The metal above the phase matching layer does not necessarily need to have a low work function because it does need to form an ohmic contact with the n-contact layer) and the n-doped contact layer. | 2009-04-09 |
| 20090090933 | METHOD OF PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THE SAME - A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer | 2009-04-09 |
| 20090090934 | Field Effect Transistor and Method for Manufacturing the Same - A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode. | 2009-04-09 |
| 20090090935 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 2009-04-09 |
| 20090090936 | ELECTRIC FIELD READ/WRITE HEAD, METHOD OF MANUFACTURING THE SAME, AND INFORMATION STORAGE DEVICE COMPRISING ELECTRIC FIELD READ/WRITE HEAD - Provided is an electric field head including a resistance sensor to read information recorded on a recording medium. The resistance sensor includes a first semiconductor layer including a source and a drain, and a second semiconductor layer that is heterogeneously combined with the first semiconductor layer. Also, the electric field head further includes a channel between the source and the drain, in a junction region of the first and second semiconductor layers. | 2009-04-09 |
| 20090090937 | Unit pixels, image sensor containing unit pixels, and method of fabricating unit pixels - Example embodiments provide a unit pixel, an image sensor containing unit pixels, and a method of fabricating unit pixels. The unit pixel may include a semiconductor substrate, photoelectric transducers formed within the semiconductor substrate, multi-layered wiring layers formed on a frontside of the semiconductor substrate, inner lenses formed on a backside of the semiconductor substrate corresponding to the photoelectric transducers, and microlenses formed above the inner lenses. | 2009-04-09 |
| 20090090938 | CHANNEL STRESS ENGINEERING USING LOCALIZED ION IMPLANTATION INDUCED GATE ELECTRODE VOLUMETRIC CHANGE - A method for fabricating a semiconductor structure uses a volumetric change ion implanted into a volumetric change portion of a gate electrode that is located over a channel region within a semiconductor substrate to form a volume changed portion of the gate electrode located over the channel region within the semiconductor substrate. The volume changed portion of the gate electrode is typically bidirectionally symmetrically graded in a vertical direction. The volume-changed portion of the gate electrode has a first stress that induces a second stress different than the first stress into the channel region of the semiconductor substrate. | 2009-04-09 |
| 20090090939 | SELF-ASSEMBLED SIDEWALL SPACER - A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self-assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that utilizes self-assembled block copolymer technology. | 2009-04-09 |
| 20090090940 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes a first insulating layer over a first substrate, a transistor over the first insulating layer, a second insulating layer over the transistor, a first conductive layer connected to a source region or a drain region of the transistor through an opening provided in the second insulating layer, a third insulating layer over the first conductive layer, and a second substrate over the third insulating layer. The transistor comprises a semiconductor layer, a second conductive layer, and a fourth insulating layer provided between the semiconductor layer and the second conductive layer. One or plural layers selected from the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer have a step portion which is provided so as not to overlap with the transistor. | 2009-04-09 |
| 20090090941 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between. | 2009-04-09 |
| 20090090942 | Wiring structure, array substrate, display device having the same and method of manufacturing the same - A wiring structure includes a substrate, a copper oxide layer having 16˜39 at % oxygen on the substrate and a copper layer on the copper oxide layer. The copper oxide layer has a thickness of 10-1000 Å and the copper layer has a thickness of 300-8000 Å. The copper layer and the copper oxide layer further have an alloy element less than 10 wt % and the alloy element is selected from the group of Ag, Ni, Mg, Zr, N. | 2009-04-09 |
| 20090090943 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD OF THE SAME - A solid-state imaging device of the present invention includes: a semiconductor substrate including a first region of a first conductivity type; a signal accumulation region of a second conductivity type formed within the first region; a gate electrode formed above the first region; a drain region of a second conductivity type formed on the first region; an isolation region having insulation properties, which is formed to surround a region where the signal accumulation region, the gate electrode, and the drain region are formed; a first conductivity type dopant doping region formed in contact with a side face and a bottom face of the isolation region, the first conductivity type dopant doping region having a higher dopant concentration than the first region; and a second conductivity type dopant doping region formed in the first is region, under an end of the gate electrode in a gate width direction. | 2009-04-09 |
| 20090090944 | Image Sensor and Method of Fabricating the Same - Provided is an image sensor and a method of fabricating the image sensor. The image sensor can comprise: a semiconductor substrate comprising a photodiode; a metal wiring layer disposed on the semiconductor substrate and comprising a metal wiring and an interlayer dielectric; a trench formed in the interlayer dielectric to correspond to the photodiode; and a color filter formed in the trench. Accordingly, the distance between the photodiode and the color filter can be significantly reduced by forming the color filter in the trench. | 2009-04-09 |
| 20090090945 | PIXEL WITH TRANSFER GATE WITH NO ISOLATION EDGE - A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench isolation. The transfer transistor gate does not overlap the shallow trench isolation region. | 2009-04-09 |
| 20090090946 | DRAM CELL WITH MAGNETIC CAPACITOR - A DRAM cell includes a substrate, a transistor, and a magnetic capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the magnetic capacitor is formed in a metal layer. The transistor includes a source region and a drain region formed at the main surface of the substrate. The transistor also includes a control gate placed between the source region and the drain region, and separated from the substrate by a thin control dielectric. The magnetic capacitor includes a first electrode layer, a dielectric layer formed on the surface of the first electrode layer, and a second electrode layer formed on the surface of the dielectric layer. The DRAM cell increases the density, simplifies the manufacturing process, and reduces or eliminates the refresh rate. A DRAM cell with the magnetic capacitor formed in multiple layers is also provided. | 2009-04-09 |
| 20090090947 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first area and a second area, a first active structure disposed in the first area, a second active structure disposed in the second area, a first transistor disposed in the first area and a second transistor disposed in the second area. The second active structure may have a height substantially the same as a height of the first active structure. The first transistor includes a first gate structure enclosing an upper portion of the first active structure, a first impurity region formed at a lower portion of the first active structure, and a second impurity region formed at the upper portion of the first active structure. The second transistor includes a second gate structure formed on the second active structure and third impurity regions formed at an upper portion of the second active structure. | 2009-04-09 |
| 20090090948 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process. A first capacitor is formed between an active region of a semiconductor substrate provided through a first capacitive insulating film and a lower electrode comprised of a conductor film in the same layer as a select gate electrode of a select, a second capacitor is formed between the lower electrode, and an upper electrode comprised of a conductor film in the same layer as a memory gate electrode of a memory, provided through the second capacitive insulating film in the same layer as the insulating films of a multi-layer structure, including a charge storage layer, and a stacking-type capacitive element is comprised of the first capacitor and the second capacitor, wherein a planar shape of the lower electrode is a grid-like shape having a plurality of lengths of linear conductor films each having a first width, formed along a first direction with a first interval provided therebetween, and a plurality of lengths of linear conductor films each having a second width, formed along a second direction (the direction intersecting the first direction) with a second interval provided therebetween. | 2009-04-09 |
| 20090090949 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: an active region insulated by an element-isolation insulating film embedded on a semiconductor substrate; multiple element forming sections that are provided in the active region; a semiconductor element that is formed in each of the element forming sections; and a channel stopper that is provided in the active region to insulate the element forming sections from each other. The channel stopper comprises: a fin that protrudes between grooves provided in the element-isolation insulating film and on both sides of the active region; a dummy-gate insulating film that covers the fin; and a dummy gate electrode that straddles the fin. | 2009-04-09 |
| 20090090950 | SEMICONDUCTOR DEVICES - Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer. | 2009-04-09 |
| 20090090951 | Capacitors Integrated with Metal Gate Formation - A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode. | 2009-04-09 |
| 20090090952 | PLASMA SURFACE TREATMENT FOR SI AND METAL NANOCRYSTAL NUCLEATION - A device, such as a nonvolatile memory device, and methods for forming the device in an integrated process tool are provided. The method includes depositing a tunnel oxide layer on a substrate, exposing the tunnel oxide layer to a plasma so that the plasma alters a morphology of a surface and near surface of the tunnel oxide to form a plasma altered near surface. Nanocrystals are then deposited on the altered surface of the tunnel oxide. | 2009-04-09 |
| 20090090953 | FLASH MEMORY DEVICE WITH STRAIGHT WORD LINES - Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation. | 2009-04-09 |
| 20090090954 | NONVOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate. Therefore, a nonvolatile memory capable of miniaturization can be provided. | 2009-04-09 |
| 20090090955 | ELEVATED CHANNEL FLASH DEVICE AND MANUFACTURING METHOD THEREOF - A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate is disposed on top of the protrusive portion and sandwiched between the two floating gates. The dielectric layer is disposed between each of the two floating gates and the control gate. Because the control gate of the FLASH device is disposed on the protrusive portion, an elevated channel can be formed. Moreover, because of the position of the two floating gates, an effective floating gate (FG) length can be increased without impacting the cell density. | 2009-04-09 |
| 20090090956 | Flash Memory Device and Method of Manufacturing Flash Memory Device - Provided is a flash memory device and a method of manufacturing the same. In the method, a tunnel oxide layer pattern and a first polysilicon pattern are formed on a semiconductor substrate. A first dielectric layer including a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer and a third oxide layer is formed on the semiconductor substrate including the first polysilicon pattern. A second polysilicon pattern is formed on the dielectric layer pattern. The flash memory device includes a tunnel oxide layer pattern and a first polysilicon pattern on a semiconductor substrate; a dielectric layer on the first polysilicon pattern, including a first oxide layer pattern, a first nitride layer pattern, a second oxide layer pattern, a second nitride layer pattern and a third oxide layer pattern; and a second polysilicon pattern on the dielectric layer pattern. | 2009-04-09 |
| 20090090957 | Multi-valued mask ROM - A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first and second nodes, respectively. A first memory cell out of the plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between the first and second nodes. The resistance of the first resistive interconnection is adjusted depending on data stored onto the first memory cell. | 2009-04-09 |
| 20090090958 | Semiconductor Constructions - Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O | 2009-04-09 |
| 20090090959 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second semiconductor layer provided in contact with the first semiconductor layer. A third lamination part includes: a plurality of first contact layers formed in contact with the respective second lamination part, extending to a first direction perpendicular to the lamination direction, and in line with each other along a second direction perpendicular to the first direction; and a plurality of contact plug layers formed in contact with any one of the first contact layers and extending to the lamination direction. The contact plug layers are arranged at different positions relative to each other in the first direction. | 2009-04-09 |
| 20090090960 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer. | 2009-04-09 |
| 20090090961 | Non-Volatile Semiconductor Memory Device - A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric. | 2009-04-09 |
| 20090090962 | Nonvolatile semiconductor memory and method of manufacturing the same - A nonvolatile semiconductor memory device includes: a semiconductor substrate; a first gate electrode formed on the semiconductor substrate through a gate insulating film; a second gate electrode formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode; and an insulating film formed at least between the semiconductor substrate and the second gate electrode to trap electric charge, as an electric charge trapping film. The first gate electrode comprises a lower portion contacting the gate insulating film and an upper portion above the lower portion of the first gate electrode, and a distance between the upper portion of the first gate electrode and the second gate electrode is longer than a distance between the lower portion of the first gate electrode and the second gate electrode. | 2009-04-09 |
| 20090090963 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A plurality of memory cells each constituted of a memory cell transistor having a gate electrode in a laminated structure composed of a charge storage layer and a control gate layer and a select transistor having source/drain diffusion layers while one of the source/drain diffusion layers is shared by the memory cell transistor are arranged in and on a semiconductor substrate. The impurity concentration of the source/drain diffusion layer shared by the memory cell transistor and the select transistor in each of the plurality of memory cells is set lower than the impurity concentration of the other source/drain diffusion layers in each of the memory cells. | 2009-04-09 |
| 20090090964 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction. | 2009-04-09 |
| 20090090965 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer. | 2009-04-09 |
| 20090090966 | HIGH DENSITY FET WITH INTEGRATED SCHOTTKY - A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween. | 2009-04-09 |
| 20090090967 | MOSFET ACTIVE AREA AND EDGE TERMINATION AREA CHARGE BALANCE - A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson. | 2009-04-09 |
| 20090090968 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a semiconductor layer of a first conductivity type; a first main electrode provided on a frontside of the semiconductor layer; a second main electrode provided on a backside of the semiconductor layer, the backside being opposite to the frontside; a plurality of semiconductor regions of a second conductivity type provided in a surface portion of the semiconductor layer in a edge termination region outside a device region in which a main current path is formed in a vertical direction between the first main electrode and the second main electrode; and a plurality of buried semiconductor regions of the second conductivity type provided in the semiconductor layer in the edge termination region, spaced from the semiconductor regions, and spaced from each other. The buried semiconductor regions provided substantially at the same depth from the frontside of the semiconductor layer are numbered as first, second, . . . , n-th, sequentially from the one nearer to the device region, the n-th buried semiconductor regions provided at different depths from the frontside of the semiconductor layer are displaced toward the device region relative to the corresponding n-th semiconductor region, and the buried semiconductor region located deeper from the frontside of the semiconductor layer is displaced more greatly toward the device region. | 2009-04-09 |
| 20090090969 | ELECTRONIC DEVICE AND METHOD OF BIASING - A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge. | 2009-04-09 |
| 20090090970 | SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA - A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact. | 2009-04-09 |
| 20090090971 | MOSFET DEVICES AND METHODS FOR MAKING THEM - A semiconductor device is disclosed. The device comprises a first MOSFET transistor. The transistor comprises a substrate, a first high-k dielectric layer upon the substrate, a first dielectric capping layer upon the first high-k dielectric, and a first gate electrode made of a semiconductor material of a first doping level and a first conductivity type upon the first dielectric capping layer. The first dielectric capping layer comprises Scandium. | 2009-04-09 |
| 20090090972 | TUNABLE VOLTAGE ISOLATION GROUND TO GROUND ESD CLAMP - A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached. | 2009-04-09 |
| 20090090973 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a device isolation insulating film which is provided in a semiconductor substrate, and an insulated-gate field-effect transistor which is disposed adjacent to the device isolation insulating film in a gate length direction, the insulated-gate field-effect transistor including a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a pair of impurity diffusion layers which are provided spaced apart in the semiconductor substrate in a manner to sandwich the gate electrode, and a redundant impurity diffusion layer which is provided between the device isolation insulating film and one of the pair of impurity diffusion layers. | 2009-04-09 |
| 20090090974 | DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD - A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET, wherein an upper surface of the compressive stress liner is substantially planar with an upper surface of the tensile stress liner at an interface therebetween. | 2009-04-09 |
| 20090090975 | INTEGRATED CIRCUIT SYSTEM EMPLOYING FLUORINE DOPING - An integrated circuit system that includes: providing a substrate including a first integrated circuit region electrically connected to a second integrated circuit region; implanting a dielectric growth material underneath a gate for each of an NFET device and a PFET device within the first integrated circuit region and the second integrated circuit region; and annealing the integrated circuit system. | 2009-04-09 |
| 20090090976 | PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY - A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths. | 2009-04-09 |
| 20090090977 | RESISTOR AND FET FORMED FROM THE METAL PORTION OF A MOSFET METAL GATE STACK - An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack. | 2009-04-09 |
| 20090090978 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region; and a high concentration source region of a second conductivity type having a diffusion depth deeper than that of the low concentration source region. A diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET. | 2009-04-09 |
| 20090090979 | HIGH PERFORMANCE MOSFET - A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The inventive structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. Such a well region may be referred to as a non-uniform super-steep retrograde well. | 2009-04-09 |
| 20090090980 | ASYMMETRIC-LDD MOS DEVICE - The present invention proposes a new asymmetric-lightly-doped drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and compared. The output power can be improved by 38% at peak power-added efficiency (PAE). The PAE is also improved by 16% at 10-dBm output power and 2.4 GHz. These significant improvements of RF power performance by this new MOS transistor make the RF-CMOS system-on-chip design a step further. Index Terms—Lightly-doped-drain (LDD), metal oxide semiconductor field effect transistor (MOSFET), metal oxide semiconductor (MOS) transistor, radio frequency (RF) power transistor. | 2009-04-09 |
| 20090090981 | SEMICONDUCTOR DEVICE - A semiconductor device which has a high dielectric strength and allows its on resistance to be made sufficiently small is provided. This semiconductor device comprises a first electroconducive-type semiconductor layer, and a gate electrode which is disposed on a given region of an insulation film formed on the main surface of the semiconductor layer. The semiconductor layer includes: a body region of the first electroconducive type which is formed near the main surface side; a drain region of the second electroconducive type which is formed near the main surface side; and a buried region of the second electroconducive type which is formed in a position that is not right under the body region and right under at least the drain region and is connected to the drain region. | 2009-04-09 |
| 20090090982 | Ultra-abrupt semiconductor junction profile - The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant. | 2009-04-09 |
| 20090090983 | DUAL WORK FUNCTION HIGH VOLTAGE DEVICES - A transistor has a substrate having a channel region and source and drain regions within the substrate on opposite sides of the channel region. The structure includes a gate oxide above the channel region of the substrate and a gate conductor above the gate oxide. The polysilicon gate conductor comprises a source side positioned toward the source and a drain side positioned toward the drain. The source side comprises a first concentration of conductive doping and the drain side comprises a second concentration of the conductive doping that is less than the first concentration. | 2009-04-09 |
| 20090090984 | Novel Method to Increase Breakdown Voltage of Semiconductor Devices - Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN. | 2009-04-09 |
| 20090090985 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having an active region and an isolation region, a gate pattern crossing both the active region and the isolation region of the substrate, and a protrusion having a surface higher than that of the substrate over at least an edge of the active region contacting a portion of the isolation region under the gate pattern. | 2009-04-09 |
| 20090090986 | FULLY AND UNIFORMLY SILICIDED GATE STRUCTURE AND METHOD FOR FORMING SAME - Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations. | 2009-04-09 |
| 20090090987 | Mems element, mems device and mems element manufacturing method - An MEMS element (A | 2009-04-09 |
| 20090090988 | SOLID STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS - A solid state imaging device includes: a plurality of sensor sections formed in a semiconductor substrate in order to convert incident light into an electric signal; a peripheral circuit section formed in the semiconductor substrate so as to be positioned beside the sensor sections; and a layer having negative fixed electric charges that is formed on a light incidence side of the sensor sections in order to form a hole accumulation layer on light receiving surfaces of the sensor sections. | 2009-04-09 |
| 20090090989 | Image Sensor and Method of Manufacturing the Same - An image sensor and a manufacturing method thereof are provided. The image sensor can comprise: a semiconductor substrate, a first dielectric, a second dielectric pattern, a planarization layer, and a color filter. The semiconductor substrate comprises a photodiode. The first dielectric is disposed on the semiconductor substrate. The second dielectric pattern is disposed on the first dielectric and comprises a trench in a region corresponding to the photodiode. The planarization layer is disposed in the trench. The color filter is disposed on the planarization layer disposed on the photodiode. | 2009-04-09 |
| 20090090990 | FORMATION OF NITROGEN CONTAINING DIELECTRIC LAYERS HAVING AN IMPROVED NITROGEN DISTRIBUTION - Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region. | 2009-04-09 |
| 20090090991 | Method for Manufacturing Semiconductor Device - A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively. | 2009-04-09 |
| 20090090992 | ISOLATION TRENCH STRUCTURE FOR HIGH ELECTRIC STRENGTH - The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches ( | 2009-04-09 |
| 20090090993 | SINGLE CRYSTAL FUSE ON AIR IN BULK SILICON - An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE. | 2009-04-09 |
| 20090090994 | ELECTROMIGRATION FUSE AND METHOD OF FABRICATING SAME - Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer. | 2009-04-09 |
| 20090090995 | On-chip inductors with through-silicon-via fence for Q improvement - A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground, wherein the plurality of through-silicon-vias provide isolations for the one or more on-chip inductors. | 2009-04-09 |
| 20090090996 | SEMICONDUCTOR DEVICE WITH CONTACT STABILIZATION BETWEEN CONTACT PLUGS AND BIT LINES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate divided into a cell array region, a core region, and a peripheral region. Bit lines are formed in the respective regions. Storage node contact plugs are formed in the cell array region, and blocking patterns are simultaneously formed around the bit lines of the core region and the peripheral region. Capacitors are formed in the cell array region to come into contact with the storage node contact plugs, and metal contact plugs are formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region. In the semiconductor device, even if the metal contact plugs are not aligned with the bit lines, the blocking pattern works to stabilize the contact between the metal contact plugs and the bit lines. | 2009-04-09 |
| 20090090997 | SOLID ELECTROLYTIC CAPACITOR ELEMENT AND PRODUCTION METHOD THEREOF - The present invention relates to a production method of solid electrolytic capacitor element, comprising a step of forming a semiconductor layer on a surface of a conductor having a dielectric oxide film thereon and having an anode lead connected thereto by conducting electrolytic oxidation-polymerization using pyrrole dimer at around room temperature, a solid electrolytic capacitor element produced by the method, solid electrolytic capacitor using the element and uses thereof. According to the invention, low-temperature polymerizability of pyrrole, which is inexpensive, can be suppressed, whereby the invention enables production of solid electrolytic capacitor elements having a semiconductor layer formed in industrially advantageous manner. | 2009-04-09 |
| 20090090998 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first and second structures formed in a first insulating layer, a lower metal interconnection formed in the second structure, a metal-insulator-metal (MIM) capacitor formed in the first structure, and first, second and third electrodes formed in the first structure and electrically connected to the MIM capacitor. The first electrode is a chip bottom metal (CBM) layer, the second electrode is a first chip top metal (CTM) layer and the third electrode is a second chip top metal (CTM) layer. | 2009-04-09 |
| 20090090999 | HIGH PERMITTIVITY LOW LEAKAGE CAPACITOR AND ENERGY STORING DEVICE AND METHOD FOR FORMING THE SAME - A method is provided for making a high permittivity dielectric material for use in capacitors. Several high permittivity materials in an organic nonconductive media with enhanced properties and methods for making the same are disclosed. A general method for the formation of thin films of some particular dielectric material is disclosed, wherein the use of organic polymers, shellac, silicone oil, and/or zein formulations are utilized to produce low conductivity dielectric coatings. Additionally, a method whereby the formation of certain transition metal salts as salt or oxide matrices is demonstrated at low temperatures utilizing mild reducing agents. Further, a circuit structure and associated method of operation for the recovery and regeneration of the leakage current from the long-term storage capacitors is provided in order to enhance the manufacturing yield and utility performance of such devices. | 2009-04-09 |
| 20090091000 | Varactores including interconnect layers - In an embodiment of the present invention is provided a varactor comprising a substrate, a plurality of bottom electrodes positioned on a surface of the substrate separated to form a gap therein, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric at least partially overlaying the plurality of electrodes, and a top electrode in contact with the tunable dielectric. | 2009-04-09 |
| 20090091001 | CRACK RESISTANT SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a peripheral of the integrated circuit unit of the semiconductor substrate and filled with a heterogeneous material different from a material of the semiconductor substrate, and a method of fabricating the semiconductor package, comprising: at least partially forming a trench around the peripheral of the integrated circuit unit of the semiconductor substrate, and filling the trench with a heterogeneous material different from that of the semiconductor substrate. In accordance with the present invention, the structural and mechanical strength and durability of the semiconductor package, specifically, the wafer level semiconductor package, are improved and the reliability of the product is significantly improved. Furthermore, a fail rate including crack/chipping during a subsequent mounting process lowers, to improve the yield and reduce the whole manufacturing cost. | 2009-04-09 |
| 20090091002 | METHODS FOR PRODUCING IMPROVED EPITAXIAL MATERIALS - This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials. | 2009-04-09 |
| 20090091003 | INSULATOR UNDERGOING ABRUPT METAL-INSULATOR TRANSITION, METHOD OF MANUFACTURING THE INSULATOR, AND DEVICE USING THE INSULATOR - Provided are an insulator that has an energy band gap of 2 eV or more and undergoes an abrupt MIT without undergoing a structural change, a method of manufacturing the insulator, and a device using the insulator. The insulator is abruptly transitioned from an insulator phase into a metal phase by an energy change between electrons without undergoing a structural change. | 2009-04-09 |
| 20090091004 | SEMICONDUCTOR DEVICE - A semiconductor device according to one aspect of the present invention includes a semiconductor substrate, an interlayer insulating film formed over the semiconductor substrate, a metal wiring formed over the interlayer insulating film, a protective insulating film formed on the metal wiring, and a resin film formed within a region having one side shorter than a predetermined length on the protective insulating film. The resin film covers all regions in which an interval of the metal wirings is equal to or less than a predetermined interval. | 2009-04-09 |
| 20090091005 | Shielding structure for semiconductors and manufacturing method therefor - A shielding structure for semiconductor includes a semiconductor substrate, at least one active region defined on the semiconductor substrate, a protecting layer, a shielding layer, and a covering layer. The protecting layer, produced by a semiconductor process, is disposed on the surface of the active region. The shielding layer produced by a semiconductor process is disposed on the surface of the protecting layer. The covering layer covers the shielding layers, and the protecting layer is harder than the covering layer. In the above-mentioned structure, the harder protecting layer is provided to prevent the active regions from heat damage. | 2009-04-09 |
| 20090091006 | Dual Capillary IC Wirebonding - The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges and/or material composition. According to a preferred embodiment of the invention, dual capillary bond head apparatus includes a rotatable ultrasonic horn with a pair of capillaries for selectably dispensing separate strands of bond wire and for forming bonds on bond targets. According to another aspect of the invention, a method is provided for dual capillary IC wirebonding including steps for using two dual capillary bond heads for contemporaneously attaching non-identical bond wires to selected bond targets on one or more IC package assemblies. | 2009-04-09 |
| 20090091007 | Semiconductor Device Having Grooved Leads to Confine Solder Wicking - A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 μm deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 μm deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions. | 2009-04-09 |
| 20090091008 | Semiconductor device - A semiconductor device for programmable logic or operation processing includes a semiconductor chip; a first connecting terminal for electrically connecting the semiconductor device to a printed circuit board on which the semiconductor device is to be mounted; a second connecting terminal for electrically connecting the semiconductor device to another semiconductor device; and a packaging material for sealing the semiconductor chip, the first connecting terminal, and the second connecting terminal. Then, the first connecting terminal is formed of the lead frame, and the second connecting terminal is formed on the wiring board. | 2009-04-09 |
| 20090091009 | STACKABLE INTEGRATED CIRCUIT PACKAGE - A packaged integrated circuit device is disclosed which includes a leadframe comprising a die paddle and a plurality of lead fingers, a plurality of integrated circuit die positioned above the paddle in a stacked arrangement, a plurality of conductive structures for coupling each of the plurality of die to the lead fingers and a body of encapsulant material positioned around the plurality of die and the plurality of conductive structures, wherein the plurality of lead fingers are folded such that a portion of the lead fingers is positioned above the top surface of the body of encapsulant material. A method is also disclosed which includes attaching a first die to a paddle of a leadframe comprising a plurality of lead fingers, positioning at least one additional die above the first die, the first and the at least one additional die being electrically coupled to the plurality of lead fingers, forming a body of encapsulant material around the first die and the at least one additional die and folding the plurality of lead fingers such that a portion of the lead fingers is positioned above a top surface of the body of encapsulant material. | 2009-04-09 |
| 20090091010 | WIRELESS SEMICONDUCTOR PACKAGE FOR EFFICIENT HEAT DISSIPATION - Disclosed in this specification is a wireless semiconductor package with multiple dies, at least two of which are attached to a thermally and electrically conductive heat sink. The package provides an efficient means for dissipating heat. | 2009-04-09 |
| 20090091011 | SEMICONDUCTOR DEVICE HAVING INTERCONNECTED CONTACT GROUPS - The present invention is related to a method of producing a semiconductor device and the resulting device. The method is suitable in the first place for producing high power devices, such as High Electron Mobility Transistors (HEMT), in particular HEMT-devices with multiples source-gate-drain groups or multiple base bipolar transistors. According to the method, the interconnect between the source contacts is not produced by air bridge structures, but by etching vias through the semiconductor layer directly to the ohmic contacts and applying a contact layer on the backside of the device. | 2009-04-09 |
| 20090091012 | THERMOPLASTIC RESIN COMPOSITION FOR SEMICONDUCTOR, ADHESION FILM, LEAD FRAME, AND SEMICONDUCTOR DEVICE USING THE SAME, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - The object of the present invention is to provide an adhesion film for semiconductor that is capable of bonding a semiconductor chip to a lead frame tightly at an adhesion temperature lower than that of the adhesion film of a traditional polyimide resin without generation of voids and that can also be used for protection of lead frame-exposed area, a thermoplastic resin composition for semiconductor for use in the adhesive agent layer therein, and a lead frame having the adhesive film and a semiconductor device; and, to achieve the object, the present invention provides a thermoplastic resin composition for semiconductor, comprising a thermoplastic resin obtained in reaction of an amine component containing an aromatic diamine mixture (A) containing 1,3-bis(3-aminophenoxy)benzene, 3-(3′-(3″-aminophenoxy)phenyl)amino-1-(3′-(3″-aminophenoxy)phenoxy)benzene and 3,3′-bis(3″-aminophenoxy)diphenylether, and an acid component (C), an adhesion film for semiconductor using the same, a lead frame having the adhesion film and a semiconductor device using the same. | 2009-04-09 |
