| 14th week of 2021 patent applcation highlights part 43 |
| Patent application number | Title | Published |
|---|
| 20210104370 | FUSE CUTOUT COVER WITH VARIABLE ROOFS FOR DIFFERENT FUSE CUTOUTS | 2021-04-08 |
| 20210104371 | BREAKER AND SAFETY CIRCUIT EQUIPPED WITH THE SAME | 2021-04-08 |
| 20210104372 | Three Phase Surge Protection Device | 2021-04-08 |
| 20210104373 | CATHODE ASSEMBLY COMPONENT FOR X-RAY IMAGING | 2021-04-08 |
| 20210104374 | MULTI-SOURCE ION BEAM ETCH SYSTEM | 2021-04-08 |
| 20210104375 | LOW KEV ION BEAM IMAGE RESTORATION BY MACHINE LEARNING FOR OBJECT LOCALIZATION | 2021-04-08 |
| 20210104376 | DEVICE FOR PROVIDING ELECTRONS AND METHOD FOR MAKING THE SAME | 2021-04-08 |
| 20210104377 | ION BEAM PROCESSING APPARATUS, ELECTRODE ASSEMBLY, AND METHOD OF CLEANING ELECTRODE ASSEMBLY | 2021-04-08 |
| 20210104378 | APPARATUS AND METHOD FOR REDUCTION OF PARTICLE CONTAMINATION BY BIAS VOLTAGE | 2021-04-08 |
| 20210104379 | EXPOSURE DEVICE | 2021-04-08 |
| 20210104380 | ION BEAM SPUTTERING APPARATUS AND METHOD | 2021-04-08 |
| 20210104381 | GAS SUPPLY ASSEMBLY AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME | 2021-04-08 |
| 20210104382 | PLASMA ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION METHOD INCLUDING THE SAME | 2021-04-08 |
| 20210104383 | PLASMA PROCESSING APPARATUS | 2021-04-08 |
| 20210104384 | INTEGRATED ELECTRODE AND GROUND PLANE FOR A SUBSTRATE SUPPORT | 2021-04-08 |
| 20210104385 | SUBSTRATE SUPPORT PEDESTAL AND PLASMA PROCESSING APPARATUS | 2021-04-08 |
| 20210104386 | STAGE AND PLASMA PROCESSING APPARATUS | 2021-04-08 |
| 20210104387 | SYSTEM AND METHOD FOR REMOTE SENSING A PLASMA | 2021-04-08 |
| 20210104388 | SYSTEM AND METHOD FOR PHOTOMULTIPLIER TUBE IMAGE CORRECTION | 2021-04-08 |
| 20210104389 | THERMIONIC WAVE GENERATOR (TWG) | 2021-04-08 |
| 20210104390 | MASS SPECTRAL ANALYSIS OF LARGE MOLECULES | 2021-04-08 |
| 20210104391 | INORGANIC MASS SPECTROMETER | 2021-04-08 |
| 20210104392 | APPARATUSES FOR OPTICAL AND MASS SPECTROMETRY DETECTION | 2021-04-08 |
| 20210104393 | SYSTEMS AND METHODS FOR IONIZING A SURFACE | 2021-04-08 |
| 20210104394 | MULTIPLE BEAM SECONDARY ION MASS SPECTROMETRY DEVICE | 2021-04-08 |
| 20210104395 | METHOD OF MANUFACTURING HIGH ELECTRON MOBILITY TRANSISTOR AND HIGH ELECTRON MOBILITY TRANSISTOR | 2021-04-08 |
| 20210104396 | CONFORMAL AND SMOOTH TITANIUM NITRIDE LAYERS AND METHODS OF FORMING THE SAME | 2021-04-08 |
| 20210104397 | SMOOTH TITANIUM NITRIDE LAYERS AND METHODS OF FORMING THE SAME | 2021-04-08 |
| 20210104398 | Planarizing Process and Composition | 2021-04-08 |
| 20210104399 | METHODS FOR FORMING A TOPOGRAPHICALLY SELECTIVE SILICON OXIDE FILM BY A CYCLICAL PLASMA-ENHANCED DEPOSITION PROCESS | 2021-04-08 |
| 20210104400 | EDGE EXCLUSION APPARATUS AND METHODS OF USING THE SAME | 2021-04-08 |
| 20210104401 | NOVEL METHOD FOR GATE INTERFACE ENGINEERING | 2021-04-08 |
| 20210104402 | SONOS ONO STACK SCALING | 2021-04-08 |
| 20210104403 | Process and Manufacture of Low-Dimensional Materials Supporting Both Self-Thermalization and Self-Localization | 2021-04-08 |
| 20210104404 | SEMICONDUCTOR DEVICE STRUCTURE WITH A FINE PATTERN | 2021-04-08 |
| 20210104405 | SUBSTRATE BONDING APPARATUS | 2021-04-08 |
| 20210104406 | Electrode with Alloy Interface | 2021-04-08 |
| 20210104407 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING | 2021-04-08 |
| 20210104408 | PROCESSING METHOD OF WAFER | 2021-04-08 |
| 20210104409 | METHOD OF FORMING PATTERNS | 2021-04-08 |
| 20210104410 | THREE-DIMENSIONAL SEMICONDUCTOR FABRICATION | 2021-04-08 |
| 20210104411 | ETCHING SOLUTION, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE | 2021-04-08 |
| 20210104412 | SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING SYSTEM | 2021-04-08 |
| 20210104413 | METHOD OF ETCHING SILICON CONTAINING FILMS SELECTIVELY AGAINST EACH OTHER | 2021-04-08 |
| 20210104414 | THERMAL ATOMIC LAYER ETCH WITH RAPID TEMPERATURE CYCLING | 2021-04-08 |
| 20210104415 | DEFECT REDUCTION OF SEMICONDUCTOR LAYERS AND SEMICONDUCTOR DEVICES BY ANNEAL AND RELATED METHODS | 2021-04-08 |
| 20210104416 | STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME | 2021-04-08 |
| 20210104417 | APPARATUS AND METHOD FOR TREATING SUBSTRATE | 2021-04-08 |
| 20210104418 | APPARATUS FOR TREATING SUBSTRATE AND METHOD FOR TREATING SUBSTRATE | 2021-04-08 |
| 20210104419 | WAFER COOLING SYSTEM | 2021-04-08 |
| 20210104420 | SUPPORT UNIT, SUBSTRATE TREATING APPARATUS INCLUDING THE SAME, AND SUBSTRATE TREATING METHOD | 2021-04-08 |
| 20210104421 | CONTROL DEVICE, PROCESSING APPARATUS, AND CONTROL METHOD | 2021-04-08 |
| 20210104422 | LEAK MEASUREMENT SYSTEM, SEMICONDUCTOR MANUFACTURING SYSTEM, AND LEAK MEASUREMENT METHOD | 2021-04-08 |
| 20210104423 | PROCESS OPTIMIZATION USING DESIGN OF EXPERIMENTS AND RESPONSE SURFACE MODELS | 2021-04-08 |
| 20210104424 | LOAD PORT APPARATUS AND METHOD OF DRIVING THE SAME | 2021-04-08 |
| 20210104425 | ACCOMMODATING DEVICE FOR RETAINING WAFERS | 2021-04-08 |
| 20210104426 | ELECTROSTATIC CHUCK AND METHOD FOR MANUFACTURING SAME | 2021-04-08 |
| 20210104427 | APPARATUS AND METHODS FOR ISOLATING A REACTION CHAMBER FROM A LOADING CHAMBER RESULTING IN REDUCED CONTAMINATION | 2021-04-08 |
| 20210104428 | WAFER CHUCK, METHOD FOR PRODUCING THE SAME, AND EXPOSURE APPARATUS | 2021-04-08 |
| 20210104429 | METHODS FOR FORMING HOLE STRUCTURE IN SEMICONDUCTOR DEVICE | 2021-04-08 |
| 20210104430 | SILICON-ON-INSULATOR SUBSTRATE INCLUDING TRAP-RICH LAYER AND METHODS FOR MAKING THEREOF | 2021-04-08 |
| 20210104431 | CONTACT PLUGS FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME | 2021-04-08 |
| 20210104432 | PROCESSES FOR FORMING FULLY ALIGNED VIAS | 2021-04-08 |
| 20210104433 | CONFORMAL TITANIUM NITRIDE-BASED THIN FILMS AND METHODS OF FORMING SAME | 2021-04-08 |
| 20210104434 | METHODS AND APPARATUSES FOR FORMING INTERCONNECTION STRUCTURES | 2021-04-08 |
| 20210104435 | TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE, AND ASSOCIATED CONFIGURATIONS | 2021-04-08 |
| 20210104436 | 3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK | 2021-04-08 |
| 20210104437 | SEMICONDUCTOR DEVICE | 2021-04-08 |
| 20210104438 | Configuring Different Via Sizes for Bridging Risk Reduction and Performance Improvement | 2021-04-08 |
| 20210104439 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME | 2021-04-08 |
| 20210104440 | VERTICAL TUNNELING FIELD EFFECT TRANSISTOR WITH DUAL LINER BOTTOM SPACER | 2021-04-08 |
| 20210104441 | FINFET DEVICES AND METHODS OF FORMING THE SAME | 2021-04-08 |
| 20210104442 | STABLE MIXED OXIDE CATALYSTS FOR DIRECT CONVERSION OF ETHANOL TO ISOBUTENE AND PROCESS FOR MAKING | 2021-04-08 |
| 20210104443 | Fin Field-Effect Transistor Device and Method | 2021-04-08 |
| 20210104444 | MODULES INCORPORATING ENCAPSULATION LAYERS | 2021-04-08 |
| 20210104445 | SILICON CARBIDE POWER DEVICE WITH IMPROVED ROBUSTNESS AND CORRESPONDING MANUFACTURING PROCESS | 2021-04-08 |
| 20210104446 | PACKAGED SEMICONDUCTOR DEVICES HAVING ENHANCED THERMAL TRANSPORT AND METHODS OF MANUFACTURING THE SAME | 2021-04-08 |
| 20210104447 | SILICON ON DIAMOND THERMAL AND SHIELDING MITIGATION | 2021-04-08 |
| 20210104448 | LATERAL HEAT REMOVAL FOR 3D STACK THERMAL MANAGEMENT | 2021-04-08 |
| 20210104449 | Power Semiconductor Package with Highly Reliable Chip Topside | 2021-04-08 |
| 20210104450 | LIQUID COOLED HEAT DISSIPATION DEVICE | 2021-04-08 |
| 20210104451 | SEMICONDUCTOR DEVICES WITH BACK-SIDE COILS FOR WIRELESS SIGNAL AND POWER COUPLING | 2021-04-08 |
| 20210104452 | FILM PACKAGE AND METHOD OF FABRICATING PACKAGE MODULE | 2021-04-08 |
| 20210104453 | BIDIRECTIONAL SWITCH AND BIDIRECTIONAL SWITCH DEVICE INCLUDING THE SWITCH | 2021-04-08 |
| 20210104454 | WIRING SUBSTRATE DEVICE | 2021-04-08 |
| 20210104455 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF | 2021-04-08 |
| 20210104456 | Electronic Device with Stud Bumps | 2021-04-08 |
| 20210104457 | ELECTRONIC DEVICE COMPRISING A CHIP AND AT LEAST ONE SMT ELECTRONIC COMPONENT | 2021-04-08 |
| 20210104458 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 2021-04-08 |
| 20210104459 | FUSE LINES AND PLUGS FOR SEMICONDUCTOR DEVICES | 2021-04-08 |
| 20210104460 | SEMICONDUCTOR FUSE STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR FUSE STRUCTURE | 2021-04-08 |
| 20210104461 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | 2021-04-08 |
| 20210104462 | SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER | 2021-04-08 |
| 20210104463 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | 2021-04-08 |
| 20210104464 | ALIGNMENT CARRIER FOR INTERCONNECT BRIDGE ASSEMBLY | 2021-04-08 |
| 20210104465 | ELECTRONIC PACKAGE, PACKAGING SUBSTRATE, AND METHODS FOR FABRICATING THE SAME | 2021-04-08 |
| 20210104466 | APPARATUSES INCLUDING CONDUCTIVE STRUCTURE LAYOUTS | 2021-04-08 |
| 20210104467 | PACKAGE COMPRISING A DIE AND DIE SIDE REDISTRIBUTION LAYERS (RDL) | 2021-04-08 |
| 20210104468 | INTEGRATED CIRCUIT WITH SCRIBE LANE PATTERNS FOR DEFECT REDUCTION | 2021-04-08 |
| 20210104469 | MARKING PATTERN IN FORMING STAIRCASE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE | 2021-04-08 |
