| 14th week of 2010 patent applcation highlights part 17 |
| Patent application number | Title | Published |
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| 20100085016 | METHOD AND APPARATUS FOR BATTERY GAUGING IN PORTABLE TERMINAL - A method and apparatus for battery gauging in a portable terminal are provided. In the battery gauging method, it is determined in a low-power mode whether a listening interval occurs for detecting the presence of a received signal. The remaining battery capacity is detected if the listening interval occurs. An interrupt signal is transmitted to the second processor, operating in a low-power mode, if the remaining battery capacity is less than or equal to a threshold. Upon receipt of the interrupt signal, the second processor wakes up to interrupt the power of the portable terminal. | 2010-04-08 |
| 20100085017 | APPARATUS WITH RECHARGEABLE POWER SUPPLY - A fraction of the battery energy is kept in reserve during operational use of a battery-powered apparatus. The motor of the apparatus is switched off when the battery has discharged to the level of this reserve fraction. The reserve is made available again for operational use when the user has recharged the apparatus for a little while. This approach | 2010-04-08 |
| 20100085018 | SHARED CONTROL OF THERMISTOR AND DUAL PURPOSE THERMISTOR LINE - A battery pack can include a temperature sensor that can provide an output that is indicative of a temperature associated with the battery pack. A battery management unit can directly measure the temperature sensor when the battery pack is by itself or engaged with a tool. A charger can directly read the temperature sensor when the battery pack is engaged with the charger. Thus, the temperature sensor can be shared by the battery pack and the charger. The battery pack can utilize a same terminal that provides access to the temperature sensor to indicate a stop-charge signal. The charger can read the stop-charge signal on the same terminal used to directly access the temperature sensor. | 2010-04-08 |
| 20100085019 | BATTERY TEMPERATURE CONTROL SYSTEM - A battery temperature control system, in temperature rise control, sets a maximum chargeable current and a maximum dischargeable current based on detection values of current, voltage, and temperature of a high-voltage battery, and and controls charging/discharging power so that the current of the high-voltage battery does not exceed the maximum chargeable current or the maximum dischargeable current. For this reason, it is possible to prevent the high-voltage battery from abnormal heating and promptly raise its temperature according to change in the internal state of the high-voltage battery. In this control, a plurality of electrical equipment is selectively used. The amplitude of charging/discharging is controlled to reduce vibration noise and driving force fluctuation. | 2010-04-08 |
| 20100085020 | Charging system for electric power tool, battery pack for electric power tool, and battery charger for electric power tool - Each of a battery charger and a battery pack has a microcomputer. The respective microcomputers mutually perform data communication while the battery pack is being charged by the battery charger, and confirm an operational state of the microcomputer of the communication counterpart (mutual operation confirmation) based on a result of the data communication. When an abnormality of one of the microcomputers is detected, the other microcomputer executes a predetermined process for stopping charging. | 2010-04-08 |
| 20100085021 | METHOD FOR STEPPING CURRENT OUTPUT BY A BATTERY CHARGER - A battery charger is provided for implementing a charging method having a stepped output current. The battery charger includes: a power supply circuit that receives an AC input signal and outputs a DC output signal. The power supply circuit includes a power supply controller configured to receive a feedback signal indicative of current being output by the power supply circuit via an amplifier and operates to control current output by the power supply circuit in accordance with the feedback signal. A charger controller is interfaced with the power supply controller to implement a charging method having a stepped output current. The charger controller may set the output current level by adjusting gain of an operational amplifier having a negative feedback configuration with the feedback signal input to a non-inverting input terminal of the operational amplifier, where the charger controller sets the output current level by changing the resistance at an inverting input terminal of the operational amplifier. | 2010-04-08 |
| 20100085022 | Charging apparatus - A charging apparatus includes: a charging voltage output unit; a duty ratio setting unit; a PWM signal output unit; a reference voltage generation unit; a reference voltage limit unit; a detected voltage generation unit; and a charging voltage control unit. The reference voltage generation unit generates a reference voltage for determining whether or not a charging voltage has reached a target charging voltage, by smoothing a PWM signal outputted from the PWM signal output unit. The reference voltage limit unit limits at least one of a maximum value and a minimum value of the reference voltage generated by the reference voltage generation unit. | 2010-04-08 |
| 20100085023 | Control Device for Automobile Battery-Charging Generator - This invention provides a control device for automobile battery-charging generators, adapted to supply a plurality of sets of specifications in a highly reliable and stable form by simple switching between electrical characteristics assigning and limiting functions so as to meet various needs of users. | 2010-04-08 |
| 20100085024 | POWER SUPPLY CONTROLLER WITH DIFFERENT STEADY STATE AND TRANSIENT RESPONSE CHARACTERISTICS - An embodiment of a power-supply controller includes a control circuit and a detection circuit. The control circuit has a signal characteristic, and is operable in response to a regulated output signal and a reference signal to cause at least one power-supply phase to generate the regulated output signal. The detection circuit is operable to detect a change in the regulated output signal, and to alter the signal characteristic of the control circuit in response to the detected change. | 2010-04-08 |
| 20100085025 | DRIVING CIRCUIT OF LOAD - A driving circuit of a load has an output semiconductor element connected in series in a power supply path from a power source to the load, to control a current of the load, a PWM signal generator for controlling ON/OFF of the output semiconductor element, a driver of the output semiconductor element according to the PWM signal, a detection resistor made of a semiconductor detecting a current of the load, a current output amplifier outputting a monitored current of detection resistor without being influenced by variation of ambient temperature, a resistor converting the monitored current into a monitored voltage, a current source outputting a constant current without being influenced by variation of ambient temperature, a resistor outputting a reference voltage according to the constant current, and an A/D converter converting the monitored voltage according to the reference voltage into a detected current value of the current of the load. | 2010-04-08 |
| 20100085026 | POWER SOURCE DEVICE AND OUTPUT VOLTAGE STABILIZING METHOD - A power source device includes: a switching section switching an input voltage supplied to a load section; a smoothing inductor section smoothing and outputting an output current to be supplied to the load section in accordance with a switching of the switching section; a first inductor section decreasing an output inductance value of the smoothing inductor section; a second inductor section increasing the output inductance value of the smoothing inductor section; an electromagnetic induction activating section activating the electromagnetic induction between the smoothing inductor section and the first or the second inductor section; a load current fluctuation detecting section detecting a steep fluctuation in a load current; and a control section controlling the electromagnetic induction activating section so as to activate the electromagnetic induction between the smoothing inductor section and the first or the second inductor section when the steep fluctuation of the load current is detected. | 2010-04-08 |
| 20100085027 | SYSTEM AND METHOD FOR PROVIDING LINEAR BUCK BOOST TRANSITIONS WITHIN A BUCK BOOST CONVERTER - A voltage regulator, comprising first circuitry for generating an output voltage responsive to an input voltage and a plurality of switching control signal. Switching control circuitry generates the switching control signals responsive to the output voltage and at least one of a buck ramp signal and a boost ramp signal. Voltage ramp generation circuitry generates each of the buck ramp signal and the boost ramp signal. The boost ramp signal comprises the buck ramp signal offset by the peak value of the buck ramp signal. | 2010-04-08 |
| 20100085028 | SYSTEM AND METHOD FOR PROVIDING LINEAR BUCK BOOST TRANSITIONS WITHIN A BUCK BOOST CONVERTER - A voltage regulator, comprises first circuitry for generating an output voltage responsive to an input voltage and a plurality of switching control signal. Switching control circuitry generates the switching control signals responsive to the output voltage and at least one of a buck ramp signal and a boost ramp signal. Voltage ramp generation circuitry generates each of the buck ramp signal and the boost ramp signal. The boost ramp signal comprises the buck ramp signal offset by the peak value of the buck ramp signal. | 2010-04-08 |
| 20100085029 | ADVANCED SLOPE INJECTION FOR INPUT CURRENT LIMITING OF SWITCH-MODE DC/DC CONVERTER - A DC/DC converter comprising voltage conversion circuitry for generating a regulated output voltage responsive to an input current and at least one switching control signal. A current control loop generates the at least one switching control signal to limit an input current responsive to the input current, a reference voltage and a slope signal injected with the reference voltage. | 2010-04-08 |
| 20100085030 | Semiconductor Device and RFID Tag Using the Semiconductor Device - A semiconductor device monitors a voltage between a reference potential and an input potential and obtains a constant output potential regardless of a value of the voltage, after the voltage exceeds a predetermined threshold voltage in such a manner that the semiconductor device divides a voltage between the reference potential and the input potential using a plurality of first non-linear elements and at least one linear element to constantly generate a first bias voltage regardless of a value of the voltage, divides a voltage between the reference potential and the input potential using a plurality of second non-linear elements with reference to the first bias voltage to constantly generate a second bias voltage regardless of a value of the voltage, and determines the output potential with reference to the second bias voltage. | 2010-04-08 |
| 20100085031 | Operating an Integrated Circuit at a Minimum Supply Voltage - In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit. | 2010-04-08 |
| 20100085032 | Boost Device for Voltage Boosting - A boost device boosts an input voltage to an output voltage across an output capacitor, and includes first and second output diodes coupled to the output capacitor, and a transformer coupled to first and second switches, first and second switching circuits, and to the first and second output diodes, and receiving the input voltage. The first and second switches are operated alternately in an ON-state, and have overlapping duty cycles. The first and second switching circuits are operable to suppress conduction losses for the first and second switches. The transformer has a bi-directional magnetic circuit. Electric energy is transformed through induced currents of the transformer, and a small amount of energy attributed to an exciting current of the transformer is used for voltage boosting, thereby attaining a relatively high output power. | 2010-04-08 |
| 20100085033 | ION CURRENT MEASUREMENT DEVICE - The invention provides an ion current measurement device for a tool having an ion source. The ion current measurement device comprises an ion collecting cup and a replaceable liner. The ion collecting cup is disposed in the tool and the ion collecting cup possesses a cup opening facing the ion source. The replaceable liner is disposed in the ion collecting cup and the replaceable liner entirely covers a continuous inner sidewall of the ion collecting cup. | 2010-04-08 |
| 20100085034 | Current Measurement Circuit, Current Detection Circuit And Saturation Prevention And Recovery Circuit For Operational Amplifier - A current measurement circuit includes: a constant-voltage loop circuit including an operational amplifier, and a first resistor for current detection connected to an output of the operational amplifier, the output of the operational amplifier being fed back to an inverting input terminal of the operational amplifier via the first resistor; a differential amplifier for current detection with an input of a voltage between both ends of the first resistor; and a saturation prevention and recovery circuit connected to the both ends of the first resistor for preventing saturation of the operational amplifier and/or accelerating recovery from the saturation thereof. | 2010-04-08 |
| 20100085035 | Method and apparatus for determining AC voltage waveform anomalies - A method and apparatus for determining AC voltage waveform anomalies. The apparatus comprises a threshold generator for generating at least one time-variant threshold based on information regarding an AC voltage waveform. The apparatus further comprises a threshold detector for comparing a sample of the AC voltage waveform to the at least one time-variant threshold to identify an AC voltage waveform anomaly. | 2010-04-08 |
| 20100085036 | Overhead Communicating Device - A power line monitoring device is mounted to a power line. The device includes circuitry for monitoring the power line and communicating information regarding the power line. A ground reference point of the circuitry is electrically coupled to the power line. Therefore, the monitoring device, including its circuitry, has substantially the same voltage potential as the power line. Accordingly, there is a substantially equalized or uniform electric field around the device. The substantially equal voltage potential and electric field allow communications with the monitoring device to have reduced noise and interference, as compared to other devices that have different voltage potentials than their corresponding power lines. A pad of semi-conductive material may be disposed between the power line and the electrical conductors to slow a rate of change of the voltage potential of the device circuitry when mounting the device to the power line, thereby minimizing risk of corona discharge. | 2010-04-08 |
| 20100085037 | System and Method for Measuring Reactive Power - A system and method for measuring reactive power which uses a pair of quadrate carriers to add a 90 degree phase shift to a voltage path or a current path in a power meter. The quadrate carriers have the same frequency but are offset in phase from each other by 90 degrees. | 2010-04-08 |
| 20100085038 | Arrangement comprising a magnetic-field-dependent angle sensor - In order to reduce the dimensions of the mechanical components and the number and size of the sensory and electronic components in an arrangement comprising a magnetic-field-dependent angle sensor which is effectively connected to a magnetic transmitter which is arranged such that it can rotate with respect to the angle sensor, while maintaining or improving the resolution of the output signal, the angle sensor is formed by at least one magnetoelectric converter, the electrical properties of which are dependent on the magnetic field strength but independent of the polarity of the magnetic field acting on the at least one converter. The magnetic field strength is selected such that the at least one converter is controlled in saturation. | 2010-04-08 |
| 20100085039 | POSITION SENSOR - A plurality of layers of flat coils are stacked and connected in series with each other to form a single coil pole, and the coil pole is energized by an A.C. signal. Magnetism-responsive member, provided to be opposed to the coil pole in a non-contact manner, is displaced relative to the coil pole, so that correspondency, to the coil section, of the magnetism-responsive member varies in response to variation in the relative position and thus impedance variation occurs in the coil pole. Position detection signal is provided on the basis of an output signal, responsive to the impedance variation, taken out from the coil pole. | 2010-04-08 |
| 20100085040 | APPARATUS AND METHOD FOR DETERMINING SPEED AND DIRECTION OF SLOTTED TARGETS UTILIZING DUAL MAGNETIC SENSOR PACKAGING - A magnetic sensing apparatus and method that determines the speed and direction of gears or slotted targets. A magnet can be placed proximate to the slotted target to create a magnetic field. An integrated circuit is formed on a substrate containing two or more magnetoresistive sensors occupying the same area. This integrated circuit is biased from the magnet which is placed in close proximity. The magnetoresistive sensors are intertwined with the first magnetoresistive sensor, offset from the second magnetoresistive sensor. The magnetoresistive sensors produce phase shifted output signals representing magnetic flux flowing through the magnetoresistive sensors such that the magnetoresistive sensors are reactive to gap and angular changes in the circular track of the ferrous target. The phase shift of the signals needed to determine direction is sufficiently maintained for a variety of target feature sizes and spacing. | 2010-04-08 |
| 20100085041 | MAGNETO-RESISTANCE BASED NANO-SCALE POSITION SENSOR - A position sensor and method include a magnetic component, a first magneto-resistive sensor disposed in proximity to the magnet/coil; and a second magneto-resistive sensor disposed in proximity to the magnetic component and the first magneto-resistive sensor. The first magneto-resistive sensor and second magneto-resistive sensor are configured to sense changes in a stray magnetic field created by the magnetic component in accordance with a relative positional change between the magnetic component and the first and second magneto-resistive sensors. | 2010-04-08 |
| 20100085042 | EDDY CURRENT TESTING APPARATUS AND EDDY CURRENT TESTING METHOD - The eddy current testing apparatus includes a probe having an eddy current testing sensor including a pair of eddy current testing coils. The apparatus also includes an eddy current testing flaw detector inputting detection signals from the eddy current testing sensor. The diameter of a magnetic core used in each of the pair of eddy current testing coils is within the range of 0.1 mm to 0.5 mm. | 2010-04-08 |
| 20100085043 | EDDY CURRENT TESTING APPARATUS AND EDDY CURRENT TESTING METHOD - The eddy current testing apparatus includes a probe having an eddy current testing sensor including a pair of eddy current testing coils. The apparatus also includes an eddy current testing flaw detector inputting detection signals from the eddy current testing sensor. The diameter of a magnetic core used in each of the pair of eddy current testing coils is within the range of 0.1 mm to 0.5 mm. | 2010-04-08 |
| 20100085044 | EDDY CURRENT TESTING METHOD, EDDY CURRENT TESTING DIFFERENTIAL COIL AND EDDY CURRENT TESTING PROBE FOR INTERNAL FINNED PIPE OR TUBE - The invention provides an eddy current testing method for an internal finned pipe or tube which can securely detect a micro defect generated in a trough portion in an inner surface of the pipe or tube, even in the case that an inner surface shape of the internal finned pipe or tube is ununiform in a circumferential direction of the pipe or tube. The eddy current testing method in accordance with the invention detects a defect existing in a trough portion of the pipe or tube (P) by arranging a differential coil ( | 2010-04-08 |
| 20100085045 | Omnidirectional Eddy Current Array Probes and Methods of Use - Omnidirectional eddy current array probes for detecting flaws in a conductive test object generally includes semi-circular wave shaped continuous drive lines in two rows disposed in two layers that are multiplexed for omnidirectional inspection without blind spots. The semicircular wave shaped continuous drive lines are superimposed to form pseudo-circular drive lines, wherein each row of drive lines is offset laterally by a distance preferably equal to a quarter wavelength of the wave pattern. For only parallel and perpendicular flaws, the drive multiplexing is not needed and each row will have only one set of drive lines. In alternate embodiments, there can be square-shaped, oval shaped, rectangular-shaped or other shaped wave patterns as well. Also disclosed are methods for sensing surface flaws and compensating their response. | 2010-04-08 |
| 20100085046 | HYPERPOLARIZED DYNAMIC CHEMICAL SHIFT IMAGING WITH TAILORED MULTIBAND EXCITATION PULSES - A method for performing magnetic resonance spectroscopy is described. The method generally includes applying a tailored multiband spectral-spatial radio frequency excitation pulse to a sample including a first species and at least a second species having a different resonant frequency than the first species. The multiband excitation pulse excites the first species according to a first amplitude and excites the second species according to a second amplitude that is substantially greater than the first amplitude. Data is acquired from the sample. The acquired data is then utilized to generate a spectroscopic output. By way of example, the spectroscopic output is a spectroscopic image. In particular embodiments, the data for the first and second species is acquired dynamically over an observation window of time. | 2010-04-08 |
| 20100085047 | METHOD FOR DETECTING PARAFFIN WAX AND ASPHALTENE CONTENT IN OIL - This invention relates to geology, geochemistry, oil refinery and petroleum chemistry and can be implemented for determination of paraffin and asphaltene concentration in oil, in particular, for analysis of heavy oils and bitumens. To determine concentration of paraffins and asphaltenes in oil, three crude oil samples are extracted; two extracted samples are dissolved in a solvent and the solvent alongside with light oil fractions is then removed; meanwhile, asphaltenes are removed from one of the solvent-treated samples. A nucleic magnetic resonance method is employed for measuring free inductance drop-down curves for all three samples; thereafter, a ratio of solid hydrogen-containing fractions suspended in oil, to liquid hydrogen-containing fractions is defined. The paraffin concentration is judged by the content of solid hydrogen-containing fractions in the solvent-treated sample, from which asphaltenes have been removed. The asphaltene concentration is judged by the content of solid hydrogen-containing fractions in the other solvent-treated sample, with the consideration of the defined concentration of paraffins. The concentration of paraffins and asphaltenes in original oil is determined based on the defined paraffin-to-asphaltene ratio in solid hydrogen-containing fractions. | 2010-04-08 |
| 20100085048 | ROTATING-FRAME GRADIENT FIELDS FOR MAGNETIC RESONANCE IMAGING AND NUCLEAR MAGNETIC RESONANCE IN LOW FIELDS - A system and method for Fourier encoding a nuclear magnetic resonance (NMR) signal is disclosed. A static magnetic field B | 2010-04-08 |
| 20100085049 | METHOD OF OBTAINING A MAGNETIC RESONANCE IMAGE IN WHICH THE STREAK ARTIFACTS ARE CORRECTED USING NON-LINEAR PHASE CORRECTION - A non-linear phase correction method is provided. For the non-linear phase correction method, image information is acquired by gradient echo echo planar imaging (EPI). Reference information is acquired by spin echo EPI. The image information is corrected based on the reference information. | 2010-04-08 |
| 20100085050 | SPECTRAL RESOLUTION ENHANCEMENT OF MAGNETIC RESONANCE SPECTROSCOPIC IMAGING - A method and apparatus for enhancing the spectral resolution of magnetic resonance spectroscopic (MRS) measurements include receiving time domain echo data from an MRS measurement for an MRS volume in a subject. Also received are high spatial resolution complex signal values within the MRS volume based on magnetic resonance imaging (MRI) measurements. Frequency-domain content is determined for the echo data based at least in part on the complex signal values. For example, in some embodiments, receiving complex signal values includes receiving high spatial resolution complex signal values within the MRS volume for each of two different echo time settings. The frequency-domain content of the echo data is corrected for a lineshape profile based on high resolution frequency dispersion values for the MRS volume determined from differences in the complex signal values for the two different echo time settings. | 2010-04-08 |
| 20100085051 | METHOD AND DEVICE TO DETERMINE AN INVERSION TIME VALUE OF TISSUE BY MEANS OF MAGNETIC RESONANCE TECHNOLOGY - In a method to determine an inversion time value for contrast improvement between different tissue in a contrast agent-supported magnetic resonance imaging, a series of magnetic resonance images of an imaging area is acquired using an inversion recovery sequence with different inversion times. A structure in the magnetic resonance images is segmented and a time response of the signal intensity of image elements corresponding to one another in the magnetic resonance images of the segmented structure is automatically determined. Minima of the signal intensity in the segmented structure are determined automatically and associated with the associated inversion time values. The optimal inversion time value for contrast improvement is automatically determined from the inversion time values that have been associated with the minima of the signal intensity in the segmented structure. | 2010-04-08 |
| 20100085052 | METHOD FOR MAGNITUDE CONSTRAINED PHASE CONTRAST MAGNETIC RESONANCE IMAGING - A method for magnitude constrained phase contrast magnetic resonance imaging (MRI) is provided. The method utilizes an assumption that the image magnitude is shared across a series of images reconstructed from a set of phase contrast enhanced k-space data. In this manner, one common magnitude image and a plurality of phase images are reconstructed substantially contemporaneously from the acquired image data. The method is further applicable to other phase contrast MRI methods, such as phase contract velocimetry. Moreover, simultaneous phase contrast velocimetry and chemical shift imaging, in which water and fat signal separation is achieved, is provided. | 2010-04-08 |
| 20100085053 | MAGNETIC RESONANCE IMAGING APPARATUS AND GRADIENT COIL COOLING CONTROL METHOD - A feedforward control unit predicts the maximum value of the temperature of a gradient coil based on a power duty and a scan time of a pulse sequence, and a present temperature of the gradient coil. When the maximum value exceeds a predetermined upper limit, the feedforward control unit then instructs a temperature adjusting unit to start a water circulation in a chiller at the start of a prescan, and the temperature adjusting unit starts the water circulation based on the instruction. | 2010-04-08 |
| 20100085054 | SYSTEMS AND METHODS FOR GENERATING ELECTRONIC RECORDS OF LOCATE AND MARKING OPERATIONS - Systems and methods for generating electronic records of locate operations and marking operations are described. Exemplary systems and methods include marking devices that generate, store and/or transmit electronic records of marking information, locate devices that generate, store and/or transmit electronic records of locate information, and locate devices and marking devices that communicate with each other (and optionally with other devices or systems) to share/exchange locate information and/or marking information. An exemplary method for analyzing and processing locate information and marking information includes a computer-implemented method for visually rendering (e.g., in a display field of a display device) various aspects of locate and marking operations. | 2010-04-08 |
| 20100085055 | METHOD OF MAPPING HYDROCARBON RESERVOIRS IN SHALLOW WATERS AND ALSO AN APPARATUS FOR USE WHEN PRACTISING THE METHOD - A system for marine electromagnetic surveying of hydrocarbon reservoirs is proposed. The system proposed is characterized by high sensitivity to targets containing hydrocarbons and an ability to work in shallow and deep waters. The system includes a transmitter setting up current pulses in water ( | 2010-04-08 |
| 20100085056 | MAGNETO-RESISTANCE BASED TOPOGRAPHY SENSING - A topography sensor and method include a probe configured to traverse a surface to determine a topography. A stray magnetic field is disposed in proximity to the probe. A magneto-resistive sensor is configured so that the stray magnetic field passing through it changes in accordance with positional changes of the probe as the probe tip traverses the surface. | 2010-04-08 |
| 20100085057 | DEVICE ESTIMATING A STATE OF A SECONDARY BATTERY - A diffusion estimation unit follows a diffusion equation in an active material that is represented by a polar coordinate to estimate a distribution in concentration of lithium in the active material. An open circuit voltage estimation unit obtains an open circuit voltage in accordance with a local SOC(θ) based on a concentration of lithium obtained at an interface of the active material as estimated by the diffusion estimation unit. A current estimation unit uses a battery's voltage measured by a voltage sensor, the estimated open circuit voltage, and a parameter value that is set for the battery by a battery parameter value setting unit, and follows a voltage-current relationship model expression simplified from an electrochemical reaction expression to estimate the battery's current density. A boundary condition setting unit sequentially sets a boundary condition for the diffusion equation of the diffusion estimation unit for the active material's interface, as based on the battery's estimated current density. Thus a battery model that allows an internal state to be estimated based on an electrochemical reaction dynamically and can also achieve an alleviated operating load can be used to estimate a state of a secondary battery. | 2010-04-08 |
| 20100085058 | TRAINLINE INTEGRITY LOCOMOTIVE TEST DEVICE - A trainline integrity locomotive test device is provided that is configured to provide conventionally provided End-Of-Train (EOT) functionality required for a single locomotive test as well as functionality necessary for troubleshooting electrical problems in trainline electrical conductors, wherein the trainline integrity locomotive test device includes a reduced number of components in comparison with a conventional EOT device. Additionally, the test device is provided in more compact, durable and robust form relative to conventional EOT devices. As part of the transmission of trainline integrity data from the test device to the Head-End-Unit, a communications heartbeat signal is substituted for brake pipe pressure conventionally detected by EOT devices, so as to provide an indication of data communication reliability. | 2010-04-08 |
| 20100085059 | DIFFERENTIAL POWER DETECTION - A method of determining a differential power condition includes comparing a voltage across a resistor to a first threshold. The voltage across the resistor is proportional to a difference between a first current and a second current. The method also includes comparing a difference between the first current and the second current to a second threshold. A differential power condition is determined in response to the voltage across the resistor exceeding the first threshold, the difference exceeding the second threshold, or both. | 2010-04-08 |
| 20100085060 | ELECTRIC POWER SOURCE CIRCUIT AND ABNORMALITY DIAGNOSIS SYSTEM - In a power source circuit for supplying electric power of a battery, a capacitor is charged by the battery when an ignition switch and a power supply relay are closed. The power supply relay is opened after the ignition switch is closed. The charge voltage of the capacitor falls, if the power supply relay has no fixed-closure abnormality. The charge voltage of the capacitor does not fall, if the power supply relay has the fixed-closure abnormality. A microcomputer diagnoses the power supply relay with respect to its fixed-closure abnormality based on the charge voltage of the capacitor when the ignition switch and the power supply relay are operated to open. | 2010-04-08 |
| 20100085061 | CALIBRATED TWO PORT PASSIVE INTERMODULATION (PIM) DISTANCE TO FAULT ANALYZER - A PIM measurement circuit enables making forward and reverse PIM measurements on any 1 port (reflection) or 2 port (transmission) device with the ability to determine in distance where individual PIM impairments are located as well as their magnitude. The PIM measurement circuit includes two frequency sources that are provided through a combiner for a CW characterization of the PIM circuit. To enable distance determination, an FM measurement is created by using a saw tooth offset sweep generator attached to one of the two frequency sources. With downconversion and processing of signals from the PIM impairments, the FM signal provides a frequency variation that is converted using a Fourier transform or spectrum analysis for separation of frequencies, enabling determination of the distance of the PIM sources as well as their magnitudes. | 2010-04-08 |
| 20100085062 | Network Device, Network Connection Detector and Detection Method Thereof - A network device, a network connection detector and a detection method thereof are disclosed. The network device comprises a socket, a waveform generator and a reflected wave detector. The waveform generator sends a first test wave to at least a first contact of a plurality of contacts of a socket and then the reflected wave detector detects a first reflected wave that is corresponding to the first test wave and is reflected from the first contact. Thus a first control signal is generated according to detection result of the first reflected wave. | 2010-04-08 |
| 20100085063 | METHOD OF DIAGNOSING DEFECTIVE ELEMENTS IN A STANDALONE SYSTEM, POWERED BY AN INTERMITTENT POWER SOURCE - The diagnostic method applies to a standalone system including a generator, a power regulator and a power storage element. The method includes comparison of the effective charging power or current of the power storage element respectively with a predefined power or current threshold. If the effective charging power or current is lower than said threshold, the power storage element is disconnected. An abnormal behavior is then detected either by comparing the effective charging power with the smaller of the values representative of the theoretical charging power of the power storage element and of the maximum power able to be delivered by the generator and comparing the effective and theoretical charging voltages, or by comparing the effective and theoretical charging currents. | 2010-04-08 |
| 20100085064 | UNIVERSAL POWER AND TESTING PLATFORM - The present invention is directed to a Universal Power Platform (UPP) that powers the pump or pumps that may not be on the platform but that are in a skid subsea near the pipeline for a desired pre-commissioning method to be carried out, such as cleaning, filling, chemical treating, pigging, hydrostatic testing or dewatering the pipeline. The UPP is suspended from a vessel by an umbilical that provides the electric power for running the selected pump(s). The Power Platform also is used as a testing system for control umbilicals that usually are near the pipelines. | 2010-04-08 |
| 20100085065 | PASSIVE AGENT SYSTEM IMPEDANCE MONITORING STATION AND METHOD - This invention relates to a hybrid passive agent system impedance monitoring station and method. The method of monitoring impedance of an electrical system includes the steps of providing an impedance monitoring station adapted to test and monitor system impedance, solving for system impedance in a time domain, solving for system impedance in a frequency domain, and determining a time domain driving point impedance and a frequency domain driving point impedance to identify the impedance of the system. | 2010-04-08 |
| 20100085066 | METHODS AND SYSTEMS FOR THE RAPID DETECTION OF CONCEALED OBJECTS - The present invention provides for an improved scanning process having microwave arrays comprised of microwave transmitters in radiographic alignment with microwave receivers. The microwave array emits controllably directed microwave radiation toward an object under inspection. The object under inspection absorbs radiation in a manner dependent upon its metal content. The microwave radiation absorption can be used to generate a measurement of metal content. The measurement, in turn, can be used to calculate at least a portion of the volume and shape of the object under inspection. The measurement can be compared to a plurality of predefined threats. The microwave screening system is used in combination with other screening technologies, such as NQR-based screening, X-ray transmission based screening, X-ray scattered based screening, or Computed Tomography based screening. | 2010-04-08 |
| 20100085067 | ANESTHESIA MONITOR, CAPACITANCE NANOSENSORS AND DYNAMIC SENSOR SAMPLING METHOD - Embodiments of nanoelectronic sensors are described, including sensors for detecting analytes such as anesthesia gases, CO2 and the like in human breath. An integrated monitor system and disposable sensor unit is described which permits a number of different anesthetic agents to be identified and monitored, as well as concurrent monitoring of other breath species, such as CO2. The sensor unit may be configured to be compact, light weight, and inexpensive. Wireless embodiments provide such enhancements as remote monitoring. A simulator system for modeling the contents and conditions of human inhalation and exhalation with a selected mixture of a treatment agent is also described, particularly suited to the testing of sensors to be used in airway sampling. | 2010-04-08 |
| 20100085068 | SENSOR DEVICE FOR DETECTING ELECTRICAL PROPERTIES OF A FLUID - The sensor device for detecting electrical properties of a fluid under high pressure has: a pressure-tight housing, whose cavity is connectable to a high pressure line via an opening, a sensor for electrical properties, which is situated in the cavity, glass feedthroughs, which electrically connect the contacts on an external surface of the housing to the sensor. | 2010-04-08 |
| 20100085069 | Impedance optimized interface for membrane probe application - In a membrane probing apparatus, the impedance of the interface between coaxial cables connected to the test instrumentation and the membrane supported co-planar waveguide that conductively connects to the probe's contacts is optimized by eliminating a ground plane in the interface board. | 2010-04-08 |
| 20100085070 | CARRIER TRAY FOR USE WITH PROBER - A carrier tray for use with a prober is arranged to allow the prober to measure or test not only semiconductor wafers but also semiconductor packages and accurately position each of different-shaped semiconductor packages. A carrier tray includes a lowermost tray and an uppermost tray interposing therebetween an intermediate tray. The lowermost and uppermost trays and are each of a circular shape having a diameter D | 2010-04-08 |
| 20100085071 | THERMOELECTRIC DEVICE AND METHOD - A system, device and method for electrically addressing an element include providing a thermoelectric layer in proximity with an area to be addressed and positioning a probe in proximity of the thermoelectric layer. Electrical activity is induced in the thermoelectric layer by applying heat from the probe. A response is caused in the area to be addressed. | 2010-04-08 |
| 20100085072 | DETECTION CONTROL CIRCUIT FOR ANTI-LEAKAGE - The present invention discloses a detection control circuit for preventing a leakage current, which comprises a register unit comprising a clock signal input terminal for receiving a clock signal; a reset signal input terminal, for receiving a reset signal; a signal generating terminal, for generating a logic signal; and a logic gate, coupled to said register unit, comprising a first signal input terminal for receiving said logic signal; a second signal input terminal for receiving a control signal; and a signal output terminal, for outputting an output signal according to said logic signal and said control signal; wherein said control signal controls said logic gate so as to keep said output signal to be in a fixed state which detects a leakage current in an integrated circuit due to the process flaw. | 2010-04-08 |
| 20100085073 | ACCURATE MEASURING OF LONG STEADY STATE MINORITY CARRIER DIFFUSION LENGTHS - Surface photo-voltage measurements are used to accurately determine very long steady state diffusion length of minority carriers and to determine iron contaminant concentrations and other recombination centers in very pure wafers. Disclosed methods use multiple (e.g., at least two) non-steady state surface photovoltage measurements of diffusion length done at multiple (e.g., at least two) modulation frequencies. The measured diffusion lengths are then used to obtain a steady state diffusion length with an algorithm extrapolating diffusion length to zero frequency. The iron contaminant concentration is obtained from near steady state measurement of diffusion length at elevated frequency before and after iron activation. The concentration of other recombination centers can then be determined from the steady state diffusion length and the iron concentration measured at elevated frequency. | 2010-04-08 |
| 20100085074 | POWER CONVERTER, SHORT DETECTION CIRCUIT THEREOF, AND METHOD FOR DETECTING SHORT - A short detection circuit, for detecting an output node corresponding to an output voltage converted from an input voltage of a power converter, includes a first current source, a charging/discharging unit, a comparator, and a logic control unit. The charging/discharging unit performs charging operation in accordance with the first current source to generate a charging signal in a shorted condition of the output node. The comparator outputs an enable signal by comparing the charging signal with a reference signal. The logic control unit is controlled by the enable signal to generate a fault signal for turning off a first switch coupled between the output node and the input voltage in the shorted condition of the output node. A method for detecting short of an output node corresponding to an output voltage converted from an input voltage of a power converter is also disclosed herein | 2010-04-08 |
| 20100085075 | INTEGRATED CIRCUIT AND METHOD FOR PREVENTING AN UNAUTHORIZED ACCESS TO A DIGITAL VALUE - An integrated circuit including a digital key provider comprising an output and an enable-input, wherein the digital key provider is configured to provide the digital key at the output only when an enable-signal is provided to the enable-input; and a fuse unit comprising a first fuse and a second fuse, wherein the fuse unit is configured to provide the enable-signal to the enable-input when the first fuse is broken while the second fuse is intact. | 2010-04-08 |
| 20100085076 | CIRCUIT COMPRISING A MATRIX OF PROGRAMMABLE LOGIC CELLS - An integrated circuit comprises a matrix ( | 2010-04-08 |
| 20100085077 | FPGA WITH HYBRID INTERCONNECT - An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose FPGA device or fabric, this fast reconfigurability is normally implemented by special reconfiguration support circuitry and/or additional configuration memory. Unfortunately, this flexibility requires a large amount of programmable routing resource and silicon area—limiting the viability in volume production applications. This invention describes how multi-program FPGA functionalities may be migrated to smaller die by constructing implementations with a hybrid FPGA/ASIC interconnect structure. These implementations retain multi-program capability while requiring a much smaller silicon area than a conventional FPGA when customized for a particular set of user applications. | 2010-04-08 |
| 20100085078 | Digital Logic Voltage Level Shifter - A digital logic level shifter having three stages. An initial stage includes a conventional 4-terminal bridge-type inverter circuit. A middle stage includes a 5-terminal first logic reversing circuit that has two middle stage inputs that are not connected in common. And a final stage includes a 5-terminal second logic reversing circuit that has two final stage inputs that are not connected in common. | 2010-04-08 |
| 20100085079 | Low Latency, Power-Down Safe Level Shifter - In one embodiment, an apparatus comprises a circuit supplied by a first supply voltage during use, the circuit having at least a first input signal; and a level shifter supplied by the first supply voltage during use and coupled to provide the first input signal to the circuit. The level shifter is coupled to receive a second input signal sourced from circuitry supplied by a second supply voltage during use, and is configured to generate the first input signal by level shifting the second input signal. Coupled to receive a power control signal indicating, when asserted, that the second supply voltage is to be powered down, the level shifter is configured to assert a predetermined level on the first input signal independent of the second input signal and responsive to an assertion of the power control signal. | 2010-04-08 |
| 20100085080 | ELECTRONIC DEVICE WITH A HIGH VOLTAGE TOLERANT UNIT - An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (V | 2010-04-08 |
| 20100085081 | INVERTER MANUFACTURING METHOD AND INVERTER - To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in which a channel layer includes at least one element selected from In, Ga and Zn formed on a same substrate, the inverter being the E/D inverter having plural thin film transistors, is characterized by comprising the steps of: forming a first transistor and a second transistor, the thicknesses of the channel layers of the first and second transistors being mutually different; and executing heat treatment to at least one of the channel layers of the first and second transistors. | 2010-04-08 |
| 20100085082 | TERNARY SENSOR INPUTS - One of a first signal, a second signal, and a third signal is received respectively from each of three inputs. A pattern formed by the first signal, the second signal, and the third signal is compared to a set of predetermined patterns. Based on the comparing, it is determined whether an error exists. If an error condition exists, a specific one of the inputs is identified as a cause of the error. | 2010-04-08 |
| 20100085083 | GATE DRIVING CIRCUIT HAVING A LOW LEAKAGE CURRENT CONTROL MECHANISM - A gate driving circuit having a low leakage current control mechanism is disclosed for providing a plurality of gate signals forwarded to a plurality of gate lines respectively. The gate driving circuit includes a plurality of shift registers. Each shift register includes a driving unit, an energy store unit, a buffer unit, a voltage regulation unit, and a control unit. The driving unit generates a gate signal based on a driving control voltage and a first clock. The buffer unit functions to receive a start pulse signal. The energy store unit provides the driving control voltage through performing a charging process based on the start pulse signal. The control unit generates a control signal based on the first clock and a second clock having a phase opposite to the first clock. The voltage regulation unit regulates the driving control voltage based on the control signal. | 2010-04-08 |
| 20100085084 | CLOCK-SHARED DIFFERENTIAL SIGNALING INTERFACE AND RELATED METHOD - The present invention provides a clock-shared differential signaling interface and a method of driving output data to a display panel. The apparatus includes a plurality of driver circuits, wherein each driver circuit in the plurality of driver circuits respectively provides output data. The apparatus also includes a timing controller providing a first clock signal to the plurality of driver circuits via a multi-drop connection, and providing a respective differential data signal to each driver circuit via a respective point-to-point connection. | 2010-04-08 |
| 20100085085 | FREQUENCY SYNTHESIZER, FREQUENCY PRESCALER THEREOF, AND FREQUENCY SYNTHESIZING METHOD THEREOF - A frequency synthesizer is provided, including a voltage-controlled oscillator (VCO), a frequency prescaler, a divide-by-2.5 circuit, and a selector. The VCO determine the frequency of a first signal according to an input voltage. The frequency prescaler determines the frequency of a second signal to be the frequency of the first signal divided by 3, 3.5, or 4 according to a first selection signal, and the frequency prescaler also determines the frequency of a third signal to be the frequency of the first signal divided by 6, 7, or 8 according to the first selection signal. The divide-by-2.5 circuit generates a fourth signal, wherein the frequency of the fourth signal is the frequency of the first signal divided by 2.5. The selector selects one of the second signal, the third signal, and the fourth signal as a fifth signal according to a second selection signal. | 2010-04-08 |
| 20100085086 | Digital Frequency Detector - In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values. | 2010-04-08 |
| 20100085087 | AUTOMATIC ON-CHIP DETECTION OF POWER SUPPLY CONFIGURATION-MODES FOR INTEGRATED CHIPS - A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication. | 2010-04-08 |
| 20100085088 | Semiconductor device and method of supplying internal power to semiconductor device - Provided is a semiconductor device including a step-down circuit group including multiple step-down circuits that step down an external power supply voltage to a predetermined voltage; multiple functional circuits that require a reset operation upon power-on; and a power-on reset circuit that outputs a reset command to the multiple functional circuits, when an internal power supply voltage supplied from the step-down circuit group exceeds a voltage level necessary for an initialization operation. The multiple step-down circuits of the step-down circuit group are classified into a startup operating step-down circuit group that performs a step-down operation from power-on to supply the internal power supply voltage, and a startup non-operating step-down circuit group that stops operation upon power-on to interrupt supply of the internal power supply voltage. The startup non-operating step-down circuit group includes the multiple step-down circuits sequentially selected from one having a shortest wiring distance from the power-on reset circuit. | 2010-04-08 |
| 20100085089 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals. | 2010-04-08 |
| 20100085090 | CLOCK CLEAN-UP PHASE-LOCKED LOOP (PLL) - A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal. | 2010-04-08 |
| 20100085091 | PROPORTIONAL PHASE COMPARATOR AND METHOD FOR PHASE-ALIGNING DIGITAL SIGNALS - Embodiments of a proportional phase comparator and method for aligning digital signals are generally described herein. In some embodiments, circuitry to align digital signals comprises a proportional phase comparator that generates triangular-shaped pulses for application to a charge pump. The triangular-shaped pulses may reduce an amount of charge injection in the charge pump close to convergence. | 2010-04-08 |
| 20100085092 | Phase-Locked Loop Integrated Circuits Having Dual Feedback Control - Phase-locked loop (PLL) integrated circuits according to embodiments of the invention provide dual feedback control. The first feedback control utilizes a conventional phase locking scheme that passes a feedback clock signal to an input of a phase-frequency detector (PFD). The second feedback control utilizes an automatic frequency calibrator that evaluates a frequency of an output of a voltage-controlled oscillator (VCO) relative to a locked frequency detected during calibration and provides separate calibration control to a charge pump. | 2010-04-08 |
| 20100085093 | MULTI-PHASE CLOCK SYSTEM - The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLK | 2010-04-08 |
| 20100085094 | MULTI-PHASE SIGNAL GENERATOR AND METHOD - A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse. | 2010-04-08 |
| 20100085095 | APPARATUS AND METHOD FOR MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount. | 2010-04-08 |
| 20100085096 | ENERGY-EFFICIENT CLOCK SYSTEM - A system comprises first timing logic configured to produce a first signal and second timing logic configured to produce a second signal. The system also comprises processing logic coupled to the first and second timing logic. The system further comprises clock logic that determines elapsed time using the first signal. The processing logic compares the first and second signals and, based on the comparison, the system adjusts the elapsed time. | 2010-04-08 |
| 20100085097 | Pulse-Elimination Pulse-Width Modulation - Instead of reducing the pulse widths of all pulses simultaneously in order to reduce the output power of a switched-mode amplifier linearized by a pulse-width modulator, the width of every other (or every n-th) pulse is reduced. When the widths of the selected pulses have been reduced to zero, the amplifier's output power can be further reduced by selecting further pulses from the remaining non-zero-width pulses, and reducing the widths of those pulses. For example, after every other pulse of an original output signal has been removed, every other pulse of the remaining pulses can be reduced to obtain still lower amplifier output power. In this way, the number of pulses (and thus the number of switching transitions) is reduced for small signals, and therefore the amplifier's switching losses are reduced and efficiency is improved. | 2010-04-08 |
| 20100085098 | DIGITAL DELAY LINE DRIVER - Improved digital delay line driver is described. A delay line driver circuit includes elements to drive the delay line in one or multiple locations to provide a dynamic, adjustable slew rate on the output signal. The delay line driver circuit may also include active elements coupled to the transistors of the delay line to deactivate the delay line transistors substantially simultaneously, rather than cascading in series. Shutting off the delay line transistors substantially simultaneously reduces or eliminates crowbar or shoot through current on an edge transition of the output signal. | 2010-04-08 |
| 20100085099 | MULTI-PHASE SIGNAL GENERATOR AND METHOD - Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One of the intermediate clock signals may be used as an enable signal to guide locking of all signals. For example, the 180 degree clock signal may be inverted and used as an enable signal to guide locking of the initial and 360 degree signals in a single phase adjustment procedure. The 0 and 360 degree signals may be delayed before their phase is compared to compensate for duty cycle error in the clock signals. | 2010-04-08 |
| 20100085100 | Low-Power Clock Generation and Distribution Circuitry - A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal. | 2010-04-08 |
| 20100085101 | RECEPTION COMPARATOR FOR SIGNAL MODULATION UPON A SUPPLY LINE - A receiving stage for a multi-stage signal modulated upon a supply voltage, including: a supply potential terminal and a ground potential terminal, a voltage divider and a low-pass filter, whose input is connected to the supply potential terminal and the ground potential terminal, and which has an output which is arranged to output the low-pass filter output signal. The stage also includes a high comparator having an high threshold value, an output and a receiving signal input that is connected to the output of the low-pass filter and is arranged to receive the low-pass filter output signal; a low comparator having a low threshold value, an output and a receiving signal input that is connected to the output of the low-pass filter and is arranged to receive the low-pass filter output signal; and a high threshold value generator which is arranged to raise the high threshold value if the low-pass filter output signal is less than the high threshold value, and to lower the high threshold value if the low-pass filter output signal is greater than the high threshold value. Finally, the stage includes a low threshold value generator which is arranged to raise the low threshold value if the low-pass filter output signal is less than the low threshold value, and to lower the low threshold value if the low-pass filter output signal is greater than the low threshold value. A method for receiving a multi-stage signal is also provided which operates according to the operating principle of the receiving stage. | 2010-04-08 |
| 20100085102 | METHOD AND AN APPARATUS FOR PROCESSING A SIGNAL - A method of processing a signal is disclosed. The present invention includes receiving (a) a downmix signal being generated from plural-channel signal and (b) spatial information indicating attribute of the plural-channel signal, in order to upmix the downmix signal; obtaining inter-channel phase difference(IPD) coding flag indicating whether IPD value is used to the spatial information from a header of the spatial information; obtaining IPD mode flag indicating whether the IPD is used to frame of the spatial information from the frame based on the IPD coding flag; obtaining the IPD value from a parameter band in the frame based on the IPD mode flag; generating plural-channel signal by applying the IPD value to the downmix signal, wherein the spatial information is divided by header and a plurality of the frame and wherein the IPD value indicates phase difference between two channels of the plural-channel signal and wherein the parameter band is at least one sub-band of frequency domain including the IPD value. | 2010-04-08 |
| 20100085103 | System and Method for Charge Integration - An arrangement for charge integration comprises an input ( | 2010-04-08 |
| 20100085104 | MIXER CIRCUIT - Regarding N-channel first transistor and a P-channel second transistor, their first terminals are connected to each other and their second terminals are connected to each other. Regarding third transistor and a fourth transistor, their first terminals are also connected to each other and their second terminals are also connected to each other. For the first transistor through the fourth transistor, a first capacitor through a fourth capacitor used for coupling are provided. A first impedance element through a fourth impedance element are provided in a path where a bias voltage is applied to the first transistor through the fourth transistor. A fifth capacitor is provided between the first terminals of the first-fourth transistors and a first input terminal. A fifth impedance element and a sixth impedance element are provided as differential pair loads. | 2010-04-08 |
| 20100085105 | CIRCUIT ARRANGEMENT INCLUDING A VOLTAGE SUPPLY CIRCUIT AND SEMICONDUCTOR SWITCHING ELEMENT - A circuit arrangement comprising a first semiconductor switching element, which has a load path and a drive terminal. A voltage supply circuit, is provided including an inductance connected in series with the load path of the first semiconductor switching element, and a capacitive charge storage arrangement, which is connected in parallel with the inductance and which has a first and a second output terminal for providing a supply voltage. | 2010-04-08 |
| 20100085106 | Method for Operating a Converter Circuit with Voltage Boosting - Method for operating a converter circuit with voltage boosting with N half-bridges, which in each case can be connected by their center connection to a phase of an N-phase generator and at an end side are connected in parallel with a series circuit formed by two capacitances, wherein each half-bridge contains a Top switch and a Bot switch, in which, in a PWM method with a fixed period duration at the beginning of the period duration, all the TOP switches are simultaneously switched on for the duration of a TOP switched-on interval. After half the period duration all the BOT switches are simultaneously switched on for the duration of a BOT switched-on interval wherein the TOP switched-on interval, and the BOT switched-on interval amount at most to half the duration of the period. | 2010-04-08 |
| 20100085107 | Trim fuse circuit capable of disposing trim conducting pads on scribe lines of wafer - A trim fuse circuit includes a metal fuse, a trim pad coupled to the first end of the metal fuse, a first transistor coupled to the first end of the metal fuse, a second transistor coupled to the second end of the metal fuse, an inverter coupled to the second end of the metal fuse, a switch coupled to the second end of the metal fuse, and a common trim pad coupled to the control end of the switch. The inverter outputs a data signal according to the status of the metal fuse. The trim pad can be disposed on the scribe line of a wafer. When the trim pad is cut and accordingly connects to the substrate of the wafer, the data signal is not affected. | 2010-04-08 |
| 20100085108 | SYSTEM AND METHOD FOR ADJUSTING SUPPLY VOLTAGE LEVELS TO REDUCE SUB-THRESHOLD LEAKAGE - A voltage regulation module which includes an adjustable voltage which reduces the positive supply voltage and increases the negative supply voltage during a lower power mode. The voltage regulation module includes a voltage generator which provides an N-type substrate bias voltage at the normal operating voltage level of the positive supply voltage and which provides a P-type substrate bias voltage at the normal operating voltage level of the negative supply voltage during the lower power mode. Thus, the supply voltage levels are adjusted rather than the substrate bias voltages during the lower power mode. The voltage generator may be implemented as a voltage regulator, or may be implemented as a bias generator or charge pump or the like. | 2010-04-08 |
| 20100085109 | SWITCH CIRCUIT, VARIABLE CAPACITOR CIRCUIT AND IC OF THE SAME - A first terminal T | 2010-04-08 |
| 20100085110 | Integrated Circuit Active Power Supply Regulation - Method and apparatus for compensating for voltage fluctuations on a voltage supply line in an integrated circuit device. In accordance with some embodiments, the apparatus includes a voltage fluctuation sensor which senses a voltage on the supply line, and a compensation circuit comprising a switch and a charge storage device (CSD). The switch actively connects the CSD to the supply line when the voltage sensed by the voltage fluctuation sensor passes outside a predetermined voltage range. | 2010-04-08 |
| 20100085111 | Charge pump-type voltage booster circuit and semiconductor integrated circuit device - A booster circuit includes first and second transistors, a first capacitor, a first drive circuit, a second capacitor, a first controller, and a second controller. The first and second transistors are connected in series between a first voltage and a second voltage. One end of the first capacitor is connected to a connection node between the first transistor and the second transistor. The first drive circuit boosts the voltage at the other end of the first capacitor. The second capacitor is connected between the second voltage and a reference voltage. The first controller controls conduction/non-conduction of the first transistor. The second controller inputs any of the first voltage and the second voltage to the second transistor, and thereby controls conduction/non-conduction of the second transistor. The boost circuit is supplied with the reference voltage, a supply voltage, and a boost clock signal, and generates the second voltage by boosting the supply voltage. | 2010-04-08 |
| 20100085112 | Method of Manufacturing a Transistor, and Method of Controlling a Threshold Voltage of the Transistor - A transistor has a gate electrode, a gate insulation layer structure, a channel layer and source/drain layers. The gate insulation layer structure includes a lower gate insulation layer, a control layer for controlling a threshold voltage of the transistor, and an upper gate insulation layer. The channel layer contacts a surface of the gate insulation layer structure and vertically overlaps the gate electrode. The source/drain layers are adjacent to but not contacting the gate electrode. | 2010-04-08 |
| 20100085113 | Internal voltage generation circuit - An internal voltage generation circuit includes a signal generation unit which generates first and second level signals and first and second control signals from a reference voltage generated by voltage-dividing an internal power and generates first and second driving signals by comparing levels of the internal power and the reference voltage, a driving control unit which receives the first and second level signals and drives the internal voltage in response to an active signal, and a driving unit which receives the first and second driving signals and drives the internal voltage. | 2010-04-08 |
| 20100085114 | HIGH-VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE PROVIDED THEREWITH AND SEMICONDUCTOR INTEGRATED DEVICE - A voltage generation circuit includes a pump circuit, a first unit, a first switch, and a first capacitor. The pump circuit generates a first voltage and outputs the first voltage to a first node. The first unit includes a first resistance unit to output a second voltage at a second node. The first switch connects the second node and an output terminal. A resistance value of a parasitic resistance formed in an interconnection from the second node to the output terminal is smaller than a resistance value of the first resistance unit. The first capacitor includes one of electrodes and the other electrodes. The one of electrodes is connected to an interconnection connecting the second node and the first switch element. The other of the electrodes is grounded. A capacitance of the first capacitor element is larger than a capacitance connected to the output terminal. | 2010-04-08 |
| 20100085115 | SIGNAL GENERATOR - This invention generally relates to signal generation, clock signal generation and ramp signal generation, and trimming the temperature coefficient of a signal. | 2010-04-08 |
