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14th week of 2010 patent applcation highlights part 14
Patent application numberTitlePublished
20100084714DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL - A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.2010-04-08
20100084715PHOTO ALIGNMENT MARK FOR A GATE LAST PROCESS - A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.2010-04-08
20100084716Semiconductor device - Provided is a semiconductor device including a substrate, a gate insulating film which is formed on the substrate, and a gate electrode which is provided on the gate insulating film. The gate electrode includes a first metal silicide including a first metal material, and a second metal silicide including one of a second metal material and the second metal material in a contact portion between the gate insulating film and the gate electrode. The second metal silicide including the second metal material is a metal-rich silicide in which the composition ratio of the second metal material to silicon in the second metal silicide including the second metal is greater than 1.2010-04-08
20100084717Semiconductor device - Provided is a semiconductor device in which occurrence of humps can be suppressed and variations in characteristics of the semiconductor device can be suppressed. The semiconductor device includes: an element isolation film (2010-04-08
20100084718ADVANCED METAL GATE METHOD AND DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.2010-04-08
20100084719 TRANSISTOR PERFORMANCE WITH METAL GATE - The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.2010-04-08
20100084720Gate in semiconductor device and method of fabricating the same - A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.2010-04-08
20100084721Micro-Electromechanical System Microstructure - A micro-electromechanical system microstructure includes: a substrate adapted to support an electrode thereon; a suspension mechanism supported on the substrate; and a movable active part adapted to cooperate with the electrode to define a capacitor therebetween, and suspended on the substrate through the suspension mechanism so as to be movable to and fro relative to the substrate and the electrode. The suspension mechanism includes at least one supporting frame that protrudes from and that cooperates with an outer surface of the substrate to define a frame space therebetween, and at least one cantilever beam interconnecting the supporting frame and the active part.2010-04-08
20100084722Method for manufacturing a micromechanical chip and a component having a chip of this type - In a method for manufacturing a micromechanical chip, a sacrificial layer and an epitaxy layer are initially applied to a semiconductor substrate to produce a layer stack. An opening is subsequently introduced into the epitaxy layer from the front side of the layer stack. In order to electrically insulate the subsequent filling of the opening using a conductive contact layer from the material of the epitaxy layer, the walls of the opening are provided with an insulating layer. For removing the sacrificial layer and thus for producing the chip, separation trenches are subsequently etched through the epitaxy layer to the sacrificial layer also from the front side of the layer stack, which separation trenches also delimit the lateral extension of the chip.2010-04-08
20100084723MEMS STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An MEMS structure and a method of manufacturing the same are provided. The MEMS structure includes a substrate and at least one suspended microstructure located on the substrate. The suspended microstructure includes a plurality of metal layers, at least one dielectric layer, and at least one peripheral metal wall. The dielectric layer is sandwiched by the metal layers, and the peripheral metal wall is parallel to a thickness direction of the suspended microstructure and surrounds an edge of the dielectric layer.2010-04-08
20100084724MEMORY CELL WITH STRESS-INDUCED ANISOTROPY - A magnetic memory element that has a stress-induced magnetic anisotropy. The memory element has a ferromagnetic free layer having a switchable magnetization orientation switchable, a ferromagnetic reference layer having a pinned magnetization orientation, and a non-magnetic spacer layer therebetween. The free layer may be circular, essentially circular or nearly circular.2010-04-08
20100084725MAGNETIC MEMORY WITH ASYMMETRIC ENERGY BARRIER - A magnetic tunnel junction cell includes a ferromagnetic reference layer, a ferromagnetic free layer, and a non-magnetic barrier layer separating the ferromagnetic reference layer from the ferromagnetic free layer. The magnetic tunnel junction cell has an asymmetric energy barrier for switching between a high resistance data state and a low resistance data state. Memory devices and methods are also described.2010-04-08
20100084726Wafer level packaging image sensor module having lens actuator and method of manfacturing the same - Disclosed herein is a wafer level packaging image sensor module, including a wafer including an image sensor, a circuit portion and a lower electrode on one side thereof, a lens actuator disposed on the lower electrode and made of electroactive polymer, an upper electrode disposed on the lens actuator, and a lens unit disposed on the upper electrode to allow light to be transmitted to the image sensor therethrough. The wafer level packaging image sensor module includes the lens actuator made of electroactive polymer, and thus it enables realization of the autofocusing of the wafer level packaging image sensor module.2010-04-08
20100084727PRINTED WIRING BOARD, A METHOD OF MANUFACTURING PRINTED WIRING BOARD, A SENSOR MODULE, AND A SENSING DEVICE - A printed wiring board on which a package to be arranged, including: a first layer that is relatively rigid; and a second layer that is relatively flexible and on which the package is to be soldered, wherein an area other than a package arrangement area of the second layer is joined to the first layer by an adhesion layer.2010-04-08
20100084728SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging device according to the present invention includes light-receiving units formed on a surface in a substrate, a photo-shield film formed above the substrate and having openings above the light-receiving units, a light-transmissive insulating film formed above the photo-shield film and in the openings in the photo-shield film, downwardly convex in-layer lenses made of a material having a refractive index different from that of the light-transmissive insulating film and formed above the light-transmissive insulating film, an OCCF formed above the in-layer lenses and having a first filter and a second filter which are positioned above different ones of the light-receiving units and transmit lights of different wavelengths, and OCLs formed above the in-layer lenses. The width of the openings in the photo-shield film and the curvature of the in-layer lenses provided under the first filter and those under the second filter are different from each other, respectively.2010-04-08
20100084729INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES - A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.2010-04-08
20100084730Front Illuminated Back Side Contact Thin Wafer Detectors - The present invention is directed toward a detector structure, detector arrays, a method of detecting incident radiation, and a method of manufacturing the detectors. The present invention comprises several embodiments that provide for reduced radiation damage susceptibility, decreased affects of cross-talk, and increased flexibility in application. In one embodiment, the present invention comprises a plurality of front side illuminated photodiodes, optionally organized in the form of an array, with both the anode and cathode contact pads on the back side. The front side illuminated, back side contact photodiodes have superior performance characteristics, including less radiation damage, less crosstalk using a suction diode, and reliance on reasonably thin wafers. Another advantage of the photodiodes of the present invention is that high density with high bandwidth applications can be effectuated.2010-04-08
20100084731IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes a trench formed by a shallow trench isolation (STI) process, a channel stop layer formed over a substrate in the trench, an isolation structure filled in the trench, and a photodiode formed in the substrate adjacent to a sidewall of the trench. In more detail of the image sensor, a trench is formed in a substrate through a STI process, and a channel stop layer is formed over the substrate in the trench. An isolation structure is formed in the trench, and a photodiode is formed in the substrate adjacent to a sidewall of the trench.2010-04-08
20100084732Semiconductor Device and Method of Manufacturing the Same - Disclosed herein is a method of manufacturing a semiconductor device that is adapted to improve the production yield. The method generally includes etching a semiconductor substrate to form a trench, filling the trench with a conductive material, separating the filled conductive material to form a plurality of gate patterns and a bit line contact region, and etching the substrate to define an isolation region.2010-04-08
20100084733ISOLATION LAYER OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device isolation layer includes a semiconductor substrate defining an upper trench etched to a predetermined depth, a lower trench defined in the semiconductor substrate at a lower part of the upper trench, the lower trench having a smaller width than the upper trench, and an insulating oxide embedded in the upper and lower trenches. Accordingly, since a stepped structure is formed in the trenches, generation voids may be restrained while improving the gap-filling efficiency.2010-04-08
20100084734MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - To provide a semiconductor substrate in which a semiconductor element having favorable crystallinity and high performance can be formed. A single crystal semiconductor substrate having an embrittlement layer and a base substrate are bonded with an insulating layer interposed therebetween; the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment; a single crystal semiconductor layer is fixed to the base substrate; the single crystal semiconductor layer is irradiated with a laser beam; the single crystal semiconductor layer is in a partially melted state to be recrystallized; and crystal defects are repaired. In addition, the energy density of a laser beam with which the best crystallinity of the single crystal semiconductor layer is obtained is detected by a microwave photoconductivity decay method.2010-04-08
20100084735SEMICONDUCTOR ASSEMBLY AND METHOD FOR FORMING SEAL RING - A method for forming a seal ring is disclosed. First, a substrate including a MEMS region, a logic region and a seal ring region is provided. Second, a trench is formed in the MEMS region and multiple recesses are formed in the seal ring region. An oxide fills the trench and the recesses. Later, a MOS is form in the logic region and a dielectric layer is formed on the substrate. Then, an etching procedure is carried out to partially remove the dielectric layer and simultaneously remove the oxide in the multiple recesses completely to form a seal ring space. Afterwards, a metal fills the seal ring space to from the seal ring.2010-04-08
20100084736SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA - A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.2010-04-08
20100084737Tunable Semiconductor Component Provided with a Current Barrier - This invention pertains to a color coatings blender apparatus to be used for color composition customization for the application of color coatings on 2D and 3D surfaces. The apparatus is comprised of a main body and interchangeable inserts all with central blender chambers and primary and secondary ports, and interchangeable spindles; the configurations of which are governed by coating technical characteristics. This invention integrates gradient specific programmable computer digital processes to function as internal editors, manipulate information and present the operator with multiple options and production overrides. This invention will make data analysis more interactive by utilizing existing external software applications as editors and expanding the process of visual communications for multiple purposes. While the blender apparatus, complete with external selectable appurtenances, can be used manually, it can also be combined with a programmable computer for producing physical gradient layers.2010-04-08
20100084738CAPACITANCE ELEMENT, PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR CIRCUIT - A capacitive element that can efficiently reduce high-frequency noise generated in a circuit is provided. A capacitive element 2010-04-08
20100084739Semiconductor device and method of manufacturing the same - A semiconductor device includes a MIM capacitor that includes an insulating film and a first electrode and a second electrode which are formed in the same layer in the insulating film and are facing to each other with the insulating film interposed therebetween. The first electrode and the second electrode respectively include a first high aspect via and a second high aspect via which extend as long as a length, in a stacked direction of the substrate, of a via and an interconnect provided on the via so as to be connected to the via formed in another region. A first potential and a second potential are respectively supplied to the first electrode and the second electrode.2010-04-08
20100084740CAPACITOR WITH ZIRCONIUM OXIDE AND METHOD FOR FABRICATING THE SAME - A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2010-04-08
20100084741Integrated Circuit - According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.2010-04-08
20100084742Method for manufacturing semiconductor epitaxial crystal substrate - The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.2010-04-08
20100084743METHOD FOR REDUCING CRYSTAL DEFECT OF SIMOX WAFER AND SIMOX WAFER - The method includes: a first step of colliding ions implanted from a surface of a SIMOX wafer into a silicon layer underneath a BOX layer against crystal defects to destroy the crystal defects; and a second step of heating the wafer obtained in the first step to recrystallize the silicon layer. If the ions to be implanted into the silicon layer are oxygen ions, then the first step initiates ion implantation with the temperature of the SIMOX wafer being 50° C. or lower, and sets an ion dose to 5×102010-04-08
20100084744Thermal processing of substrates with pre- and post-spike temperature control - Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.2010-04-08
20100084745Nitride semiconductor substrate - A nitride semiconductor substrate has a first surface forming a principal surface of the substrate. A first edge is formed by beveling at least a portion of an edge of the first surface of the substrate. A scattering region is formed in at least a portion of the first edge. The scattering region scatters more external incident light than the first surface.2010-04-08
20100084746PROCESS FOR PRODUCING LAMINATED SUBSTRATE AND LAMINATED SUBSTRATE - A method of manufacturing a laminated substrate is provided. The method includes: forming an oxide film on at least a surface of a first substrate having a hardness of equal to or more than 150 GPa in Young's modulus, and then smoothing the oxide film; implanting hydrogen ions or rare gas ions, or mixed gas ions thereof from a surface of a second substrate to form an ion-implanted layer inside the substrate, laminating the first substrate and the second substrate through at least the oxide film, and then detaching the second substrate in the ion-implanted layer to form a laminated substrate, heat-treating the laminated substrate and diffusing outwardly the oxide film.2010-04-08
20100084747Zigzag Pattern for TSV Copper Adhesion - A system and method for forming a TSV contact is presented. A preferred embodiment includes a TSV in contact with a portion of the uppermost metal layer of a semiconductor die. The interface between the TSV conductor and the contact pad is preferably characterized by a non-planar zigzag pattern that forms a grid pattern of contacts. Alternatively, the contacts may form a plurality of metal lines that make contact with the contact pad.2010-04-08
20100084748THIN FOIL FOR USE IN PACKAGING INTEGRATED CIRCUITS - Methods for minimizing warpage of a welded foil carrier structure used in the packaging of integrated circuits are described. Portions of a metallic foil are ultrasonically welded to a carrier to form a foil carrier structure. The ultrasonic welding helps define a panel in the metallic foil that is suitable for packaging integrated circuits. Warpage of the thin foil can be limited in various ways. By way of example, an intermittent welding pattern that extends along the edges of the panel may be formed. Slots may be cut to define sections in the foil carrier structure. Materials for the metallic foil and the carrier may be selected to have similar coefficients of thermal expansion. An appropriate thickness for the metallic foil and the carrier may be selected, such that the warpage of the welded foil carrier structure is limited when the foil carrier structure is subjected to large increases in temperature. Foil carrier structures for use in the above methods are also described.2010-04-08
20100084749Package and fabricating method thereof - A package and a fabricating method thereof are provided. The package includes a lead frame, a chip and a sealant. The lead frame has a notch and a plurality of first notch-side leads, a plurality of first notch-side pads, a plurality of second notch-side leads and a plurality of second notch-side pads. The first notch-side leads extend to a first side of the notch. The first notch-side pads are correspondingly disposed on the first notch-side leads. The second notch-side leads extend to a second side of the notch. The second notch-side pads are correspondingly disposed on the second notch-side leads. The sealant seals up the chip and the lead frame and exposes a lower surface of the lead frame. The notch exposes a portion of the sealant.2010-04-08
20100084750MODULE HAVING A STACKED PASSIVE ELEMENT AND METHOD OF FORMING THE SAME - A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material.2010-04-08
20100084751Double Broken Seal Ring - The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating two seal rings with non-adjacent gaps. In one embodiment, the same effect can be achieved by fabricating a wide seal ring with a channel having offset ingress and egress portions. Either of these embodiments can also have grounded seal ring segments which further reduce signal propagation.2010-04-08
20100084752SYSTEMS AND METHODS FOR IMPLEMENTING A WAFER LEVEL HERMETIC INTERFACE CHIP - Systems and methods for enabling hermetic sealing at the wafer level during fabrication of a microelectromechanical sensor (MEMS) device. The MEMS device has a specialized hermetic interface chip (HIC) that facilitates a stable hermetic sealing process. The HIC includes a plurality of vias in a substrate layer, a plurality of mesas having etched portions, a seal ring, a plurality of conductive leads on a first side of the HIC, and a plurality of conductive leads on a second side of the HIC. The plurality of conductive leads on the first side of the HIC feeds from the etched portions of the plurality of mesas through the plurality of vias in the substrate layer to the plurality of conductive leads on the second side of the HIC. The conductive leads are capable of connecting an external circuit to the MEMS device.2010-04-08
20100084753MULTI-CHIP PACKAGE - A multi-chip package is presented which includes a substrate, a lower semiconductor, an upper semiconductor chip, metal wires, an encapsulant, and mounting units. The substrate has electrode terminals on an upper surface and ball lands on a lower surface. The lower semiconductor chip is placed face-down on the substrate. The lower semiconductor chip has first bonding pads, first connectors and metal patterns. The upper semiconductor chip is placed face-down type on the back surface of the lower semiconductor chip. The upper semiconductor has second bonding pads and second connectors. The metal wires electrically the lower semiconductor chip to the substrate. The encapsulant seals the substrate, the lower semiconductor chip, the upper semiconductor chip and the metal wires. The mounting units are on the lower surface of the substrate.2010-04-08
20100084754Semiconductor package - A semiconductor package which includes a first substrate having a pre-designed pattern formed thereon; a first chip mounted by a flip chip method on one side of the first substrate; a support formed to a predetermined thickness on an edge of the first substrate; an interposer having an edge thereof placed on the support, such that the interposer covers the first substrate and forms a cavity between the interposer and the first substrate, and having a pre-designed pattern formed respectively on both sides thereof; a via penetrating the support and the interposer; a second chip mounted on one side of the interposer facing the first substrate; a second substrate placed on the other side of the interposer with at least one conductive ball positioned in-between; and a third chip mounted on the second substrate.2010-04-08
20100084755Semiconductor Chip Package System Vertical Interconnect - Stacked semiconductor chip package system vertical interconnects and related methods are disclosed. A preferred embodiment of the invention includes a first semiconductor chip with a surface bearing a plurality of first fusible metallic coupling elements. A second semiconductor chip has a plurality of second fusible metallic coupling elements. The first and second fusible metallic coupling elements correspond at the adjoining surfaces of the first and second semiconductor chips when stacked, and are fused to form a gold-tin eutectic alloy fused metallic coupling vertically interconnecting the stacked chips.2010-04-08
20100084756DUAL OR MULTIPLE ROW PACKAGE - A dual or multiple row package (2010-04-08
20100084757CONDUCTIVE COMPOSITIONS AND METHODS OF USING THEM - A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.2010-04-08
20100084758Semiconductor package - Provided is a semiconductor package including a mark pattern and a method of manufacturing the same. The semiconductor package may include at least one semiconductor chip including a circuit region, a protection layer covering the circuit region, a molding portion sealing the protection layer and the at least one semiconductor chip, the molding portion having an exposed top surface on the circuit region, and a mark pattern at the top surface of the molding portion. A method of fabricating the semiconductor package may include providing at least one semiconductor chip including a circuit region, forming a protection layer covering the circuit region, forming a molding portion sealing the protection layer and the at least one semiconductor chip, the molding portion having an exposed top surface on the circuit region, and forming a mark pattern at the top surface of the molding portion using a laser.2010-04-08
20100084759Die Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration - A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material.2010-04-08
20100084760SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a semiconductor chip mounting substrate, a control circuit board, a power terminal holder and a semi-fixing member. The semiconductor chip mounting substrate includes a substrate, a semiconductor chip provided on a first major surface of the substrate, and a first and second semiconductor chip connection electrodes. The control circuit board is provided generally in parallel to the first major surface and includes a control circuit, a control signal terminal connected to the control circuit, and a through hole extending in a direction generally perpendicular to the first major surface. The power terminal holder is provided on opposite side of the control circuit board from the semiconductor chip mounting substrate and includes a power terminal. The semi-fixing member includes a shank portion and an end portion. The shank portion is fixed to the power terminal holder and penetrates through the through hole. A cross section of the shank portion in a plane orthogonal to the extending direction of the through hole is smaller than a size of the through hole. The end portion is connected to a tip of the shank portion. A cross section of the end portion in the plane is larger than the size of the through hole. The first semiconductor chip connection electrode is connected to a first terminal of the semiconductor chip and the control signal terminal. The second semiconductor chip connection electrode is connected to a second terminal of the semiconductor chip and the power terminal.2010-04-08
20100084761SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SAME - A semiconductor device includes a mounting substrate, a plurality of semiconductor chips mounted on the mounting substrate, and a heat-dissipation area formed above the plurality of semiconductor chips. A distance between one of the plurality of semiconductor chips which generates a greatest amount of heat and the heat-dissipation area is smaller than a distance between the other semiconductor chips and the heat-dissipation area.2010-04-08
20100084762MEMORY CARD - Memory card (2010-04-08
20100084763Metallic Bump Structure Without Under Bump Metallurgy And Manufacturing Method Thereof - The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.2010-04-08
20100084764Carbon nanotube-reinforced solder caps, methods of assembling same, and chip packages and systems containing same - A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.2010-04-08
20100084765Semiconductor package having bump ball - Disclosed is a semiconductor package having a bump ball as an external connection terminal, the bump ball including a core layer containing copper, a copper alloy, aluminum, an aluminum alloy or a combination thereof and a shell layer surrounding the core layer and containing tin, a tin alloy or a combination thereof.2010-04-08
20100084766SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS - Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss.2010-04-08
20100084767DISCONTINUOUS/NON-UNIFORM METAL CAP STRUCTURE AND PROCESS FOR INTERCONNECT INTEGRATION - An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.2010-04-08
20100084768ELECTRONIC COMPONENT, A SEMICONDUCTOR WAFER AND A METHOD FOR PRODUCING AN ELECTRONIC COMPONENT - An electronic component includes a semiconductor substrate defined by a generally planar first face, a generally planar second face and side faces extending between the generally planar second face and the generally planar first face. The semiconductor substrate has a curved contour between the generally planar second face and the side faces.2010-04-08
20100084769SEMICONDUCTOR DEVICE AND DUMMY PATTERN ARRANGEMENT METHOD - A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each of the plurality of dummy patterns is arranged spaced apart from each of the plurality of wiring patterns and includes one or more dummy lands formed by separating a part of the dummy pattern opposed to the wiring pattern, from the rest part of the dummy pattern.2010-04-08
20100084770SEMICONDUCTOR DEVICE WHICH INCLUDES CONTACT PLUG AND EMBEDDED INTERCONNECTION CONNECTED TO CONTACT PLUG - A semiconductor memory device includes: a first dielectric formed on top of a semiconductor substrate; a contact plug embedded in the first dielectric; a second dielectric formed on top of the first interlayer dielectric; an interconnection layer embedded in a groove formed in the second dielectric on top of the contact plug; and an insulating film formed in the second dielectric adjacent to a side surface of the interconnection layer. The contact plug has a notch in a part of a top surface of the contact plug. The insulating film is formed to extend from a top surface of the second dielectric to the notch included in the contact plug.2010-04-08
20100084771FLEXIBLE SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.2010-04-08
20100084772Package and fabricating method thereof - A package and a fabricating method thereof are provided. The package includes a conductive layer, a chip, a plurality of first pads, a plurality of bonding wires and a sealant. The conductive layer has a die pad and includes a plurality of wires. A path of each wire is substantially parallel to a supporting surface of the die pad. Each wire has an upper surface and a lower surface. The chip disposed on the supporting surface has a plurality of pads. The first pads are correspondingly formed on the upper surfaces of the wires. The bonding wires electrically connect the pads of the chip to the first pads. The sealant seals up the conductive layer, the first pads, the chip and the bonding wires, and exposes the lower surface of the conductive layer. The conductive layer projects from a bottom surface of the sealant.2010-04-08
20100084773SEMICONDUCTOR DEVICE AND METHOD OF BONDING WIRES BETWEEN SEMICONDUCTOR CHIP AND WIRING SUBSTRATE - A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip.2010-04-08
20100084774Device and Method for Forming Ceramic Ferrule Blank - A device and a method for forming a ceramic ferrule blank are provided. A shaped wire (2010-04-08
20100084775BIOMEDICAL DEVICES CONTAINING INTERNAL WETTING AGENTS - This invention includes a wettable biomedical device containing a high molecular weight hydrophilic polymer and a hydroxyl-functionalized silicone-containing monomer.2010-04-08
20100084776METHOD FOR PRODUCING SEMICONDUCTOR PARTICLES - A method for producing semiconductor particles includes the steps of: forming granules of predetermined mass from a feedstock including a semiconductor powder by a granulation process; heating the granules to melt and fuse the semiconductor powder included in the granules, to obtain molten spheres; and cooling the molten spheres to solidify them, to obtain spherical semiconductor particles. The granules preferably contain a binder that binds the particles of the semiconductor powder together. When the granules contain a binder, it is preferable to perform a preliminary heating step for removing the binder from the granules before the heating step for melting the semiconductor powder.2010-04-08
20100084777PYROSPHERELATOR - Crystalline alumina particles are intimately mixed with a gaseous fuel, air and oxygen. The mixture is then ignited in a torch. Such blending of the powder with the combustible gas allows the alumina particles to be immediately heated to above their melting temperature and allows the particles to form into spheres. The spheres are then rapidly cooled to ambient temperature, providing high purity micron-sized polymorphic alumina spheres without the use of additives or special treatment.2010-04-08
20100084778DENTAL POST - A method of manufacturing a dental post according to the present invention comprises the steps of: (i) overjacketing extrusion of at least one thermoplastic material over at least one filament or yarn, such that the thermoplastic material cross-sectionally enwraps the at least one filament or yarn; (ii) solidifying the extruded product of step (i); (iii) equipping the solidified extruded product of step (ii) with a surface texture, such that the thermoplastic wrapping is not modified in a way as to expose or dam-age the at least one filament or yarn.2010-04-08
20100084779GOLF BALL - A golf ball component, such as a golf ball cover layer, formed from a high or increased melt index thermoplastic polyurethane, polyurea or polyurethane/polyurea is disclosed. The cover layer may be relatively thin (i.e., 0.075 or less, preferably 0.050 inches or less, more preferably less than 0.040 inches, even more preferably less than 0.030 inches). In addition, an operation in which the outer cover is exposed to an isocyanate solution is described to improve certain physical properties of the resulting golf ball.2010-04-08
20100084780TISSUE HOLDING DEVICES AND METHODS FOR MAKING THE SAME - Various methods are provided for forming tissue holding devices having predetermined shapes suitable for use in surgical applications, and devices formed in accordance with such methods are also provided. These methods include press forming methods, and press forming methods in combination with profile punching. Tissue holding devices formed in accordance with such methods include various configurations for a core and a plurality of tissue holding elements extending outwardly from the core.2010-04-08
20100084781Concrete Manufacturing Processes and Methods - Concrete manufacturing processes are provided that can include providing a plurality of substantially dry concrete raw materials to a mixing chamber, providing water to the mixing chamber, and mixing the water and raw materials to form a concrete raw material mixture. Concrete manufacturing processes can also include providing water, a silica source, a calcium source and an aluminum source to within a mixing chamber, with the calcium source being provided to within the chamber prior to the aluminum source. Concrete manufacturing processes can also include providing a combustion waste, a silica source, water and an aluminum source to form a concrete raw material mixture, processing the raw material mixture to form a concrete product. Concrete materials are provided that can include a combustion waste material, with the combustion waste material having at least 10% (wt./wt.) CaO.2010-04-08
20100084782GASKET MATERIAL - A gasket material comprising polytetrafluoroethylene (PTFE) and a thermoplastic polymer have a melting point lower than the melting point of PTFE. Preferred thermoplastic polymers comprise fluorinated thermoplastic polymers, and most preferred fluorinated thermoplastic polymers comprise fluorinated ethylene propylene and perfluoroalkoxy copolymer. The PTFE component preferably comprises full density PTFE, and a filler material may optionally be added. The PTFE component is present in the gasket material in an amount from approximately 50% to less than 100%, based on the total weight of the gasket material, and the thermoplastic polymer is present in an amount from greater than 0% to approximately 20%, based on the total weigh to the gasket material.2010-04-08
20100084783NON-ROUND SPINNERET PLATE HOLE - The present invention concerns a spinneret plate for manufacturing a nonwoven fabric, having multiple non-round holes, which are similar to trilobal or multiarmed holes in particular, for polymer flow outlet to produce filaments, in which identical holes are positioned in rows offset relative to one another. At least a first row has a positional arrangement of the holes that differs from the positional arrangement of a second row of rows through rotation of the holes.2010-04-08
20100084784Fabrication of Biomimetic Scaffolds with Well-Defined Pore Geometry by Fused Deposition Modeling - A method for fabrication of a scaffold by fused deposition modeling is provided. The method includes forming a sacrificial mold with fused deposition modeling, the sacrificial mold comprising a dissolvable material. The method further includes infusing the sacrificial mold with a biodegradable composition and applying a solvent to the biodegradable composition infused sacrificial mold to dissolve the sacrificial mold and leave a scaffold formed from the biodegradable composition.2010-04-08
20100084785METHOD FOR MANUFACTURING MASTER AND METHOD FOR MANUFACTURING OPTICAL DISC - A method for manufacturing a master includes the steps of forming an inorganic resist layer on a master-forming substrate and forming, on a surface of the inorganic resist layer, a protective thin film containing a high-refractive-index material which has a refractive index n satisfying n≧NA of an exposure optical system and which is mixed in a light-transmitting material, performing near-field exposure with NA>1 on the protecting thin film using an exposure optical system, separating the protective thin film from an inorganic resist master subjected to the exposure, and forming a protrusion/depression pattern including exposed portions and unexposed portions by development of the inorganic resist master from which the protective thin film is separated.2010-04-08
20100084786Making twist-on wire connectors - A method of making a twist-on wire connector including a method of making a sealant containing twist-on wire connector by in situ formation of a shell around the coil wherein a sealant may be injected into a cavity in the coil prior to removing the shell from the mold to form a ready-to-use sealant containing twist on wire connector without further steps outside the mold.2010-04-08
20100084787Composite Load Bearing Structure - A composite load bearing member is provided comprising an elongated inner structural member and a thick polymeric composite outer member. An apparatus for producing the composite load bearing member is provided including devices for suspending the inner structural member within a mold cavity prior to and during injection of the polymeric composite outer member. A method of using the apparatus to produce the composite load bearing member is provided.2010-04-08
20100084788MOULD FOR COMPRESSION-FORMING A CAPSULE WITH HINGED LID - Method for forming an item through compression-moulding having an asymmetrical section with differentiated volumes and thicknesses, comprising the steps of introducing a dose of semi-liquid resin into the recess of a mould, inserting a plunger in said recess to create the interspace intended to be occupied by the material pushed by the plunger, removing said plunger and withdrawing the item that stays stuck to the plunger or to the recess, where the interspace intended for the forming of the item is created in two successive steps, the first comprising the insertion of a first plunger into the recess, and the second comprising the action of a second plunger that acts in a portion (accumulation chamber) of the interspace created by the insertion of the first plunger, completing the creation of the interspace in which the item is formed.2010-04-08
20100084789GOLF PRODUCTS PRODUCED BY A STOICHIOMETRICALLY IMBALANCED RIM SYSTEM - Disclosed herein are golf products, such as golf balls and/or components thereof, including the product of a fast-chemical-reaction mixture comprising a polyol and an isocyanate. The component is formed by reaction injection molding the reaction mixture. In the reaction mixture, the stoichiometry of the reactants is imbalanced.2010-04-08
20100084790METHOD FOR PRODUCING AN ADHESIVE FASTENING ELEMENT MADE OF PLASTIC AND DEVICE FOR CARRYING OUT SAID METHOD - The invention relates to a method for producing an adhesive fastening element made of plastic, comprising a support part (2010-04-08
20100084791METHODS OF MANUFACTURING FIBERS - A method of fabricating micro- and nano-scale fiber comprises: spreading micro- and nano-scale particles into a liquid or fluid-like material prior to forcing portions of the liquid or fluid-like material that surround the particles to depart from the original liquid or fluid-like environment by using a force field; stretching to elongate the portions of the liquid or fluid-like material until the free ends of the stretched portions stop motion to complete fiber or fiber-like structures in micro- and nano-scales.2010-04-08
20100084792POLYMER-ZEOLITE NANOCOMPOSITE MEMBRANES FOR PROTON-EXCHANGE-MEMBRANE FUEL CELLS - A suite of polymer/zeolite nanocomposite membranes. The polymer backbone is preferably a film forming fluorinated sulfonic acid containing copolymer, such as a Teflon type polymer, a perfluorinated polymer, or a perfluorinated polymer with sulfonic groups. The zeolites formed in accordance with the present invention and which are used in the membranes are plain, phenethyl functionalized and acid functionalized zeolite FAU(Y) and BEA nanocrystals. The zeolite nanocrystals are incorporated into polymer matrices for membrane separation applications like gas separations, and in polymer-exchange-membrane fuel cells. For the purpose of developing zeolite-polymer nanocomposite membranes, the zeolite nanocrystals are size-adjustable to match the polymer-network dimensions.2010-04-08
20100084793Electro-spinning apparatus and electro-spinning method - An electro-spinning apparatus includes a spinning jet, a stuff supply unit, a solvent supply unit, a collection unit, and a voltage driving unit. The spinning jet has a first channel and a second channel. The first channel has a first outlet, and the second channel has a second outlet. The stuff supply unit is connected to the first channel and supplies a liquid stuff to the first outlet. The solvent supply unit is connected to the second channel and supplies a gaseous solvent to the second outlet. The voltage driving unit applies a voltage difference between the spinning jet and the collection unit, so that the liquid stuff is spun and collected to the collection unit after being output from the first outlet and passing through the gaseous solvent released from the second outlet. Besides, an electro-spinning method is also provided.2010-04-08
20100084794METHOD OF IN-MOLD DECORATION - A method of in-mold decoration (IMD) comprises the steps of providing a thin-film substrate having a first surface and a second surface opposed to the first surface, printing a pattern on the first surface of the thin-film substrate, coating a hard-coating layer on the pattern and applying a UV light to harden the hard-coating layer, cutting the thin-film substrate, and performing an injection molding procedure to form a plastic layer on the second surface of the thin-film substrate.2010-04-08
20100084795METHOD FOR OPERATING A CONVERTER - In a method for operating a converter (2010-04-08
20100084796IRON CORE ANNEALING FURNACE - An iron core annealing furnace that is used in annealing of an amorphous iron core requiring strict control of annealing temperature. There is provided an iron core annealing furnace comprising a furnace body fitted at its superior area with a heat source and a fan, wherein the furnace body has a double layer structure consisting of a furnace interior defined by the inside division wall of the furnace body and an interspace defined by the division wall and the outside wall of the furnace body, and wherein the fan is disposed in the center of a superior area of the furnace body, and wherein the fan is adapted to introduce hot air from the furnace interior of the double layer structure, feed the hot air to the outside of the double layer structure, allow the hot air to enter the furnace interior from an inferior area of the furnace body and heat the iron core, and circulate the hot air.2010-04-08
20100084797VIBRATION DAMPING SYSTEM - A vibration damping system includes a laminated body (2010-04-08
20100084798CLAMPING AND OR SPREADING TOOL - A clamping and/or spreading tool comprises a drive for displacement of a push or pull rod to which a movable jaw is fixed with respect to a support carrying a stationary jaw in longitudinal direction of the push and pull rod, said drive comprising a torsion spring and being adapted to enter torque transmitting engagement with the push or pull rod for displacement of the same.2010-04-08
20100084799Single hand operated ratchet clamp - A single hand operated ratchet clamp comprises a finger ring lever and a typical ratchet clamp having a slide rail, a sliding arm, a fixed arm, and a lever element with pressure plate. The finger ring lever is pivoted to the free end of the lever element so that the ratchet clamp can be operated with one hand only. An alternate design is to make a finger hole on the free end of the lever element.2010-04-08
20100084800CLAMPING SYSTEMS FOR LARGE WORKPIECES - Arrangements for clamping a large workpiece such as an I-beam to a precision assembly table (or fitup table) or other workpiece support. The clamping arrangement includes a base; a first track supported by the base; a first slider for sliding along the track; a second slider for sliding along the first track, wherein the first slider and the second slider are moveable relative to one another along the first track; a first spacer supported by the first slider; and a second spacer supported by the second slider; wherein the first spacer and the second spacer are adapted to grip the workpiece therebetween.2010-04-08
20100084801PRECISION NOTCH MACHINING FIXTURE AND METHOD - A fixture includes an enlarged plate having slots in an upper surface, and support members are secured to the plate at the slots. The fixture is utilized to machine parts that are initially flame-cut from a large plate/sheet of hot-roll steel. A plurality of notches are flame-cut into the perimeter of the part. The support members engage the flame-cut slots to secure the part to the plate for machining a first side of the part. Precision notches are machined into the part, and precisely-shaped protrusions on the support members are closely received in the precision notches to precisely locate the part for further machining on a second side thereof.2010-04-08
20100084802MEDIA STACKING APPARATUS FOR MEDIA DISPENSER - The present invention relates to a media stacking apparatus for an automatic media dispenser. A media stacking apparatus according to the present invention comprises a media box provided with a seating space allowing media to be pulled and stacked therein, inlet rollers provided to face each other and to rotate in opposite directions relative to one another so that the media are pulled into the seating space, a damping unit colliding against the medium pulled into the seating space by the inlet rollers, and a pressing unit for pressing down a trailing end of the medium. The damping unit and the pressing unit are connected to both ends of a link by the pins to cooperate with each other. Thus, the media are stacked in the seating space, so that the following medium can be pulled therein without any interference. According to the present invention, there is an advantage in that a stacking reliability is enhanced when media are stacked.2010-04-08
20100084803Sheet transfer mechanism for printer - A sheet transfer mechanism for a printer 2010-04-08
20100084804SYSTEMS AND METHODS FOR CONTROLLING SUBSTRATE FLATNESS IN PRINTING DEVICES USING VACUUM AND/OR THE FLOW OF AIR - Systems and methods are provided for controlling substrate flatness for sensor measurements in printing device using vacuum and/or the flow or air. A source of low pressure, such as a vacuum, may be provided. A printed sheet of media may be transported between upper and lower transport baffles that are generally spaced apart to permit the sheet of media to pass. Located on one of transport baffles may be a sensor to measure a property of the printed sheet. The source of low pressure is connected to the one of the transport baffle so as to draw the surface of the sheet toward the sensor. In addition, air flow may be directed to the opposite surface of the sheet to urge it toward the sensor.2010-04-08
20100084805Image forming apparatus - An image forming apparatus includes a medium placing portion on which a medium is placed, a feed roller rotatably provided in contact with the medium placed on the medium placing portion so as to feed the medium, guide members disposed on both sides of the feed roller for guiding the medium being fed. The guide members are movable in a direction substantially perpendicular to a surface of the medium. A biasing unit is provided for biasing the guide members in a direction toward the medium.2010-04-08
20100084806Paper feed unit for printer - A paper feed unit for a printer to form an image on a print paper by an image former, the paper feed unit including: a paper feed tray that stacks print papers to be fed; a paper transfer route that transfers print papers; a register roller that is provided upstream of the image former in a paper transfer direction in the paper transfer route and holds a fed print paper to adjust a timing to transfer the fed print paper to the image former; a pick-up roller that transmits a print paper stacked in the paper feed tray to the register roller, the pick-up roller being smaller in width than a width of a print paper to be transmitted; and a regulator that comes into contact with a loose portion of a print paper loosened in a paper feed route in between the pick-up roller and the register roller.2010-04-08
20100084807SHEET CONTAINING DEVICE AND IMAGE FORMING DEVICE AND METHOD OF OPERATING SHEET CONTAINING DEVICE - A sheet containing device includes a supporting part that supports a first sheet and a second sheet, wherein the first sheet and the second sheet are different types of media, and the first sheet and the second sheet are stacked on one another; a feeding member that is located at a front end of the supporting part and that feeds the first sheet and the second sheet in correspondence with rotation of the feeding member; a sheet operating member that selectively prevents one of the first sheet and the second sheet from being fed by the feeding member.2010-04-08
20100084808SHEET POST-PROCESS APPARATUS - A sheet post-process apparatus includes a waiting tray and a processing tray. The waiting tray is provided in the middle of a conveying path and makes standby sheets in the case where a post-process is required. The processing tray has a function which causes the sheets made standby on the waiting sheet to be dropped by self-weight. With this function, the processing tray receives the sheets moved to be dropped and the sheets conveyed from the conveying path without intervening the waiting tray, before carrying out the post-process. Sheet bundles formed on the processing tray are stacked on a storage tray by a sheet conveying mechanism after they have been post-processed.2010-04-08
20100084809SYSTEMS AND METHODS FOR CONTROLLING SUBSTRATE FLATNESS IN PRINTING DEVICES USING THE FLOW OF AIR - Systems and methods are provided for controlling substrate flatness for sensor measurements in printing device. A flow of air may be provided from a blower to a plenum. A printed sheet of media may be transported between upper and lower transport baffles that are generally spaced apart to permit the sheet of media to pass. Located on one of transport baffles may be a sensor to measure a property of the printed sheet. Air from the plenum is provided to the back surface of the sheet to urge it toward the sensor.2010-04-08
20100084810SHEET INPUTTING MECHANISM WITH STOPPER AND AUTOMATIC SHEET FEEDER USING THE SAME - A sheet inputting mechanism includes a first body, a first roller, a second body, a second roller and a stopper. The first roller is mounted on the first body. The second body is rotatably connected to the first body. The second roller is mounted on the second body. The stopper rotatably mounted on the first body is directly driven by the second body. When the second body is rotated to a first state relatively to the first body, the stopper is rotated to a closing state relatively to the first body to prevent a sheet from being moved to a sheet input position. When the second body is rotated to a second state relatively to the first body, the stopper is rotated to an open state relatively to the first body to allow the sheet to be moved to the sheet input position and in contact with the first roller.2010-04-08
20100084811PRINTING MEDIA LOADING APPARATUS - A printing media loading apparatus includes a roller that has a narrow slit thereon and is used for loading a printing media. There are two nicks respectively on the two sides of the roller, and the narrow slit extends to the two nicks. The printing media loading apparatus further includes at least a detachable fixing unit, installed in a nick on one of the two sides of the roller for fixing the diameter of the roller.2010-04-08
20100084812DOUBLE SIDED SOCCER MAN - A game table including first and second substantially parallel player sides extending along a length direction, first and second substantially parallel goal sides extending along a width direction and a game playing surface defined within the player and goal sides. The game table includes at least one handle assembly connected to the game table. The handle assembly includes at least one turning rod carrying at least one player member, and a handle engaged with the turning rod whereby turning the handle operates to rotate the player to strike a playing piece. The player member includes a first foot portion, a second foot portion, and a body extending longitudinally therebetween.2010-04-08
20100084813CARD OUTPUT DEVICE FOR SHUFFLING MACHINE - A card output device for a shuffling machine is mounted adjacent to a shuffling wheel of a shuffling device and has a housing and a stacking assembly, a pushing assembly and three sensors being mounted in the housing. When the sensors sense that there are cards on the stacking assembly, the stacking assembly and the pushing assembly begin to push the cards toward an outlet of the housing and the shuffling device stops pushing the cards out of the shuffling wheel. When there are fewer cards being stacked in the outlet of the housing, the shuffling device begins to push the cards out of the shuffling wheel and into the card output device. Therefore, the cards are not scattered around the outlet of the card output device and keep a desk for playing a card game neat and tidy.2010-04-08
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