14th week of 2010 patent applcation highlights part 13 |
Patent application number | Title | Published |
20100084614 | PROCESS OF PREPARING REGIOREGULAR POLYMERS - The invention relates to a process of preparing regioregular polymers, in particular head-to-tail (HT) poly-(3-substituted) thiophenes or selenophenes with high regioregularity and defined molecular weight, to novel polymers prepared by this process, to the use of the novel polymers as semiconductors or charge transport materials in optical, electrooptical or electronic devices including field effect transistors (FETs), electroluminescent, photovoltaic and sensor devices, and to FETs and other semiconducting components or materials comprising the novel polymers. | 2010-04-08 |
20100084615 | Synthesis of Crystalline Nanometric LiFeMPO4 - The present invention relates to lithium secondary batteries and more specifically to positive electrode materials operating at potentials greater than 2.8 V vs. Li | 2010-04-08 |
20100084616 | CONDUCTING COMPOSITE MATERIAL CONTAINING A THERMOPLASTIC POLYMER AND CARBON NANOTUBES - The invention relates to methods for controlling and improving the conductivity of thermoplastic polymer composites containing CNTs or even for making these materials conductive when they are initially insulating. | 2010-04-08 |
20100084617 | STATIC DISSIPATIVE POLYACETAL COMPOSITIONS - Polyacetal compositions comprising polyacetal, electroconductive carbon black, and substituted urea provide a combination of good static dissipation properties, good thermal stability during processing, and good stability to contact with fuel. | 2010-04-08 |
20100084618 | Electrically Conductive, Optically Transparent Polymer/Carbon Nanotube Composites - The present invention is directed to the effective dispersion of carbon nanotubes (CNTs) into polymer matrices. The nanocomposites are prepared using polymer matrices and exhibit a unique combination of properties, most notably, high retention of optical transparency in the visible range (i.e., 400-800 nm), electrical conductivity, and high thermal stability. By appropriate selection of the matrix resin, additional properties such as vacuum ultraviolet radiation resistance, atomic oxygen resistance, high glass transition (T | 2010-04-08 |
20100084619 | SEMICONDUCTOR CERAMIC MATERIAL - A semiconductor ceramic material which contains no Pb and has a high Curie point, low resistivity, and PTC characteristicsis represented by the formula ABO | 2010-04-08 |
20100084620 | LAYING NETWORK CABLES IN SEWERS - One form of sewer comprises a pipe having a bottom section | 2010-04-08 |
20100084621 | Wire Guiding Device - A wire guiding device for use with an electrical fitting such as an “LB” fitting is provided. The wire pulling device comprises a frame and two rollers mounted on axles. A first roller allows a wire to be pulled around the angle of the fitting and may be of sufficient diameter to prevent damage to the wire, while a second roller may prevent the wire from contacting the damaging edges of the fitting. The rollers are mounted within a frame which is adaptable to the access port of an LB fitting. Holes may be located in the frame such that fasteners engage the pre-existing threaded holes located in a standard LB fitting. | 2010-04-08 |
20100084622 | LINE RETRIEVAL SYSTEM AND METHOD - A line retrieval system comprises a retrieval device having a radially magnetized magnet adapted to be magnetically coupled to an object disposed on an opposite side of a structure for drawing the object in a desired direction relative to the structure. | 2010-04-08 |
20100084623 | PERIMETER SECURITY BARRIERS - A perimeter security barrier ( | 2010-04-08 |
20100084624 | Dielectric mesh isolated phase change structure for phase change memory - A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure. | 2010-04-08 |
20100084625 | Memory Device - An electrical device includes a first electrode and a second electrode. A first active material is between the first electrode and second electrode. A second active material is between the first electrode and second electrode. A nonlinear electrode material is disposed between the first electrode and the second electrode. The nonlinear electrode material is electrically in series with the first electrode, the first active material, the second active material, and the second electrode. The first electrode and the first active material undergo no chemical or electrochemical reaction when current passes between the first electrode and the second electrode. | 2010-04-08 |
20100084626 | ELECTRONIC DEVICE COMPRISING A CONVERTIBLE STRUCTURE, AND A METHOD OF MANUFACTURING AN ELECTRONIC DEVICE - An electronic device ( | 2010-04-08 |
20100084627 | Negative differential resistance polymer devices and circuits incorporating same - A device includes: a first electrical contact; a second electrical contact; a semiconducting or semimetallic organic layer disposed at least partially between the first and second electrical contacts; and a tunneling barrier layer disposed at least partially between the semiconducting or semimetallic organic layer and the first electrical contact. The tunneling barrier layer has a thickness effective to enable flow of an electrical current through the tunneling barrier layer responsive to an operative electrical bias applied across the first and second electrical contacts, the electrical current exhibiting negative differential resistance for at least some applied electrical bias values. Circuits are also disclosed that utilize one or more negative differential resistance polymer diodes to implement logic, memory, or mixed signal applications. | 2010-04-08 |
20100084628 | BRANCHED NANOWIRE AND METHOD FOR FABRICATION OF THE SAME - Disclosed herein are a branched nanowire having parasitic nanowires grown at a surface of the branched nanowire, and a method for fabricating the same. The branched nanowire may be fabricated in a fractal form and seeds of the parasitic nanowires may be formed by thermal energy irradiation and/or a wet-etching process. The branched nanowire may effectively be used in a wide variety of applications such as, for example, sensors, photodetectors, light emitting elements, light receiving elements, and the like. | 2010-04-08 |
20100084629 | QUANTUM DOT-METAL OXIDE COMPLEX, METHOD OF PREPARING THE SAME, AND LIGHT-EMITTING DEVICE COMPRISING THE SAME - Provided is a quantum dot-metal oxide complex including a quantum dot and a metal oxide forming a 3-dimensional network with the quantum dot. In the quantum dot-metal oxide complex, the quantum dot is optically stable without a change in emission wavelength band and its light-emitting performance is enhanced. | 2010-04-08 |
20100084630 | Apparatus and Method of Detecting Electromagnetic Radiation - A high speed and miniature detection system, especially for electromagnetic radiation in the GHz and THz range comprises a semiconductor structure having a 2D charge carrier layer or a quasi 2D charge carrier layer with incorporated single or multiple defects, at least first and second contacts to the charge carrier layer, and a device for measuring photovoltage between the first and second contacts. System operation in various embodiments relies on resonant excitation of plasma waves in the semiconductor structure. | 2010-04-08 |
20100084631 | Phase-controlled field effect transistor device and method for manufacturing thereof - A phase controllable field effect transistor device is described. The device provides first and second scattering sites disposed at either side of a conducting channel region, the conducting region being gated such that on application of an appropriate signal to the gate, energies of the electrons in the channel region defined between the scattering centres may be modulated. | 2010-04-08 |
20100084632 | NANOSTRUCTURE INSULATED JUNCTION FIELD EFFECT TRANSISTOR - A novel nanostructure device operating in Junction Field Effect Transistor (JFET) mode is provided that avoids the majority of the carriers that interact with the interface (e.g. surface roughness, high-k scattering). | 2010-04-08 |
20100084633 | SPIN TRANSISTOR USING DOUBLE CARRIER SUPPLY LAYER STRUCTURE - A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer. | 2010-04-08 |
20100084634 | Nano-crystal diamond film, manufacturing method thereof, and device using nano-crystal diamond film - A nano-crystal diamond film synthesized on a substrate and containing, as a major component, nano-crystal diamond having a grain diameter from 1 nm to less than 1000 nm. This nano-crystal diamond film can be formed on a substrate by means of a plasma CVD method using a raw material gas containing a hydrocarbon and hydrogen, allowing the formation of the nano-crystal diamond film to take place outside the plasma region. This nano-crystal diamond film is applicable to the manufacture of an electrochemical device, an electrochemical electrode, a DNA chip, an organic electroluminescent device, an organic photoelectric receiving device, an organic thin film transistor, a cold electron-emission device, a fuel cell and a catalyst. | 2010-04-08 |
20100084635 | Recording level gauge type organic light emitting diode - Diode for which one of the conducting layers presents a suitable surface resistance so that when a power supply voltage is applied between a connection element and this conducting layer and the other conducting layer, a potential distribution is generated at the surface of this resisting conducting layer which is able to cause light to be emitted by a portion of the surface of the organic light emitting layer which is proportional to this power supply voltage. This diode is advantageously used to visualise the signal value. | 2010-04-08 |
20100084636 | COMPOSITION FOR PHOTOSENSITIVE ORGANIC DIELECTRIC MATERIAL AND APPLICATION THEREOF - A composition for photosensitive dielectric material is provided. The composition includes 4 to 10 percent by weight of a polymer material, 1.5 to 10 percent by weight of a crosslinking agent, 0.32 to 2 percent by weight of a photoacid generator (PAG) and 78 to 94.18 percent by weight of solvent, based on a total weight of the composition. | 2010-04-08 |
20100084637 | ORGANIC TRANSISTOR AND METHOD FOR FABRICATING THE SAME - The present invention provides an organic transistor that includes an organic semiconductor layer containing a material having conductive particles and an organic semiconductor polymer chemically bonded to each other and a method of producing the same. | 2010-04-08 |
20100084638 | Thin Film Transistor - A method of making a top-gate organic thin film transistor, comprising forming source and drain contacts on a substrate; oxidizing portions of the source and drain contacts; depositing an organic semiconductor layer to form a bridge between the oxidized portions of the source and drain contacts; depositing a gate insulating layer over the organic semiconductor layer; and forming a gate electrode over the gate insulating layer. | 2010-04-08 |
20100084639 | Electric Organic Component and Method for the Production Thereof - An electric organic component and a method for the production thereof is disclosed. The component includes a substrate, a first electrode, a first electrically semiconductive layer on the first electrode, an organic functional layer on the first electrically semiconductive layer and a second electrode on the organic functional layer. The first or the second electrode may be arranged on the substrate. The electrically semiconductive layer is doped with a dopant which comprises rhenium compounds. | 2010-04-08 |
20100084640 | POLYMER HAVING UNIT OBTAINED BY CONDENSATION OF DIFLUOROCYCLOPENTANEDIONE RING AND AROMATIC RING, ORGANIC THIN FILM USING THE SAME, AND ORGANIC THIN FILM DEVICE - A polymer having a repeating unit represented by the following general formula (I) and a ferrocene-based reduction potential of −1.5 to −0.5 V as measured by a cyclic voltammetry method | 2010-04-08 |
20100084641 | METHOD FOR MANUFACTURING AN ORGANIC LIGHT EMITTING DEVICE AS WELL AS SUCH A DEVICE - Electronic device comprising at least:
| 2010-04-08 |
20100084642 | ORGANIC EL DEVICE - An organic EL device includes an array substrate including an insulating substrate and an organic EL element which is disposed above the insulating substrate, a sealing substrate which is disposed on that side of the array substrate, which faces the organic EL element, and is attached to the array substrate, a light sensor which is provided in the array substrate and includes a light-sensing part which receives incident light via the sealing substrate, and a light-shield layer which is disposed between the light sensor and the sealing substrate, and includes an opening portion which is formed right above the light-sensing part of the light sensor. | 2010-04-08 |
20100084643 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND ELECTRONIC APPARATUS - A thin film transistor includes an insulating layer formed from an organic material, an oxide material, or a silicon based material, a source electrode and a drain electrode disposed on the insulating layer by using an electrically conductive oxide material, a self-organized film covering exposed surfaces of the insulating layer, the source electrode, and the drain electrode, and a semiconductor thin film disposed, on the insulating layer provided with the self-organized film, over from the source electrode to the drain electrode. | 2010-04-08 |
20100084644 | DISPLAY SUBSTRATE METHOD OF MANUFACTURING THE SAME - A display substrate includes a base substrate, a barrier pattern, a source electrode, a drain electrode, a semiconductor layer, an insulating layer, and a gate electrode. The barrier pattern protrudes from the base substrate. The source and gate electrodes are formed adjacent to opposite sides of the barrier pattern on the base substrate. The semiconductor layer is provided on the barrier pattern to connect the source electrode with the drain electrode, and the insulating layer covers the semiconductor layer, the source electrode, and the drain electrode. The gate electrode is provided on the insulating layer, and is overlapped with the semiconductor layer. | 2010-04-08 |
20100084645 | COMPOSITE MATERIAL, AND LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE USING THE COMPOSITE MATERIAL - An object is to provide a light emitting element with low drive voltage which contains an organic compound and an inorganic compound. One feature of a light emitting element of the present invention is to include a layer containing a light emitting material between a pair of electrodes, in which the layer containing a light emitting material has a layer containing a carbazole derivative represented by General Formula (1) and an inorganic compound which exhibits an electron accepting property to the carbazole derivative represented by General Formula (1). With such a structure, the inorganic compound accepts electrons from the carbazole derivative, carriers are generated internally, and a drive voltage of the light emitting element can be reduced. | 2010-04-08 |
20100084646 | LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE - A light emitting element, including a light emitting section and a connecting section, the light emitting section and the connecting section being provided over a substrate, along the in-plane direction of the substrate, an insulating section being formed between the light emitting section and the connecting section, the light emitting element, including: the light emitting section including: a bottom electrode, a phosphor layer formed over the bottom electrode; a first charge transporting layer formed over the phosphor layer; and a first top electrode formed over the first charge transporting layer, the connecting section including: an auxiliary electrode; a second charge transporting layer formed over the auxiliary electrode and connected electrically to the first charge transporting layer of the light emitting section; and a second top electrode formed over the second charge transporting layer and connected electrically to the first top electrode of the light emitting section; the insulating section electrically insulates, with the auxiliary electrode of the connecting section, the bottom electrode and the phosphor layer of the light emitting section, and further, a HOMO (eV) and a LUMO (eV) in the first charge transporting layer are identical to a HOMO (eV) and a LUMO (eV) in the second charge transporting layer, yet further, a work function Ip (eV) of the first top electrode is identical to a work function Ip (eV) of the second top electrode, and the HOMO (eV), the LUMO (eV) and the work function Ip (eV) satisfy the following expression. | 2010-04-08 |
20100084647 | ELECTROLUMINESCENT DEVICES INCLUDING ORGANIC EIL LAYER - An OLED device comprises a cathode, an anode, and has therebetween a light emitting layer (LEL) comprising a phosphorescent emitting compound disposed in a host comprising a mixture of at least one electron transporting co-host which is a benzophenone derivative with a spiro substituent and at least one hole transporting co-host which is a triphenylamine which contains one trivalent nitrogen atom that is bonded only to carbon atoms, at least one of which is a member of an aromatic ring, wherein there is present an electron transporting layer contiguous to the LEL (HBL?) on the cathode side comprising an anthracene or a fluoranthene and wherein there is present an election injecting layer comprising a phenanthroline or a lithium quinolate contiguous to the cathode. | 2010-04-08 |
20100084648 | LIGHT-EMITTING APPARATUS AND PRODUCTION METHOD THEREOF - Provided is a method of producing a light-emitting apparatus having a field effect transistor for driving an organic EL device, the field effect transistor including an oxide semiconductor containing at least one element selected from In and Zn, the method including the steps of: forming a field effect transistor on a substrate; forming an insulating layer; forming a lower electrode on the insulating layer; forming an organic layer for constituting an organic EL device on the lower electrode; forming an upper electrode on the organic layer; and after the step of forming the semiconductor layer of the field effect transistor and before the step of forming the organic layer, performing heat treatment such that an amount of a component that is desorbable as H | 2010-04-08 |
20100084649 | OXIDE THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - An oxide thin film transistor (TFT) and its fabrication method are disclosed. In a TFT of a bottom gate structure using amorphous zinc oxide (ZnO)-based semiconductor as an active layer, source and drain electrodes are formed, on which the active layer made of oxide semiconductor is formed to thus prevent degeneration of the oxide semiconductor in etching the source and drain electrodes. The oxide TFT includes: a gate electrode form on a substrate; a gate insulating layer formed on the gate electrode; source and drain electrodes formed on the gate insulating layer and having a multi-layer structure of two or more layers; and an active layer formed on the source and drain electrodes and formed of amorphous zinc oxide-based semiconductor, wherein a metal layer such as indium-tin-oxide, molybdenum, and the like, having good ohmic-contact characteristics with titanium and a titanium alloy having good bonding force with oxygen or the oxide-based semiconductor is formed at an uppermost portion of the source and drain electrodes. In a method for fabricating an oxide TFT, a silicon nitride film is deposited with a sputter equipment without the necessity of H | 2010-04-08 |
20100084650 | DISPLAY DEVICE - A pixel portion and a driver circuit driving the pixel portion are formed over the same substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor layer is used and a channel protective layer is provided over the oxide semiconductor layer serving as a channel formation region which is overlapped with the gate electrode. The driver circuit as well as the pixel portion is provided over the same substrate to reduce manufacturing costs. | 2010-04-08 |
20100084651 | DISPLAY DEVICE - With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an IC chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit for driving the pixel portion are formed over one substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor is used. The driver circuit as well as the pixel portion is provided over the same substrate, whereby manufacturing costs are reduced. | 2010-04-08 |
20100084652 | DISPLAY DEVICE - A display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area is necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions are over the first oxide semiconductor layer and overlap with the gate electrode. The gate electrode of the non-linear element is connected to a scan line or a signal line, the first wiring layer or the second wiring layer of the non-linear element is directly connected to the gate electrode layer so as to apply potential of the gate electrode. | 2010-04-08 |
20100084653 | DISPLAY DEVICE - The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode. | 2010-04-08 |
20100084654 | DISPLAY DEVICE - In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode. | 2010-04-08 |
20100084655 | FIELD EFFECT TRANSISTOR AND PROCESS FOR PRODUCTION THEREOF - A field effect transistor has a gate electrode, gate-insulating layer, a channel and a source and drain electrodes connected electrically to the channel, the channel comprising an oxide semiconductor, the source electrode or the drain electrode comprising an oxynitride. | 2010-04-08 |
20100084656 | PARTICLE EMISSION ANALYSIS FOR SEMICONDUCTOR FABRICATION STEPS - A structure and a method for operating the same. The method includes providing a detecting structure which includes N detectors. N is a positive integer. A fabrication step is simultaneously performed on the detecting structure and M product structures in a fabrication tool resulting in a particle-emitting layer on the detecting structure. The detecting structure is different than the M product structures. The M product structures are identical. M is a positive integer. An impact of emitting particles from the particle-emitting layer on the detecting structure is analyzed after said performing is performed. | 2010-04-08 |
20100084657 | THIN FILM TRANSISTOR ARRAY SUBSTRATE - A thin film transistor array substrate includes a substrate having a display area and a peripheral area, a plurality of pixel units, a plurality of signal lines, and a testing circuit. The signal lines are electrically connected with the pixel units disposed in the display area. The testing circuit disposed in the peripheral area is electrically connected with terminals, located in the peripheral area, of a portion of the signal lines. The testing circuit includes a common gate line having a plurality of notches formed on an edge thereof, a plurality of channel layers, source electrodes, and drain electrodes. The source electrodes and the drain electrodes are disposed correspondingly on the channel layers disposed above the common gate line. Each drain electrode extends from the top of the common gate line to the top of one notch and extends to the terminal of one signal line for electrically connecting thereto. | 2010-04-08 |
20100084658 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate having a low-resistance metallic layer and a method of manufacturing the display substrate. The gate conductors are extended in a first direction. The source conductors are extended in a second direction crossing the first direction including a lower layer of molybdenum or a molybdenum alloy, and an upper layer of aluminum or an aluminum alloy. The pixel areas are defined by the gate conductors and the source conductors. A switching element is formed in each of the pixel areas and includes a gate electrode extended from the gate conductor and a source electrode extended from the source conductor. The pixel electrode includes a transparent conductive material, and is electrically connected to a drain electrode of the switching element. | 2010-04-08 |
20100084659 | GATE DRIVER-ON-ARRAY STRUCTURE AND DISPLAY PANEL - A gate driver-on-array structure for using in a display panel including first conductive patterns, semiconductor patterns, second conductive patterns, third conductive patterns, first electrode line, and first connectors is provided. The first conductive patterns, the second conductive patterns, the semiconductor patterns and the third conductive patterns together form a plurality of thin film transistors. The first electrode line is located at a side of the first conductive patterns and spaced from the first conductive patterns by a first distance. The first connectors are connected to the corresponding first conductive patterns and the first electrode line. | 2010-04-08 |
20100084660 | Semiconductor Structures - A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed thereon, an insulation layer disposed on the substrate and overlying the gate, a patterned semiconductor layer disposed on the insulation layer, a source and a drain disposed on the patterned semiconductor layer, a protective layer overlying the insulation layer, the source and the boundary of the drain to expose a portion of the drain, and a pixel electrode disposed on the substrate, overlying the protective layer overlying the boundary of the drain, electrically connected to the exposed drain. | 2010-04-08 |
20100084661 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME - The present invention relates to a display substrate in which sound devices serving as speakers or a microphones are built, and the display substrate includes a substrate including a sound processing area and a display area, a plurality of sound devices arranged in the sound processing area, and a plurality of pixels arranged in the display area. The sound devices may be formed on the substrate together with the pixels using a same manufacturing process as that used to form the pixels. | 2010-04-08 |
20100084662 | SEMICONDUCTOR STRUCTURE PROCESSING USING MULTIPLE LASER BEAM SPOTS OVERLAPPING LENGTHWISE ON A STRUCTURE - Methods and systems use laser pulses to process a selected structure on or within a semiconductor substrate. The structure has a surface, a width, and a length. The laser pulses propagate along axes that move along a scan beam path relative to the substrate as the laser pulses process the selected structure. The method simultaneously generates on the selected structure first and second laser beam pulses that propagate along respective first and second laser beam axes intersecting the selected structure at distinct first and second locations. The first and second laser beam pulses impinge on the surface of the selected structure respective first and second beam spots. Each beam spot encompasses at least the width of the selected link. The first and second beam spots are spatially offset from one another along the length of the selected structure to define an overlapping region covered by both the first and the second beam spots and a total region covered by one or both of the first and second beam spots. The total region is larger than the first beam spot and also larger than the second beam spot. The method sets respective first and second energy values of the first and second laser beam pulses to cause complete depthwise processing of the selected structure across the width of the structure in at least a portion of the total region. | 2010-04-08 |
20100084663 | Silicon Carbide Zener Diode - A silicon carbide Zener diode is a bipolar semiconductor device that has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, formed thereon, a silicon carbide conductive layer of a first conductivity type, and a silicon carbide conductive layer of a second conductivity type formed on the silicon carbide conductive layer of a first conductivity type, wherein a depletion layer that is formed under reverse bias at a junction between the silicon carbide conductive layer of a first conductivity type and the silicon carbide conductive layer of a second conductivity type does not reach a mesa corner formed in the silicon carbide conductive layer of a first conductivity type. | 2010-04-08 |
20100084664 | ZINC SULFIDE SUBSTRATES FOR GROUP III-NITRIDE EPITAXY AND GROUP III-NITRIDE DEVICES - A semiconductor structure includes a substrate which may be formed from a ZnS single crystal of wurtzite (2H) structure with a predetermined crystal orientation, and which has a first surface and a second surface. The structure includes a layer of a group III-nitride crystalline material deposited as an epitaxial layer on the first surface of the substrate. In one embodiment, the group III-nitride deposit is epitaxially grown using a MOCVD (or MOVPE) technique or a HVPE technique or a combination thereof. There may be a mask and/or a buffer layer on the first surface and/or a protective layer on the second surface. | 2010-04-08 |
20100084665 | SOLID STATE LIGHT SHEET AND ENCAPSULATED BARE DIE SEMICONDUCTOR CIRCUITS - An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface. | 2010-04-08 |
20100084666 | ILLUMINATING MEANS - An illuminating means, including a radiation source for emitting electromagnetic radiation in the optical range, a support base, and an electrode arrangement with a first and at least a second electrode. The radiation source is disposed on the support base and connected by connecting wires to the electrode arrangement so as to be electrically conductive, and the radiation source is provided in the form of a first and at least a second semiconductor component. The first electrode is connected to the first semiconductor component via a first contact point, and the second electrode is connected to the second semiconductor component via a second contact point, so as to be electrically conductive. The distance of the first contact point from a center point or a line of symmetry of the support base is different from the distance of the second contact point from the center point or line of symmetry. | 2010-04-08 |
20100084667 | Semiconductor Light Source Element for Beam Forming - A semiconductor light source element includes a substrate to which at least one semiconductor light source is mounted. An optical body is mounted to the substrate with its light receiving surface located adjacent the light emitting surface of the at least one semiconductor light source. The optical body has a shape and light output surface profile which are selected to produce a desired beam pattern with the light emitted by the at least one semiconductor light source. When two or more semiconductor light sources are employed in the semiconductor light source element, the light sources can be positioned at different locations about the light receiving surface to emit light from the front edge of the optical body in correspondingly diverse patterns. | 2010-04-08 |
20100084668 | SEMICONDUCTOR COLOR-TUNABLE BROADBAND LIGHT SOURCES AND FULL-COLOR MICRODISPLAYS - Methods and systems are provided that may be used to utilize and manufacture a light sources apparatus. A first light emitting diode emits light having a first wavelength, and a second light emitting diode for emitting light having a second wavelength. Each of the first and second light emitting diodes may comprise angled facets to reflect incident light in a direct toward a top end of the first light emitting diode. The second light emitting diode comprising angled facets may reflect incident light in a direction toward a top end of the second light emitting diode. A first distributed Bragg reflector is disposed between the top end of the first light emitting diode and a bottom end of the second light emitting diode to allow light from the first light emitting diode to pass through and to reflect light from the second light emitting diode. | 2010-04-08 |
20100084669 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A light emitting device and a method for manufacturing the same are provided. The light emitting device includes: a first substrate having electrical conductivity; a foundation layer; a bonded metal layer configured to bond one major surface of the foundation layer to the first substrate; a mask layer provided on the other major surface of the foundation layer, having a window, and made of an insulator; and a multilayer body selectively provided on the foundation layer exposed to the window, and including a light emitting layer. | 2010-04-08 |
20100084670 | LED CHIP WITH EXPANDED EFFECTIVE REFLECTION ANGLES - An LED chip with enhanced effective reflection angles is revealed, primarily comprising an epitaxial substrate, a first reflection mirror on the epitaxial substrate, a second reflection mirror, a light-emitting mechanism, and a first electrode. The first reflection mirror consists of a plurality of first DBRs with a first paired thickness. The second reflection mirror is formed on the first reflection mirror and consists of a plurality of second DBRs with a second paired thickness. Accordingly, two different ranges of effective reflection angles is provided to increase the effective reflection angles to overcome issues of lower production yield during the conventional thermally-bonding processes with reflection metal plates. | 2010-04-08 |
20100084671 | BRIGHTNESS ENHANCEMENT METHOD AND APPARATUS OF LIGHT EMITTING DIODES - A light source with enhanced brightness includes an angle-selective optical filter and a light emitting diode (LED) having a high reflective layer. The angle-selective filter is located on the top surface of emitting diode to pass lights at specified angles. According to one embodiment, the angle-selective filter comprises index-alternating layers. With a reflective polarizer, the light source can produce polarized light with enhanced brightness. | 2010-04-08 |
20100084672 | ORGANIC ELECTROLUMINESCENT ELEMENT AND METHOD FOR PRODUCING THE SAME - An organic EL device includes an organic luminescent layer between an anode and a cathode. The organic luminescent layer comprises at least two host materials and a dopant which is a luminescent compound. The at least two host materials are identical to or substantially identical to each other in the energy value of LUMO, but on the other hand, are different from each other in the energy value of HOMO. Alternatively, the at least two host materials are identical to or substantially identical to each other in the energy value of HOMO, but on the other hand, are different from each other in the energy value of LUMO. According to the above constitution, the balance of mobility between the electrons and holes can be regulated to solve the above problem of the prior art. | 2010-04-08 |
20100084673 | Light-emitting semiconductor packaging structure without wire bonding - A light-emitting semiconductor packaging structure without wire bonding, including a heat conduction board, a light-emitting semiconductor chip bonded on the heat conduction board and a lead frame positioned around the chip. The lead frame has at least one connection section extending to upper side of the chip to connect with a conductive protruding block adhered to an active surface of the chip. The conductive protruding block is bonded with the chip and the connection section of the lead frame by larger area so that the heat conduction area is increased to enhance heat dissipation effect for the chip. It is unnecessary to save upward and outward extension room for wire bonding so that the volume and thickness of the packaging structure are minified. The chip is received in a cavity of the lead frame to form a lightweight and miniaturized heat dissipation packaging structure. | 2010-04-08 |
20100084674 | OLED with Color Conversion - An OLED is thus specified which includes a layer construction comprising at least an anode, a cathode and a functional layer arranged in between, the layer construction being arranged on a substrate. At least one electrode, selected from the anode and cathode, is transmissive to the light emitted by the functional layer and is arranged on the light-emitting side, emission side, of the layer construction. The at least one color conversion layer has quantum dots and is arranged on the emission side above or below the layer construction. | 2010-04-08 |
20100084675 | SEMICONDUCTOR LIGHT EMITTING APPARATUS - A semiconductor light emitting apparatus for emitting a desired colored light by coating the top surface thereof with a wavelength conversion member prevents the color unevenness from occurring due to the unevenness of the coating thickness of the wavelength conversion member. The semiconductor light emitting apparatus can include a semiconductor layer having a light emitting layer with a light emitting surface having at least one corner area, a supporting substrate configured to support the semiconductor layer, and a wavelength conversion material layer formed on top of the semiconductor layer, the wavelength conversion layer having a thickness thinner from a center portion of the semiconductor layer to an outer peripheral portion. The at least one corner area can include a non-emitting portion where light cannot be projected. The non-emitting portion can be a light shielding portion, a non-light emission portion or a current confined portion. | 2010-04-08 |
20100084676 | ORGANIC EL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An organic EL display device forms an organic EL layer on a pixel portion by a transfer method without using a sophisticated optical system. A patterned light reflection layer is formed on a donor substrate. A light absorption layer is formed on the light reflection layer. An organic EL material layer is formed on the light absorption layer. An element substrate on which banks, lower electrodes and the like are formed is arranged to face a donor substrate in an opposed manner. When light is radiated to the donor substrate from a flash lamp or the like, only portions of the optical absorption layer where the light reflection layers are not formed are heated, and such portions of the organic EL material layer are evaporated and applied to a lower electrode formed on the element substrate. Due to such steps, the organic EL layer can be formed by a transfer method without using a sophisticated optical system. | 2010-04-08 |
20100084677 | Oled or group of adjacent oleds with a light-extraction layer efficient over a large range of wavelengths - An organic light emitting diode comprises, between a bottom electrode and a top electrode, an organic light-emitting layer and a light-extraction enhancement layer made of a dielectric material. According to the invention, if n | 2010-04-08 |
20100084678 | Luminescent Diode Chip - A luminescent diode chip includes a semiconductor body, which produces radiation of a first wavelength. A luminescence conversion element produces radiation of a second wavelength from the radiation of the first wavelength. An angular filter element reflects radiation that impinges on the angular filter element at a specific angle in relation to a main direction of emission back in the direction of the semiconductor body. | 2010-04-08 |
20100084679 | LIGHT-EMITTING DEVICE - A light-emitting device having a substrate, a light-emitting stack, and a transparent connective layer is provided. The light-emitting stack is disposed above the substrate and comprises a first diffusing surface. The transparent connective layer is disposed between the substrate and the first diffusing surface of the light-emitting stack; an index of refraction of the light-emitting stack is different from that of the transparent connective layer. | 2010-04-08 |
20100084680 | SPONTANEOUS/STIMULATED LIGHT EMITTING .mu.-CAVITY DEVICE - A light emitting device with a p-cavity including a first spacer of single crystal dielectric material and an active area including single crystal erbium dielectric material positioned on the first spacer. The erbium dielectric material and the single crystal dielectric material of the first spacer are substantially crystal lattice matched at their juncture. A second spacer of single crystal dielectric material is positioned on the active area. The erbium dielectric material and the single crystal dielectric material of the second spacer are substantially crystal lattice matched at the second surface. The high-κ erbium dielectric provides a high gain μ-cavity that emits increased amounts of light in either spontaneous or stimulated modes of operation. | 2010-04-08 |
20100084681 | PRODUCTION PROCESS FOR SURFACE-MOUNTING CERAMIC LED PACKAGE, SURFACE-MOUNTING CERAMIC LED PACKAGE PRODUCED BY SAID PRODUCTION PROCESS, AND MOLD FOR PRODUCING SAID PACKAGE - The present invention is related to a surface-mounting ceramic LED package and a method for its production comprising: layering a ceramic green sheet which has a hole and a second ceramic green sheet, inserting a mold with a groove to form a partition in the bottom of the ceramic green sheet substrate, and firing the ceramic green sheet substrate. | 2010-04-08 |
20100084682 | OHMIC ELECTRODE AND METHOD THEREOF, SEMICONDUCTOR LIGHT EMITTING ELEMENT HAVING THIS - There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective layer made of Ag metal, formed on the contact layer and having some particles in-diffused to the semiconductor layer, and a protective layer formed on the reflective layer to restrain out-diffusion of the reflective layer; a method of forming the ohmic electrode; and a semiconductor light emitting element having the ohmic electrode. The present invention has strong adhesive strength and low contact resistance since the reflective layer and the light emitting layer directly form an ohmic contact due to the interface reaction during heat treatment, and the present invention has high light reflectance and excellent thermal stability since the contact layer and the protective layer restrain out-diffusion of the reflective layer during heat treatment. | 2010-04-08 |
20100084683 | LIGHT EMITTING DIODE PACKAGE AND FABRICATING METHOD THEREOF - A light emitting diode (LED) package is provided. The LED package includes a carrier, a package housing, a strength enhancement structure, an ESD protector and an LED chip. The carrier has a first surface and a second surface. The carrier includes a first electrode and a second electrode, wherein a gap is between the first electrode and the second electrode. The package housing is disposed on the carrier and has a first aperture and a second aperture. The first surface is exposed by the first aperture while the second surface is exposed by the second aperture. The strength enhancement structure is disposed at the gap. The ESD protector is disposed on the carrier and located within the second aperture. The LED chip is disposed on the carrier and located within the first aperture, wherein the ESD protector and the LED chip is electrically connected to the carrier. | 2010-04-08 |
20100084684 | Insulated gate bipolar transistor - Provided is an insulated gate bipolar transistor (IGBT) which occupies a small area and in which a thermal breakdown is suppressed. The IGBT includes: an n-type semiconductor layer ( | 2010-04-08 |
20100084685 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an SiGe film formed on part of a semiconductor substrate and including a channel region and at least part of source/drain extension regions between which the channel region is positioned, source/drain contact regions formed in a surface area of the semiconductor substrate and brought into contact with the pair of source/drain extension regions, a gate structure having a gate insulation film formed on the SiGe film and a gate electrode formed on the gate insulation film, first sidewall films formed on the SiGe film along side surfaces of the gate structure, second sidewall films formed on the SiGe film along the first sidewall films, third sidewall films formed on the source/drain contact regions along side surfaces of the SiGe film and the second sidewall films, and first silicide films formed on the source/drain contact regions. | 2010-04-08 |
20100084686 | ASSYMETRIC HETERO-DOPED HIGH-VOLTAGE MOSFET (AH2MOS) - An asymmetric heterodoped metal oxide (AH | 2010-04-08 |
20100084687 | ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS - Structures, devices and methods are provided for creating enhanced back barriers that improve the off-state breakdown and blocking characteristics in aluminum gallium nitride AlGaN/GaN high electron mobility transistors (HEMTs). In one aspect, selective fluorine ion implantation is employed when developing HEMTs to create the enhanced back barrier structures. By creating higher energy barriers at the back of the two-dimensional electron gas channel in the unintentionally doped GaN buffer, higher off-state breakdown voltage is advantageously provided and blocking capability is enhanced, while allowing for convenient and cost-effective post-epitaxial growth fabrication. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures. | 2010-04-08 |
20100084688 | ENHANCEMENT-MODE NITRIDE TRANSISTOR - A heterojunction for use in a transistor structure is provided. The heterojunction includes a barrier layer positioned beneath a gate region of the transistor structure. The barrier layer includes nitride-based semiconductor materials. A channel layer provides electrical conduction An intermediate layer near the barrier layer and including nitride-based semiconductor materials having a wider bandgap than the channel layer | 2010-04-08 |
20100084689 | SEMICONDUCTOR DEVICE - A semiconductor device in accordance with an exemplary aspect of the present invention includes: an even number of transistor pairs; connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and inter-gate wiring lines connected to the connection nodes, each inter-gate wiring line connecting a gate of the p-type transistor of one of the transistor pairs disposed in the subsequent stage of one of the transistor pairs for which each connection node is provided, wherein the n-type transistor of a first transistor pair is disposed in a p-well region different from both a p-well region in which the n-type transistor of a second transistor pair disposed in two stages preceding of the first transistor pair is disposed and a p-well region in which the n-type transistor of a third transistor pair disposed in two stages subsequent of the first transistor pair is disposed. | 2010-04-08 |
20100084690 | CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE - A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface. | 2010-04-08 |
20100084691 | SEMICONDUCTOR COMPONENT WITH STRESS-ABSORBING SEMICONDUCTOR LAYER, AND ASSOCIATED FABRICATION METHOD - The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material ( | 2010-04-08 |
20100084692 | IMAGE SENSOR WITH LOW CROSSTALK AND HIGH RED SENSITIVITY - A color pixel array includes first, second, and third pluralities of color pixels each including a photosensitive region disposed within a first semiconductor layer. In one embodiment, a second semiconductor layer including deep dopant regions is disposed below the first semiconductor layer. The deep dopant regions each reside below a corresponding one of the first plurality of color pixels but substantially not below the second and third pluralities of color pixels. In one embodiment, buried wells are disposed beneath the second and third pluralities of color pixels but substantially not below the first plurality of color pixels. | 2010-04-08 |
20100084693 | Method of Forming a Semiconductor Device and Semiconductor Device Thereof - According to one embodiment of the present invention, a method of forming a semiconductor device is provided, the method including: forming a substrate; forming a first gate on the substrate; forming a mask layer on the substrate, the mask layer including a first window covering an area within which the first gate is formed so that the first gate divides the substrate exposed by the first window into a first region and a second region; and doping the exposed substrate using rays inclined with respect to the substrate top surface, where the position of the first gate with respect to a border of the first window is chosen such that the inclined doping rays impinge more on the first region than on the second region. | 2010-04-08 |
20100084694 | IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME - An image sensor module includes a semiconductor chip. Photodiode units are disposed in an active region of the semiconductor chip to convert light into electric signals. Pads are disposed in a peripheral region formed around the active region and the pads are electrically connected to the photodiode units. A connecting region is formed around the peripheral region. Re-distribution layers are electrically connected to respective pads and extend to the connecting region. A transparent substrate covers the photodiode units and the pads and exposes at least a portion of the re-distribution layers. Connecting layers are electrically connected to the respective re-distribution layers and extend to a top surface of the transparent substrate. Connecting members are connected to the respective connecting layers disposed on the top surface of the transparent substrate. | 2010-04-08 |
20100084695 | METHOD OF FABRICATING CMOS IMAGE SENSOR - A CMOS image sensor and a method of fabricating the same. The CMOS image sensor may minimize disappearance of electrons generated by light without transmission of electrons to a transfer gate. A method of manufacturing a CMOS image sensor may include forming a trench over an isolation region of a semiconductor substrate to define an active region including a photodiode region and a transistor region. The method may include forming first conductivity-type ion implanted regions over a trench side wall of a photodiode region and over a region adjacent to the transistor region. The method may include forming second conductivity-type ion implanted regions between a first conductivity-type ion implanted region and a trench, and between a lower part of a transistor region and a first conductivity-type ion implanted region. The method may include forming an isolation layer, forming a gate electrode and a spacer, and/or forming a photodiode. | 2010-04-08 |
20100084696 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device having plural memory cells, each composed of a memory cell transistor and a memory cell capacitor including a lower electrode that is independent for each memory cell capacitor, a ferroelectric layer formed on the lower electrode, and an upper electrode layer formed on the ferroelectric layer. A plurality of the upper electrode layers are connected together and constitute a plate electrode, and the width of the upper electrode is narrower than the width of the ferroelectric layer. Accordingly, by making the width of the upper electrode narrower than the width of the ferroelectric layer, it is possible to prevent current leakage between the upper electrode and the lower electrode, which reduces the placement interval of the memory cell capacitors without causing current leakage between the upper electrode and the lower electrode, and results in a smaller memory cell size. | 2010-04-08 |
20100084697 | NOVEL CAPACITORS AND CAPACITOR-LIKE DEVICES - A capacitor and capacitor-like device or any other device showing capacitive effects, including FETs, transmission lines, piezoelectric and ferroelectric devices, etc., with at least two electrodes, of which at least one electrode consists of or comprises a material or is generated as electron system, whose absolute value of the electronic charging energy as defined by the charging-induced change of E | 2010-04-08 |
20100084698 | SEMICONDUCTOR DEVICE HAVING PLURAL DRAM MEMORY CELLS AND A LOGIC CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - A memory cell capacitor (C | 2010-04-08 |
20100084699 | FLOTOX-TYPE EEPROM AND METHOD FOR MANUFACTURING THE SAME - A FLOTOX-TYPE EEPROM of the invention has a configuration wherein an N region | 2010-04-08 |
20100084700 | EEPROM and Method for Manufacturing EEPROM - An electrically erasable programmable read only memory (EEPROM) is disclosed. The EEPROM includes a tunneling region in a semiconductor substrate, a control gate region in the semiconductor substrate and separated from the tunneling region by a device isolating layer, a tunnel oxide layer in a trench in the semiconductor substrate between the tunneling region and the control gate region, and a polysilicon layer on the tunnel oxide layer. | 2010-04-08 |
20100084701 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells. | 2010-04-08 |
20100084702 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer. The second semiconductor layer is formed to extend in a first direction parallel to the substrate. The second low resistive layer is formed at both ends of the second semiconductor layer in the first direction. | 2010-04-08 |
20100084703 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A STACKED GATE HAVING A CHARGE STORAGE LAYER AND A CONTROL GATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more. | 2010-04-08 |
20100084704 | Devices Containing Permanent Charge - An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material. | 2010-04-08 |
20100084705 | SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench. | 2010-04-08 |
20100084706 | Power Semiconductor Devices and Methods of Manufacture - A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities. | 2010-04-08 |
20100084707 | Polysilicon control etch-back indicator - This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions. | 2010-04-08 |
20100084708 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from the second conductivity-type well. | 2010-04-08 |
20100084709 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common. | 2010-04-08 |
20100084710 | Capacitor-Less Dynamic Random Access Memory (DRAM) Devices - Dynamic random access memory (DRAM) devices including an insulating layer on a semiconductor substrate; a silicon layer on the insulating layer; an active region in the silicon layer; and a unit cell of a transistor on the active region are provided. The DRAM device does not include a capacitor. | 2010-04-08 |
20100084711 | ELECTROSTATIC DISCHARGE PROJECTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electrical device, including a semiconductor device such an electrostatic discharge protection semiconductor device, and a method for manufacturing the same. An electrostatic discharge protection semiconductor device may include a substrate and a gate in and/or over the substrate. The gate may be multi-layered, and may include a gate oxide layer and a gate electrode. An electrostatic discharge protection semiconductor device may include a source region formed in and/or over a predetermined area of the substrate on a side of the gate, and a plurality of drain regions which may be sequentially multi-layered in and/or over the substrate on an opposing side of the gate in a vertical direction. At least one drain region may be overlapped with the gate in a horizontal direction. | 2010-04-08 |
20100084712 | MULTIPLE SPACER AND CARBON IMPLANT COMPRISING PROCESS AND SEMICONDUCTOR DEVICES THEREFROM - An integrated circuit (IC) and multi-spacer methods for forming the same includes at least one metal-oxide semiconductor (MOS) transistor including a substrate having a semiconductor surface, a gate stack formed in or on the surface comprising a gate electrode on a gate dielectric, wherein a channel region is located in said semiconductor surface below the gate dielectric. A spacer structure is on the sidewalls of the gate stack, wherein the spacer structure includes a first spacer and a second spacer positioned outward from the first spacer. A source and a drain region are on opposing sides of the gate stack each having a maximum C concentration≧1×10 | 2010-04-08 |
20100084713 | Semiconductor device manufacturing method and semiconductor device - A second mask is provided so as to cover a second gate pattern and a first gate pattern is heated to a temperature at which a material gas containing a first metal thermally decomposes, polysilicon constituting the first gate pattern is reacted with the first metal for silicidation under the conditions that the layer of the first metal does not deposit, and thus the first gate pattern is turned into a first gate electrode constituted by a silicide of the first metal. After the second mask is removed, a first mask is provided so as to cover the first electrode and the second gate pattern is heated to a temperature at which the material gas thermally decomposes, polysilicon constituting the second gate pattern is reacted with the first metal for silicidation under the conditions that the layer of the first metal does not deposit, and thus the second gate pattern is turned into a second gate electrode constituted by the silicide of the first metal. Then, the first mask is removed. With such a manufacturing method, a silicide layer is formed without adding an annealing process. | 2010-04-08 |