14th week of 2022 patent applcation highlights part 46 |
Patent application number | Title | Published |
20220108938 | RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME - The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die. | 2022-04-07 |
20220108939 | BLOCKING ELEMENT FOR CONNECTING PINS OF SEMICONDUCTOR DICE - A blocking element is provided for connecting an electronic, micro-mechanical and/or micro-electro-mechanical component, in particular for controlling the propulsion of an electric vehicle. The pin blocking element is formed by a holed body having a first end, a second end and an axial cavity configured for fittingly accommodating a connecting pin. A first flange projects transversely from the holed body at the first end and a second flange projects transversely from the holed body at the second end. The first flange has a greater area than the second flange and is configured to be ultrasonically soldered to a conductive bearing plate to form a power module. | 2022-04-07 |
20220108940 | SEMICONDUCTOR DEVICE - A power semiconductor module, which is a semiconductor device, includes a semiconductor element | 2022-04-07 |
20220108941 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND POWER CONVERTER - Inner leads having die pads having upper surfaces to which semiconductor elements are mounted each have a stepped profile, and surfaces of portions of the inner leads are exposed from a sealing resin in plan view. Outer leads connected to the inner leads have first bends at side surfaces of the sealing resin to extend in a direction on a side of the upper surfaces of the die pads, so that a miniaturized semiconductor device can be obtained. | 2022-04-07 |
20220108942 | SEMICONDUCTOR PACKAGE INCLUDING A WIRE AND A METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE - A semiconductor package is described. The semiconductor packager includes a chip stack mounted on a package substrate, a first wire disposed on the package substrate, and a molding layer surrounding the chip stack and the first wire. The first wire has an acute angle. | 2022-04-07 |
20220108943 | MULTILAYER WIRING SUBSTRATE - A multilayer wiring substrate includes a first wiring substrate including a plurality of stacked layers made of a thermosetting resin and having a wiring layer formed between each adjacent layers of the layers in a state in contact with the adjacent layers; a second wiring substrate made of a ceramic; and a joining layer disposed between a back surface of the first wiring substrate and a front surface of the second wiring substrate and configured to join the first wiring substrate and the second wiring substrate to each other. At least a surface of the joining layer adjacent to the second wiring substrate is made of a thermoplastic resin. | 2022-04-07 |
20220108944 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE - Provided is a technique that enables a passive component to be arranged with a short wiring distance to a power terminal of a semiconductor element mounted on a semiconductor module. In a semiconductor module, a plurality of first connection terminal groups having connection terminals arranged with a first gap therebetween, and a second connection terminal group having connection terminals arranged with a second gap therebetween in a rectangular ring so as to surround the first connection terminal groups, are arranged with a second group gap therebetween that is wider than the first gap and the second gap. In a plan view, a first power terminal of a first semiconductor element overlaps a target terminal group that is one of the first connection terminal groups. In the plan view, a second power terminal of a second semiconductor element overlaps the second connection terminal group. | 2022-04-07 |
20220108945 | SEMICONDUCTOR MODULE - A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector. | 2022-04-07 |
20220108946 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element. | 2022-04-07 |
20220108947 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure. | 2022-04-07 |
20220108948 | Method for Producing an Interconnect Via - A method includes: producing on a substrate a stack of: a first layer including a first dielectric material, a second layer including dielectric material on the first layer, and an etch stop layer between the first layer and the second layer, etching a trench through the second layer, the etch stop layer, and the first layer, producing a lower conductive line in the trench, producing a third layer including a second dielectric material in the trench and on the tower conductive line, removing a first portion of the second layer, such that a second portion of the second layer remains in contact with the etch stop layer, etching a via opening through the third layer in the trench, using the second portion of the second layer as a mask, and depositing a conductive upper line and an interconnect via on the lower conductive line within the via opening. | 2022-04-07 |
20220108949 | SEMICONDUCTOR PACKAGES INCLUDING A U-SHAPED RAIL - One example of a semiconductor package includes a first die pad, a first die, a second die pad, and a second die. The first die pad includes a main portion and a U-shaped rail portion extending from the main portion. The first die is electrically coupled to the first die pad. The second die pad is proximate the U-shaped rail portion of the first die pad. The second die is electrically coupled to the second die pad. The second die includes a magnetic field sensor. | 2022-04-07 |
20220108950 | METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS - An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions. | 2022-04-07 |
20220108951 | SUBSTRATE WITH A BURIED CONDUCTOR UNDER AN ACTIVE REGION FOR ENHANCED THERMAL CONDUCTIVITY AND RF SHIELDING - A semiconductor device is provided, the semiconductor device comprising a substrate having merged cavities in the substrate. An active region is over the merged cavities in the substrate. A thermally conductive layer is in the merged cavities in the substrate, whereby the thermally conductive layer at least partially fills up the merged cavities in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavities in the substrate with a metallization layer above the active region. | 2022-04-07 |
20220108952 | METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH COMPOSITE LANDING PAD - The present disclosure relates to method for preparing a semiconductor device with a composite landing pad. The method includes forming a first dielectric layer over a semiconductor substrate. The semiconductor device also includes forming a lower metal plug and a barrier layer in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes forming an inner silicide portion over the lower metal plug, and an outer silicide portion over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion. | 2022-04-07 |
20220108953 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge. | 2022-04-07 |
20220108954 | ELECTRONIC PACKAGE WITH ROTATED SEMICONDUCTOR DIE - An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate. | 2022-04-07 |
20220108955 | EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE - Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure. | 2022-04-07 |
20220108956 | FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT FEATURE - A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure. | 2022-04-07 |
20220108957 | MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER - A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die. | 2022-04-07 |
20220108958 | SEMICONDUCTOR WAFER AND METHOD OF MANUFACTURING SEMICONDUCTOR CHIP - A semiconductor wafer includes: a rectangular circuit formation region provided on the semiconductor wafer; an electronic circuit formed in the circuit formation region; a first seal ring formed along each of four outer peripheral parts of the circuit formation region so as to surround an outer periphery of the circuit formation region; and a second seal ring formed, in parallel with the first seal ring, on outer peripheral parts other than at least one outer peripheral part out of the four outer peripheral parts of the circuit formation region. | 2022-04-07 |
20220108959 | SEMICONDUCTOR MODULE - Provided is a semiconductor module, including: a semiconductor chip; a circuit board on which the semiconductor chip is mounted; a sealing resin including epoxy resin for sealing the semiconductor chip and the circuit board; and a reinforcing material, with a higher Young's modulus than the sealing resin, provided in close contact with the sealing resin above at least a part of the sealing resin. The semiconductor module includes a resin case for enclosing spaces for housing the semiconductor chip, wherein the sealing resin may be provided inside the resin case. | 2022-04-07 |
20220108960 | EX-SITU MANUFACTURE OF METAL MICRO-WIRES AND FIB PLACEMENT IN IC CIRCUITS - A method includes attaching a first portion of a preformed metal micro-wire to a multilayer structure. The preformed metal micro-wire has a diameter of 10 microns or less. The method also includes attaching a second portion of the preformed metal micro-wire to the multilayer structure. | 2022-04-07 |
20220108961 | Semiconductor Device and Method of Manufacture - A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer. | 2022-04-07 |
20220108962 | SEMICONDUCTOR CHIP - A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region. | 2022-04-07 |
20220108963 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate. | 2022-04-07 |
20220108964 | METHOD AND APPARATUS TO IMPROVE CONNECTION PITCH IN DIE-TO-WAFER BONDING - Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die having a first bonding surface that is formed with a first set of contacts patterned with a first connection pitch. A second semiconductor die has a second bonding surface that is formed with a second set of contacts patterned with a second connection pitch. The second set of contacts are further patterned with a paired offset. The second semiconductor die is bonded to the first semiconductor die such that the first set of contacts is disposed in opposed electrical engagement with at least a portion of the second set of contacts. | 2022-04-07 |
20220108965 | LOW TEMPERATURE, REWORKABLE, AND NO-UNDERFILL ATTACH PROCESS FOR FINE PITCH BALL GRID ARRAYS HAVING SOLDER BALLS WITH EPOXY AND SOLDER MATERIAL - A ball grid array (BGA) including at least one BGA chip and a plurality of solder balls directly connected to a substrate, such as a printed circuit board (PCB), where the solder balls include an epoxy. A method for producing a BGA package including providing a BGA having a plurality of epoxy-containing solder balls, positioning the BGA on a substrate, such as a PCB, and applying heat to reflow the epoxy-containing solder balls and to create a connection between the BGA and the PCB. | 2022-04-07 |
20220108966 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element. | 2022-04-07 |
20220108967 | CHIP PACKAGE STRUCTURE - A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive bump connected between the first chip and the first redistribution structure. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the first redistribution structure. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive bump connected between the second chip and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the first redistribution structure. | 2022-04-07 |
20220108968 | INTEGRATED CIRCUIT ASSEMBLY WITH HYBRID BONDING - Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly. | 2022-04-07 |
20220108969 | POWER SEMICONDUCTOR MODULE AND POWER CONVERSION APPARATUS - A power semiconductor module includes a circuit substrate, a power semiconductor device including a semiconductor substrate, and at least one bonding portion. The at least one bonding portion includes a first metal member distal to the semiconductor substrate, a second metal member proximal to the semiconductor substrate, and a bonding layer that bonds the first metal member and the second metal member to each other. At an identical temperature, 0.2% offset yield strength of the first metal member is smaller than the 0.2% offset yield strength of the second metal member and is smaller than shear strength of the bonding layer. | 2022-04-07 |
20220108970 | SEMICONDUCTOR DIE WITH CAPILLARY FLOW STRUCTURES FOR DIRECT CHIP ATTACHMENT - A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate. | 2022-04-07 |
20220108971 | BONDING WIRE FOR SEMICONDUCTOR DEVICES - Bonding wire for semiconductor devices contains one or more of Be, B, P, Ca, Y, La, and Ce in a total of 0.031 at % to obtain a 0.180 at %, further contains one or more of In, Ga, and Cd in a total of 0.05 at % to 5.00 at %, and has a balance of Ag and unavoidable impurities. Due to this, it is possible to obtain a bonding wire for semiconductor devices sufficiently forming an intermetallic compound layer at a ball bond interface to secure the bond strength of the ball bond, not causing neck damage even in a low loop, having a good leaning characteristic, and having a good FAB shape. | 2022-04-07 |
20220108972 | PRESSURE-CONTACT SEMICONDUCTOR DEVICE - An object of the present invention is to suppress electrical contact between an outer peripheral portion of an intermediate electrode and a front surface electrode of a semiconductor chip without increasing the area of the semiconductor chip. A facing surface of the first intermediate electrode facing a first main electrode is smaller than a facing surface of the first main electrode facing the first intermediate electrode, and has an outer peripheral protective region and a connection region surrounded by the protective region. A pressure-contact semiconductor device includes a plurality of first conductor films partially formed in the connection region, and a first insulating film formed in regions in the connection region where no first conductor films are formed and in the protective region. | 2022-04-07 |
20220108973 | SEMICONDUCTOR DEVICE ASSEMBLY AND METHOD THEREFOR - A method of forming a semiconductor device includes attaching a semiconductor die to a flag of a leadframe and forming a conductive connector over a portion of the semiconductor die and a portion of the flag. A conductive connection between a first bond pad of the semiconductor die and the flag is formed by way of the conductive connector. A second bond pad of the semiconductor die is connected to a conductive lead of the plurality by way of a bond wire. | 2022-04-07 |
20220108974 | METHOD OF FORMING A CHIP PACKAGE AND CHIP PACKAGE - A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer. | 2022-04-07 |
20220108975 | SILVER NANOPARTICLES SYNTHESIS METHOD FOR LOW TEMPERATURE AND PRESSURE SINTERING - The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200° C. and in some embodiments at about 150° C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution. | 2022-04-07 |
20220108976 | PACKAGE STACKING USING CHIP TO WAFER BONDING - Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer. | 2022-04-07 |
20220108977 | SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction. | 2022-04-07 |
20220108978 | Carrier Film And Apparatus And Method For Repairing LED Display Panel - The present invention comprises a plurality of repair devices ( | 2022-04-07 |
20220108979 | DISPLAY DEVICE - A display device is provided. The display device includes: a substrate; a first electrode located on the substrate; a second electrode located between the substrate and the first electrode; a first light emitting element located on the same layer as the first electrode; and a contact electrode located on the first light emitting element, wherein one end of the first light emitting element contacts the first electrode, and the other end of the first light emitting element contacts the contact electrode. | 2022-04-07 |
20220108980 | INTEGRATED THIN FILM RESISTOR AND METAL-INSULATOR-METAL CAPACITOR - The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film. | 2022-04-07 |
20220108981 | ARRAY OF MULTI-STACK NANOSHEET STRUCTURES AND METHOD OF MANUFACTURING THE SAME - An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column. | 2022-04-07 |
20220108982 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device including a pair of first fin type active areas protruding from a substrate in a vertical direction and extending in parallel with each other, a gate interposed between the pair of first fin type active areas, spaced apart from each of the pair of first fin type active areas in a first horizontal direction, and longitudinally extending in parallel with the pair of first fin type active areas, a gate insulating layer filling a first space between one of the pair of first fin type active areas and the gate and a second space between the other of the pair of first fin type active areas and the gate, and a pair of source/drain areas at both sides of the gate, respectively, in a second horizontal direction perpendicular to the first horizontal direction and on the pair of first fin type active areas may be provided. | 2022-04-07 |
20220108983 | SEMICONDUCTOR DEVICE WITH SUPERLATTICE FIN - Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet. | 2022-04-07 |
20220108984 | Input/Output Semiconductor Devices - A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer. | 2022-04-07 |
20220108985 | MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced. | 2022-04-07 |
20220108986 | SEMICONDUCTOR DEVICE AND METHOD FABRICATING THE SAME - A method for fabricating a semiconductor device, including the steps of: providing a substrate having an etch stop layer formed thereon; forming a preliminary stacked structure on the etch stop layer, the preliminary stacked structure including a lower sacrifice layer contacting the etch stop layer, a support layer, and an upper sacrifice layer; forming a hole penetrating the preliminary stacked structure and the etch stop layer; forming a conductive pattern in the hole; removing the upper sacrifice layer and a portion of the support layer; removing the lower sacrifice layer; forming a first conductive layer covering the conductive pattern; and forming a dielectric layer covering the first conductive layer, a remaining portion of the support layer, and the etch stop layer. | 2022-04-07 |
20220108987 | MULTI-DIRECTION CONDUCTIVE LINE AND STAIRCASE CONTACT FOR SEMICONDUCTOR DEVICES - Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction. | 2022-04-07 |
20220108988 | CONDUCTIVE LINE CONTACT REGIONS HAVING MULTIPLE MULTI-DIRECTION CONDUCTIVE LINES AND STAIRCASE CONDUCTIVE LINE CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES - Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region. | 2022-04-07 |
20220108989 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes power supply lines extending in a first direction; first transistors, each of which is formed in a first region and has a first threshold voltage; and second transistors, each of which is formed in a second region and has a second threshold voltage higher than the first threshold voltage. One of the plurality of power supply lines is interposed between the first region and the second region, the first transistors implement a first portion of a multiplexer, a clock buffer and a first latch that are disposed on a data path, the second transistors implement a second portion of the multiplexer circuit and a second latch that are disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed in a common location along the first direction. | 2022-04-07 |
20220108990 | METHOD OF MAKING SEMICONDUCTOR DEVICE WHICH INCLUDES FINS - In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins. | 2022-04-07 |
20220108991 | Semiconductor Device Including a Layer Between a Source/Drain Region and a Substrate - Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet. | 2022-04-07 |
20220108992 | SEMICONDUCTOR STORAGE DEVICE - Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other. | 2022-04-07 |
20220108993 | 3D NAND FLASH MEMORY DEVICE - A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation. | 2022-04-07 |
20220108994 | MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device includes: forming a preliminary memory cell array on a support structure, the preliminary memory cell array with a stack structure and cell pillars; removing the support structure to expose a portion of each of the cell pillars; forming a protective layer that covers the exposed portion of each of the cell pillars; forming a mask pattern that exposes an opening defined between inclined surfaces of the protective layer wherein the inclined surfaces are disposed between the cell pillars; and etching at least one conductive layer among the conductive layers that is adjacent to the opening, thereby isolating the at least one conductive layer into select lines. | 2022-04-07 |
20220108995 | THREE-DIMENSIONAL FUSE ARCHITECTURES AND RELATED SYSTEMS, METHODS, AND APPARATUSES - Apparatuses, methods, and computing systems relating to three-dimensional fuse architectures are disclosed. An apparatus includes a semiconductor substrate, a fuse array on or in the semiconductor substrate, and fuse circuitry on or in the semiconductor substrate. The fuse array includes fuse cells. The fuse circuitry is configured to access the fuse cells. The fuse circuitry is offset from the fuse array such that the fuse circuitry is disposed between the semiconductor substrate and the fuse array, or the fuse array is disposed between the semiconductor substrate and the fuse circuitry. | 2022-04-07 |
20220108996 | READ-ONLY MEMORY WITH VERTICAL TRANSISTORS - Provided is a read-only memory (ROM) device. The ROM device comprises a substrate that has a plurality of vertical transport field effect transistors (VFETs). The ROM device further comprises an un-activated semiconductor layer provided on each VFET. The un-activated semiconductor layer includes implanted dopants that have not been substantially activated. | 2022-04-07 |
20220108997 | LOW-VOLTAGE FLASH MEMORY INTEGRATED WITH A VERTICAL FIELD EFFECT TRANSISTOR - A circuit may include a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may provide a lower significance conductance and the non-volatile memory element may provide a higher significance conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer. | 2022-04-07 |
20220108998 | MICROELECTRONIC DEVICES WITH SUPPORT PILLARS SPACED ALONG A SLIT REGION BETWEEN PILLAR ARRAY BLOCKS, AND RELATED METHODS AND SYSTEMS - A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems. | 2022-04-07 |
20220108999 | THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A three-dimensional memory device includes a lower stack and an upper stack stacked one on the other, and each including a plurality of word lines which are stacked alternately with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part which couples the first cell part and the second cell part, and a staircase part which extends parallel to the coupling part from the first cell part and in which pad areas of the word lines are disposed in a stepwise manner, and wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack. | 2022-04-07 |
20220109000 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described. | 2022-04-07 |
20220109001 | MICROELECTRONIC DEVICES WITH SLIT STRUCTURES INLCUDING METAL PLUGS AND RELATED METHODS AND SYSTEMS - A microelectronic device may include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures, the stack structure divided into block portions. The microelectronic device may additionally include slit structures horizontally interposed between the block portions of the stack structure. Each of the slit structures may include a dielectric liner covering side surfaces of the stack structure and an upper surface of an additional structure underlying the stack structure, and a plug structure comprising at least one metal surrounded by the dielectric liner. | 2022-04-07 |
20220109002 | ELECTRONIC DEVICES WITH RECESSED CONDUCTIVE STRUCTURES AND RELATED METHODS AND SYSTEMS - An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed. | 2022-04-07 |
20220109003 | THREE-DIMENSIONAL NAND MEMORY DEVICE WITH REDUCED REVERSE DIPOLE EFFECT AND METHOD FOR FORMING THE SAME - A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film and a vertical semiconductor channel. The memory film includes a tunneling dielectric layer, a charge storage layer that laterally surrounds the tunneling dielectric layer, a dielectric metal oxide blocking dielectric layer that laterally surrounds the charge storage layer and contacts the vertical semiconductor channel, and a silicon oxide blocking dielectric layer that laterally surrounds the dielectric metal oxide blocking dielectric layer and contacts the vertical semiconductor channel. | 2022-04-07 |
20220109004 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device may include a substrate; a first stacked structure on the substrate; a second stacked structure on the first stacked structure; a channel structure including a first portion passing through the first stacked structure and a second portion passing through the second stacked structure; and a filling structure including a first portion passing through the first stacked structure and extending in a first horizontal direction and a second portion passing through the second stacked structure and extending in the first horizontal direction. The upper end of the first portion of the filling structure may be at a same height as the upper end of the first portion of the channel structure. | 2022-04-07 |
20220109005 | ARRAY SUBSTRATE AND DISPLAY DEVICE THEREOF - The application provides an array substrate and a display device thereof. The array substrate includes a substrate, a gate layer, a first signal electrode layer, an active layer, and a second signal electrode layer, which are stacked, wherein the first signal electrode layer is patterned to form a first signal electrode, the second signal electrode layer is patterned to form a second signal electrode, the first signal electrode is one of a source or a drain, and the second signal electrode is the other one of the source or the drain. | 2022-04-07 |
20220109006 | DISPLAY PANEL AND DISPLAY - A display panel and a display comprising the display panel. The display panel comprises a primary display area ( | 2022-04-07 |
20220109007 | DISPLAY DEVICE INCLUDING A PATTERNED CONDUCTIVE LAYER - A display device includes: a gate line including a gate line portion; a data line; a transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; and a connecting member disposed between the data line and the source electrode, connected to the data line and the source electrode to cross a gate electrode edge of the gate electrode. A connecting portion where a data line edge and a connecting member edge are connected to each other does not overlap the gate line and the gate electrode in a plan view. The data line includes a first data line portion crossing the gate line and a second data line portion connected to the first data line portion and does not overlap the gate line in the plan view. | 2022-04-07 |
20220109008 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly which includes a base structure. The base structure includes a series of conductive structures which extend along a first direction. The conductive structures have steps which alternate with recessed regions along the first direction. Pillars of semiconductor material are over the steps. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The semiconductor material may be semiconductor oxide in some applications. Some embodiments include methods of forming integrated assemblies. | 2022-04-07 |
20220109009 | THIN-FILM TRANSISTORS - The present disclosure is drawn to thin-film transistors, electronic displays that include thin-film transistors, and methods of making thin-film transistors. In one example, a thin-film transistor can include a nonconductive substrate, a semiconductor layer on the nonconductive substrate, a source electrode adjacent a first side of the semiconductor layer and partially overlapping a first peripheral portion of the semiconductor layer, a drain electrode adjacent a second side of the semiconductor layer and partially overlapping a second peripheral portion of the semiconductor layer, an etch stop layer on the semiconductor layer, a gat insulator layer on the etch stop layer, and a gate electrode on the gate insulator layer. The source electrode and the drain electrode do not overlap the etch stop layer. | 2022-04-07 |
20220109010 | ARRAY SUBSTRATE, TEST METHOD OF FILM LAYER STRESS, AND DISPLAY PANEL - An array substrate, a test method of a film layer stress, and a display panel are provided. The array substrate includes: a base substrate; a first film layer on the base substrate, the first film layer provided with a first mounting groove; and a first strain sensor arranged in the first mounting groove. The first strain sensor is used to detect a stress of the first film layer. | 2022-04-07 |
20220109011 | METHOD OF MANUFACTURING DISPLAY APPARATUS - A method of manufacturing a display apparatus includes forming a first conductive layer on a base substrate including a panel area and a margin area disposed next to the panel area, the margin area including a dummy pattern area, forming a photoresist layer on the first conductive layer, forming a photoresist pattern by exposing and developing the photoresist layer, forming a first conductive pattern by etching the first conductive layer using the photoresist pattern, and removing the photoresist pattern. The forming the first conductive pattern includes forming a first pixel circuit pattern in the panel area, and forming a dummy pattern in the dummy pattern area of the margin area. An opening ratio of a portion where the dummy pattern is not formed with respect to the dummy pattern area is about 30% or more. | 2022-04-07 |
20220109012 | IMAGE SENSOR AND ELECTRONIC SYSTEM INCLUDING THE SAME - An image sensor includes a substrate having a sensing area, a floating diffusion region arranged in the sensing area, a plurality of photodiodes arranged around the floating diffusion region in the sensing area, and an inter-pixel overflow (IPO) barrier in contact with each of the plurality of photodiodes, the IPO barrier overlapping the floating diffusion region in a vertical direction at a position vertically spaced apart from the floating diffusion region within the sensing area. | 2022-04-07 |
20220109013 | IMAGE SENSOR - An image sensor includes: on a substrate that includes a first surface and a second surface opposite to the first surface, photoelectric conversion regions located in the substrate, the photoelectric conversion regions being separated from each other; partition layers spaced apart from the first surface and between the photoelectric conversion regions; and pixel separation layers on the partition layers that separate the photoelectric conversion regions from each other. | 2022-04-07 |
20220109014 | IMAGE SENSOR WITH TRENCH STRUCTURES - Disclosed is an image sensor including a first substrate having first and second surfaces opposite to each other and including a pixel array area that includes unit pixel regions, a pad area that surrounds the pixel array area, and an optical black area between the pixel array area and the pad area, a dielectric pattern on the first surface of the first substrate, and a light-shield pattern on a top surface of the dielectric pattern on the optical black area. The first substrate includes first and second trenches recessed from the first surface. The dielectric pattern includes a first part filling the first trench and defining the unit pixel regions, a second part filling the second trench, and a third part on the first surface of the first substrate and connected to the first and second parts. | 2022-04-07 |
20220109015 | IMAGE SENSOR - An image sensor is provided. The image sensor includes a first pixel region and a second pixel region located within a semiconductor substrate, a first isolation layer surrounding the first pixel region and the second pixel region, a second isolation layer located between the first pixel region and the second pixel region, and a microlens arranged on the first pixel region and the second pixel region. Each of the first pixel region and the second pixel region include a photoelectric conversion device. The second isolation layer includes at least one first open region that exposes a portion of an area located between the first pixel region and the second pixel region. | 2022-04-07 |
20220109016 | IMAGE SENSOR - An image sensor is provided. An image sensor includes: a substrate including an active pixel sensor region, an optical black sensor region, and a boundary region provided between the active pixel sensor region and the optical black sensor region; a photoelectric conversion element provided inside the substrate on the boundary region; a passivation layer provided on the substrate; a grid trench formed on the boundary region of the substrate and extending from an upper surface of the passivation layer toward an inside of the passivation layer; grid patterns, each of the grid patterns being provided on the passivation layer on each of the active pixel sensor region and the boundary region of the substrate, at least a part of a grid pattern being provided inside the grid trench; and a color filter provided between the grid patterns. | 2022-04-07 |
20220109017 | IMAGING DEVICE AND ELECTRONIC APPARATUS - An imaging device according to one embodiment of the present disclosure includes a first electrode, a second electrode, and a photoelectric converter. The first electrode includes an oxide semiconductor material having an amorphous state. The second electrode is opposed to the first electrode. The photoelectric converter is provided between the first electrode and the second electrode, and includes a compound semiconductor material. | 2022-04-07 |
20220109018 | CAMERA MODULE AND MOLDED CIRCUIT BOARD ASSEMBLY THEREOF, ARRAY CAMERA MODULE AND ELECTRONIC DEVICE - A camera module and a molded circuit board assembly thereof, a semi-finished product of the molded circuit board assembly, and an array camera module and a molded circuit board assembly thereof, as well as a manufacturing method and an electronic device, wherein the camera module comprises at least one optical lens, at least one back surface molded portion, at least one photosensitive element and a circuit board. The circuit board comprises at least one substrate and at least one electronic component that is conductively connected to the substrate; a part of the non-photosensitive area of the photosensitive element is attached to the substrate back surface of the substrate, and the photosensitive area and another part of the non-photosensitive area of the photosensitive element correspond to a substrate channel of the substrate; the back surface molded portion is integrally bonded to at least one part of the area of the substrate back surface of the substrate; and the optical lens is held in the photosensitive path of the photosensitive element. | 2022-04-07 |
20220109019 | LIGHT SENSING DEVICE WITH FILTER ELEMENT - A light sensing device is provided. The light sensing device includes a semiconductor substrate and a light sensing region in the semiconductor substrate. The light sensing device also includes a filter element over the light sensing region and a light shielding element over the semiconductor substrate and beside the filter element. The light sensing device further includes a dielectric element over the light shielding element and beside the filter element. A top of the light shielding element and a bottom of the dielectric element have different widths. | 2022-04-07 |
20220109020 | IMAGE SENSOR - An image sensor includes a substrate that has a first pixel region and a second pixel region and a microlens layer on a first surface of the substrate. The microlens layer includes a first lens pattern on the first pixel region of the substrate; and a second lens pattern on the second pixel region of the substrate. A width of the first pixel region is greater than a width of the second pixel region, and a height of the first lens pattern is greater than a height of the second lens pattern. | 2022-04-07 |
20220109021 | MICRO LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A micro light emitting display apparatus and a method of manufacturing the micro light emitting display apparatus are disclosed. The micro light emitting display apparatus includes a micro light emitting element, a driving transistor connected to the micro light emitting element, a switching transistor connected to the driving transistor, and a first opening is provided to expose a source region or a drain region of the switching transistor, and a gate electrode of the driving transistor is provided in the first opening and in contact with the source region or the drain region of the switching transistor. | 2022-04-07 |
20220109022 | MICRO LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A micro light-emitting display apparatus and a method of manufacturing the same are disclosed The micro light-emitting display apparatus includes a first semiconductor layer, an isolation structure provided on the first semiconductor layer and configured to define a plurality of sub-pixels each configured to emit light, a first light-emitting unit including a first active layer provided in a first sub-pixel among the plurality of sub-pixels, and a second semiconductor layer provided on the first active layer, and a second light-emitting unit including a rod semiconductor layer provided in a second sub-pixel among the plurality of sub-pixels, a second active layer provided on the rod semiconductor layer, and a third semiconductor layer provided on the second active layer. The first active layer is configured to emit blue light and the second active layer is configured to emit green light. | 2022-04-07 |
20220109023 | DISPLAY DEVICE - A display device includes a first electrode and a second electrode spaced apart from each other and disposed on a substrate, a light emitting element extending in a first direction and including a first end disposed on the first electrode in the first direction and a second end disposed on the second electrode in the first direction. A diameter of the first end of the light emitting element is different from a diameter of the second end of the light emitting element. The light emitting element includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer. The active layer is adjacent to one of the first end and the second end of the light emitting element, which has a larger diameter than a diameter of the other. | 2022-04-07 |
20220109024 | MEMORY DEVICE - According to one embodiment, a memory device includes: a first variable resistance layer; first and second semiconductor layers being in contact with the first variable resistance layer; a first word line; a second word line being adjacent to the first word line; and a third word line being adjacent to the first and second word lines with the first semiconductor layer, the first variable resistance layer, and the second semiconductor layer interposed therebetween, and provided between the first word line and the second word line. In the first variable resistance layer, a first region including a shortest path connecting the first word line and the third word line functions as a first memory cell, and a second region including a shortest path connecting the third word line and the second word line functions as a second memory cell. | 2022-04-07 |
20220109025 | DOUBLE SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES - Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line. | 2022-04-07 |
20220109026 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer. | 2022-04-07 |
20220109027 | DISPLAY DEVICE - An embodiment provides a display device including: a first pixel, a second pixel, and a third pixel that form one dot and display different colors; a first light emitting element disposed in the first pixel, a second light emitting element disposed in the second pixel, and a third light emitting element disposed in the third pixel; and a first color conversion area in which a first color conversion layer overlapping the first light emitting element is disposed, a second color conversion area in which a second color conversion layer overlapping the second light emitting element is disposed, and a third color conversion area in which a third color conversion layer overlapping the third light emitting element is disposed, wherein the first color conversion area, the second color conversion area, and the third color conversion area have polygonal planar shapes having at least 5 sides. | 2022-04-07 |
20220109028 | DISPLAY DEVICE - A display device includes: a display panel displaying an image and including a light emitting area and a non-light-emitting area adjacent to the light emitting area, wherein a light emitting element is disposed in the light emitting area; and an input sensor disposed on the display panel and comprising a sensing electrode, wherein an opening in the sensing electrode partially exposes the light emitting area, wherein the sensing electrode includes: a first touch electrode disposed to overlap the non-light-emitting area; and a second touch electrode overlapping the light emitting area and the non-light-emitting area and electrically connected to the first touch electrode. | 2022-04-07 |
20220109029 | DISPLAY DEVICE - A display device includes a light sensing array layer (LSAL), a substrate, a selective light transmission layer (SLTL), a pixel circuit layer (PCL), a display element layer (DEL), and pixels. The LSAL includes an optical sensor to sense incident light. The substrate is on the LSAL and includes a display area (DA) including pixel areas (PAs), and a non-DA adjacent to the DA. The SLTL is disposed on the substrate and includes through-holes to form a path of light onto the optical sensor, and a light-blocking conductive pattern (LBCP) between the through-holes. The PCL is disposed on the SLTL and includes a conductive layer and an insulation layer. The DEL is disposed on the PCL and emits light. Each pixel includes a pixel circuit disposed on the PCL, and a light emitting element on the DEL in a corresponding pixel area. The LBCP is electrically connected to the conductive layer. | 2022-04-07 |
20220109030 | DISPLAY DEVICE - A display device includes: a substrate including a first display area, a second display area, and a third display area which are arranged along a row direction; a first pixel row on the substrate, extending in the row direction, and including first pixel circuit portions overlapping the second and third display areas; a second pixel row extending in the row direction and including second pixel circuit portions overlapping the second display area; display elements overlapping the first display area; and bridge lines adjacent to the second pixel circuit row, overlapping the second display area, and connecting the first pixel circuit portions and the display elements. | 2022-04-07 |
20220109031 | DISPLAY APPARATUS - A display apparatus includes: a first substrate having a front surface and a rear surface; a first display layer disposed on the front surface of the first substrate, the first display layer configured to emit light in a front direction; a second display layer disposed on the rear surface of the first substrate, the second display layer configured to emit light in a rear direction; and a pressure sensor disposed on the rear surface of the first substrate, the pressure sensor configured to sense a pressure of a touch of a user. | 2022-04-07 |
20220109032 | OLED DISPLAY STRUCTURE AND ELECTRONIC EQUIPMENT - The present application discloses an OLED display structure, including pixels. The pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel. The first sub-pixel includes a first storage capacitor, a first auxiliary capacitor and a first light emitting area. The second sub-pixel includes a second storage capacitor, a second auxiliary capacitor and a second light emitting area. The third sub-pixel includes a third storage capacitor, a third auxiliary capacitor and a third light emitting area. The areas of the first light emitting area, the second light emitting area and the third light emitting area are respectively defined as S ( | 2022-04-07 |
20220109033 | PIXEL ARRANGEMENT STRUCTURE AND DRIVING METHOD THEREOF, DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate including a first display area including a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, wherein the display substrate includes a plurality of first pixel groups each of which includes two third sub-pixels, one first sub-pixel and one second sub-pixel, the two third sub-pixels are arranged adjacent to each other along a first direction, the one first sub-pixel and the one second sub-pixel are adjacent to at least one of the two third sub-pixels, located on both sides of a straight line passing centers of the two third sub-pixels, and arranged along a second direction different from the first direction; a size of the first sub-pixel and the second sub-pixel in the second direction is smaller than a size of the first sub-pixel and the second sub-pixel in the first direction, respectively. | 2022-04-07 |
20220109034 | METHOD FOR MANUFACTURING PIXEL STRUCTURE AND DISPLAY PANEL - The present application provides a method for manufacturing a pixel structure and a display panel. The pixel structure includes a substrate, a plurality of first pixel banks, and a plurality of second pixel banks. The first pixel banks intersect a long side direction of the substrate. The second pixel banks are parallel to the long side direction of the substrate. Light emitting materials with a same color are disposed between two adjacent second pixel banks, so that this pixel design can be compatible with MMG line-bank printing, which alleviates a problem that existing MMG pixel arrangement mode restricts a printing mode. | 2022-04-07 |
20220109035 | DISPLAY MODULE HAVING A CIRCUIT INSULATING LAYER - A display module may include a display panel that includes a base layer, a circuit insulating layer, a first electrode, and an emission layer. The circuit insulating layer may include a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness. The first electrode may include a first electrode portion disposed on the first portion and a second electrode portion extending from the first electrode portion and disposed on the second portion. The emission layer may include a first light-emitting portion disposed on the first electrode portion and a second light-emitting portion extending from the first light-emitting portion and disposed on the second electrode portion. | 2022-04-07 |
20220109036 | DISPLAY DEVICE - Embodiments of the present disclosure relate to a display device including a substrate, an optical device located under the substrate in a display area, and a subpixel layer located over the substrate in the display area, wherein the subpixel layer includes at least one of first transistor with a first characteristic are located at a first area overlapping with the optical device, and at least one of second transistor with a second characteristic are located at a second area not overlapping with the optical device. | 2022-04-07 |
20220109037 | DISPLAY PANEL AND PREPARATION METHOD THEREOF, AND DISPLAY DEVICE - Provided are a display panel and a preparation method thereof, and a display device. The display panel includes a base substrate; a first transistor, a second transistor, a third transistor; and a pixel circuit supplying a drive current to a display element, and a driver circuit supplying a drive signal to the pixel circuit; where the driver circuit includes the first transistor, and the pixel circuit includes the second transistor and the third transistor; and the subthreshold swing of the first transistor is SS | 2022-04-07 |