14th week of 2022 patent applcation highlights part 45 |
Patent application number | Title | Published |
20220108838 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes each provided at one of two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers provided on both sides in a length direction of a surface of the capacitor main body. The two interposers each include a protrusion extending from one of the two interposers to another of the two interposers. | 2022-04-07 |
20220108839 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrodes each at one of two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers on a surface in a lamination direction of the capacitor main body, and opposed and spaced apart from each other in a length direction connecting the two end surfaces. The two interposers each include a first recess portion on an end surface of the interposer opposed to an end surface facing the other interposer, in an area around a middle portion of the interposer in a width direction, and second recess portions on both sides in the width direction of the first recess portion, and each having a thickness of about ±10% of a half of a thickness of the interposer. | 2022-04-07 |
20220108840 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes each at end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers on a surface in a lamination direction of the capacitor main body, and spaced apart from each other in a length direction connecting the two end surfaces and intersecting the lamination direction. The external electrodes each include a bulge portion protruding in the lamination direction on the surface of the capacitor main body. The interposers each include a recess portion on each of the end surfaces, and in a cross section extending in the lamination direction and the length direction and passing through a center in a width direction. The bulge portion is closer to the end surface in the length direction than the recess portion. | 2022-04-07 |
20220108841 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes at two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers on a surface of the capacitor main body in a lamination direction and opposed and spaced apart from each other. The interposers each include a first surface at or adjacent to the capacitor main body, and a second surface parallel or substantially parallel to each other, and the first surface is sloped with respect to the second surface at a predetermined angle approaching the surface of the capacitor main body toward a side at which the two interposers face each other. | 2022-04-07 |
20220108842 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes at two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers on a surface of the capacitor main body, and opposed and spaced apart from each other. The two interposers each include a first surface at or adjacent to the capacitor main body, and a second surface opposite to the first surface, the first and second surfaces being parallel or substantially parallel with each other, and the first surface is sloped with respect to the surface of the capacitor main body at a predetermined angle to be spaced from the surface of the capacitor main body toward a side at which the two interposers face each other. | 2022-04-07 |
20220108843 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a capacitor main body, and two interposers on both sides in a length direction of a surface of the capacitor main body. When a distance between a side surface of one interposer on one side in the length direction, and a side surface of the capacitor main body is defined as X1, a distance between another side surface of the one interposer, and another side surface of the capacitor main body is defined as X4, a distance between a side surface of another interposer on another side in the length direction, and the side surface of the capacitor main body is defined as X2, and a distance between another side surface of the other interposer on the other side in the length direction, and the other side surface of the capacitor main body is defined as X3; X2>X3 and X1>X4 are satisfied. | 2022-04-07 |
20220108844 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrodes each at one of two end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers on a surface of the capacitor main body, and opposed and spaced apart from each other. The two interposers include a nickel-plated layer and a tin-plated layer on an outer periphery thereof. The two interposers each include a non-plated region without the nickel-plated layer on an end surface at which the two interposers face each other. | 2022-04-07 |
20220108845 | CAPACITOR COMPONENT - A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode. | 2022-04-07 |
20220108846 | Solid Electrolytic Capacitor Containing Polyaniline - A solid electrolytic capacitor containing a capacitor element is provided. The capacitor element contains a sintered porous anode body, a dielectric that overlies the anode body, a solid electrolyte that overlies the dielectric, and an external polymer coating that overlies the solid electrolyte and includes conductive polymer particles. The solid electrolyte includes a conductive polymer having repeating units derived from an aniline monomer having the following general formula (I): | 2022-04-07 |
20220108847 | CONVERSION OF HALIDE PEROVSKITE SURFACES TO INSOLUBLE, WIDE-BANDGAP LEAD OXYSALTS FOR ENHANCED SOLAR CELL STABILITY - Electronic devices comprising a first layer, said first layer comprising a perovskite material; and a coating layer disposed on a surface of said first layer; wherein said coating layer comprises a coating oxysalt. Also provided herein are perovskite materials comprising: a coating layer on at least a portion of a surface of said perovskite material; wherein said coating layer comprises a coating oxysalt. Further provided herein are methods for forming a coating layer on a surface of a perovskite material comprising steps of: exposing said surface to a fluid having a precursor oxysalt dissolved therein such that said coating layer forms on said surface via a chemical reaction between said perovskite material and said precursor oxysalt; wherein said coating layer comprises a coating oxysalt. | 2022-04-07 |
20220108848 | RECONFIGURABLE MICROWAVE METADEVICES - Embodiments of the present disclosure provide a metadevice including a substrate, a resonator loop coupled to the substrate. The resonator loop having a first gap in the resonator loop. The metadevice includes an organic electrochemical transistor positioned in the first gap, a gate electrode, and an electrolyte extending between the organic electrochemical transistor and the gate electrode. | 2022-04-07 |
20220108849 | OPTIMIZED CURRENT SWITCH ON POWER LINE - A current switch arranged between a first power line segment and a second power line segment, including: a first switch element, including a main contact and a secondary contact rigidly connected to the main contact, mounted so as to be mobile on the first power line segment so as to follow a separating travel between a closed position and an open position and a second switch element mounted so as to be freely mobile on the second power line segment and forced towards a rest position by elastic loading. | 2022-04-07 |
20220108850 | PRESSING DEVICE - A pressing device includes a base board, an upper board unit that is disposed over the base board, and an intermediate unit that is disposed between the base board and the upper board unit. The upper board unit includes a panel, a circuit board, and a tact switch. The intermediate unit includes a middle portion that corresponds in position to the tact switch, a surrounding frame member, and a plurality of interconnecting board members. When the upper board unit is pressed, at least one of the interconnecting board members is deformed, and the middle portion is driven to convert the tact switch from an initial state to a triggered state. | 2022-04-07 |
20220108851 | RETROFIT REMOTE CONTROL DEVICE - A control device may be configured to be mounted over a bezel portion of an electrical device and to control a lighting load. The control device may comprise a base portion having planar extensions removably attached or affixed thereto. The planar extensions may be adapted to be received in a gap between a faceplate of the electrical device and the bezel portion for holding the control device against the faceplate. The planar extensions may comprise barbs that allow for insertion of the extensions in the gap, and may bite into the faceplate to hinder removal of the control device. The planar extensions may be defined by a mounting structure that is configured to be received in the gap between the bezel portion and the faceplate. The mounting structure may protrude beyond a front surface of the faceplate. | 2022-04-07 |
20220108852 | VACUUM CIRCUIT BREAKER - Disclosed are example embodiments of a dead tank circuit breaker for protecting electrical components against electrical surges and other voltage anomalies such as transient overvoltages. The circuit breaker includes: one or more vacuum interrupters; a current bypass circuit electrically coupled to the one or more vacuum interrupters; a dead tank encasing and hermetically sealing the one or more vacuum interrupters and the current bypass circuit, wherein the dead tank is pressurized with a non-SF6 gas; and a controllable mechanism coupled to the one or more vacuum interrupters and to the current bypass circuit. The controllable mechanism is configured to actuate the one or more vacuum interrupters and the current bypass circuit to open or close a main circuit path such that any pre-strike arcing occurs on the current bypass circuit instead of the one or more vacuum interrupters. | 2022-04-07 |
20220108853 | CIRCUIT BREAKER HAVING INTERNAL TRANSIENT RECOVERY VOLTAGE CAPACITOR ASSEMBLY - A circuit breaker having at least one capacitor assembly connected in parallel across a contact of the circuit breaker. The capacitor assembly can be housed with the contact within a sealed enclosure of the circuit breaker. The enclosure can be configured to house an insulating medium that is configured to reduce or quench an arc(s) that may form at least when the contact of the circuit breaker is displaced from a closed position to an open position. The capacitor assembly, which includes a transient recovery voltage (TRV) capacitor, can be configured to delay terminal fault and short line fault TRV and the rate of rise of the initial TRV (ITRV) that can appear across the open contact of the circuit breaker. | 2022-04-07 |
20220108854 | VACUUM INTERRUPTER - A vacuum interrupter ( | 2022-04-07 |
20220108855 | VOLTAGE READINGS USING HIGH VOLTAGE RESISTOR ACROSS VACUUM INTERRUPTER - A switch assembly including a switch and a high impedance element used for energy harvesting purposes that are connected to a power line and assembly electronics. The high impedance element has higher impedance than the switch so that current flows through the switch from the power line when the switch is closed and through the high impedance element from the power line when the switch is open. The switch assembly also includes a current sensing device, such as a current sensing resistor, electrically coupled in series with the high impedance element and the electronics. By measuring the current flow using the current sensing device, it is possible to infer the voltage across the high impedance element since its impedance is known. This voltage can be used to provide point on wave closing of the switch and to determine the line voltage magnitude. | 2022-04-07 |
20220108856 | VACUUM INTERRUPTER - A vacuum interrupter includes: an insulation cylinder; a fixed-side flange; a movable-side flange; a fixed-side electrode rod fixed to the fixed-side flange at one end and having a fixed-side electrode fitting shaft on a fixed-side end surface at another end; a movable-side electrode rod connected to the movable-side flange via a bellows at one end and having a movable-side electrode fitting shaft on a movable-side end surface at another end; a fixed-side windmill-shaped electrode fixed to the fixed-side electrode fitting shaft; and a movable-side windmill-shaped electrode fixed to the movable-side electrode fitting shaft. A fixed-side support member having a fixed-side spacer portion and a fixed-side planar portion is provided between the fixed-side end surface and the fixed-side windmill-shaped electrode, and a movable-side support member having a movable-side spacer portion and a movable-side planar portion is provided between the movable-side end surface and the movable-side windmill-shaped electrode. | 2022-04-07 |
20220108857 | ELECTROMAGNETIC DEVICE - An electromagnetic device includes a spool including a cylindrical body portion in which a through hole extending to a first direction is provided, a coil wound around the body portion, an iron core disposed in a through hole of the body portion, a yoke including a first member and a second member, the first member being connected to the iron core and the second member extending from the first member along an outer peripheral surface of the coil, and a movable iron piece, which has a plate shape, including a bent portion in a middle thereof. The yoke includes at least one positioning projection provided in a middle of the free end in the second direction. The movable iron piece includes a positioning recessed portion that accommodates and positions the positioning projection, the positioning recessed portion being provided in a middle between the pair of rotation supporting points. | 2022-04-07 |
20220108858 | Relay Device and Control Method of Relay Device - A relay device includes a coil portion, a fixed contact, a moving contact and a spring. The coil portion generates an electromagnetic force that moves the moving contact toward the fixed contact through energization. The spring applies an elastic force in a direction in which the moving contact separates from the fixed contact. The drive circuit controls an electromagnetic force of the coil portion to be a first electromagnetic force, continuously for a first time, when switching the fixed contact and the moving contact in a non-contact state to a contact state, and after that, to be increased in sages on the basis of a tolerance range of the spring constant of the spring. | 2022-04-07 |
20220108859 | RELAY - First and second movable contacts are connected to a first movable contact piece. A second movable contact piece is provided separately from the first movable contact piece. Third and fourth movable contacts are connected to the second movable contact piece. A drive device moves the first movable contact piece and the second movable contact piece by moving a movable iron core by a magnetic force generated from a coil. In a state where the first to fourth movable contacts are contacts the first to fourth fixed contacts, respectively, the first movable contact piece and the second movable contact piece are electrically connected in parallel with the first fixed terminal and the second fixed terminal. | 2022-04-07 |
20220108860 | RELAY - A relay includes a first fixed terminal, a first fixed contact, a second fixed terminal, a second fixed contact, a first movable contact piece, a first movable contact, a second movable contact, an insulating member, and a drive device. The first fixed contact is connected to the first fixed terminal. The second fixed contact is connected to the second fixed terminal. The first movable contact and the second movable contact are connected to the first movable contact piece. The insulating member is connected to the first movable contact piece. The drive device includes a coil and a movable iron core. The movable iron core is connected to the insulating member. The drive device moves the movable iron core by a magnetic force generated from the coil to move the movable contact piece. The first movable contact piece and the movable iron core are electrically insulated by the insulating member. | 2022-04-07 |
20220108861 | METHOD FOR THE PRODUCTION OF A FUSE - A method of manufacturing a fuse includes stacking a base plate, an at least partially conductive fabric over the base plate and a cover layer over the fabric, each with an intervening bonding layer. At least one cavity is provided on both sides of the fabric, adjoining the fabric, between the respective edge regions. In addition, the fabric includes at least one first fiber which is electrically conductive and second fibers which are non-conductive and which have a lower melting temperature than the first fiber. The method further includes heating the stacked elements to a temperature below the melting temperature of the first fiber and above the melting temperature of the second fibers. | 2022-04-07 |
20220108862 | ELECTRON SOURCE WITH MAGNETIC SUPPRESSOR ELECTRODE - An electron source is disclosed. The electron source may include an electron emitter configured to generate one or more electron beams. The electron source may further include a magnetic suppressor electrode surrounding at least a portion of the electron emitter. The magnetic suppressor electrode may be formed from one or more magnetic materials. The magnetic suppressor may be configured to shield at least a portion of the electron emitter from an axial magnetic field. The electron source may further include an extractor electrode positioned adjacent to a tip of the electron emitter. | 2022-04-07 |
20220108863 | Method and Systems Useful for Producing Aluminum Ions - Described are ion implantation devices, systems, and methods, and in particular to an ion source that is useful for generating an aluminum ion beam. | 2022-04-07 |
20220108864 | Charged Particle Beam System - A charged particle beam system includes a charged particle source that generates a first charged particle beam and a multi beam generator that generates a plurality of charged particle beamlets from an incoming first charged particle beam. Each individual beamlet is spatially separated from other beamlets. The charged particle beam system also includes an objective lens that focuses incoming charged particle beamlets in a first plane so that a first region in which a first individual beamlet impinges in the first plane is spatially separated from a second region in which a second individual beamlet impinges in the first plane. The charged particle beam system also includes a projection system and a detector system including a plurality of individual detectors. The projection system images interaction products leaving the first region within the first plane due to impinging charged particles onto a first detector and images interaction products leaving the second region in the first plane onto a second detector. | 2022-04-07 |
20220108865 | APPARATUS OF CHARGED-PARTICLE BEAM SUCH AS ELECTRON MICROSCOPE COMPRISING CO-CONDENSERS FOR CONTINUOUS IMAGE RESOLUTION TUNING - The present invention provides an apparatus of charged-particle beam such as an electron microscope with co-condensers. A source of charged particles is configured to emit a beam of charged particles, and the co-condensers including two or more magnetic condensers are configured to coherently focus the beam to a single crossover spot. The invention exhibits numerous technical merits such as continuous image resolution tuning, and automatic switching between multiple resolutions, among others. | 2022-04-07 |
20220108866 | DEVICE DEFECT DETECTION METHOD USING A CHARGED PARTICLE BEAM - A method of detecting a defect in a device using a charged particle beam includes inputting a charged particle beam condition, a light condition, and electronic device circuit information, controlling a charged particle beam applied to a sample based on the electron beam condition, controlling light applied to the sample based on the light condition, detecting second electrons emitted from the sample by the application of the charged particle beam and the light, and generating a calculation netlist based on the electronic device circuit information, generating a light irradiation netlist based on the calculation netlist and the light condition, estimating a first irradiation result when the charged particle beam and the light are applied to the sample based on the light irradiation netlist and the charged particle beam condition, and comparing the first irradiation result with a second irradiation result when the charged particle beam and the light are actually applied to the sample based on the electron beam condition. | 2022-04-07 |
20220108867 | DIGITAL DETECTOR, APPARATUS OF CHARGED-PARTICLE BEAM SUCH AS ELECTRON MICROSCOPE COMPRISING THE SAME, AND METHOD THEREOF - The present invention provides a digital high-resolution detector for detecting X-ray, UV light or charged particles. In various embodiments, the digital detector comprises an array of CMOS or CCD pixels and a layer of conversion material on top of the array designed for converting incident X-ray, UV light or charged particles into photons for CMOS or CCD sensors to capture. The thin and high-resolution detector of the invention is particularly useful for monitoring and aligning beams in, and optimizing system performance of, an apparatus of charged-particle beam e.g. an electron microscope. | 2022-04-07 |
20220108868 | SUBSTRATE TREATING APPARATUS - Disclosed is a substrate treating apparatus. The substrate treating apparatus includes a load lock chamber, of which a pressure of an interior space is changed between a first pressure and a second pressure that is lower than the first pressure, an index chamber connected to the load lock chamber, and a measurement unit that measures a level of particles in the interior space, and the measurement unit is located outside the load lock chamber. | 2022-04-07 |
20220108869 | NOVEL STAGE DRIVING SYSTEM AND APPARATUS OR DEVICE SUCH AS APPARATUS OF CHARGED-PARTICLE BEAM COMPRISING THE SAME - The present invention provides a driving system comprising two actuators for moving a stage through two elastic connectors; and a general apparatus/device comprising such a driving system, such as a machine tool, an analytical instrument, an optical microscope, and an apparatus of charged-particle beam such as electron microscope and an electron beam lithographical apparatus. When used in an electron microscope, the stage can be used as a specimen stage or a plate having apertures for electron beam to pass through. The novel stage driving system exhibits numerous technical merits such as simpler structure, better manufacturability, improved cost-effectiveness, and higher reliability, among others. | 2022-04-07 |
20220108870 | MICROSCOPE - A microscope includes: an electronic optical column configured to emit scanning electron beams; a specimen stage configured to place a specimen; a target movably disposed between the electronic optical column and the specimen stage; and a driving mechanism for driving the target to move between a first position and a second position, wherein the first position is a position at which the electron beams act on the specimen, and the second position is a position at which the electron beams act on the target to generate X-rays irradiating the specimen. In the present disclosure, through one time mounting of the specimen, the microscope enables the dual-function detection of the specimen, i.e., detection of the specimen by an SEM and detection of the specimen by a Nano-CT. | 2022-04-07 |
20220108871 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING COIL - A plasma processing apparatus includes: a main coil disposed on or above a plasma processing chamber; and a sub-coil assembly disposed radially inside or outside the main coil. The sub-coil assembly includes a first spiral coil and a second spiral coil. Each turn of the first spiral coil and each turn of the second spiral coil are alternately arranged in a vertical direction. A first upper terminal of the first spiral coil is connected to a ground potential via one or more capacitors, and a first lower terminal of the first spiral coil is connected to the ground potential. A second upper terminal of the second spiral coil is connected to the ground potential via one or more capacitors or one or more other capacitors, and a second lower terminal of the second spiral coil is connected to the ground potential. | 2022-04-07 |
20220108872 | BEVEL BACKSIDE DEPOSITION ELIMINATION - Exemplary semiconductor processing systems may include a chamber body comprising sidewalls and a base. The systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate defining a plurality of channels through an interior of the support plate. Each channel of the plurality of channels may include a radial portion extending outward from a central channel through the support plate. Each channel may also include a vertical portion formed at an exterior region of the support plate fluidly coupling the radial portion with a support surface of the support plate. The substrate support may include a shaft coupled with the support plate. The central channel may extend through the shaft. The systems may include a fluid source coupled with the central channel of the substrate support. | 2022-04-07 |
20220108873 | GAS SUPPLY RING AND SUBSTRATE PROCESSING APPARATUS - A gas supply ring for use in a substrate processing apparatus includes an inner face, an outer face, a first face between the inner face and the outer face, and a second face between the inner face and the outer face and opposite to the first face. The outer face has at least one gas inlet and the first face has an outer groove in communication with the at least one gas inlet. The second face has first and second middle grooves in communication with the outer groove. The first face further has first to fourth inner grooves disposed medial to the outer groove. The inner face has a plurality of gas outlets and each of the gas outlets is in communication with any one of the first to fourth inner grooves. | 2022-04-07 |
20220108874 | LOW CURRENT HIGH ION ENERGY PLASMA CONTROL SYSTEM - Exemplary semiconductor processing systems may include a processing chamber, an inductively coupled plasma (ICP) source disposed in or on the processing chamber, and a support configured to position a substrate. The support can be disposed at least partially within the processing chamber and can include a bias electrode. An ion screen may be disposed within the chamber to be above a substrate on the support. The ion screen is semitransparent to ions and electrons so that the density of plasma sustained above the ion screen is unaffected by RF bias power applied to the bias electrode. Plasma energy control is therefore accomplished while maintaining independence of plasma density from RF bias power so that high ion energy and low bias current may be afforded. | 2022-04-07 |
20220108875 | MULTI-LOCATION GAS INJECTION TO IMPROVE UNIFORMITY IN RAPID ALTERNATING PROCESSES - A gas delivery system configured to provide deposition and etch gases to a processing chamber for a rapid alternating process includes a first valve arranged to provide deposition gas from a deposition gas manifold to a first zone of a gas distribution device via a first orifice and provide the deposition gas from the deposition gas manifold to a second zone of the gas distribution device via a second orifice having a diameters than the first orifice. A second valve is arranged to provide etch gas from the etch gas manifold to the first zone of the gas distribution device via a third orifice and provide the etch gas from the etch gas manifold to the second zone of the gas distribution device via a fourth orifice having a different diameter than the third orifice. | 2022-04-07 |
20220108876 | GAS SUPPLY UNIT AND SUBSTRATE PROCESSING APPARATUS INCLUDING GAS SUPPLY UNIT - A gas supply unit is disclosed. An exemplary gas supply unit includes an upper plate provided with a plurality of injection holes; and a divider plate constructed and arranged against the upper plate to guide a flow of gas from the injection holes; wherein one of the plurality of injection holes is a center injection hole and the other than said one of the plurality of injection holes are arranged concentrically around the center injection hole as outer injection holes; and wherein the divider plate is provided with a center through hole fluidly communicating with the center injection hole and is provided with a plurality of protrusions extending towards the upper plate thereby creating a plurality of zones, each of the zones fluidly communicating with one of the outer injection holes. | 2022-04-07 |
20220108877 | ELECTROSTATIC CHUCK APPARATUS AND SEMICONDUCTOR MANUFACTURING APPARATUS - According to one embodiment, an electrostatic chuck apparatus includes a substrate support plate formed of a dielectric material. The substrate support plate includes: a plurality of support bases protruding from an upper surface of the substrate support plate, a plurality of ground electrodes formed inside the substrate support plate, each of the ground electrodes at a corresponding position to a respective one the support bases, and an electrostatic chuck electrode provided below the ground electrodes. | 2022-04-07 |
20220108878 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A disclosed plasma processing method includes a direct-current power source configured to generate a negative direct-current voltage. A bias electrode of a substrate support provided in the chamber is alternately connected to the direct-current power source and the ground. A time until a potential of the bias electrode reaches a ground potential after the bias electrode is connected to the ground is set to be longer than a time until the potential of the bias electrode reaches the negative direct-current voltage after the direct-current power source is connected to the bias electrode. | 2022-04-07 |
20220108879 | SUBSTRATE SUPPORT, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE PROCESSING METHOD - A technique allows control of the etching rate at an outer periphery of a substrate being processed. A substrate support includes a substrate support portion that supports a substrate, and an edge ring support that supports an edge ring surrounding the substrate supported on the substrate support portion. The edge ring support includes a plurality of heating elements arranged in a circumferential direction of the edge ring support and a plurality of heater power feeders. Each of the plurality of heater power feeders is included in a corresponding heating element of the plurality of heating elements to provide power from an external source to the corresponding heating element. | 2022-04-07 |
20220108880 | MAGNETRON SPUTTERING APPARATUS AND MAGNETRON SPUTTERING METHOD - A magnetron sputtering apparatus is provided. The apparatus comprises: a vacuum chamber storing a substrate; a plurality of sputtering mechanisms, each including a target having one surface facing the inside of the vacuum chamber, a magnet array, and a moving mechanism for reciprocating the magnet array between a first position and a second position on the other surface of the target; a power supply for forming plasma by supplying power to targets of selected sputtering mechanisms for film formation; a gas supplier for supplying a gas for plasma formation into the vacuum chamber; and a controller for outputting a control signal, in performing the film formation, such that magnet arrays of selected and unselected sputtering mechanisms, extension lines of moving paths of the magnet arrays thereof intersecting each other in plan view, move synchronously or are located at certain positions so as to be distinct from each other. | 2022-04-07 |
20220108881 | METHOD AND SYSTEM FOR FORMING SILICON NITRIDE ON A SIDEWALL OF A FEATURE - Methods of forming silicon nitride on a sidewall of a feature are disclosed. Exemplary methods include providing a substrate comprising a feature comprising a sidewall surface and a surface adjacent the sidewall surface, forming a silicon oxide layer overlying the sidewall surface and the surface adjacent the sidewall surface, using a cyclical deposition process, depositing a silicon nitride layer overlying the silicon oxide layer, and exposing the silicon nitride layer to activated species generated from a hydrogen-containing gas. Exemplary methods can additionally include selectively removing a portion of the silicon nitride layer. Structures formed using the methods and systems for performing the methods are also disclosed. | 2022-04-07 |
20220108882 | PROCESSING METHOD OF WORKPIECE - A processing method of a workpiece with a circular disc shape includes sticking a tape to one surface of the workpiece and integrating the workpiece and a frame through the tape, holding the workpiece by a holding unit with the interposition of the tape, and irradiating the other surface of the workpiece located on the opposite side to the one surface with a pulsed laser beam having such a wavelength as to be absorbed by the workpiece from the side of the other surface. In irradiating the laser beam, the other surface is annularly irradiated with the laser beam in the state in which the orientation of the laser beam is adjusted in such a manner that the laser beam has an angle of incidence formed due to inclination with respect to a normal to the other surface of the workpiece by a predetermined angle. | 2022-04-07 |
20220108883 | METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER - A method for flattening a surface on an epitaxial lateral overgrowth (ELO) layer, resulting in obtaining a smooth surface with island-like III-nitride semiconductor layers. The island-like III-nitride semiconductor layers are formed by stopping the growth of the ELO layers before they coalesce to each other. Then, a growth restrict mask is removed before at least some III-nitride device layers are grown. Removing the mask decreases an excess gases supply to side facets of the island-like III-nitride semiconductor layers, which can help to obtain a smooth surface on the island-like III-nitride semiconductor layers. The method also avoids compensation of a p-type layer by decomposed n-type dopant from the mask, such as Silicon and Oxygen atoms. | 2022-04-07 |
20220108884 | SYSTEMS AND METHODS FOR FORMING UV-CURED LOW-K DIELECTRIC FILMS - Semiconductor processing methods are described for forming UV-treated, low-κ dielectric films. The methods may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-and-carbon-containing precursor. The methods may further include generating a deposition plasma from the deposition precursors within the substrate processing region, and depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The as-deposited silicon-and-carbon-containing material may be characterized by greater than or about 5% hydrocarbon groups. The methods may still further include exposing the deposited silicon-and-carbon-containing material to ultraviolet light. The exposed silicon-and-carbon-containing material may be characterized by less than or about 2% hydrocarbon groups. | 2022-04-07 |
20220108885 | METHODS FOR PREPARING ALN BASED TEMPLATE HAVING SI SUBSTRATE AND GAN BASED EPITAXIAL STRUCTURE HAVING SI SUBSTRATE - A method for preparing an AlN based template having a Si substrate and a method for preparing a GaN based epitaxial structure having a Si substrate are provided. The method for preparing the AlN based template having the Si substrate, which includes: providing the Si substrate; growing an AlN nucleation layer on the Si substrate; and introducing an ion passing through the AlN nucleation layer and into the Si substrate. After the AlN nucleation layer is prepared on the Si substrate, the ions are introduced into the Si substrate and the AlN nucleation layer through the AlN nucleation layer. In this way, types of the introduced ions can be expanded. In addition, a carrier concentration at an interface between the Si substrate and the AlN nucleation layer and a carrier concentration in the AlN nucleation layer can also be reduced. | 2022-04-07 |
20220108886 | METHOD OF FORMING A 2-DIMENSIONAL CHANNEL MATERIAL USING ION IMPLANTATION - A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer. | 2022-04-07 |
20220108887 | DISLOCATION FREE SEMICONDUCTOR NANOSTRUCTURES GROWN BY PULSE LASER DEPOSITION WITH NO SEEDING OR CATALYST - There is a method for forming a semiconductor nanostructure on a substrate. The method includes placing a substrate and a semiconductor material in a pulsed laser deposition chamber; selecting parameters including a fluence of a laser beam, a pressure P inside the chamber, a temperature T of the substrate, a distance d between the semiconductor material and the substrate, and a gas molecule diameter a | 2022-04-07 |
20220108888 | Selective Deposition of Germanium - Methods for selectively depositing germanium containing films are disclosed. Some embodiments of the disclosure provide deposition on a bare silicon with little to no deposition on a silicon oxide surface. Some embodiments of the disclosure provide conformal films on trench sidewalls. Some embodiments of the disclosure provide superior gap fill without seams or voids. | 2022-04-07 |
20220108889 | METHODS FOR DEPOSITING III-ALLOYS ON SUBSTRATES AND COMPOSITIONS THEREFROM - A method for depositing III-V alloys on substrates and compositions therefrom. A first layer comprises a Group III element. A second layer comprises a silica. A substrate has a surface. The second layer is deposited onto a first layer. The depositing is performed by a sol-gel method. The second layer is exposed to a precursor that comprises a Group V element. At least one of the precursor or the Group V element diffuse through the silica. The first layer is transformed into a solid layer comprising a III-V alloy, wherein at least a portion of the first layer to a liquid. The silica retains the liquified first layer, enabling at least one of the precursor or the Group V element to diffuse into the liquid, resulting in the forming of the III-V alloy. | 2022-04-07 |
20220108890 | METHOD FOR PREPARING A SUBSTRATE - Disclosed is a method for preparing a substrate relate to the field of semiconductors. The method comprises the following steps: S | 2022-04-07 |
20220108891 | MODULAR ZONE CONTROL FOR A PROCESSING CHAMBER - Exemplary semiconductor processing chambers may include a faceplate assembly characterized by at least one surface defining a number of voids. Each void is configured to receive an interchangeable thermal body that can be selected from multiple interchangeable thermal bodies. Exemplary semiconductor processing chambers may also include a gas box characterized by movable members. Each movable member is configured to engage a delivery port and is movable to provide flow control for a gas being delivered to the processing volume through a gas flow path. Zoned flow and/or temperature control may be provided by the faceplate assembly, the gas box, or both. | 2022-04-07 |
20220108892 | BORON CONCENTRATION TUNABILITY IN BORON-SILICON FILMS - Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H | 2022-04-07 |
20220108893 | TECHNIQUES TO INCREASE CMOS IMAGE SENSOR WELL DEPTH BY CRYOGENIC ION CHANNELING OF ULTRA HIGH ENERGY IONS - Provided herein are approaches for forming an image sensor with increased well depth due to cryogenic ion channeling of ultra-high energy (UHE) ions. In some embodiments, a method may include providing a wafer of a semiconductor device, the semiconductor device including a photoelectric conversion region, and cooling the wafer to a temperature less than −50° C. The method may further include performing an ion implant to the photoelectric conversion region to form a photodiode well after cooling the wafer. | 2022-04-07 |
20220108894 | METHOD FOR FORMING SEMICONDUCTOR MEMORY STRUCTURE - A method for forming a semiconductor memory structure includes sequentially forming an active layer, a hard mask layer and a core layer over a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of supporting features abutting the first and second strips. The method also includes forming a spacer layer alongside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, etching the hard mask layer using the photoresist pattern and the spacer layer to form a hard mask pattern, and transferring the hard mask pattern into the active layer to form a gate stack. | 2022-04-07 |
20220108895 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes: alternately stacking a first film and a second film on a surface of a semiconductor substrate to form a multilayer film; partially removing the multilayer film to form stacks and a depression between one of the stacks and another one of the stacks and expose an end portion of the surface; forming a first insulating film to fill the depression; forming a first protective film on the stacks, the first insulating film, and the end portion; forming a second insulating film on the first protective film, the second insulating film overlapping at least a part of the other one of the stacks and the end portion; and removing the second insulating film in a thickness direction using chemical mechanical polishing. | 2022-04-07 |
20220108896 | TESTING SEMICONDUCTOR COMPONENTS - A method of manufacturing a semiconductor package includes covering a semiconductor die and a plurality of conductive terminals coupled to the semiconductor die in a mold compound, positioning the mold compound between a first pair of electrodes and a second pair of electrodes, and moving a movable electrode of the first pair and a movable electrode of the second pair into a first clamping position. In the first clamping position, each of the first pair of electrodes and the second pair of electrodes electrically couples to a unique subset of the plurality of conductive terminals. The method also includes applying, by the first pair of electrodes, a first voltage to the semiconductor die within the mold compound; and applying, by the second pair of electrodes, a second voltage to the semiconductor die within the mold compound. The second voltage is less than the first voltage. | 2022-04-07 |
20220108897 | ETCHING DEVICE - The present invention relates to an etching device comprising: an etching chamber; an opening/closing unit for opening/closing the etching chamber; and a locking unit for selectively locking the opening/closing unit. | 2022-04-07 |
20220108898 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - Substrates can be suppressed from being separated from supporting grooves. A substrate processing apparatus includes a substrate holding unit and a processing tub. The substrate holding unit is configured to hold multiple substrates. The processing tub is configured to store a processing liquid therein. The substrate holding unit comprises a supporting body, an elevating device and a restriction unit. The supporting body has multiple supporting grooves and is configured to support the multiple substrates with a vertically standing posture from below in the multiple supporting grooves, respectively. The elevating device is configured to move the supporting body between a standby position above the processing tub and a processing position within the processing tub. The restriction unit is configured to be moved up and down along with the supporting body by the elevating device and configured to restrict an upward movement of the substrates with respect to the supporting body. | 2022-04-07 |
20220108899 | FREQUENCY AND PHASE CONTROLLED TRANSDUCERS AND SENSING - Localized heating can use a fixed-frequency planar transmission line resonators arranged along a main-line, selected by tuning an electromagnetic input signal frequency applied to the main line for depositing heat in an adjacent active substrate. More generally, adjusting input signal frequency can be used to selectively address and energize an electromagnetic-to-heat, an electromagnetic-to-vibration, or other transducer to controllably direct energy toward a desired transducer load. Resonators or other electromagnetically energized transducers can be arranged to electromagnetically interfere, such that specifying or adjusting a relative phase of applied electrical signals can be used to specify or adjust the energy directed toward a desired transducer load. Temperature sensing can characterize a material in a target region near the transducer. A cold-hot-cold temperature profile can better manage temperature and avoid overheating a dielectric material such as the active substrate material. | 2022-04-07 |
20220108900 | Heat Insulation Structure, Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Substrate Processing Method - There is provided a technique capable of shortening a temperature stabilization time in a process chamber by improving a heat insulation performance of a lower portion of the process chamber. A heat insulation structure is arranged in a vicinity of a furnace opening of a heat treatment furnace wherein a temperature gradient is formed at the vicinity of the furnace opening. The heat insulation structure includes a plurality of heat insulation plates with predetermined gaps therebetween. Each heat insulation plate includes a heat shield made of metal; and a seal made of quartz or ceramics and configured to cover a front surface and a rear surface of the heat shield. The heat shield is arranged in a vacuum cavity provided in the seal. | 2022-04-07 |
20220108901 | DETAPE APPARATUS FOR AN OPTICAL ALIGNMENT MACHINE - A detape apparatus has a support unit with a deck surface for supporting a tape carrier. The deck surface defines a support plane on which the tape carrier is supportable, and a conveyor is configured to move the tape carrier in a conveyance direction along the deck surface. During a detape process, a receiving segment of a first urging element is movable to a first detape position next to a first side of the tape carrier, while a second urging element is movable to a second detape position abutting the tape carrier on an opposite side of the tape carrier to thereby push the tape carrier out of the support plane to separate at least one electronic component from the tape carrier. The receiving segment may then receive the at least one electric component which is thus separated from the tape carrier. | 2022-04-07 |
20220108902 | AUTO-CALIBRATION TO A STATION OF A PROCESS MODULE THAT SPINS A WAFER - A method for calibration including determining a temperature induced offset in a pedestal of a process module under a temperature condition for a process. The method includes delivering a wafer to the pedestal of the process module by a robot, and detecting an entry offset. The method includes rotating the wafer over the pedestal by an angle. The method includes removing the wafer from the pedestal by the robot and measuring an exit offset. The method includes determining a magnitude and direction of the temperature induced offset using the entry offset and exit offset. | 2022-04-07 |
20220108903 | PROCESSING APPARATUS - A processing apparatus includes a wafer unloading unit, a wafer table, a frame unloading unit, a frame table, a tape affixing unit, a tape-affixed frame transporting unit, a tape compression-bonding unit, a frame unit unloading unit that unloads a frame unit in which a tape of a tape-affixed frame and the undersurface of a wafer are compression-bonded to each other from the wafer table, a reinforcing portion removing unit, a no-ring unit unloading unit, and a frame cassette table. | 2022-04-07 |
20220108904 | SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor manufacturing apparatus includes a substrate storage unit configured to store a semiconductor wafer W, a substrate processing unit including a rotation holding unit configured to rotate the semiconductor wafer W while holding the semiconductor wafer W, and a coating liquid supply unit configured to supply a coating liquid onto the semiconductor wafer W, a substrate transfer unit including a transfer arm configured to take out the semiconductor wafer W and transfer the semiconductor water W to the rotation holding unit, and a moving mechanism configured to move the transfer arm, and a position detection unit configured to detect the position of the transfer arm. The moving mechanism moves the transfer arm onto the rotation holding unit while correcting the position of the transfer arm based on the position detection result of the transfer arm by the position detection unit. | 2022-04-07 |
20220108905 | OVERHEAD TRANSPORT VEHICLE AND METHOD FOR CALCULATING ROTATION AMOUNT OF WINDING DRUM IN OVERHEAD TRANSPORT VEHICLE - An overhead transport vehicle includes a lift stage to transfer an article, a winding drum to overlap and wind a suspension attached to the lift stage, and a controller to control a rotation amount of the winding drum to control a lifting/lowering amount of the lift stage. The controller is configured or programmed to execute a first processing including calculating, as individual values of the overhead transport vehicle, an individual value of an entire length of the suspension, an individual value of a diameter of the winding drum, and an individual value of a thickness of the suspension, and a second processing including calculating a rotation amount of the winding drum with respect to a lifting/lowering amount of the lift stage based on the individual value of the entire length of the suspension, the individual value of the diameter of the winding drum, and the individual value of the thickness of the suspension calculated in the first processing. | 2022-04-07 |
20220108906 | OVERHEAD HOIST TRANSPORT SYSTEM - An overhead hoist transport system includes a vehicle, a wafer box and a controller. The vehicle includes a combiner. The combiner includes at least one magnetic module. The magnetic module is fixed to a base plate. The magnetic module is downwardly protruded. The wafer box includes a header. The header includes a combining member configured to correspond to the magnetic module. The controller is configured to generate a control signal for controlling attachment and detachment operations between the combiner and the wafer box. The magnetic module includes a frame, a first permanent magnet, a second permanent magnet and a magnetic switch. The frame has an annular cross-sectional shape. The first permanent magnet is fixed to the frame. The second permanent magnet is rotatably arranged in the frame. The magnetic switch is configured to rotate the second magnet in response to the control signal. | 2022-04-07 |
20220108907 | SEMICONDUCTOR SUBSTRATE SUPPORT LEVELING APPARATUS - Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The chamber body may define an interior volume. The systems may include a substrate support extending through the base of the chamber body. The substrate support may be configured to support a substrate within the interior volume. The systems may include a faceplate positioned within the interior volume of the chamber body. The faceplate may define a plurality of apertures through the faceplate. The systems may include a leveling apparatus seated on the substrate support. The leveling apparatus may include a plurality of piezoelectric pressure sensors. | 2022-04-07 |
20220108908 | SHADOW RING KIT FOR PLASMA ETCH WAFER SINGULATION PROCESS - Shadow ring kits and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber, the electrostatic chuck including a conductive pedestal to support a substrate carrier sized to support a wafer having a first diameter. A shadow ring assembly is between the plasma source and the electrostatic chuck, the shadow ring assembly sized to process a wafer having a second diameter smaller than the first diameter. | 2022-04-07 |
20220108909 | MEMBER FOR SEMICONDUTOR MANUFACTURING APPARATUS - A member for semiconductor manufacturing apparatus has a structure in which a hollow ceramic shaft is provided on a back surface of a ceramic plate having a front surface serving as a wafer placement surface. The member for semiconductor manufacturing apparatus includes an RF electrode embedded in the ceramic plate, an RF connector disposed outside of the hollow interior of the ceramic shaft, and an RF link member provided between the RF connector and the RF electrode. The RF link member has a branching portion consisting of a plurality of RF rods, and the branching portion extends to the outside of the ceramic shaft. | 2022-04-07 |
20220108910 | HOLDING MECHANISM - A holding mechanism includes a wafer holding section that holds a wafer under suction, and a frame support section that is disposed on the outer circumference of the wafer holding section and that supports a frame. The frame support section includes a permanent magnet. | 2022-04-07 |
20220108911 | INDUSTRIAL ROBOT - A first sensor is disposed in such a way that optical axes of a light emitting element and a light receiving element thereof are parallel to a left-right direction. A second sensor is disposed in such a way that optical axes of a light emitting element and a light receiving element thereof are parallel to a front-rear direction. When a position of a wafer to be loaded on a loading portion is taught, a position of the loading portion or a teaching jig to be loaded on the loading portion in the front-rear direction is detected by the first sensor by moving a hand in the front-rear direction by a moving mechanism, and a position of the loading portion or the teaching jig in the left-right direction is detected by the second sensor by moving the hand in the left-right direction by the moving mechanism. | 2022-04-07 |
20220108912 | CARRIER RING DESIGNS FOR CONTROLLING DEPOSITION ON WAFER BEVEL/EDGE - Various carrier ring designs and configurations to control an amount of deposition at a wafer's front side and bevel edge are provided. The carrier ring designs can control the amount of deposition at various locations of the wafer while deposition is performed on the wafer's back side, with no deposition desired on the front side of the wafer. These locations include front side, edge, and back side of bevel; and front and back side of the wafer. Edge profiles of the carrier rings are designed to control flow of process gases, flow of front side purge gas, and plasma effects. In some designs, through holes are added to the carrier rings to control gas flows. The edge profiles and added features can reduce or eliminate deposition at the wafer's front side and bevel edge. | 2022-04-07 |
20220108913 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - There is provided a method of processing a substrate using a substrate processing apparatus including: a processing container configured to process the substrate therein; a plasma generation space formed inside the processing container; a processing space in communication with the plasma generation space via a partition plate; a stage provided inside the processing space and configured to place the substrate on a top surface of the stage; and a lifting mechanism configured to raise and lower the substrate on the stage, the method including, during a plasma processing on the substrate in the processing space, raising and lowering the substrate using the lifting mechanism to cause a potential change in the substrate during the plasma processing. | 2022-04-07 |
20220108914 | Treatment methods for titanium nitride films - Embodiments herein are directed to methods of forming titanium nitride films suitable for use as a bulk fill material for conductive features in a semiconductor device, such as for capacitor electrodes and/or buried word lines in a dynamic random-access memory (DRAM) device. In one embodiment, a method of forming conductive features in a semiconductor device is provided. The method includes thermally treating a substrate surface comprising at least portions of a titanium nitride layer in the presence of hydrogen radicals. Thermally treating the substrate includes positioning the substrate in a processing volume of a processing chamber, heating the substrate to a treatment temperature of more than about 250° C., generating the hydrogen radicals using a remote plasma source fluidly coupled to the processing volume, and maintaining the substrate at the treatment temperature while concurrently exposing the at least portions of the titanium nitride layer to the generated hydrogen radicals. Here, the substrate includes a field surface having a plurality of openings formed therein and the at least portions of the titanium nitride layer are disposed in the plurality of openings. | 2022-04-07 |
20220108915 | DEPOSITION METHOD AND AN APPARATUS FOR DEPOSITING A SILICON-CONTAINING MATERIAL - The current disclosure relates to methods of depositing silicon-containing material on a substrate comprising a gap, wherein the method comprises providing the substrate in a reaction chamber and depositing a carbon-containing inhibition layer on the substrate, and depositing silicon-containing material on the substrate. Depositing the inhibition layer comprises supplying a carbon precursor comprising carbon in the reaction chamber and supplying first plasma in the reaction chamber to form a first reactive species from the carbon precursor for forming the inhibition layer on the substrate. The inhibition layer is deposited preferentially in the vicinity of the top of the gap. The disclosure further relates to methods of forming a structure, methods of manufacturing a device and to a semiconductor processing apparatus. | 2022-04-07 |
20220108916 | METHODS AND APPARATUS FOR SEAM REDUCTION OR ELIMINATION - A method of forming a contact structure in a semiconductor device having a feature includes forming a barrier layer in the feature, wherein the barrier layer is TiN; and forming a metal layer in the feature and over the barrier layer, wherein the metal layer is at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo). | 2022-04-07 |
20220108917 | LOW RESISTANCE AND HIGH RELIABILITY METALLIZATION MODULE - Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces. | 2022-04-07 |
20220108918 | DRY ETCH BACK SUBSTRATE INTERCONNECTIONS - A method of forming electrical interconnections comprises patterning a trace on a dielectric layer and then masking the dielectric layer for plating. The dielectric layer is plated to form electrical interconnections. After plating the masking is removed. A laser etch back of the trace is performed after removing the masking, in which the laser etch back removes tails on the trace. After the laser etch back, the patterned traces and the dielectric layer are cleaned. | 2022-04-07 |
20220108919 | METHOD AND STRUCTURE FOR BARRIER-LESS PLUG - A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal. | 2022-04-07 |
20220108920 | INTEGRATED CIRCUIT DEVICES INCLUDING ENLARGED VIA AND FULLY ALIGNED METAL WIRE AND METHODS OF FORMING THE SAME - Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate. | 2022-04-07 |
20220108921 | SELF-ALIGNED SUPERVIA AND METAL DIRECT ETCHING PROCESS TO MANUFACTURE SELF-ALIGNED SUPERVIA - A semiconductor device structure includes: at least one inter-metal layer stacked in a vertical direction; and a 1 | 2022-04-07 |
20220108922 | FULLY ALIGNED TOP VIAS - A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer. | 2022-04-07 |
20220108923 | Partial Self-Aligned Contact for MOL - Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided. | 2022-04-07 |
20220108924 | SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor substrate and a method of manufacturing the same are provided. The method includes epitaxially growing a buffer layer and a silicon carbide layer on a silicon surface of an N-type silicon carbide substrate, and the silicon carbide layer is high-resistivity silicon carbide or N-type silicon carbide (N—SiC). Next, a gallium nitride epitaxial layer is epitaxially grown on the silicon carbide layer to obtain a semiconductor structure composed of the buffer layer, the silicon carbide layer, and the gallium nitride epitaxial layer. After the epitaxial growth of the gallium nitride epitaxial layer, a laser is used to form a damaged layer in the semiconductor structure, and a chip carrier is bonded to the surface of the gallium nitride epitaxial layer, and then the N-type silicon carbide and the semiconductor structure are separated at the location of the damaged layer. | 2022-04-07 |
20220108925 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - A semiconductor structure is provided. The semiconductor structure includes: a base substrate having an opening; and a first gate layer formed in the opening. In the first gate layer closes a top of the opening and the first gate layer includes at least one void. The semiconductor structure further includes a second gate layer formed on the first gate layer. An atomic radius of the material of the second gate layer is smaller than gaps among atoms of the material of the first gate layer and the void is filled by atoms of one of the material of the first gate layer and the material of the second gate layer. | 2022-04-07 |
20220108926 | System and Method for Die Crack Detection in a CMOS Bonded Array - A system and method for die crack detection in a CMOS bonded array includes a capacitor that is formed in an edge seal, where one of the capacitor plates is in the edge seal portion of a first wafer, and the other capacitor plate is in the edge seal portion of a second wafer. A crack in the die can be detected by applying an alternating current waveform to a testing contact on the integrated circuit and monitoring for a shift in the alternating current waveform, as a crack would cause modulation in the capacitance. | 2022-04-07 |
20220108927 | WAFER REGISTRATION AND OVERLAY MEASUREMENT SYSTEMS AND RELATED METHODS - A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed. | 2022-04-07 |
20220108928 | ELECTRONIC COMPONENT MEASURING EQUIPMENT, ELECTRONIC COMPONENT MEASURING METHOD, AND LED MANUFACTURING METHOD - An electronic component measuring equipment includes a first mounting platform, a second mounting platform, an actuating device, a current output module, a switching device and an optical measuring component. Multiple probe pairs are disposed on a probe substrate mounted on the first mounting platform. Multiple under-test electronic components are disposed on a testing substrate mounted on the second mounting platform. The actuating device is configured to make at least partial of the probe pairs on the probe substrate in contact with at least partial of under-test electronic components. The current output module provides a constant current to the probe substrate, and conducting loops are formed between the probe pairs and the under-test electronic components in contact therewith. The switching device switches the constant current to each probe pairs. The optical measuring component measures light signals generated by the under-test electronic components. | 2022-04-07 |
20220108929 | SEMICONDUCTOR STRUCTURE - The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The plurality of unit cells are disposed in the test edge area, and the dummy area is free of the unit cells. A dimension of the test edge area in a top view is different from a dimension of the edge area in the top view. | 2022-04-07 |
20220108930 | ELECTRONIC COMPONENT WITH METALLIC CAP - This disclosure describes an electronic component comprising a package with a top side and a bottom side and at least one electronic chip housed within an enclosure inside the package. The package comprises a package base on its top side and a metallic cap on its bottom side. At least one electronic chip is separated from the metallic cap by a gap and the metallic cap is attached to the package base to form an enclosure. | 2022-04-07 |
20220108931 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a lead frame assembly in which a first side wall portion and a second side wall portion, both made of a resin, are joined to each other in a state of having a metal lead frame sandwiched therebetween; applying a sintering metal paste to a disposition region of the lead frame assembly and disposing the lead frame assembly on the sintering metal paste; and sintering the sintering metal paste between a metal base of the semiconductor device and the lead frame assembly to join the base and the lead frame assembly to each other. | 2022-04-07 |
20220108932 | SEMICONDUCTOR PACKAGE STRUCTURE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure, an electronic device, and method for manufacturing the same are provided. The semiconductor package structure includes a wiring structure, a first electronic device, a second electronic device, and a protection material. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The second electronic device defines a plurality of recesses on a first lateral side surface thereof. The protection material is disposed on the wiring structure and encapsulates the recesses of the second electronic device. | 2022-04-07 |
20220108933 | Display Device - The present disclosure relates to display devices, and more specifically, a display device including a display panel including an active area and a non-active area surrounding the active area and including a pad area, a driving integrated circuit disposed in the pad area, a stiffener disposed between the driving integrated circuit and the active area, spaced apart from the driving integrated circuit, and disposed to surround a portion of a lateral surface of the driving integrated circuit, and a color-changing layer having a color, disposed to surround a portion, or all, of the lateral surface of the driving integrated circuit, and overlapping with at least a portion of an upper surface of the stiffener. As the display device includes the color-changing layer, even without separate measurement equipment, quality and a process condition or situation of the display device can be easily checked or identified. | 2022-04-07 |
20220108934 | PACKAGE STRUCTURE - A package structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive lead, and a molding compound. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive lead contacts at least one of the second circuit layer and the third circuit layer. The conductive lead has a vertical height, and the vertical height is greater than a vertical distance between the second circuit layer and the third circuit layer. The molding compound covers the first circuit board, the second circuit board, the electronic component, and the conductive lead. The molding compound exposes the first circuit layer and the fourth circuit layer, and the conductive lead extends outside the molding compound. | 2022-04-07 |
20220108935 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate including a wiring pattern, an interposer substrate including lower and upper redistribution patterns, a semiconductor structure, a heat dissipation structure, a plurality of external connection bumps disposed on a lower surface of the base substrate, a plurality of lower connection bumps disposed between the base substrate and the interposer substrate, and a plurality of upper connection bumps disposed between the interposer substrate and the semiconductor structure. | 2022-04-07 |
20220108936 | SEMICONDUCTOR MODULE - In a semiconductor module, a first conductive portion is raised on a lower surface of a first member to which a second member including a semiconductor element and being smaller than the first member in plan view is joined. A second conductive portion is raised at the second member in the same direction as the first conductive portion. The first and second members are mounted on a module substrate with the interposed first and second conductive portions. A sealing material is disposed on a mounting surface of the module substrate, while covering at least an area of the first member. The sealing material has a top surface facing in the same direction as the top surface of the first member and side surfaces connected to its top surface. A metal film is disposed on the top and side surfaces of the sealing material and side surfaces of the module substrate. | 2022-04-07 |
20220108937 | POWER DEVICE EMBEDDED DRIVER BOARD ASSEMBLIES WITH COOLING STRUCTURES AND METHODS THEREOF - A driver board assembly includes first and second substrates, one or more power device assemblies and a cooling manifold. At least one jet impingement assembly is formed on a first surface of the first substrate and includes an impingement receiving portion that is at least partially circumferentially surrounded by a plurality of fluid microchannels that extend radially from the impingement receiving portion along the first surface. The second substrate is bonded onto the first substrate. The second substrate surface has a recess. The plurality of receiving contours are etched within the first surface of the first substrate. The one or more power device assemblies are bonded into the recess of the second substrate. A first cooling surface of the cooling manifold is bonded to the first surface such that the first cooling surface bonds within the plurality of receiving contours within the first surface of the first substrate. | 2022-04-07 |