14th week of 2016 patent applcation highlights part 41 |
Patent application number | Title | Published |
20160099287 | MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a magnetoresistive memory device, includes a metal buffer layer provided on a substrate, a crystalline metal nitride buffer layer provided on the metal buffer layer, and a magnetoresistive element provided on the metal nitride buffer layer. The metal nitride buffer layer and the metal buffer layer contain a same material. | 2016-04-07 |
20160099288 | MAGNETIC MEMORY AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a magnetic memory includes a first magnetic layer, a second magnetic layer, a non-magnetic intermediate layer provided between the first magnetic layer and the second magnetic layer and an underlying layer provided on an opposite side of the first magnetic layer with respect to the intermediate layer, and the underlying layer contains AlN of a hcp structure. | 2016-04-07 |
20160099289 | SEMICONDUCTOR MEMORY DEVICE - A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position. | 2016-04-07 |
20160099290 | MEMORY DEVICE - According to one embodiment, a memory device includes a first gate electrode, a second gate electrode, a third gate electrode, a first active area and a second active area on a substrate. The first to the third gate electrodes extend in a first direction. The first active area and the second active area extend in a second direction. The first direction and the second direction cross each other. The memory device includes a first contact, a second contact, a third contact, a fourth contact, variable resistance layer, a first interconnection layer, a second interconnection layer and the second interconnection layer. The variable resistance layer and the first interconnection layer extend in the first direction. The second interconnection layer and the third interconnection layer extend in the second direction. | 2016-04-07 |
20160099291 | METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF - Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area. | 2016-04-07 |
20160099292 | RESISTANCE-CHANGE SEMICONDUCTOR MEMORY - According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor. A second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction. The other end of the resistive memory element is connected to one of the first and second bit lines which is apart from the second source/drain region. The second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared. | 2016-04-07 |
20160099293 | Organic Light Emitting Diode Display Device - Disclosed is an organic light emitting diode (OLED) display device for preventing a dark spot (dead pixel). The OLED display device includes a white OLED disposed in each of a plurality of pixels, a driving circuit unit disposed in each of the plurality of pixels, a first color filter disposed between the white OLED and the driving circuit unit, and a second color filter or a third color filter configured to overlap the first color filter between the white OLED and the driving circuit unit. | 2016-04-07 |
20160099294 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device includes a substrate having a first width in a first direction and a second width in a second direction, the second width being perpendicular to and smaller than the first width, and pixel regions on the substrate, each of the pixel regions including a first light emitting portion, a second light emitting portion, a third light emitting portion, and a transmission portion arranged along the second direction, each of the first to third light emitting portions extending in the first direction. | 2016-04-07 |
20160099295 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a plurality of first sub-pixels arranged adjacent to each other along a first direction, each of the first sub-pixels includes a first emission region configured to emit light of a first color and a first transmission region configured to transmit external light, the first emission regions of at least two of the first sub-pixels are adjacent to each other; and a plurality of second sub-pixels arranged adjacent to each other along the first direction and adjacent to corresponding ones of the plurality of first sub-pixels along a second direction crossing the first direction, each of the plurality of second sub-pixels includes a second emission region configured to emit light of a second color and a second transmission region configured to transmit external light, the second emission regions of at least two of the sub-pixels are adjacent to each other. | 2016-04-07 |
20160099296 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus includes a substrate; a plurality of pixels provided on a first surface of the substrate and each comprising a first area configured to emit light and a second area configured to have external light transmit therethrough; a pixel circuit unit provided in the first area of each of the plurality of pixels and comprising at least one thin-film transistor (TFT); a first electrode provided in the first area of each of the plurality of pixels and electrically connected to the pixel circuit unit; a second electrode facing the plurality of first electrodes, electrically connected throughout the plurality of pixels, and provided in at least in the first area of each of the plurality of pixels; an intermediate layer disposed between the first electrode and the second electrode and comprising an organic emission layer; and an inorganic insulating film provided in the second area of each of the plurality of pixels, and comprising a plurality of layers having different refractive indices, wherein at least one of the plurality of layers has a moth eye structure. | 2016-04-07 |
20160099297 | FLEXIBLE ACTIVE MATRIX DISPLAY - High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer. | 2016-04-07 |
20160099298 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus includes a thin film transistor including an active layer, gate, source and drain electrodes, a first insulating layer disposed between the active layer and the gate electrode, and a second insulating layer disposed between the gate electrode and the source and drain electrodes; a pad electrode including a first pad layer disposed on the same layer as the source and drain electrodes and a second pad layer disposed on the first pad layer; a third insulating layer covering the source electrode and the drain electrode and an end portion of the pad electrode; a pixel electrode including a semi-transmissive metal layer and disposed in an opening formed in the third insulating layer; and a fourth insulating layer having an opening formed in a location corresponding to an opening formed in the third insulating layer and covering the end portion of the pixel electrode. | 2016-04-07 |
20160099299 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate comprising a major surface; a display region and a peripheral region surrounding the display region when viewed in a viewing direction perpendicular to the major surface; an array of a plurality of pixels disposed in the display region; and a first power line extending from the peripheral region into the display region, the first power line being electrically connected to the array of pixels at a contact point in the display region. When viewed in the viewing direction, the first power line includes: a first extension extending from the peripheral region to the display region; and a second extension connected to the first extension; and a third extension connected to the second extension and extending from a location in the display region toward the peripheral region. | 2016-04-07 |
20160099300 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DIODE DISPLAY INCLUDING THE SAME - A thin film transistor (TFT) array substrate and organic light-emitting diode (OLED) display including the same are disclosed. In one aspect, the array substrate includes a substrate, a driving TFT formed over the substrate and including a driving gate electrode, and a storage capacitor including a first electrode electrically connected to the driving gate electrode and a second electrode formed over and insulated from the first electrode. The array substrate also includes an interlayer insulating film at least partially covering the first electrode and a driving voltage line formed over the interlayer insulating film and configured to supply a voltage to the driving TFT. The driving voltage line is formed on the same layer as the second electrode. | 2016-04-07 |
20160099301 | Structure of integrated inductor - This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure. | 2016-04-07 |
20160099302 | EMBEDDED METAL-INSULATOR-METAL CAPACITOR - A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure. | 2016-04-07 |
20160099303 | Doped Electrode for DRAM Capacitor Stack - In some embodiments, a metal oxide second electrode material is formed as part of a MIM DRAM capacitor stack. The second electrode material is doped with one or more dopants. The dopants may influence the crystallinity, resistivity, and/or work function of the second electrode material. The dopants may be uniformly distributed throughout the second electrode material or may be distributed with a gradient in their concentration profile. | 2016-04-07 |
20160099304 | MoNx as a Top Electrode for TiOx Based DRAM Applications - A capacitor stack includes a base bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. A molybdenum nitride or a molybdenum oxy-nitride layer is formed above the dielectric layer. A fourth top electrode layer is formed above the third top electrode layer. The base top electrode layer includes a conductive metal nitride material. | 2016-04-07 |
20160099305 | Integrated Circuitry and Methods of Forming Transistors - Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped. | 2016-04-07 |
20160099306 | MONOLITHIC MERGED PIN SCHOTTKY DIODE STRUCTURE - A monolithic merged PIN Schottky (MPS) diode including a chip, at least one PIN diode, at least one Schottky diode and a termination structure is provided. The chip has a first active area, a second active area and a termination area. The PIN diode is disposed in the first active area. The Schottky diode is disposed in the second active area. The termination structure is disposed in the termination area. The first active area and the second active area are separated by the termination area. The PIN diode and the Schottky diode share the termination structure. | 2016-04-07 |
20160099307 | TERMINATION DESIGN BY METAL STRAPPING GUARD RING TRENCHES SHORTED TO A BODY REGION TO SHRINK TERMINATION AREA - This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches extending vertically through a body region of a second conductivity type near a top surface of the semiconductor substrate and further extending through a surface shield region of the first conductivity type. A dopant region of the second conductivity type disposed below the surface shield region extending across and surrounding a trench bottom portion of the trenches. At least a metal connector disposed above the top surface of the semiconductor substrates electrically connecting to the shield electrode of at least two trenches and shorted to the body region. | 2016-04-07 |
20160099308 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. | 2016-04-07 |
20160099309 | Method for Growing III-V Epitaxial Layers - Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device. | 2016-04-07 |
20160099310 | SEMICONDUCTOR DEVICE INTEGRATING HIGH AND LOW VOLTAGE DEVICES - The present invention is directed to a method for forming multiple active components, such as bipolar transistors. MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance. | 2016-04-07 |
20160099311 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage. | 2016-04-07 |
20160099312 | NANOWIRE FABRICATION METHOD AND STRUCTURE THEREOF - A method of providing an out-of-plane semiconductor structure and a structure fabricated thereby is disclosed. The method comprises acts of: providing a substrate defining a major surface; providing a template layer having a predetermined template thickness on the major surface of the substrate; forming a recess in the template layer having a recess pattern and a recess depth smaller than the template thickness; and epitaxilally growing a semiconductor structure from the recess. A planar shape of the recess pattern formed in the template layer substantially dictates an extending direction of the semiconductor structure. | 2016-04-07 |
20160099313 | SEMICONDUCTOR STRUCTURE FOR A TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a confronting pair of wall parts. One of the wall parts is more arcuate than the other of the wall parts. A method for fabricating the semiconductor structure is also disclosed. | 2016-04-07 |
20160099314 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value. | 2016-04-07 |
20160099315 | NANOTUBE SEMICONDUCTOR DEVICES - Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation. | 2016-04-07 |
20160099316 | Semiconductor Device and Manufacturing Method Thereof - In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n | 2016-04-07 |
20160099317 | VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS - A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins. | 2016-04-07 |
20160099318 | STRUCTURE AND METHOD FOR TRANSIENT VOLTAGE SUPPRESSION DEVICES WITH A TWO-REGION BASE - A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer. | 2016-04-07 |
20160099319 | SEMICONDUCTOR WAFER INCLUDING A MONOCRYSTALLINE SEMICONDUCTOR LAYER SPACED APART FROM A POLY TEMPLATE LAYER - A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate. | 2016-04-07 |
20160099320 | SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film. | 2016-04-07 |
20160099321 | SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH STOP LAYERS - A semiconductor device includes a silicide contact region positioned at least partially in a semiconductor layer, an etch stop layer positioned above the semiconductor layer, and a dielectric layer positioned above the etch stop layer. A contact structure that includes a conductive contact material extends through at least a portion of the dielectric layer and through an entirety of the etch stop layer to the silicide contact region, and a silicide protection layer is positioned between sidewalls of the etch stop layer and sidewalls of the contact structure. | 2016-04-07 |
20160099322 | SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS - Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack. | 2016-04-07 |
20160099323 | SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION OF SAME - Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods. | 2016-04-07 |
20160099324 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE STACK - A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate. | 2016-04-07 |
20160099325 | DUAL OXIDE TRENCH GATE POWER MOSFET USING OXIDE FILLED TRENCH - A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness greater than the first thickness. | 2016-04-07 |
20160099326 | METHOD FOR MAKING AN INTEGRATED CIRCUIT - A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity. | 2016-04-07 |
20160099327 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel is capable of increasing an aperture ratio and decreasing parasitic capacitance between a gate electrode and a drain electrode by reducing an area of a thin film transistor. The thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer on the gate line; a semiconductive island on the gate insulating layer; a circular drain electrode on the semiconductive island; and a source electrode disposed on the semiconductive island and shaped like a circular band bent in a direction from which the drain electrode is disposed. The gate electrode may include a circular portion that is overlapped by the drain electrode and a circular sector portion that is overlapped by the source electrode. | 2016-04-07 |
20160099328 | METHOD OF FORMING NANOWIRES - According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second nanowire over the substrate and substantially symmetric with the first nanowire. | 2016-04-07 |
20160099329 | SUSPENDED BODY FIELD EFFECT TRANSISTOR - A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor. | 2016-04-07 |
20160099330 | SEMICONDUCTOR DEVICE WITH NANOWIRES IN DIFFERENT REGIONS AT DIFFERENT HEIGHTS - A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses. | 2016-04-07 |
20160099331 | Self-Aligned Dual-Metal Silicide and Germanide Formation - A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy. | 2016-04-07 |
20160099332 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 2016-04-07 |
20160099333 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION - An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor. | 2016-04-07 |
20160099334 | BIPOLAR TRANSISTOR MANUFACTURING METHOD - A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench. | 2016-04-07 |
20160099335 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts. | 2016-04-07 |
20160099336 | OPC ENLARGED DUMMY ELECTRODE TO ELIMINATE SKI SLOPE AT ESIGE - Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width. | 2016-04-07 |
20160099337 | GATE STRUCTURE HAVING DESIGNED PROFILE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate. The semiconductor structure further includes spacers formed on the curved sidewalls of the metal gate structure. In addition, each curved sidewall of the metal gate structure has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall of the metal gate structure is smaller than 180° C. | 2016-04-07 |
20160099338 | STACKED PLANAR DOUBLE-GATE LAMELLAR FIELD-EFFECT TRANSISTOR - A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness. | 2016-04-07 |
20160099339 | NOVEL EMBEDDED SHAPE SIGE FOR STRAINED CHANNEL TRANSISTORS - An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors. | 2016-04-07 |
20160099340 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME - A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer. The substrate has a first insulating structure disposed therein. The gate structure is disposed on the substrate and comprises a first portion covering a portion of the first insulating structure. The drain region and the source region are disposed in the substrate at two respective sides of the gate, and comprise a first conductivity type. The base region encompasses the source region, wherein the base region comprises a second conductivity type complementary to the first conductivity type. The gate dielectric layer is between the gate and the drain region, the base region and the substrate. The gate structure further comprises a second portion penetrating into the base region. A method of forming the HVMOS is further provided. | 2016-04-07 |
20160099341 | HIGH BREAKDOWN VOLTAGE LDMOS DEVICE - A multi-region ( | 2016-04-07 |
20160099342 | STRUCTURE AND METHOD TO INCREASE CONTACT AREA IN UNMERGED EPI INTEGRATION FOR CMOS FINFETS - Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type FinFETs and p-type FinFETs. Each of first source/drain contact structures for the n-type FinFETs includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type FinFETs includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion. | 2016-04-07 |
20160099343 | TUNNELING FIELD EFFECT TRANSISTOR AND METHODS OF MAKING SUCH A TRANSISTOR - One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region. | 2016-04-07 |
20160099344 | FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS - Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges. | 2016-04-07 |
20160099345 | High Electron Mobility Transistor with Periodically Carbon Doped Gallium Nitride - A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride. | 2016-04-07 |
20160099346 | SEMICONDUCTOR DEVICE - A semiconductor device including a gate structure, a source region, a drain region, a first conductive type epitaxial layer, a high voltage second conductive type well, a linear graded high voltage first conductive type well and a first conductive type buried layer is provided. The first conductive type buried layer is located within the first conductive type epitaxial layer and below the high voltage second conductive type well, and a length of the first conductive type buried layer is smaller than a length of the high voltage second conductive type well. | 2016-04-07 |
20160099347 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S | 2016-04-07 |
20160099348 | HIGH VOLTAGE DOUBLE-DIFFUSED MOS (DMOS) DEVICE AND METHOD OF MANUFACTURE - A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell. | 2016-04-07 |
20160099349 | SEMICONDUCTOR DEVICE WITH NON-ISOLATED POWER TRANSISTOR WITH INTEGRATED DIODE PROTECTION - A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices. | 2016-04-07 |
20160099350 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the bottom of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the top of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode. | 2016-04-07 |
20160099351 | SELF-ALIGNED SLOTTED ACCUMULATION-MODE FIELD EFFECT TRANSISTOR (ACCUFET) STRUCTURE AND METHOD - This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt. | 2016-04-07 |
20160099352 | FETS AND METHODS OF FORMING FETS - An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial portion. The isolation regions are on opposing sides of the fin, and at least the first epitaxial portion of the fin protrudes from between the isolation regions. The dielectric region directly underlies the first epitaxial portion. A material of the dielectric region is different from a material of the isolation regions. The gate structure is along sidewalls and is over an upper surface of the fin. The gate structure defines a channel region in the first epitaxial portion. | 2016-04-07 |
20160099353 | SEMICONDUCTOR DEVICE - A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is provided. The semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film including c-axis aligned crystal parts, and an oxide film including c-axis aligned crystal parts. In the semiconductor device, the first oxide semiconductor film, the second oxide semiconductor film, and the oxide film are each formed using a IGZO film, where the second oxide semiconductor film has a higher indium content than the first oxide semiconductor film, the first oxide semiconductor film has a higher indium content than the oxide film, the oxide film has a higher gallium content than the first oxide semiconductor film, and the first oxide semiconductor film has a higher gallium content than the second oxide semiconductor film. | 2016-04-07 |
20160099354 | Recessed Transistors Containing Ferroelectric Material - Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another. | 2016-04-07 |
20160099355 | NON-VOLATILE MEMORY DEVICES WITH THIN-FILM AND MONO-CRYSTALLINE SILICON TRANSISTORS - A non-volatile memory device combines thin-film transistor-based memory cells with bulk mono-crystalline silicon transistors, which can more efficiently drive bit lines for fast sensing of the stored data in the thin-film memory cells. | 2016-04-07 |
20160099356 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A multi-gate structure is used and a width (d | 2016-04-07 |
20160099357 | THIN FILM TRANSISTOR - Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%. | 2016-04-07 |
20160099358 | Method of Manufacturing Semiconductor Device - A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired. | 2016-04-07 |
20160099359 | SOLAR PANEL AND METHOD FOR MANUFACTURING SUCH A SOLAR PANEL - A solar panel is provided with a stack including at least one back contacted solar cell and a back-sheet layer. The back-sheet layer has a patterned conductive layer of a first material. The conductive layer is arranged with contacting areas each located at a location corresponding to a location of an electrical contact on the solar cell. The solar cell is arranged on top of the conductive layer with the rear surface of the solar cell facing the patterned conductive surface. Each electrical contact of the solar cell is in contact with a corresponding contacting area on the conductor circuit by a body of conductive connecting material. The conductive layer includes at the location of the contacting area a patch of a second material. Each patch is arranged in between the body of conductive connecting material on one electrical contact and the layer of the first material. | 2016-04-07 |
20160099360 | WAFER FOR SOLAR CELL, METHOD OF PRODUCING WAFER FOR SOLAR CELL, METHOD OF PRODUCING SOLAR CELL, AND METHOD OF PRODUCING SOLAR CELL MODULE - Provided is a wafer for solar cell which can be produced using a polycrystalline semiconductor wafer cut out using a bonded abrasive wire, which wafer can be used for manufacturing a solar cell with high conversion efficiency. | 2016-04-07 |
20160099361 | ELEMENT AND PHOTOVOLTAIC CELL - The invention provides an element including a semiconductor substrate and an electrode disposed on the semiconductor substrate, the electrode being a sintered product of a composition for an electrode that includes phosphorus-containing copper alloy particles, glass particles and a dispersing medium, and the electrode includes a line-shaped electrode having an aspect ratio, which is defined as electrode short length : electrode height, of from 2:1 to 250:1. | 2016-04-07 |
20160099362 | System and Method for Deploying Radiation Energy Conversion Cells - A radiation energy conversion system comprises: an environmental barrier cover having a barrier cover inner surface; an environmental barrier enclosure supporting the environmental barrier cover, the environmental barrier enclosure having a barrier enclosure internal surface extending to the barrier cover inner surface; a radiation-tranparent optic disposed in at least one of the environmental barrier cover and the environmental barrier enclosure; and at least one radiation energy conversion cell secured to at least one of the barrier enclosure internal surface and the barrier cover inner surface. | 2016-04-07 |
20160099363 | USING SOLAR CELLS AS BYPASS DIODE HEAT SINKS - A solar panel includes a plurality of solar cells, a bypass diode unit, and a heat spreader. The bypass diode unit includes a bypass diode coupled in an electrical shunting configuration across at least a first solar cell of the plurality of solar cells to bypass current around at least the first solar cell in an event of failure of the first solar cell. The heat spreader is disposed over a portion of one or more of the solar cells. The bypass diode unit is disposed on a first side of the heat spreader with the bypass diode in thermal contact with the heat spreader. A second side of the heat spreader is mounted in thermal contact with the one or more of the solar cells to dissipate heat generated in the bypass diode to the one or more of the solar cells. | 2016-04-07 |
20160099364 | METHOD FOR FORMING DENDRITIC SILVER WITH PERIODIC STRUCTURE AS LIGHHT-TRAPPING LAYER - The invention is related to a method for forming dendritic silver with periodic structure as light-trapping layer, includes these steps: form a photoresist layer on a conductive substrate, and at least two coherent light beams is provided in using a laser interference lithography apparatus, to form a plurality of particular patterns respectively on the setting-exposure positions of the conductive substrate in sequence till the particular periods pattern formed. Thereafter, form the dendritic silver nanostructure with period pattern on the conductive substrate via electrochemical process, wherein operating voltage is 2V or higher, and electrochemical reaction time is 10 sec or higher. | 2016-04-07 |
20160099365 | Collector grid and interconnect structures for photovoltaic arrays and modules - An interconnected arrangement of photovoltaic cells is achieved using laminating current collector electrodes. The electrodes comprise a pattern of conductive material extending over a first surface of sheetlike substrate material. The first surface comprises material having adhesive affinity for a selected conductive surface. Application of the electrode to the selected conductive surface brings the first surface of the sheetlike substrate into adhesive contact with the conductive surface and simultaneously brings the conductive surface into firm contact with the conductive material extending over first surface of the sheetlike substrate. Use of the laminating current collector electrodes allows facile and continuous production of expansive area interconnected photovoltaic arrays. | 2016-04-07 |
20160099366 | SOLAR CELL MODULE AND METHOD FOR MANUFACTURING THE SAME - A solar cell module, a method for manufacturing the solar cell module, a solar power system, and an interconnection ribbon are provided. The solar cell module includes a plurality of solar cells which are connected in series or in parallel through interconnection ribbons, wherein the interconnection ribbons have a zigzag shape to reduce tension generated according to bending of the solar cell module. | 2016-04-07 |
20160099367 | Hybrid Trough Solar Power System using Photovoltaic Two-Stage Light Concentration - A solar power method is provided using two-stage light concentration to drive concentrating photovoltaic conversion in conjunction with thermal collection. The method concentrates light rays received in a plurality of transverse planes towards a primary linear focus in an axial plane, which is orthogonal to the transverse planes. T hand wavelengths of light are transmitted to the primary linear focus. R hand wavelengths of light are reflected towards a secondary linear focus in the axial plane, which is parallel to the primary linear focus. The light received at the primary linear focus is translated into thermal energy. The light received at the secondary linear focus is focused by optical elements along a plurality of tertiary linear foci, which are orthogonal to the axial plane. The focused light in each tertiary primary focus is focused into a plurality of receiving areas, and translated into electrical energy. | 2016-04-07 |
20160099368 | NANOSTRUCTURED UNITS FORMED INSIDE A SILICON MATERIAL AND THE MANUFACTURING PROCESS TO PERFORM THEM THEREIN - The invention bears on elementary nanoscale units nanostructured-formed inside a silicon material and the manufacturing process to implement them. Each elementary nanoscale unit is created by means of a limited displacement of two Si atoms outside a crystal elementary unit. A localized nanoscale transformation of the crystalline matter gets an unusual functionality by focusing in it a specific physical effect as is a highly useful additional set of electron energy levels that is optimized for the solar spectrum conversion to electricity. An adjusted energy set allows a low-energy secondary electron generation in a semiconductor, preferentially silicon, material for use especially in very-high efficiency all-silicon light-to-electricity converters. The manufacturing process to create such transformations in a semiconductor material bases on a local energy deposition like ion implantation or electron beam irradiation and suitable thermal treatment and is industrially easily available. | 2016-04-07 |
20160099369 | MONOLITHICALLY INTEGRATED THIN-FILM ELECTRONIC CONVERSION UNIT FOR LATERAL MULTIJUNCTION THIN-FILM SOLAR CELLS - An integrated thin-film lateral multi junction solar device and fabrication method are provided. The device includes, for instance, a substrate, and a plurality of stacks extending vertically from the substrate. Each stack may include layers, and be electrically isolated against another stack. Each stack may also include an energy storage device above the substrate, a solar cell above the energy storage device, a transparent medium above the solar cell, and a micro-optic layer of spectrally dispersive and concentrating optical devices above the transparent medium. Furthermore, the device may include a first power converter connected between the energy storage device and a power bus, and a second power converter connected between the solar cell and the power bus. Further, different solar cells of different stacks may have different absorption characteristics. | 2016-04-07 |
20160099370 | MULTI-JUNCTION SOLAR CELL - A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell. | 2016-04-07 |
20160099371 | BACK SIDE ILLUMINATED IMAGE SENSOR WITH GUARD RING REGION REFLECTING STRUCTURE - A photon detector includes a single photon avalanche diode (SPAD) disposed proximate to a front side of a semiconductor layer. The SPAD includes a multiplication junction that is reversed biased above a breakdown voltage such that light directed into the SPAD through a backside of the semiconductor layer triggers an avalanche multiplication process. A guard ring is disposed in a guard ring region that surrounds the SPAD to isolate the SPAD in the semiconductor layer. A guard ring region reflecting structure is disposed in the guard ring region proximate to the guard ring and proximate to the front side of the semiconductor layer such that light directed into the guard ring region through the backside of the semiconductor layer that bypasses the SPAD is redirected by the guard ring region reflecting structure back into the semiconductor layer and into the SPAD. | 2016-04-07 |
20160099372 | Gate-controlled Charge Modulated Device for CMOS Image Sensors - A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. | 2016-04-07 |
20160099373 | WAFER LEVEL PACKAGING, OPTICAL DETECTION SENSOR AND METHOD OF FORMING SAME - An optical detection sensor functions as a proximity detection sensor that includes an optical system and a selectively transmissive structure. Electromagnetic radiation such as laser light can be emitted through a transmissive portion of the selectively transmissive structure. A reflected beam can be detected to determine the presence of an object. The sensor is formed by encapsulating the transmissive structure in a first encapsulant body and encapsulating the optical system in a second encapsulant body. The first and second encapsulant bodies are then joined together. In a wafer scale assembling the structure resulting from the joined encapsulant bodies is diced to form optical detection sensors. | 2016-04-07 |
20160099374 | SEMICONDUCTOR DEVICE - A semiconductor device used for a semiconductor relay includes: a first diode; a second diode; an electric field shield film for covering the second semiconductor island region, where the second diode is formed; and a wiring for electrically connecting the first diode to the second diode. The wiring is arranged so as to cross above a silicon oxide film surrounding the second semiconductor island region. The electric field shield film is positioned below the wiring, and has a cutout portion in an overlapping region which overlaps the wiring. By forming the cutout portion, end portions of the electric field shield film is arranged to be shifted. Therefore, formation of a deep concave portion which is based on a concave portion on the silicon oxide film and a step of the electric field shield film over the entire width of the wiring can be prevented, and the disconnection of the wiring can be prevented. | 2016-04-07 |
20160099375 | SOLAR CELL HAVING DOPED BUFFER LAYER AND METHOD OF FABRICATING THE SOLAR CELL - A method includes: forming a buffer layer over an absorber layer of a photovoltaic device; and extrinsically doping the buffer layer after the forming step. | 2016-04-07 |
20160099376 | METHOD OF MANUFACTURING NANOSTRUCTURE SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to an example embodiment, a method of manufacturing a nanostructure semiconductor light-emitting device includes forming nanocores of a first-conductivity type nitride semiconductor material on abase layer to be spaced apart from each other, and forming a multilayer shell including an active layer and a second-conductivity type nitride semiconductor layers on surfaces of each of the nanocores. At least a portion the multilayer shell is formed by controlling at least one process parameter of a flux of source gas, a flow rate of source gas, a chamber pressure, a growth temperature, and a growth rate so as to have a higher film thickness uniformity. | 2016-04-07 |
20160099377 | LIGHT-EMITTING ELEMENT - A light-emitting element, a light-emitting element unit and a light-emitting element package are provided, which are each reduced in reflection loss and intra-film light absorption by suppressing multiple light reflection in a transparent electrode layer and hence have higher luminance. The light-emitting element | 2016-04-07 |
20160099378 | METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE - A method of fabricating a semiconductor light emitting device includes forming a first conductivity type semiconductor layer, forming an active layer by alternately forming a plurality of quantum well layers and a plurality of quantum barrier layers on the first conductivity type semiconductor layer, and forming a second conductivity type semiconductor layer on the active layer. The plurality of quantum barrier layers include at least one first quantum barrier layer adjacent to the first conductivity type semiconductor layer and at least one second quantum barrier layer adjacent to the second conductivity type semiconductor layer. The forming of the active layer includes allowing the at least one first quantum barrier layer to be grown at a first temperature and allowing the at least one second quantum barrier layer to be grown at a second temperature lower than the first temperature. | 2016-04-07 |
20160099379 | Nanowire Sized Opto-Electronic Structure and Method for Modifying Selected Portions of Same - A LED structure includes a support and a plurality of nanowires located on the support, where each nanowire includes a tip and a sidewall. A method of making the LED structure includes reducing or eliminating the conductivity of the tips of the nanowires compared to the conductivity of the sidewalls during or after creation of the nanowires. | 2016-04-07 |
20160099380 | EPITAXIAL STRUCTURE - An epitaxial structure including an epitaxial substrate, a first buffer layer, a first pattern mask layer, a second buffer layer and a second pattern mask layer. The first buffer layer is disposed on the epitaxial substrate. The first pattern mask layer is disposed on the first buffer layer. The second buffer layer is disposed on the first pattern mask layer and a part of the first buffer layer. The second pattern mask layer is disposed on the second buffer layer. A projection of the first pattern mask layer projected on the first buffer layer and a projection of the second pattern mask layer projected on the first buffer layer cover at least 70% of the total area of the first buffer layer. | 2016-04-07 |
20160099381 | EPITAXY BASE, SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHODS THEREOF - An epitaxy base including a substrate and a nucleating layer disposed on the substrate. The nucleating layer is an AlN layer with a single crystal structure. A diffraction pattern of the nucleating layer includes a plurality of dot patterns. Each of the dot patterns is substantially circular, and a ratio between lengths of any two diameters perpendicular to each other on each of the dot patterns ranges from approximately 0.9 to approximately 1.1. A semiconductor light emitting device, a manufacturing method of the epitaxy base, and a manufacturing method of the light emitting semiconductor device are further provided. | 2016-04-07 |
20160099382 | ULTRAVIOLET LIGHT EMITTING DEVICE DOPED WITH BORON - In an example, the present invention provides a light-emitting device configured to emit electromagnetic radiation in a range of 210 to 360 nanometers. The device has a substrate member comprising a surface region. The device has a thickness of AlGaN material formed overlying the surface region and an aluminum concentration characterizing the AlGaN material having a range of 0 to 100%. The device has a boron doping concentration characterizing the AlGaN material having a range between 1e15 to 1e20 atoms/centimeter3. | 2016-04-07 |
20160099383 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer which are sequentially stacked; a first conductivity type upper electrode portion and a first conductivity type lower electrode portion disposed to correspond to each other with the first conductivity type semiconductor layer interposed therebetween; a second conductivity type upper electrode portion and a second conductivity type lower electrode portion disposed to correspond to each other with the first and second conductivity type semiconductor layers interposed therebetween; and a second conductivity type electrode connection portion electrically connecting the second conductivity type upper electrode portion and the second conductivity type lower electrode portion. | 2016-04-07 |
20160099384 | Light Emitting Device - A light emitting device includes a light emitting structure having a plurality of light emitting regions including a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode in one of the light emitting regions, a second electrode in another of the light emitting regions, and at least one connection electrode to sequentially connect the light emitting regions in series. The light emitting regions connected in series are divided into 1st to ith light emitting region groups. Areas of light emitting regions that belong to different groups are different. An area of a light emitting region which is more frequently used among the plurality of light emitting regions is larger than an area of a light emitting region which is less frequently used among the plurality of light emitting regions. | 2016-04-07 |
20160099385 | Method for Manufacturing Vertical Type Light Emitting Diode, Vertical Type Light Emitting Diode, Method for Manufacturing Ultraviolet Ray Light Emitting Diode, and Ultraviolet Ray Light Emitting Diode - A vertical type light emitting diode includes a nitride semiconductor having a p-n conjunction structure with a transparent material layer formed on a p type clad layer, the transparent material layer having a refractive index different from that of the p type clad layer and having a pattern structure of mesh, punched plate, or one-dimensional grid form, etc. A reflective metal electrode layer is formed on the transparent material layer as a p-electrode. A stereoscopic pattern is formed in the transparent material layer and the p-electrode deposited, and thereby forming the pattern in the p-electrode. Depositing the p-electrode on only 10 to 70% of the upper portion of the p type clad layer in an ultraviolet ray light emitting diode such that an area where the p type clad layer is exposed is wide increases the transmittance of ultraviolet rays through an area where the p-electrode is not deposited. | 2016-04-07 |
20160099386 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes: a substrate; an n-type semiconductor layer disposed on the substrate; an active layer disposed on the n-type semiconductor layer; a p-type semiconductor layer disposed on the active layer; a first electrode disposed on the p-type semiconductor layer and made of a metal oxide; a second electrode disposed on the first electrode and made of graphene; a p-type electrode disposed on the second electrode; and an n-type electrode disposed on the n-type semiconductor layer, wherein a work function of the first electrode is less than a work function of the p-type semiconductor layer, but is greater than a to work function of the second electrode. | 2016-04-07 |