| 14th week of 2012 patent applcation highlights part 49 |
| Patent application number | Title | Published |
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| 20120084447 | End-Point Identifiers in SIP - A system and method for uniquely identifying an SIP device extends the SIP communications protocol with an end point identifier, carried for example in the header of an SIP transmission. The end point identifier is useful for routing, registration, subscription, and authentication. The end point (device) of a given user epid can be uniquely identified by creating a key from an epid and a user's address-of-record (URI). This in turn enables improved connection management and security association management when the connections/IP addresses are transient, such as when HTTPS tunneling is used. | 2012-04-05 |
| 20120084448 | Communication Control Device, Communication System and Communication Method - A communication control device includes: a device connection unit that is configured to establish connection to a plurality of communication devices; a controller that is configured to control communication between the plurality of communication devices, which is connected to the communication control device by the device connection unit, and a counterpart device via a line; and a memory that is configured to store protection-target information including at least information for communication with the plurality of communication devices connected by the device connection unit. The controller is configured to: register at least one communication device from among communication devices connectable by the device connection unit; determine whether or not the at least one registered communication device is connected by the device connection unit; and when the at least one registered communication device is determined to be connected, permit an output of predefined protection-target information for the connected communication device. | 2012-04-05 |
| 20120084449 | DYNAMIC SELECTION OF PACKET DATA NETWORK GATEWAYS - A device receives a PDN connection request from a UE, and exchanges, with a HSS, authentication and authorization information associated with the UE. The device also constructs an APN FQDN based on the authentication and authorization information, and sends a query, that includes the APN FQDN, to a DNS server. The device further receives, from the DNS server, PGW FQDNs that contain the APN FQDN, and compares the PGW FQDNs with a FQDN associated with a SGW. The device determines, based on the comparison, a PGW, associated with a PGW FQDN that is a closest match to the FQDN associated with the SGW, to be a primary PGW for the PDN connection request. The device also determines, based on the comparison, one or more PGWs, residing within a predetermined distance of the SGW, to be one or more backup PGWs for the PDN connection request. | 2012-04-05 |
| 20120084450 | Audio challenge for providing human response verification - There is provided a system and method for audio challenges for providing human response verification. There is provided a method comprising receiving a request to verify whether a client is human controlled, generating, using a database, a challenge question and a corresponding answer set, selecting a plurality of images and an audio instruction corresponding to the challenge question, presenting the plurality of images and the audio instruction to the client, receiving a submission to the challenge question from the client, and responding to the request by verifying whether the submission is contained in the answer set to determine whether the client is human controlled. By utilizing easily understood elements such as common shapes and objects, familiar characters, colors, sizes, orientations, and sounds, even young children can solve the challenge question, whereas automated systems are deterred by the complex audio and image analysis required. | 2012-04-05 |
| 20120084451 | Methods, Apparatuses, And Related Computer Program Product For Network Security - It is disclosed a method (and related apparatus) including selecting, at a first endpoint entity, at least one range of protection to be granted, the range of protection relating to one of a plurality of network elements in at least one access network and at least one core network and to a second endpoint entity, and transmitting, to a network element entity, a signaling message including first establishment information indicating the at least one range of protection to be granted; and a method (and related apparatus) including receiving, at the network element entity, the signaling message from the first endpoint entity, obtaining, from a second endpoint entity and based on the first establishment information, second establishment information indicating protection granted by the second endpoint entity, and signaling, from the network element entity to the first endpoint entity, third establishment information indicating the protection granted to the first endpoint entity. | 2012-04-05 |
| 20120084452 | REMOTE CONTROL COMMAND TRANSLATION - Embodiments are disclosed that relate to translating remote control commands. One embodiment provides a remote control command translation device comprising a network receiver configured to receive one or more metacommands via a first protocol and a transmitter configured to output one or more translated commands via a unidirectional protocol, wherein the unidirectional protocol is different than the first protocol. The remote control command translation device further comprises a logic subsystem configured to execute instructions and a data-holding subsystem comprising mass storage containing translation information and instructions executable by the logic subsystem to receive, via the network receiver, a metacommand from a remote device via the first protocol, to translate the metacommand into a translated command based on the translation information, and to transmit, via the transmitter, the translated command corresponding to the metacommand via the unidirectional protocol. | 2012-04-05 |
| 20120084453 | ADJUSTING AUDIO AND VIDEO SYNCHRONIZATION OF 3G TDM STREAMS - Systems and methods of adjusting synchronization of audio media streams and video media streams in 3G mobile communications systems that can mitigate the effects of temporal skew due to intervening processing elements associated with media channels carrying the respective media streams. The systems and methods are operative to adjust the synchronization of audio media streams and video media streams by receiving control messages that report delays due to such intervening processing elements, calculating a relative amount of delay using the reported delays for each media channel, and applying a delay factor based on the relative amount of delay to the faster media channel to place the audio media streams and the video media streams in proper temporal alignment. The delay factor is applied to the faster media channel at those locations within the mobile communications systems where the audio and video media streams are combined and/or separated for subsequent transmission. | 2012-04-05 |
| 20120084454 | METHODS AND APPARATUSES FOR ADAPTIVE CONTROL OF STREAMING - Apparatuses and methods used in a media streaming system in which at least two representations of a media content item are available are provided. An apparatus ( | 2012-04-05 |
| 20120084455 | SYSTEM AND METHOD FOR RENDERING DIGITAL CONTENT USING TIME OFFSETS - A system and method for rendering digital content includes a media player having access to at least one server via a network. In addition to storing digital data corresponding to a printed document, such as an eBook, the one or more servers also stores a descriptor file. The descriptor file includes time information for defining the digital data, which is determined relative to a timeline of an audio recording of the text of the printed document. The digital content to be rendered is selected using the time information in the descriptor file and a time offset external to the descriptor file. | 2012-04-05 |
| 20120084456 | METHOD AND SYSTEM FOR LOW-LATENCY TRANSFER PROTOCOL - A method and system for providing computer-generated output and in particular graphical output. An output capturing and encoding engine is configured to intercept graphical output from an application on a server, organize the output into regions having similar motion and/or graphical characteristics, and convert the data from each region into a format suitable to balance transmission efficiencies versus display quality or capability at the receiving end. | 2012-04-05 |
| 20120084457 | RELAY DEVICE, RELAY METHOD AND RELAY SYSTEM - A relay device includes a screen information receiving unit that receives screen information from the application server, a cycle screen storage unit that stores screen information, a cycle detecting unit that detects a cycle of a change as first cycle information when the screen information cyclically changes, a cycle converting unit that converts the first cycle information into second cycle information, and a screen, information transmitting unit that acquires screen information from the cycle screen storage unit and transmits the screen information to the client terminal at a timing based on the second cycle information. | 2012-04-05 |
| 20120084458 | COMMUNICATION BETWEEN A HOST OPERATING SYSTEM AND A GUEST OPERATING SYSTEM - In an embodiment, a guest operating system receives first host network information that identifies a host virtual network adapter. The first host network information uniquely identifies the host virtual network adapter. The guest operating system sends a first frame that comprises the first host network information to a guest virtual network adapter. The guest virtual network adapter sends the first frame to the host virtual network adapter. The guest operating system receives second host network information that identifies the host virtual network adapter. The second host network information uniquely identifies the host virtual network adapter. The guest operating system sends a second frame that comprises the second host network information to the guest virtual network adapter. The guest virtual network adapter sends the second frame to the host virtual network adapter identified by the second host network information in the second frame. | 2012-04-05 |
| 20120084459 | Content Router Forwarding Plane Architecture - A router forwarding plane comprising a bloom filter stored on a first tier storage medium, and a forwarding information log associated with the bloom filter and stored on a second tier storage medium. Also disclosed is a network component comprising a receiver configured to receive a content comprising a general name prefix, a first tier storage medium configured to store a plurality of bloom filters associated with a plurality of general name prefixes and a plurality of corresponding ports, a logic circuitry configured to compute a plurality of signatures based on the general name prefix of the received content, and a transmitter configured to forward the received content on at least one of the ports that are associated with at least one of the bloom filters if the general name prefix is a member of the at least one of the bloom filters. | 2012-04-05 |
| 20120084460 | METHOD AND SYSTEM FOR DYNAMIC TRAFFIC STEERING - A method and system for dynamic traffic steering is described. In one embodiment, a method for dynamic traffic steering involves receiving a request for content at a steering component, comparing information in the request with steering criteria in the steering component, steering the request based on the comparing, and continuously updating the steering criteria based on requests that are subsequently received at the steering component. Other embodiments are also described. | 2012-04-05 |
| 20120084461 | Data and Call Routing and Forwarding - A system and method for determining an order in which to communicate with a list of numbers and/or addresses for a particular contact is disclosed. Each caller that communicates with the contact may specify a different order for the contact's various phone numbers and other addresses. A communication management system may then automatically dial the numbers or use messaging addresses to initiate data communications in the specified order when the initiating party attempts to communicate with the contact. The order may specify simultaneous and/or sequential use of numbers or addresses. Alternatively or additionally, the communication management system may dynamically and/or automatically determine the communication order or a portion thereof. The automatic determination of the order may be based on a communication history or communication receiving of the initiating party. In some arrangements, the order may be partially manually defined and partially automatically defined. | 2012-04-05 |
| 20120084462 | METHOD FOR OBTAINING IP ADDRESS OF DHCPV6 SERVER, DHCPV6 SERVER, AND DHCPV6 COMMUNICATION SYSTEM - The present invention relates to the field of communications, and in particular, relates to a method for obtaining an Internet Protocol (IP) address of a Dynamic Host Configuration Protocol version 6 (DHCPv6) server, a DHCPv6 server, and a DHCPv6 communication system. The method is applied in a scenario of communication through a DHCPv6 relay agent, and includes: receiving, by a DHCPv6 server, a message of a DHCPv6 client forwarded by a DHCPv6 relay agent; sending, by the DHCPv6 server, a response message to the DHCPv6 client through the DHCPv6 relay agent, in which a payload of the response message carries an IP address of the DHCPv6 server, so that the DHCPv6 client obtains the IP address of the DHCPv6 server from the response message. | 2012-04-05 |
| 20120084463 | Delivering Content in Multiple Formats - Content may be received at an edge location in one format, but delivered to a terminal on an access network in another format. The received content may be transcoded at the edge location. The transcoded content may be stored, or immediately delivered. The transcoded content may be fragmented prior to storage. Multiple copies of the transcoded content may be maintained in multiple formats. These formats may be aligned with one another such that delivery of the content can include delivering portions of the content in one format and other portions of the content in another format. | 2012-04-05 |
| 20120084464 | Obfuscating Network Traffic from Previously Collected Network Traffic - An obfuscated network traffic server is operative to generate obfuscated network traffic. The obfuscated network traffic server maintains the relationship between extracted application content and extracted network header content such that the obfuscated network traffic is indistinguishable from the monitored network traffic. The obfuscated network traffic server may include a network monitor operative to monitor network traffic and to extract application content and network header content from the monitored network traffic. The obfuscated network traffic server may also include a data masking processor operative to mask a portion of the separated application content and/or the separated network header content. The obfuscated network traffic server may further include a masking attribute selector operative to specify the attributes of the application content and/or the network header content that is to be masked. | 2012-04-05 |
| 20120084465 | TRANSACTION ACCELERATOR FOR CLIENT-SERVER COMMUNICATIONS SYSTEMS - Transactions are accelerated by the transaction handlers by storing segments of data used in the transactions in persistent segment storage accessible to the server side transaction handler and in persistent segment storage accessible to the client side transaction handler. When data is to be sent between the transaction handlers, the sending transaction handler compares the segments of the data to be sent with segments stored in its persistent segment storage and replaces segments of data with references to entries in its persistent segment storage that match or closely match the segments of data to be replaced. The receiving transaction store reconstructs the data sent by replacing segment references with corresponding segment data from its persistent segment storage. | 2012-04-05 |
| 20120084466 | SYSTEM FOR SYNCHRONIZING TO A MOBILE DEVICE SERVER - A system that incorporates teachings of the present disclosure may include, for example, a non-transitory computer-readable storage medium operating in a mobile device server having computer instructions to execute a web server application at the mobile device server. The web server application can be operable to detect a media resource center while roaming in a communication zone of the media resource center, and to transmit a pairing key to the media resource center. The web server application can be further operable to receive authorization from the media resource center to synchronize differences between content stored in the media resource center and content stored in the mobile device server responsive to the media resource center validating the pairing key. Other embodiments are disclosed. | 2012-04-05 |
| 20120084467 | HAPTICALLY ENHANCED INTERACTIVITY WITH INTERACTIVE CONTENT - Interactive content may be presented to a user that is manipulating a peripheral. One or more state parameters that are related to the position of the peripheral may be determined. The peripheral may be identified from a plurality of possible peripherals. The interactive content may be adjusted based at least in part on the one or more position parameters and/or, the identification of the peripheral. Haptic feedback to be provided to the user may be determined based at least in part on the one or more position parameters and/or the identification of the peripheral. | 2012-04-05 |
| 20120084468 | INFORMATION PROCESSING APPARATUS, PERIPHERAL APPARATUS CONTROL METHOD, AND STORAGE MEDIUM - A peripheral apparatus control system that provides a device management screen capable of producing appropriate view contents and functions according to the use environment of each user for improving operability. The system includes an information processing apparatus, a peripheral apparatus, a driver capable of controlling the peripheral apparatus, a peripheral apparatus management function capable of managing the peripheral apparatus, and a peripheral apparatus management screen. The system determines a view content of the peripheral apparatus management screen according to an attribute of the driver. | 2012-04-05 |
| 20120084469 | USB TRANSACTION TRANSLATOR AND A BULK TRANSACTION METHOD - The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN/OUT bulk transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. In a bulk-IN transaction, before the host sends an IN packet, the controller pre-fetches data and stores the data in the buffers until all the buffers are full or a requested data length has been achieved; the pre-fetched data are then sent to the host after the host sends the IN packet. In a bulk-OUT transaction, the controller stores the data sent from the host in the buffers, and the data are then post-written to the device. | 2012-04-05 |
| 20120084470 | Utilitzing USB Resources - At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port. | 2012-04-05 |
| 20120084471 | USB TRANSACTION TRANSLATOR AND A MICRO-FRAME SYNCHRONIZATION METHOD - The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host. | 2012-04-05 |
| 20120084472 | PROGRAMMABLE MULTIMEDIA CONTROLLER WITH FLEXIBLE USER ACCESS AND SHARED DEVICE CONFIGURATIONS - A system which includes a programmable multimedia controller is provided in which flexible user access is provided through a combination of user profiles and usernames/pas swords. A configuration for a given device which may form part of the system or may interoperate with the system may be shared by multiple similar devices. A sharable device configuration is stored by a master device and can be shared by other devices of the same type as the master device. | 2012-04-05 |
| 20120084473 | METHOD AND BUS SYSTEM FOR EQUALIZING DATA INFORMATION TRAFFIC AND DECODER - In the field of integrated circuit (IC) design, a method and a bus system for equalizing data information traffic and a decoder are provided. The method includes: receiving data information sent by a device, and allocating at least two transmission interfaces for the data information according to a decoding result of decoding a designated bit in the data information, where the data information carries a device ID, and the designated bit position occupied at least one bit in the device ID; judging whether the data information traffic of the at least two transmission interfaces is balanced; and when the data information traffic of the at least two transmission interfaces is not balanced, switching the designated bit position, and decoding the designated bit after switching, so as to balance the traffic of the at least two transmission interfaces. The bus system includes an interface allocation module, a traffic judging module and a bit position switching module. The decoder includes a decoding module and a designated bit position switching module. | 2012-04-05 |
| 20120084474 | INTERFACE FOR COMMUNICATION BETWEEN SENSING DEVICES AND I2C BUS - A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to, and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs ( | 2012-04-05 |
| 20120084475 | BUS ARBITRATION APPARATUS AND BUS ARBITRATION METHOD - It may be difficult to give bus right to a bus master that cannot output a bus request signal when a bus arbitration apparatus is ready to grant bus permission precisely in a ratio of a preset number of times of the bus acquisition. The bus arbitration apparatus operates to wait until bus request signals of bus masters that have not performed transfers of the preset number of times of the bus acquisition are output while a bus slave operates. | 2012-04-05 |
| 20120084476 | ADVANCED TELECOMMUNICATIONS COMPUTING ARCHITECTURE EXCHANGE SYSTEM, ADVANCED TELECOMMUNICATIONS COMPUTING ARCHITECTURE EXCHANGE METHOD, AND COMMUNICATION APPARATUS - An ATCA exchange system is disclosed according to the embodiments of the present invention. The ATCA exchange system includes: a master exchange shelf, including a first node board and a hub board; and a slave exchange shelf, including a second node board and an I/O transfer board. The I/O transfer board includes an exchange interface, and in the slave exchange shelf, the I/O transfer board is connected to the second node board through the exchange interface. The I/O transfer board is connected to the hub board by using an external communication link through the exchange interface, so that data of the second node board reaches the hub board through the I/O transfer board when the data needs to be exchanged, so as to complete data exchange through the hub board. According to the embodiments of the present invention, the manufacturing cost can be reduced. | 2012-04-05 |
| 20120084477 | Transactional Memory Preemption Mechanism - Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction. | 2012-04-05 |
| 20120084478 | STACKED DIE WITH VERTICALLY-ALIGNED CONDUCTORS AND METHODS FOR MAKING THE SAME - Stacked die having vertically-aligned conductors and methods for making the same are disclosed for providing a non-volatile memory, such as flash memory (e.g., NAND flash memory), for use in an electronic device. | 2012-04-05 |
| 20120084479 | Modular Digital Presentation Switcher - A modular digital presentation switcher is a device that can convert different kinds of incoming multimedia signals into an outgoing signal in an analog and digital format. The device retrieves the incoming multimedia signals through input modules. Each of the input modules is capable of retrieving a unique signal such as composite video or S-video, VGA, and DVI-D. The device sends the outgoing signal through output modules, which are connected to the display device and the audio amplifier. A communication bus allows the input modules and the output modules to communicate with each other so that the device can cater and format the outgoing signal for the display device and the audio amplifier. An HDMI digital signal bus allows the input modules to send the outgoing signal in HDMI digital format to the output modules. A user interface module allows the user to access the functions of the device. | 2012-04-05 |
| 20120084480 | AUTO-CONFIGURATION OF A DOCKED SYSTEM IN A MULTI-OS ENVIRONMENT - A mobile computing device with a mobile operating system and desktop operating system running concurrently and independently on a shared kernel without virtualization. The mobile operating system provides a user experience for the mobile computing device that suits the mobile environment. The desktop operating system provides a full desktop user experience when the mobile computing device is docked to a secondary terminal environment. The mobile computing device configures the mobile operating system and/or the desktop operating system to take advantage of a docked secondary terminal environment. The mobile computing device may be a smartphone running the Android mobile OS and a full desktop Linux OS distribution on a modified Android kernel. | 2012-04-05 |
| 20120084481 | AUTO-WAKING OF A SUSPENDED OS IN A DOCKABLE SYSTEM - A mobile computing device with a mobile operating system and desktop operating system running concurrently and independently on a shared kernel without virtualization. The mobile operating system provides a user experience for the mobile computing device that suits the mobile environment. The desktop operating system provides a full desktop user experience when the mobile computing device is docked to a secondary terminal environment. The desktop operating system may be suspended when the mobile computing device is not docked with a secondary terminal environment and resumed when the mobile computing device is docked with a secondary terminal environment that provides a desktop computing experience. The mobile computing device may be a smartphone running the Android mobile OS and a full desktop Linux OS distribution on a modified Android kernel. | 2012-04-05 |
| 20120084482 | SEMICONDUCTOR DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - A communication control function is implemented with limited hardware resources without hampering the extensibility and degrading the processing performance. In an electric control unit coupled to a network bus comprises a reconfiguration module using for processing message received from the network bus. The reconfiguration module is made for configuring the processing circuit in accordance with the message transferred on the network bus to be processed. | 2012-04-05 |
| 20120084483 | DIE EXPANSION BUS - A die expansion bus efficiently couples a supplemental portion of a processing system to an original portion of the processing system on a die. The die expansion bus couples bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system. The original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing the memory endpoints associated with the bus subsystems of the supplemental portion of the processing system. | 2012-04-05 |
| 20120084484 | SELECTIVELY COMBINING COMMANDS FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM. | 2012-04-05 |
| 20120084485 | USB TRANSACTION TRANSLATOR AND AN ISOCHRONOUS-IN TRANSACTION METHOD - The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN isochronous transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A register is used to record device bus information. Before the host sends an IN packet, the controller pre-fetches data from the device according to the device bus information and then stores the data in the buffers; the controller responds with the pre-fetched data to the host after the host sends the IN packet. | 2012-04-05 |
| 20120084486 | SYSTEM AND METHOD FOR USING A MULTIPATH - In a path determination unit of a SAS expander connected to a SAS initiator and connected via first and second paths to a SAS target, an SSP controller receives an SSP command frame received from the SAS initiator; a requested-data-length manager stores a requested data length of the SSP command frame in a requested-data-length storage unit; and a data-transfer-amount manager selects one of the first and second paths having a smaller one of the data transfer amounts stored in a data-transfer-amount storage unit, and adds the requested data length to the data transfer amount of the selected path. The SSP command frame is transmitted to the SAS target via the selected path. Upon receipt of an SSP response frame responding thereto, the requested data length is deleted from the requested-data-length storage unit, and the requested data length is subtracted from the data transfer amount of the selected path. | 2012-04-05 |
| 20120084487 | System and Method for Controlling the Input/Output of a Virtualized Network - In accordance with an embodiment a method of running a virtual machine on a server includes controlling data path resources allocated to the virtual machine using a first supervisory process running on the server, controlling data path resources comprising controlling a data path of a hardware interface device coupled to the server, and controlling control path and initialization resources of the hardware interface device using a second process running on the server, where the second process is separate from the first supervisory process. | 2012-04-05 |
| 20120084488 | Dynamic Address Translation With Translation Exception Qualifier - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame. | 2012-04-05 |
| 20120084489 | SYNCHRONIZED MAINTENANCE OPERATIONS IN A MULTI-BANK STORAGE SYSTEM - A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above. | 2012-04-05 |
| 20120084490 | METHOD FOR CHANGING READ PARAMETER FOR IMPROVING READ PERFORMANCE AND APPARATUSES USING THE SAME - A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation. | 2012-04-05 |
| 20120084491 | Flash Memory for Code and Data Storage - A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution. | 2012-04-05 |
| 20120084492 | STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING - Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge. Optionally, data stored on an SSD is hardened, such as in response to determining that the SSD is to be powered off. The hardening is via power supplied by an energy storage element, such as a super capacitor or a battery. | 2012-04-05 |
| 20120084493 | NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION - Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller. | 2012-04-05 |
| 20120084494 | MEMORY FOR ACCESSING MULTIPLE SECTORS OF INFORMATION SUBSTANTIALLY CONCURRENTLY - A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently. | 2012-04-05 |
| 20120084495 | SEMICONDUCTOR PROGRAMMABLE DEVICE - An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function. | 2012-04-05 |
| 20120084496 | VALIDATING PERSISTENT MEMORY CONTENT FOR PROCESSOR MAIN MEMORY - Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor. | 2012-04-05 |
| 20120084497 | Instruction Prefetching Using Cache Line History - An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines. | 2012-04-05 |
| 20120084498 | TRACKING WRITTEN ADDRESSES OF A SHARED MEMORY OF A MULTI-CORE PROCESSOR - Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules. | 2012-04-05 |
| 20120084499 | SYSTEMS AND METHODS FOR MANAGING A VIRTUAL TAPE LIBRARY DOMAIN - Systems and methods for managing a virtual tape library (VTL) domain capable of being coupled to a host are provided. One system includes a plurality of VTL nodes configured to store multiple scratch erased volumes. Each VTL node comprises a processor configured to perform at least a portion of the below method. One method includes receiving a request from the host to de-mount a volume in one of the plurality of VTL nodes, transferring the volume to a scratch category in response to receiving the request, erasing data in the volume and categorizing the volume as a scratch erased volume, and providing ownership of the scratch erased volume to a VTL node in the plurality of VTL nodes based on pre-determined criteria for the plurality of VTL nodes. Also provided are computer storage mediums including computer code for performing the above method. | 2012-04-05 |
| 20120084500 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CREATING A SINGLE LIBRARY IMAGE FROM MULTIPLE INDEPENDENT TAPE LIBRARIES - In one embodiment, a system includes a library manager for communicating with a plurality of logical libraries having data organized therein and stored on sequential access media therein, wherein the library manager controls movement operations of a plurality of shuttle cars along one or more shuttle pathways, wherein each of the shuttle cars are for transporting a sequential access medium between any of the plurality of logical libraries, wherein each of the logical libraries comprises at least one local station for sending and/or receiving shuttle cars to and/or from the plurality of logical libraries, wherein the one or more shuttle pathways connect the stations in a multi-drop arrangement, wherein each destination station is represented by a unique export-only address, and wherein all source stations are represented by a common import-only address. Other systems, methods, and computer program products are also described according to various embodiments. | 2012-04-05 |
| 20120084501 | Information processing apparatus, tape device, and computer-readable medium storing program - An acquisition unit of an information processing apparatus acquires access information indicating the state of access to a volume of a disk device at least for data read. A determination unit detects a volume in which a sequential read was performed, on the basis of the acquired access information, and determines the volume as a backup source for a backup. | 2012-04-05 |
| 20120084502 | METHOD AND SYSTEM FOR RESPONDING TO FILE SYSTEM REQUESTS - A system for responding to file system requests having file IDs comprising V, a volume identifier specifying the file system being accessed, and R, an integer, specifying the file within the file system being accessed includes D disk elements in which files are stored, where D is greater than or equal to 2 and is an integer. The system includes a switching fabric having a first switching element and a second switching element, each of which are connected to each of the D disk elements. The system includes N network elements, each of which is connected to each of the switching elements of the switching fabric, where N is greater than or equal to 2 and is an integer and N+D is greater than or equal to 4. | 2012-04-05 |
| 20120084503 | DISK CONTROL APPARATUS, DISK CONTROL METHOD, AND STORAGE MEDIUM STORING DISK CONTROL PROGRAM - A disk control apparatus that is capable of performing a reliable mirroring control for both of an SSD and an HDD. The disk control apparatus that performs a mirroring control to the SSD and the HDD. An acquisition unit acquires the data rewriting number in the SSD. A derivation unit derives a data retention period of the SSD from the data rewriting number acquired. A comparison unit compares a predetermined threshold value with an increment between the data rewriting number acquired at a predetermined timing and the data rewriting number acquired after a retention period, which is derived from the data rewriting number at the predetermined timing, elapses. A setting unit sets so as to read data from the SSD by default and to read data from the HDD when the comparison unit determines that the increment is less than the threshold value. | 2012-04-05 |
| 20120084504 | DYNAMIC RAID GEOMETRIES IN AN SSD ENVIRONMENT - A system and method for dynamic RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to configure a first subset of the storage devices for use in a first RAID layout, the first RAID layout including a first set of redundant data. The controller further configures a second subset of the storage devices for use in a second RAID layout, the second RAID layout including a second set of redundant data. Additionally, the controller configure an additional device not included in either the first subset or the second subset to store redundant data for both the first RAID layout and the second RAID layout. | 2012-04-05 |
| 20120084505 | RECONSTRUCT READS IN A RAID ARRAY WITH DYNAMIC GEOMETRIES - A system and method for dynamic RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to configure a first subset of the storage devices for use in a first RAID layout, the first RAID layout including a first set of redundant data. The controller further configures a second subset of the storage devices for use in a second RAID layout, the second RAID layout including a second set of redundant data. Additionally, the controller configure an additional device not included in either the first subset or the second subset to store redundant data for both the first RAID layout and the second RAID layout. The controller is further configured to initiate a reconstruct read corresponding to a given read request directed to a particular storage device of the plurality of storage devices, in response to determining the particular storage device is exhibiting a non-error related relatively slow read response. | 2012-04-05 |
| 20120084506 | DISTRIBUTED MULTI-LEVEL PROTECTION IN A RAID ARRAY BASED STORAGE SYSTEM - A system and method for dynamic RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to configure a first subset of the storage devices for use in a first RAID layout, the first RAID layout including a first set of redundant data. The controller further configures a second subset of the storage devices for use in a second RAID layout, the second RAID layout including a second set of redundant data. Additionally, when writing a stripe, the controller may select from any of the plurality of storage devices for one or more of the first RAID layout, the second RAID layout, and storage of redundant data by the additional logical device. | 2012-04-05 |
| 20120084507 | MULTI-LEVEL PROTECTION WITH INTRA-DEVICE PROTECTION IN A RAID ARRAY BASED STORAGE SYSTEM - A system and method for dynamic RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to configure a first subset of the storage devices for use in a first RAID layout, the first RAID layout including a first set of redundant data. The controller further configures a second subset of the storage devices for use in a second RAID layout, the second RAID layout including a second set of redundant data. Additionally, the controller configure an additional device not included in either the first subset or the second subset to store redundant data for both the first RAID layout and the second RAID layout. Further, each page stored in the plurality of devices includes a checksum corresponding to the page | 2012-04-05 |
| 20120084508 | DISK ARRAY APPARATUS AND FIRMWARE UPDATE METHOD THEREFOR - This invention proposes a disk array apparatus capable of improving its reliability. This disk array apparatus includes a first controller, and a second controller configured redundantly with the first controller, wherein the first controller and the second controller respectively include a storage area for storing firmware and are both in an operating state. When update processing of an update portion as a portion to be updated in the firmware of the first controller is unsuccessful, the first controller confirms whether update processing of an update portion of the firmware of the second controller is also unsuccessful, and, in a case where the update processing of the update portion of the firmware of the second controller has ended normally, rewrites firmware data of the update portion of the first controller with the firmware data of the update portion of the second controller. | 2012-04-05 |
| 20120084509 | Application Independent Storage Array Performance Optimizer - A system comprising a performance module and an application. The performance module may be configured to (i) monitor a LUN for a predetermined amount of time, (ii) capture information relating to the LUN, and (iii) store the information. The application may be configured to (i) retrieve the information, (ii) analyze the information, (iii) generate a configuration based on the analysis of the information and (iv) send the configuration to the performance module. The performance module may reconfigure the LUN based on the configuration. | 2012-04-05 |
| 20120084510 | Computing Machine and Computing System - According to one embodiment, a computing machine includes a virtual machine operated on a virtual machine monitor, the computing machine includes a first memory device, and a second memory device. The virtual machine monitor is configured to assign a part of a region of the first memory device as a third memory device to the virtual machine and to assign a part of a region of the second memory device as a fourth memory device to the virtual machine. The virtual machine comprises a first cache control module configured to use the fourth memory device as a read cache of the third memory device. | 2012-04-05 |
| 20120084511 | INEFFECTIVE PREFETCH DETERMINATION AND LATENCY OPTIMIZATION - A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyses the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the infectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations. | 2012-04-05 |
| 20120084512 | FAST UNALIGNED CACHE ACCESS SYSTEM AND METHOD - A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations. | 2012-04-05 |
| 20120084513 | CIRCUIT AND METHOD FOR DETERMINING MEMORY ACCESS, CACHE CONTROLLER, AND ELECTRONIC DEVICE - A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination. | 2012-04-05 |
| 20120084514 | LOCKING A CACHE LINE FOR WRITE OPERATIONS ON A BUS - Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line. | 2012-04-05 |
| 20120084515 | CACHE MEMORY CONTROLLER AND METHOD FOR REPLACING A CACHE BLOCK - The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring whether some of the blocks arranged in the same set of the cache memory have been modified in contents, and a cache block replacing unit for replacing a block, which has not been modified in contents, if some of the blocks arranged in the same set have been modified in contents. | 2012-04-05 |
| 20120084516 | METHODS AND APPARATUSES FOR DATA RESOURCE PROVISION - Methods and apparatuses are provided for data resource provision. A method may include receiving a request for a first data resource. The request may include an indication of an additional data resource that may be requested in a future request. The method may further include determining the indicated additional data resource. The method may additionally include causing caching of the additional data resource in preparation for a future request for the additional data resource. Corresponding apparatuses are also provided. | 2012-04-05 |
| 20120084517 | Shared Memory Between Child and Parent Partitions - A mechanism for the creation of a shared memory aperture between modes in a parent and child partition is described. The shared memory aperture can be created between any memory mode between the guest and any host. For example, a shared memory aperture can be created between the kernel mode on the child partition and the user mode on the parent partition. | 2012-04-05 |
| 20120084518 | SYSTEMS AND METHODS FOR RETAINING AND USING DATA BLOCK SIGNATURES IN DATA PROTECTION OPERATIONS - A system according to certain embodiments associates a signature value corresponding to a data block with one or more data blocks and a reference to the data block to form a signature/data word corresponding to the data block. The system further logically organizes the signature/data words into a plurality of files each comprising at least one signature/data word such that the signature values are embedded in the respective file. The system according to certain embodiments reads a previously stored signature value corresponding to a respective data block for sending from a backup storage system having at least one memory device to a secondary storage system. Based on an indication as to whether the data block is already stored on the secondary storage system, the system reads the data block from the at least one memory device for sending to the secondary storage system if the data block exists on the secondary storage system, wherein the signature value and not the data block is read from the at least one memory device if the data block exists on the secondary storage system. | 2012-04-05 |
| 20120084519 | SYSTEMS AND METHODS FOR RETAINING AND USING DATA BLOCK SIGNATURES IN DATA PROTECTION OPERATIONS - A system according to certain embodiments associates a signature value corresponding to a data block with one or more data blocks and a reference to the data block to form a signature/data word corresponding to the data block. The system further logically organizes the signature/data words into a plurality of files each comprising at least one signature/data word such that the signature values are embedded in the respective file. The system according to certain embodiments reads a previously stored signature value corresponding to a respective data block for sending from a backup storage system having at least one memory device to a secondary storage system. Based on an indication as to whether the data block is already stored on the secondary storage system, the system reads the data block from the at least one memory device for sending to the secondary storage system if the data block exists on the secondary storage system, wherein the signature value and not the data block is read from the at least one memory device if the data block exists on the secondary storage system. | 2012-04-05 |
| 20120084520 | Method and Apparatus for Efficient Memory Replication for High Availability (HA) Protection of a Virtual Machine (VM) - High availability (HA) protection is provided for an executing virtual machine. At a checkpoint in the HA process, the active server suspends the virtual machine; and the active server copies dirty memory pages to a buffer. During the suspension of the virtual machine on the active host server, dirty memory pages are copied to a ring buffer. A copy process copies the dirty pages to a first location in the buffer. At a predetermined benchmark or threshold, a transmission process can begin. The transmission process can read data out of the buffer at a second location to send to the standby host. Both the copy and transmission processes can operate asynchronously on the ring buffer. The ring buffer cannot overflow because the transmission process continues to empty the ring buffer as the copy process continues. This arrangement allows for using smaller buffers and prevents buffer overflows, and thereby, it reduces the VM suspension time and improves the system efficiency. | 2012-04-05 |
| 20120084521 | Managing Snapshots of Virtual Server - Configuration information and a system log are acquired for each of virtual servers running on an external computer, and the acquired system logs are analyzed. Relation information on the relation between the acquired configuration information and a configuration item indicating an existing snapshot, which is acquired from the same virtual server and stored, is extracted on the basis of the analysis result. Identification information for identifying the acquired configuration information is generated on the basis of the extracted relation information, and the acquired configuration information and system log are stored as a configuration item indicating a snapshot in association with the generated identification information. | 2012-04-05 |
| 20120084522 | VIRTUALIZATION CONTROL APPARATUS AND STORAGE SYSTEM - A virtualization control apparatus includes a selection unit that, when receiving a copy request, conducting an access test corresponding to the copy request on each of the virtualization switch units and selects one of the virtualization switch units of the highest performance among the plurality of the virtual switch units, and a sending unit that sends the copy request to the selected virtualization switch unit. | 2012-04-05 |
| 20120084523 | DATA RECOVERY OPERATIONS, SUCH AS RECOVERY FROM MODIFIED NETWORK DATA MANAGEMENT PROTOCOL DATA - The systems and methods herein permit storage systems to correctly perform data recovery, such as direct access recovery, of Network Data Management Protocol (“NDMP”) backup data that was modified prior to being stored in secondary storage media, such as tape. For example, as described in greater detail herein, the systems and methods may permit NDMP backup data to be encrypted, compressed, deduplicated, and/or otherwise modified prior to storage. The systems and methods herein also permit a user to perform a precautionary snapshot of the current state of data (e.g., primary data) prior to reverting data to a previous state using point-in-time data. | 2012-04-05 |
| 20120084524 | ARCHIVING DATA OBJECTS USING SECONDARY COPIES - A system for archiving data objects using secondary copies is disclosed. The system creates one or more secondary copies of primary copy data that contains multiple data objects. The system maintains a first data structure that tracks the data objects for which the system has created secondary copies and the locations of the secondary copies. To archive data objects in the primary copy data, the system identifies data objects to be archived, verifies that previously-created secondary copies of the identified data objects exist, and replaces the identified data objects with stubs. The system maintains a second data structure that both tracks the stubs and refers to the first data structure, thereby creating an association between the stubs and the locations of the secondary copies. | 2012-04-05 |
| 20120084525 | METHOD AND DEVICE FOR LOADING AND EXECUTING INSTRUCTIONS WITH DETERMINISTIC CYCLES IN A MULTICORE AVIONIC SYSTEM HAVING A BUS OF WHICH THE ACCESS TIME IS NOT PREDICTABLE - A method and device for loading and executing a plurality of instructions in an avionics system including a processor including at least two cores and a memory controller, each of the cores including a private memory. The plurality of instructions is loaded and executed by execution slots such that, during a first execution slot, a first core has access to the memory controller for transmitting at least one piece of data stored in the private memory thereof and for receiving and storing at least one datum and an instruction from the plurality of instructions in the private memory thereof, while the second core does not have access to the memory controller and executes at least one instruction previously stored in the private memory thereof and such that, during a second execution slot, the roles of the two cores are reversed. | 2012-04-05 |
| 20120084526 | NONVOLATILE MEMORY UNIT - An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit. | 2012-04-05 |
| 20120084527 | DATA BLOCK MIGRATION - Techniques and mechanisms are provided for migrating data blocks around a cluster during node addition and node deletion. Migration requires no downtime, as a newly added node is immediately operational while the data blocks are being moved. Blockmap files and deduplication dictionaries need not be updated. | 2012-04-05 |
| 20120084528 | System with Internal Memory for Storing Data or a Portion of Data Written to External Memory - A system includes an internal memory configured to store data, a memory access controller, logic, and a processor. The memory access controller is operable to read data from a peripheral device in response to an event external to the system, write the data to memory external to the system and forward the data or a portion of the data to the internal memory. The logic is operable to track which portion of the data is stored in both the external memory and the internal memory. The processor has one or more caches logically and physically separated from the internal memory. The processor is operable to retrieve the data forwarded to the internal memory and use the retrieved data to begin servicing the event. | 2012-04-05 |
| 20120084529 | ARRANGEMENTS FOR MANAGING METADATA OF AN INTEGRATED LOGICAL UNIT INCLUDING DIFFERING TYPES OF STORAGE MEDIA - A file system including: a first type storage medium; a second type storage medium; and a processor providing a file system using a first area in the first type storage medium and a second area in the second type storage medium, wherein the processor manages whether metadata is permitted to be stored in each of the first area and second area, stores a first file and first metadata of the first file in the first area, which is managed to permit storing metadata, migrates the first file stored in the file system to the second area, which is managed not to permit storing metadata, and changes the first metadata stored in the first area to point to a location of the first file in the second area. | 2012-04-05 |
| 20120084530 | Data Control Method, Data Controller, and Computer Program Product - According to one embodiment, a computer program product includes a non-transitory computer-readable storage medium having computer readable program codes embodied in the medium that are executed on a computer. The computer comprises a storage module that stores a plurality of contents. The use order in which the contents are used is determined. The codes, when executed on the computer, cause the computer to perform: transmitting the contents to an external device to store the contents therein; first determining whether each of the contents stored in the storage module satisfies use condition determined according to the use order; deleting content that does not satisfy the use condition from the storage module; second determining whether content, which is stored in the external device and is not stored in the storage module, satisfies the use condition; and receiving the content from the external device if the content satisfies the use condition. | 2012-04-05 |
| 20120084531 | ADJUSTING MEMORY ALLOCATION OF A PARTITION USING COMPRESSED MEMORY PAGING STATISTICS - Acceptable memory allocation for a partition is determined during and with minimal impact on normal operation of the partitioned system. The approach includes: collecting, by a processor, statistics on a rate at which pages are transferred between uncompressed and compressed memory spaces of the partition's memory; adjusting size of the uncompressed memory space; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resultant statistics in determining an acceptable memory allocation for the partition. In one implementation, the adjusting includes stepwise decreasing size of the uncompressed memory space by reallocating uncompressed memory space to compressed memory space, and repeating the collecting of statistics for a defined measurement period for each adjusted uncompressed memory space size until performance of the partition is negatively impacted by the reallocation of uncompressed memory space to compressed memory space. | 2012-04-05 |
| 20120084532 | MEMORY ACCELERATOR BUFFER REPLACEMENT METHOD AND SYSTEM - A microcontroller using an optimized buffer replacement strategy comprises a memory configured to store instructions, a processor configured to execute said program instructions, and a memory accelerator operatively coupled between the processor and the memory. The memory accelerator is configured to receive an information request and overwrite the buffer from which the prefetch was initiated with the requested information when the request is fulfilled by a previously initiated prefetch operation. | 2012-04-05 |
| 20120084533 | Efficient Parallel Floating Point Exception Handling In A Processor - Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication. | 2012-04-05 |
| 20120084534 | SYSTEM AND METHOD FOR FAST BRANCHING USING A PROGRAMMABLE BRANCH TABLE - Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function. | 2012-04-05 |
| 20120084535 | Opcode Space Minimizing Architecture Utilizing Instruction Address to Indicate Upper Address Bits - Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the upper address bits of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory. | 2012-04-05 |
| 20120084536 | PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION - A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed. | 2012-04-05 |
| 20120084537 | SYSTEM AND METHOD FOR EXECUTION BASED FILTERING OF INSTRUCTIONS OF A PROCESSOR TO MANAGE DYNAMIC CODE OPTIMIZATION - A filter executing on a processor monitors instructions executing on the processor to identify instructions that will benefit from performance tuning. Filtering instructions before analysis for performance tuning reduces overhead by identifying candidates for performance tuning with low cost monitoring before expending resources on analysis so that only instructions that will have performance tuning are analyzed. Reducing overhead for performance tuning makes performance tuning practical in a dynamic optimization environment in which instructions and their effective addresses change over time. | 2012-04-05 |
| 20120084538 | Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor - A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool. | 2012-04-05 |
| 20120084539 | METHOD AND SYTEM FOR PREDICATE-CONTROLLED MULTI-FUNCTION INSTRUCTIONS - Techniques are disclosed for executing conditional computer instructions in an efficient manner that reduces bubbles and idle states. In one embodiment, dual-function instruction execution is disclosed where the dual-function instruction has two possible functions (or operations), the choice of which is controlled by a predicate value with a true or false value. Among other things, the disclosed techniques provide dynamic control for choosing which operation to execute leading to more efficiently executed code. | 2012-04-05 |
| 20120084540 | DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT - A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith. | 2012-04-05 |
| 20120084541 | OPTIMIZATION OF PROCESSOR CHARACTERISTICS AND LARGE SCALE SYSTEM OPTIMIZATION THROUGH DOMAIN DECOMPOSITION - Systems and methods for optimizing processor requirements for a complex hardware system are disclosed. A set of complex hardware system configuration constraints are formulated as an objective function and a set of linear inequalities, and a convex polytope is formed from the set of linear inequalities. The objective function is optimized over the convex polytope using mixed integer linear programming means to obtain an optimal solution. Processor requirements for the complex hardware system are determined based on the optimal solution. | 2012-04-05 |
| 20120084542 | Multi-Operating System - A mobile computing device with a mobile operating system and desktop operating system running concurrently and independently on a shared kernel without virtualization. The mobile operating system provides a user experience for the mobile computing device that suits the mobile environment. The desktop operating system provides a full desktop user experience when the mobile computing device is docked to a secondary terminal environment. The mobile computing device may be a smartphone running the Android mobile OS and a full desktop Linux distribution on a modified Android kernel. | 2012-04-05 |
| 20120084543 | HARDWARE ACCELERATOR MODULE AND METHOD FOR SETTING UP SAME - A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators. | 2012-04-05 |
| 20120084544 | METHODS AND SYSTEMS FOR PROVIDING AND CONTROLLING CRYPTOGRAPHICALLY SECURE COMMUNICATIONS ACROSS UNSECURED NETWORKS BETWEEN A SECURE VIRTUAL TERMINAL AND A REMOTE SYSTEM - Methods and systems for securely connecting a client computer having a secure boot device to a remote server over a communications network are disclosed. One method includes booting a client computer from a trusted set of processing modules stored in the secure boot device, verifying the contents of the trusted set of processing modules prior to execution of these processing modules, and providing authentication information from data stored upon the secure boot device to an authentication server to establish a secure connection to the remote server. The method also includes establishing the secure connection with the remote server using encryption keys stored on the secure boot device, and transferring data between the client computer and the remote server over the secure connection to perform transactions initiated by a user of the client computer. In the disclosed method, the remote server utilizes encryption keys associated with a unique ID from the secure boot device. | 2012-04-05 |
| 20120084545 | METHODS AND SYSTEMS FOR IMPLEMENTING A SECURE BOOT DEVICE USING CRYPTOGRAPHICALLY SECURE COMMUNICATIONS ACROSS UNSECURED NETWORKS - A secure boot device, method, and system for securely connecting a client computer having a secure boot device to a remote server over a communications network are disclosed. The secure boot device includes a housing having an integrated communication interface, a controller located within the housing and operatively connected to the communication interface, and a memory communicatively connected to the programmable circuit and the communication interface. The memory securely stores program instructions including a boot module, a client terminal process module, an operating system module, and a secure communications interface module. The secure communications interface module includes program instructions for communicating split and encrypted data communicated between a computing system to which the communication interface is connected and a remote computing system. | 2012-04-05 |
| 20120084546 | Termination-log acquiring program, termination-log acquiring device, and termination-log acquiring method - A client terminal receives, in response to a boot command issued by a user to boot the client terminal, a first start command to start monitoring. The client terminal acquires first time information, repeatedly at certain time intervals from a basic software, and stores the first time information in a storage area. The client terminal receives a termination command to terminate the basic software. If the termination command is a command to terminate the basic software by using the basic software, the client terminal stores normal termination information in the storage area. When a second start command is received, and no normal termination information is stored in the storage area, the client terminal acquires second time information from the basic software and creates, depending on a result of comparison between the second time information and the first time information, log information relating to a termination of the basic software. | 2012-04-05 |
