14th week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130082690 | MEASURING ARRANGEMENT FOR DETECTING ALTERNATING CURRENTS - The invention relates to a measurement arrangement for connection to an energy and power meter and for connection to a Rogowski coil for detecting of alternating currents of a conductor being metered. The measurement arrangement has an integrator circuit to create a voltage signal proportional to the detected alternating current and a voltage/current converter to create an output current that is proportional to the voltage signal created by the integrator circuit. Furthermore, the invention relates to a measurement system that has an above-described measurement arrangement and a Rogowski coil for detecting of alternating currents of a conductor being metered. | 2013-04-04 |
20130082691 | HEADSET AND EARPHONE - A headset or earphone is provided, having an electro-acoustic reproduction transducer with an oscillator coil arranged in an axis. An amplifier is coupled to the electro-acoustic reproduction transducer. The headset or earphone also has a magnetic interference sensor for measuring a magnetic interference field. A correction unit, for analyzing an output of the magnetic interference sensor and for producing a compensation signal, is coupled to the magnetic interference sensor. In addition, the headset or earphone also includes an adding unit for adding the compensation signal to an input signal and for outputting the result to the amplifier. | 2013-04-04 |
20130082692 | Detector - An inductive detector operable to measure displacement along a path comprises:
| 2013-04-04 |
20130082693 | Device and method for processing signals which represent an angular position of a motor shaft - In an apparatus and a method for processing signals that represent an angular position of a shaft of a motor, a storage unit for storing arrival times of the signals in a memory is provided, the storage unit additionally evaluating a rotation direction datum of the shaft. Storage of the times in the memory is performed in a first sequence in the event of a rotation of the shaft in a first direction, and storage in the memory is performed in a second sequence that is opposite to the first sequence in the event of a rotation of the shaft in a second direction that is opposite to the first direction. | 2013-04-04 |
20130082694 | Hall-Effect Measurement Apparatus - A Hall-Effect measure apparatus comprises a magnetic source, a wafer on a thermal chuck, a dc current source and a voltage meter. The magnetic source generates a magnetic field in a perpendicular position relative to the wafer. Furthermore, the magnetic field is targeted at a specific region of the wafer to be tested. By performing a Hall-Effect measurement and van der Pauw measurement, the carrier mobility of the specific region of the wafer can be calculated. | 2013-04-04 |
20130082695 | CLOSED CORE CURRENT PROBE - A current probe enabling measurement of current of a signal in a circuit includes a ferrite core defining a gap, a wire wrapped around the ferrite core and a magnetic field sensor. The wire is configured to receive the signal from the circuit, where the current of the signal flowing in the wire generates a magnetic field in the ferrite core. The magnetic field sensor is positioned in the gap of the ferrite core, the magnetic field generated in the ferrite core flowing through the magnetic field sensor, which produces a voltage proportional to an intensity of the magnetic field. The current is measured based on the voltage produced by the magnetic field sensor. | 2013-04-04 |
20130082696 | MAGNETIC BIAS STRUCTURE FOR MAGNETORESISTIVE SENSOR HAVING A SCISSOR STRUCTURE - A scissor style magnetic sensor having a novel hard bias structure for improved magnetic biasing robustness. The sensor includes a sensor stack that includes first and second magnetic layers separated by a non-magnetic layer such as an electrically insulating barrier layer or an electrically conductive spacer layer. The first and second magnetic layers have magnetizations that are antiparallel coupled, but that are canted in a direction that is neither parallel with nor perpendicular to the air bearing surface by a magnetic bias stricture. The magnetic bias structure includes a neck portion extending from the back edge of the sensor stack and having first and second sides that are aligned with first and second sides of the sensor stack. The bias structure also includes a tapered or wedged portion extending backward from the neck portion. | 2013-04-04 |
20130082697 | MAGNETORESISTANCE SENSING DEVICE AND MAGNETORESISTANCE SENSOR INCLUDING SAME - A magnetoresistance sensing device includes a substrate, a magnetoresistance sensing unit, and a magnetic field adjusting unit. In response to a first external magnetic field horizontal to a surface of the substrate, the magnetoresistance sensing unit results in a change of an electrical resistance. The magnetic field adjusting unit is used for changing a direction of a second external magnetic field vertical to the surface of the substrate to be consistent with the first external magnetic field, so that the magnetoresistance sensing unit results in a change of the electrical resistance in response to the second external magnetic field. A magnetoresistance sensor includes four magnetoresistance sensing devices, which are arranged in a Wheatstone bridge. An output voltage of the Wheatstone bridge is not altered as the first external magnetic field is changed, but the output voltage of the Wheatstone bridge is altered as the second external magnetic field is changed. | 2013-04-04 |
20130082698 | CURRENT SENSOR - A current sensor includes a magnetic sensor including magnetoresistive sensors configured to detect induction fields generated by a measurement current passing through a current line, a magnetic field application unit configured to apply to the magnetoresistive sensors a magnetic field having a direction perpendicular to sensitivity directions of the magnetoresistive sensors; and a computing unit configured to calculate from an output of the magnetic sensor a compensation value for the output. The computing unit is configured to be capable of calculating the compensation value from the outputs of the magnetic sensor obtained in at least two states in which magnetic fields applied by the magnetic field application unit are different from each other. | 2013-04-04 |
20130082699 | Magnatoresistive Sensing Component and Agnatoresistive Sensing Device - A magnetoresistive sensing component includes a strip of horizontal magnetoresistive layer, a conductive part and a first magnetic-field-sensing layer. The strip of horizontal magnetoresistive layer is disposed above a surface of a substrate and has a first side and a second side opposite the first side along its extending direction. The conductive part is disposed above or below the horizontal magnetoresistive layer and electrically coupled to the horizontal magnetoresistive layer. The conductive part and the horizontal magnetoresistive layer together form at least an electrical current path. The first magnetic-field-sensing layer is not parallel to the surface of the substrate and magnetically coupled to the horizontal magnetoresistive layer at the first side of the horizontal magnetoresistive layer. | 2013-04-04 |
20130082700 | NUCLEAR MAGNETIC RESONANCE IMAGING APPARATUS AND NUCLEAR MAGNETIC RESONANCE IMAGING METHOD - The present invention has an object to provide a nuclear magnetic resonance imaging apparatus or the like that avoids a region with zero sensitivity of an optical magnetometer and allows imaging by strong magnetic resonance when a common magnetic field is used as a bias field of an optical magnetometer and as a magnetostatic field to be applied to a sample. When a direction of a magnetostatic field application unit applying a magnetostatic field to a sample is a z direction, alkali metal cell of a scalar magnetometer is arranged so as not to overlap a region to be imaged in a z direction, and so as not to intersect the region to be imaged in an in-plane direction perpendicular to the z direction. | 2013-04-04 |
20130082701 | NUCLEAR MAGNETIC RESONANCE IMAGING APPARATUS AND NUCLEAR MAGNETIC RESONANCE IMAGING METHOD - The present invention has an object to provide a nuclear magnetic resonance imaging apparatus or the like that avoids a region with zero sensitivity of an optical magnetometer and allows imaging by strong magnetic resonance when a common magnetic field is used as a bias field of an optical magnetometer and as a magnetostatic field to be applied to a sample. When a direction of a magnetostatic field application unit applying a magnetostatic field to a sample is a z direction, alkali metal cells of a plurality of scalar magnetometers are arranged so as not to overlap a region to be imaged in a z direction, and so as not to intersect the region to be imaged in an in-plane direction perpendicular to the z direction. | 2013-04-04 |
20130082702 | METHOD FOR DETERMINING MAGNETIC RESONANCE DATA AND A MAGNETIC RESONANCE SYSTEM - A method is disclosed for acquiring magnetic resonance (MR) data for a plurality of layers of an object to be examined in a section of a magnetic resonance system having a basic magnetic field, wherein the section is located at the edge of a Field of View of the magnetic resonance system in the first direction. The method includes producing a first gradient field having a non-linearity of its location dependence in such a way that in the section the non-linearity compensates a local inhomogeneity of the basic magnetic field, and then multiple positioning of the object to be examined in a first direction, so the plurality of layers of the object to be examined perpendicular to the first direction successively includes the section. Finally, it includes the acquisition of magnetic resonance data for each of the layers with recording sequences. | 2013-04-04 |
20130082703 | METHOD TO GENERATE MAGNETIC RESONANCE MEASUREMENT DATA WITH IMAGE CONTRAST SELECTED AND PRODUCED BY PREPARATION PULSES - In a method and magnetic resonance apparatus to generate magnetic resonance measurement data, k-space corresponding to the examination region is subdivided into a first region and a second region. The first region includes the k-space center, and a ratio of preparation pulses radiated by the radio-frequency antenna of the magnetic resonance apparatus to RF excitation pulses radiated by the radio-frequency antenna is greater in the first region than in a second region of k-space corresponding to the examination region that is not covered by the first region of k-space. Preparation pulses in the entirety of k-space corresponding to the examination region are therefore not radiated uniformly often, but instead a reduced number of preparation pulses is applied in the second region in comparison to the first region. The total measurement time to generate magnetic resonance data, as well as a SAR exposure, are reduced. | 2013-04-04 |
20130082704 | METHOD AND MAGNETIC RESONANCE APPARATUS FOR NON-SELECTIVE EXCITATION OF NUCLEAR SPIN SIGNALS IN AN EXAMINATION SUBJECT - In a method for non-selective excitation of nuclear spin signals in an examination subject with a magnetic resonance system, RF excitation pulses are radiated to excite nuclear spin signals in the examination subject with simultaneous switching of gradients for spatial coding of the excited nuclear spin signals, wherein the RF excitation pulses are designed such that the base frequency of a radiated RF excitation pulse is adapted to the simultaneously switched gradient. By the dynamic adaptation of the radiated RF excitation pulses to the respective simultaneously switched gradients, artifacts due to insufficiently excited nuclear spins in an examination region to be examined (in particular even in examination regions that are arranged off-center) are avoided. | 2013-04-04 |
20130082705 | MAGNETIC RESONANCE SYSTEM AND METHOD FOR TIME SYNCHRONIZATION OF DIFFERENT COMPONENTS OF A MAGNETIC RESONANCE SYSTEM - A method for time synchronization of various components of a magnetic resonance system includes generating a series of amplitude-modulated radio-frequency pulses and associated gradient fields to deflect the magnetization of a slice detecting at least two spin signals, determining a phase difference between two of the spin signals, processing the phase difference in order to determine at least one time shift between two of the following variables that are generated by different components of the magnetic resonance system, an envelope of the amplitude-modulated radio-frequency pulses, a radio-frequency portion of the amplitude-modulated radio-frequency pulses, and one or more gradient fields, and synchronizing the associated components of the magnetic resonance system depending on the at least one time shift. | 2013-04-04 |
20130082706 | LOCAL ANTENNA DEVICE FOR TRANSMITTING MAGNETIC RESONANCE SIGNALS - A local antenna device for transmitting magnetic resonance (MR) signals of a plurality of MR receiving antenna elements to an MR signal processing device is provided. The local antenna device includes a plurality of analog-to-digital converters for scanning the MR signals and converting the MR signals to digital MR data, and a plurality of transmitting antenna elements for wirelessly transmitting the digital MR data to the MR signal processing device by the emission of an electromagnetic field. The local antenna device includes a plurality of transmitting devices for triggering the transmitting antenna elements and a plurality of spacer elements that is arranged and embodied on the local antenna device such that at least a defined minimum emission spacing is produced between the plurality of transmitting antenna elements and articles adjoining the local antenna device in at least one direction of a principal axis of emission of the electromagnetic field. | 2013-04-04 |
20130082707 | Method for the Control of a Magnetic Resonance System - A method for the control of a magnetic resonance system is provided. In a test phase before a magnetic resonance measurement, a test high-frequency pulse with several parallel individual high-frequency pulses is transmitted with a transmitter antenna arrangement over various different high-frequency transmitter channels. At lower transmitter power, the test high-frequency pulse generates essentially the same field distribution as an excitation high-frequency pulse to be transmitted during a subsequent magnetic resonance measurement. A high-frequency field generated by this test high-frequency pulse is measured in at least one area of a local pulse arrangement, and on the basis of the high-frequency field measured, a high-frequency field value that is to be anticipated at the local coil arrangement during the subsequent magnetic resonance measurement is determined. The control of the magnetic resonance system during a later magnetic resonance measurement includes taking the high-frequency field value into account. | 2013-04-04 |
20130082708 | MAGNETIC RESONANCE IMAGING DEVICE AND TRANSMITTING SENSITIVITY DISTRIBUTION CALCULATION METHOD - B1 distribution is calculated in a short time with a high degree of precision, and a high quality image is obtained. In the RF shimming for irradiating electromagnetic waves using an RF coil having multiple channels, the absolute values of subtraction images between multiple reconstructed images are used to calculate a transmitting sensitivity distribution which is necessary for calculating inter-channel phase difference and amplitude ratio of RF pulses provided to the respective channels. Those multiple reconstructed images are obtained by executing the imaging sequence after applying a prepulse at different flip angles respectively. Assuming an image obtained with a minimum flip angle as a reference image, for instance, the subtraction images are created between the reference image and the other respective images. It is also possible that multiple subtraction images being obtained are divided by one another, and the transmitting sensitivity distribution is created on the basis of the division result. | 2013-04-04 |
20130082709 | PARALLEL MAGNETIC RESONANCE IMAGING USING GLOBAL VOLUME ARRAY COIL - A magnetic resonance imaging (MRI) apparatus comprises a plurality of cylindrical electromagnetic coils arranged in a coaxial configuration around a sample region. The coils are used to capture resonance signals from a sample at different times according to a geometric echo effect. The measurements can then be combined to produce an MRI signal. | 2013-04-04 |
20130082710 | SYSTEM FOR TRAVELLING WAVE MR IMAGING AT LOW FREQUENCIES AND METHOD OF MAKING SAME - A system for travelling wave MR imaging includes an MR imaging apparatus having a magnet coil assembly having a magnet coil bore extending therethrough, a gradient coil assembly positioned within the magnet coil bore and having a gradient coil bore extending therethrough, and a waveguide positioned within the gradient coil bore. The waveguide has a waveguide bore extending therethrough. A computer is programmed to access a scan sequence comprising an RF pulse sequence and execute the scan sequence. During execution of the scan sequence, the computer is programmed to operate the waveguide in a hybrid mode to transmit an RF pulse of the RF pulse scan sequence as a travelling wave at a frequency lower than a cutoff frequency of a principal mode of the waveguide absent a dielectric core and to acquire MR signals from an imaging subject positioned within the waveguide bore. | 2013-04-04 |
20130082711 | SIGNAL SPLITTER - A signal splitter for creating at least two symmetrical equal-power signals from an input signal for use in an amplifier device includes at least one input terminal pair and at least two output terminal pairs. A primary conductor structure supplied from the at least one input terminal pair is provided for induction of a current flow in at least two secondary conductor structures each connected to an output terminal pair of the at least two output terminal pairs and the at least two secondary conductor structures. A center of a conductor length of each of the at least two secondary conductor structures is connected to ground, and the primary conductor structure and the at least two secondary conductor structures are realized as conductor tracks applied to a printed circuit board. | 2013-04-04 |
20130082712 | MEDICAL IMAGING APPARATUS - A medical imaging apparatus includes a first imaging modality which is formed by a magnetic resonance apparatus and which comprises a cylindrical gradient coil unit, and a further imaging modality which comprises a detector unit. The detector unit of the further imaging modality is supported in a radial direction within an area surrounded by the gradient coil unit and an annular gap is disposed between the detector unit of the further imaging modality and the gradient coil unit. The further imaging modality includes a pressure unit which is disposed in the annular gap between the detector unit of the further imaging modality and the gradient coil unit. | 2013-04-04 |
20130082713 | WIND ENERGY INSTALLATION AND METHOD FOR TESTING A ROTATIONAL SPEED RELAY OF A WIND ENERGY INSTALLATION - The disclosure relates to checking a rotational speed relay of a wind turbine. The wind turbine comprises a rotational speed sensor for the rotational speed of a shaft. The rotational speed sensor outputs a rotational speed signal, which is fed to a signal input of the rotational speed relay. According to disclosure, the rotational speed signal fed to the rotational speed relay is first inactivated. Then a signal generator is activated, which produces a check signal equivalent to the rotational speed signal. The check signal is fed to the signal input of the rotational speed relay. The signal generator is operated with a check signal that is beyond a rotational speed limit, and a check is performed to determine if the rotational speed relay generates a switch-off command. This allows the functional capability of the rotational speed relay to be checked reliably and at low cost. | 2013-04-04 |
20130082714 | METHOD FOR INSULATION FAULT MONITORING WITH DYNAMIC RESPONSE CHARACTERISTIC - A method and device for insulation fault monitoring in ungrounded electrical networks. The method includes the following steps: measuring an insulation resistance, determining a responding value for the insulation resistance, and triggering a warning signal if the measured insulation resistance falls below the responding value, wherein the responding value is determined dynamically as a momentary responding value in a warning value establishment process downstream of the insulation resistance measurement. | 2013-04-04 |
20130082715 | INSULATION STATE DETECTION CIRCUIT FOR UNGROUNDED POWER SOURCE - An insulation state detection circuit includes a first charging circuit, a second charging circuit and a third charging circuit. A charging resistance value in the case that a capacitor is charged in the first charging circuit coincides with a charging resistance value in the case that the capacitor is charged in the second charging circuit when a resistance value of the ground fault resistor of a negative terminal side of a DC power source is a ground fault alarm threshold value for an insulation state of an alarm level. The charging resistance value of the first charging circuit coincides with a charging resistance value in the case that the capacitor is charged in the third charging circuit when a resistance value of the ground fault resistor of the positive terminal side is a ground fault alarm threshold value for an insulation state of an alarm level. | 2013-04-04 |
20130082716 | MONITORING MODULE AND METHOD FOR DETERMINING THE STATUS OF ELECTRICAL COMPONENTS - According to one example, there is provided a monitoring module for determining the status of electrical components in an array of N electrical components. The monitoring module comprises a resistance measurer to measure the resistance across a pair of diagnostic terminals, a comparator to compare the measured resistance with a set of reference resistances, and a diagnostic module to determine the status of at least one electrical component in the array based on the comparison. | 2013-04-04 |
20130082717 | METHOD AND APPARATUS FOR MEASURING PERFORMANCE OF ELECTRONIC DEVICE - A method and an apparatus for measuring performance of an electronic device are provided. The apparatus includes an electromagnetic wave measuring device for measuring an actual level of an electromagnetic wave of an electronic device, and an analysis controller for applying a previously stored level change value to the actual level of the electromagnetic wave to compute a measured level of the electromagnetic wave. The method and the apparatus for measuring performance of an electronic device can easily measure an electromagnetic wave level of the electronic device without using a device suggested by an international standard. | 2013-04-04 |
20130082718 | CIRCUIT TEST INTERFACE AND TEST METHOD THEREOF - A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad. | 2013-04-04 |
20130082719 | Sensor Patterns With Reduced Noise Coupling - A capacitive sense array configured to improve noise immunity in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements disposed in straight parallel lines along a first axis of the capacitive sense array. A second set of sense elements is disposed in crooked paths about a second axis of the capacitive sense array. The first and second sets form a capacitive sense array that includes crooked sense paths in at least one of the axes of the sense array. | 2013-04-04 |
20130082720 | RC CALIBRATION USING CHOPPING - A method and apparatus for determining an RC (resistive-capacitive) time constant is disclosed. In one embodiment, a method comprises determining a first period of oscillation when an oscillator is operating in a first configuration. The method further the method further comprises determining a second period of oscillation when the oscillator is operating in a second configuration. A measurement circuit is configured to determine a resistive-capacitive (RC) time constant of the oscillator by determining a mean of the first and second periods. | 2013-04-04 |
20130082721 | MECHANISMS FOR DETECTING TAMPERING OF AN ELECTRONIC DEVICE - An electronic device has a chassis, and a printed wiring board (PWB) having a hole. A fastener is installed in the hole thereby securing the PWB to the chassis. A pair of conductive traces is formed in the PWB. A cap, being an amount of conductive glue, covers a part of the fastener and fills an electrically insulating gap between the two traces, to thereby form a conductive path that connects the two traces. A sensing circuit is coupled to the traces, to detect a change in impedance of the path and signal a tamper event alert. Other embodiments are also described and claimed. | 2013-04-04 |
20130082722 | METHOD OF FORMING NANOPORE AND STRUCTURE FORMED WITH NANOPORE - The present invention relates to a method of forming a nanopore and a structure formed with the nanopore. The present invention relates to a method of forming a nanopore by preparing a first structure and a second structure having a surface on which nucleotides can be attached; attaching one ends of a plurality of oligonucleotides complementary to each other on the surface; binding the first structure and the second structure; and removing some of the bound oligonucleotides. The present invention is effective in that a pore of a desired size can be accurately formed by adjusting the length of the oligonucleotides. | 2013-04-04 |
20130082723 | Multi-Layered Support System - In various embodiments, a support system includes a cover sheet with an electrically conductive spacer material. | 2013-04-04 |
20130082724 | PV PANEL DIAGNOSIS DEVICE, DIAGNOSIS METHOD AND DIAGNOSIS PROGRAM - A PV panel diagnosis technology is provided which can surely find a deteriorated panel in a solar power generation system. A PV panel diagnosis device includes an adjusting unit that adjusts an impedance for a PV panel circuit connected with a plurality of PV panels, a measured-value storing unit that stores, as a measured value, a voltage or a current measured through the PV panel circuit in accordance with a change in the impedance, a change-amount determining unit that determines a change amount of the voltage or the current based on the measured value in accordance with the change in the impedance, and a specifying unit that specifies a deteriorated PV panel based on a comparison result of the change amount with a predetermined threshold. | 2013-04-04 |
20130082725 | POWER SWITCHING FOR ELECTRONIC DEVICE TEST EQUIPMENT - An apparatus, system and method are provided for testing a battery-powered electronic device-under-test in a transport frame engaged with a test fixture. A transport frame power supply is arranged to provide power to the DUT in a pre-testing stage. A switching circuit is arranged to switch from the transport frame power supply to a test fixture power supply in response to receiving a power switching signal indicating satisfaction of a pre-testing condition. Power from the test fixture power supply can then be switched back to the first transport frame, or to a second transport frame, to begin testing a second DUT. The ability to start a DUT test without having to wait for the DUT to boot-up in the test fixture reduces test time and increases efficiency of use of test equipment. | 2013-04-04 |
20130082726 | TEST STRUCTURE ACTIVATED BY PROBE NEEDLE - A test structure ( | 2013-04-04 |
20130082727 | WAFER TRAY, SEMICONDUCTOR WAFER TEST APPARATUS, AND TEST METHOD OF SEMICONDUCTOR WAFER - A wafer tray which holds a semiconductor wafer includes a wafer set plate on which the semiconductor wafer is set, a tray body which supports the wafer set plate to be able to finely move, and a vibration actuator which imparts vibration to the wafer set plate. | 2013-04-04 |
20130082728 | CIRCUIT-TEST PROBE CARD AND PROBE SUBSTRATE STRUCTURE THEREOF - A circuit-test probe card and a probe substrate structure thereof are disclosed herein to effectively narrow down the pitch of testing points of the circuit-test probe card. The circuit-test probe card utilizes the top and bottom surfaces of the probe substrate to respectively electrically connect with a circuit board and a plurality of probes. The probe substrate includes a main body having a plurality of upper contacts arranged on an upper surface thereof; and a plurality of wires penetrating the main body. Two ends of each wire are respectively exposed on the upper surface and a lower surface of the main body. The pitch of the wires exposed on the upper surface is larger than the pitch of the wires exposed on the lower surface. The wires are respectively electrically connected with the upper contacts. | 2013-04-04 |
20130082729 | Probe With Cantilevered Beam Having Solid And Hollow Sections - An electrically conductive probe can comprise a post to which a beam structure is attached. The beam structure can comprise a cantilevered portion that extends away from the post to a free end to which a contact structure can be attached. The cantilevered portion of the beam can include both a solid section and a hollow section. Multiple such probes can be used in a test contactor to make electrical connections with an electronic device such as a semiconductor die or dies to be tested. | 2013-04-04 |
20130082730 | Passive Probing of Various Locations in a Wireless Enabled Integrated Circuit (IC) - Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit. | 2013-04-04 |
20130082731 | SWITCHING MATRIX AND TESTING SYSTEM FOR SEMICONDUCTOR CHARACTERISTIC MEASUREMENT USING THE SAME - A switching matrix includes a plurality of input ports, a plurality of output ports, a plurality of switching devices configured to open and close, an electrical connection between the input ports and the output ports, and an electrical sensor configured to generate a signal by measuring a predetermined electrical property of the electrical connection, the open and close of switching devices is pre-determined by status read from the electrical sensor. | 2013-04-04 |
20130082732 | POWER TEST SYSTEM FOR TESTING OPERATION VOLTAGE OF POWER SUPPLY CIRCUIT OF COMPUTER - A power test system is provided for testing an operation voltage of a power supply circuit of a computer. The power test system includes a reference voltage circuit, a comparator circuit, and a display circuit. The reference voltage circuit generates a pair of reference voltages. The pair of reference voltages defines a voltage range therebetween. The comparator circuit receives the pair of reference voltages and the operation voltage, compares the operation voltage with the pair of reference voltages, generates a first signal when the operation voltage is within the voltage range, and generates a second signal when the operation voltage exceeds the voltage range. The display circuit illuminates a first color light in response to the first signal, and illuminates a second color light in response to the second signal. | 2013-04-04 |
20130082733 | SIGNAL PROCESSING SYSTEM - A signal route of a PUF (Physical Uncloneable Function) circuit is configured in each device. The signal route of each device is connected by a connection route to form a transmission route. An arbiter is connected at the end of the transmission route. A signal is transmitted in the transmission route from a device to a device. The arbiter monitors the signal passed through the transmission route, and generates an output signal reflecting a characteristic unique to the transmission route, based on monitoring results. The authentication of identity among a combination of a plurality of devices is enabled by examining the output signal. | 2013-04-04 |
20130082734 | LOGIC CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal. | 2013-04-04 |
20130082735 | LOGIC CIRCUIT PERFORMING EXCLUSIVE OR OPERATION AND DATA PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a logic circuit that includes a transistor T | 2013-04-04 |
20130082736 | SEMICONDUCTOR DEVICE INCLUDING MULTIPLE-INPUT LOGIC CIRCUIT WITH OPERATION RATE BALANCED WITH DRIVING ABILITY - A device includes first through third logic circuits. Each of first and second logic circuits includes a first circuit portion generating a first output signal in response to a first input signal when a second input signal takes a first logic level, and a second circuit portion transferring the first input signal to output the first output signal when the second input signal takes a second logic level. The third logic circuit includes a third circuit portion generating a second output signal in response to the first output signal supplied from the first logic circuit when the first output signal supplied from the second logic circuit takes a third logic level, and a fourth circuit portion generating the second output signal in response to the first output signal supplied with the first logic circuit when the first output signal supplied from the second logic circuit takes a fourth logic level. | 2013-04-04 |
20130082737 | SEMICONDUCTOR DEVICE HAVING SERIALIZER CONVERTING PARALLEL DATA INTO SERIAL DATA TO OUTPUT SERIAL DATA FROM OUTPUT BUFFER CIRCUIT - Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2 n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off. | 2013-04-04 |
20130082738 | DOUBLE DATA RATE CLOCK GATING - Methods, systems, and computer program products are provided to implement clock gating with double data rate (“DDR”) logic. In traditional single data rate (“SDR”) clock gating, disabling the clock holds the clock logic level to a predefined value, potentially causing a logic transition that would be erroneously interpreted as a normal clock transition by DDR logic. Similar techniques can also be utilized to convert a SDR clock to a half-frequency DDR clock for use with DDR logic, realizing the energy efficiencies of DDR clocking. | 2013-04-04 |
20130082739 | CLOCK DIAGNOSIS CIRCUIT - A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock. | 2013-04-04 |
20130082740 | CONFIGURABLE ANALOG FRONT END - An integrated circuit includes a configurable interface. The configurable interface includes an operational amplifier, a programmable gain amplifier, an analog-to-digital converter and a first select circuit. The first select circuit is configured to selectively couple the operational amplifier to the analog-to-digital converter in response to a first control signal. The first select circuit is further configured to selectively couple the programmable gain amplifier to the analog-to-digital converter in response to the first control signal. | 2013-04-04 |
20130082741 | Detection of the Zero Crossing of the Load Current in a Semiconductor Device - A circuit arrangement includes a reverse conducting transistor having a gate electrode and a load current path between an emitter and collector electrode. The transistor is configured to allow for conducting a load current in a forward direction and in a reverse direction through the load current path and activated or deactivated by a respective signal at the gate electrode. The circuit arrangement further includes a gate control unit and a monitoring unit. The gate control unit is connected to the gate electrode and configured to deactivate the transistor or prevent an activation of the transistor via the gate electrode when the transistor is in a reverse conducting state. The monitoring unit is configured to detect a sudden rise of a collector-emitter voltage of the reverse conducting transistor which occurs, when the load current crosses zero, while the transistor is deactivated or activation is prevented by the gate control unit. | 2013-04-04 |
20130082742 | LOAD DETECTING CIRCUITS AND THE METHOD THEREOF - A no-load detecting circuit and the method thereof are disclosed. The no-load detecting circuit may be applied in switching mode power supplies or other circuits. The no-load detecting circuit comprises: a variable resistance circuit coupled in series to a load of the switching mode power supply; and a first comparison circuit coupled to the variable resistance circuit to receive the voltage across the variable resistance circuit, wherein based on the comparison of the voltage across the variable resistance circuit and a first threshold, the first comparison circuit generates a no-load detecting signal indicative of the load status; wherein the equivalent resistance of the variable resistance circuit varies based on the varying of the load of the switching mode power supply. | 2013-04-04 |
20130082743 | SEMICONDUCTOR DEVICE GENERATES COMPLEMENTARY OUTPUT SIGNALS - A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies. | 2013-04-04 |
20130082744 | Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers - A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry. | 2013-04-04 |
20130082745 | DRIVING CIRCUIT AND DRIVING CONTROLLER CAPABLE OF ADJUSTING INTERNAL IMPEDANCE - A driving circuit includes a power supply, a plurality of conductive paths and a plurality of driving controller. The power supply is configured for providing a predetermined voltage. The conductive paths are connected to the power supply to receive the predetermined voltage. The driving controllers are connected to the conductive paths correspondingly. A first driving controller of the driving controllers has a first internal circuit configured for employing an internal voltage to perform functions provided by the first driving controller, and a resistance adjustment unit. The resistance adjustment unit is connected between a special conductive path and the first internal circuit. The second driving controller has a second internal circuit configured for employing a second internal voltage to perform functions provided by the second driving controller. A resistance value of the resistance adjustment unit is adjustable to make the first internal voltage same to the second internal voltage. | 2013-04-04 |
20130082746 | VERTICAL TRANSISTOR HAVING REDUCED PARASITIC CAPACITANCE - A transistor includes a substrate and an electrically conductive material layer stack positioned on the substrate. The electrically conductive material layer stack includes a reentrant profile. A first electrically insulating material layer positioned is in contact with a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally positioned in contact with the first electrically insulating layer, and conformally positioned in contact with a second portion of the electrically conductive material layer stack, and conformally positioned in contact with at least a portion of the substrate. | 2013-04-04 |
20130082747 | VARIABLE FREQUENCY RATIOMETRIC MULTIPHASE PULSE WIDTH MODULATION GENERATION - Groups of phase shifted PWM signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals. | 2013-04-04 |
20130082748 | PROGRAMMABLE DIVIDER - A technique includes controlling a modulus of a programmable divider, including selectively activating and deactivating cells of the divider. The activation for at least one of the cells includes configuring an output signal of the cell to exhibit a predetermined signal state when the cell transitions from a deactivated state to an activated state. | 2013-04-04 |
20130082749 | RESET GENERATOR - A reset circuit comprising: a first depletion mode device having a first terminal coupled to a node at a reset voltage and a second terminal for providing a reset signal to at least one device; and a control circuit arranged to switch the first depletion mode device into a high impedance state after a first predetermined period. | 2013-04-04 |
20130082750 | Electronic Circuit - An electronic circuit of the present disclosure includes a noise eliminating circuit configured to eliminate noise in a reset signal and output a signal obtained by eliminating the noise in the reset signal; a digital circuit configured to be reset by the signal outputted from the noise eliminating circuit; and an early-initialization circuit configured to fix an output signal of the digital circuit at a predetermined value until a reset status due to the reset signal is released. | 2013-04-04 |
20130082751 | CONTINUOUS SIGNAL GENERATOR - Disclosed herein is a continuous signal generator including: a synchronization circuit generating a synchronized clock signal; a signal source supplying a clock signal to the synchronization circuit; and a switch unit connected between the synchronization circuit and the signal source and selectively switched so as to allow the clock signal output from the signal source to be input to the synchronization circuit or feed back a clock signal output from the synchronization circuit to input the clock signal to the synchronization circuit. | 2013-04-04 |
20130082752 | RESISTOR LADDER BASED PHASE INTERPOLATION - An apparatus comprising a reference circuit, a resistor ladder, and an output circuit. The reference circuit may be configured to generate a reference signal in response to (i) a clock signal, (ii) a first phase signal and (iii) a second phase signal. The resistor ladder circuit may be configured to generate a tap voltage in response to the reference signal. The tap voltage may be generated by enabling one or more of a plurality of tap resistors. The output circuit may be configured to generate an adjusted clock signal in response to (i) the tap voltage, (ii) the clock signal, (iii) the first phase signal, (iv) the second phase signal, and (v) a reset signal. The adjusted clock signal may have an adjusted phase with respect to the clock signal. | 2013-04-04 |
20130082753 | APPLICATION OF PHASE-LOCKED LOOP (PLL) IN OSCILLATION MONITORING FOR INTERCONNECTED POWER SYSTEMS - The present invention relates to a method for accurately detecting oscillations and improving stability of power systems. The method includes the steps of providing a phase-locked loop having a phase detector, a loop filter, and a number-controlled oscillator. The method further includes the steps of extracting an input signal from the power system, using the phase-locked loop to track the frequency and phase of a targeted mode in the input signal, and creating a locally generated reference signal to fit the input signal and to allow the input signal's modal information to be obtained. The method further includes the step of performing mode shape analysis utilizing the reference phase signals constructed from the tracked frequencies. | 2013-04-04 |
20130082754 | PHASE LOCKED LOOP CALIBRATION - An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range. | 2013-04-04 |
20130082755 | FILTERING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference. | 2013-04-04 |
20130082756 | SIGNAL INPUT DEVICE OF DIGITAL-RF CONVERTER - The present invention provides a signal input device of a digital-RF converter including: a phase-modulated signal input unit configured to input a phase-modulated carrier signal to an LO switch of a digital-RF converter; and a digital signal input unit configured to correct a digital signal to correspond to the phase-modulated carrier signal, and input the corrected digital signal to a data switch of the digital-RF converter. | 2013-04-04 |
20130082757 | FLIP-FLOP CIRCUIT, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A flip-flop circuit (FF | 2013-04-04 |
20130082758 | SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER CIRCUIT IN WHICH IMPEDANCE THEREOF CAN BE CONTROLLED - Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off. | 2013-04-04 |
20130082759 | LEVEL SHIFTER AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SHIFTER - A level shifter for converting an input pulse signal of low-voltage amplitude to high-voltage amplitude includes a low voltage circuit configured to generate complementary-pulse signals of low-voltage amplitude from the input pulse signal, and a high voltage circuit configured to generate a pulse signal of high-voltage amplitude based on the complementary-pulse signals. The low voltage circuit, including high-threshold voltage transistors, includes a plurality of inverter circuits connected in cascade and at least one resistive-switch circuit connected between an input and an output of at least one of the plurality of inverter circuits configured to operate as a resistor when in a conductive state. | 2013-04-04 |
20130082760 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. | 2013-04-04 |
20130082761 | SEMICONDUCTOR DEVICE HAVING INPUT RECEIVER CIRCUIT THAT OPERATES IN RESPONSE TO STROBE SIGNAL - Disclosed herein is a device that includes an input receiver circuit activated by a strobe signal to generate an output signal by comparing a potential of an input signal with a reference potential, and a noise canceller cancelling noise superimposed on the reference potential due to a change in the strobe signal. | 2013-04-04 |
20130082762 | POWER SWITCH SERIES CIRCUIT AND CONTROL METHOD THEREOF - The present invention provides a power switch series circuit and its control method. The power switch series circuit includes a plurality of series modules, a control module and a drive module. At least one series module has a power switch and a detection module, and the detection module includes a detection unit and an isolation unit, so as to detect the overvoltage and output a voltage detection signal based on the detected voltage. The control module receives the voltage detection signal and outputs the corresponding control signal. The drive module amplifies the control signal to drive each power switch to turn ON or turn OFF. The control module outputs the corresponding control signal to turn off each power switch when the overvoltage happens. | 2013-04-04 |
20130082763 | CAPACITIVE SENSOR DEVICE - Provided is a capacitive sensor device capable of detecting the position and magnitude of external force with high accuracy. | 2013-04-04 |
20130082764 | APPARATUS AND METHOD TO COMBINE PIN FUNCTIONALITY IN AN INTEGRATED CIRCUIT - An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit. | 2013-04-04 |
20130082765 | SEMICONDUCTOR DEVICE AND SIP DEVICE USING THE SAME - A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit. | 2013-04-04 |
20130082766 | DUAL MODE SIGMA DELTA ANALOG TO DIGITAL CONVERTER AND CIRCUIT USING THE SAME - The present invention provides a dual mode sigma delta analog to digital converter (ADC), which only in one hardware implementation, used for low IF and near zero IF receiver. The dual mode sigma delta ADC comprises a first switched-capacitor integrator; a second switched-capacitor integrator; a quantizer; a feedback circuit and a mode device. By switching the mode device on or off, one could easily change the configuration of the disclosed ADC to decide the receiving signal falling in low-IF or near zero IF. | 2013-04-04 |
20130082767 | SIGNAL DISTRIBUTION AND RADIATION IN A WIRELESS ENABLED INTEGRATED CIRCUIT (IC) - Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit. | 2013-04-04 |
20130082768 | DIODE WITH CONTROLLABLE BREAKDOWN VOLTAGE - Disclosed is a diode. An embodiment of the diode includes a semiconductor body, a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a base region arranged between the first and second emitter regions and having a lower doping concentration than the first and second emitter regions. The diode further includes a first emitter electrode only electrically coupled to the first emitter region, a second emitter electrode in electrical contact with the second emitter region, and a control electrode arrangement including a first control electrode section, and a first dielectric layer arranged between the first control electrode section and the semiconductor body. At least one pn junction extends to the first dielectric layer or is arranged distant to the first dielectric layer by less than 250 nm. | 2013-04-04 |
20130082769 | DIFFERENTIAL PVT/TIMING-SKEW-TOLERANT SELF-CORRECTING CIRCUITS - Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor. | 2013-04-04 |
20130082770 | ELECTRONIC CIRCUIT HAVING BAND-GAP REFERENCE CIRCUIT AND START-UP CIRCUIT, AND METHOD OF STARTING-UP BAND-GAP REFERNCE CIRCUIT - An electronic circuit includes a band-gap reference circuit and a start-up circuit. The band-gap reference circuit includes an operational amplifier which has an output and first and second inputs. The band-gap reference circuit is configured to generate a predetermined reference voltage at the output of the operational amplifier after a start-up phase of the band-gap reference circuit. The start-up circuit includes at least one switch arranged to connect at least one current source to at least one of the inputs of the operational amplifier during the start-up phase, and to disconnect the at least one current source from the at least one of the inputs of the operational amplifier after the start-up phase. | 2013-04-04 |
20130082771 | RESOURCE POOLING AMPLIFIER - A new type of amplifier, herein designated a resource pooling amplifier, involves extended usage of one or more inductors that is implemented by sharing. The sharing is either by switching the inductor or inductors among more than one load terminal at the same time (e.g., a bridged configuration or two different loads terminals with different polarity requirements) or by using the inductor or inductors for more than one purpose at different times. The inductor or inductors may be time shared such as by allocating different phases of a clock. The inductor or inductors may also be shared by monitoring load requirements and using the inductor or inductors only when needed (leaving other inductor cycles for other loads). In addition, inductor sharing may be implemented during different application requirements such as if two or more loads are not needed at the same time in a system. These types of sharing may be combined. | 2013-04-04 |
20130082772 | DIGITALLY-SCALABLE TRANSFORMER COMBINING POWER AMPLIFIER - A digitally configurable transformer that performs switched transformer combining is disclosed. The flexible transformer includes switches that are dynamically configurable to efficiently combine RF power from power amplifier cores to achieve different power levels. The disclosed transformer is efficient at a broad range of power levels, leading to high power output efficiency. The transformer may be part of any power amplifier design that uses the transformer for power combining. | 2013-04-04 |
20130082773 | LINEARIZATION OF POWER AMPLIFIERS THROUGH DIGITAL IN-BAND PREDISTORTION FOLLOWED BY ANALOG PREDISTORTION - A system for implementing linearization of a radio frequency (RF) power amplifier (PA) in a base station, as well as various component circuitry for implementing said system. By means of a smart partitioning of the signal processing for predistortion between the analog domain and the digital domain, a more linear relationship between the digital input data and the output RF signal is achieved. Linearization of the PA's output signal is obtained using a mixed-signal apparatus. The digital baseband signal enters the RF signal source. The RF signal source comprises an in-band predistortion circuit, a micro-controller and digital modulator. The output of the digital modulator is an RF signal that enters the PA module. The PA module is composed of the PA and the RF power amplifier linearizer (RFPAL). The RFPAL comprises an RF predistortion circuit, and RF signal analyzer and a microcontroller. | 2013-04-04 |
20130082774 | LINEARITY POWER AMPLIFICATION DEVICE - A linearity power amplification device is provided. The device comprises a divider, a combiner, n−1 first signal paths, and a second signal path coupled between the divider and the combiner. The first signal path comprises a main invariable attenuator connected to the divider, a first power amplifier connected to the combiner, and a first attenuator and a first shifter coupled between the first power amplifier and the main invariable attenuator. The second signal path comprises a main amplification circuit, and an error calibration circuit. | 2013-04-04 |
20130082775 | Systems and Methods for Adaptive Power Amplifier Linearization - An exemplary system comprises a linearizer, a power amplifier, and a feedback block. The linearizer may be configured to use a predistortion control signal to add predistortion to a receive signal to generate a predistorted signal. The power amplifier may be configured to amplify power of the predistorted signal to generate a first amplified signal. The power amplifier may also add high side and low side amplifier distortion to the predistorted signal. The high side and low side amplifier distortion may cancel at least a portion of the predistortion. The feedback block may be configured to capture a feedback signal based on a previous amplified signal from the power amplifier, to determine high side and low side distortion of the captured feedback signal, and to generate the predistortion control signal based on the determined high side and low side distortion. | 2013-04-04 |
20130082776 | AMPLIFIER FOR RECEIVING OPTICAL SIGNALS COMPLEMENTARY TO EACH OTHER - An amplifier for detecting photocurrents complementary to each other is disclosed. The optical receiver includes two trans-impedance amplifiers (TIAs) each having the single phase arrangement, a level detector to detect an average level between respective outputs of the TIAs, a controller to detect a difference between each of the output of the TIA, and an offset canceller to bypass each of the photocurrents to compensate the output offset between two TIAs depending on the average level and the difference between two levels. | 2013-04-04 |
20130082777 | BIAS CONTROLLING APPARATUS - The present invention includes: a temperature compensation circuit for generating a digital signal corresponding to a temperature of a transistor and outputting a compensation bias current obtained by adding a control current to a reference bias current or by subtracting the control signal from the reference bias current using the generated digital signal; a characteristics compensation circuit for detecting a characteristics error of a mirror transistor connected to the transistor in parallel and for outputting a compensation signal to compensate the characteristics error; and a bias compensation circuit for compensating a bias power applied to the transistor using the compensation bias current and the compensation signal to output the compensated bias power. The present invention is capable of improving the performance of the transistor. | 2013-04-04 |
20130082778 | DIFFERENTIAL AMPLIFIER - In an embodiment are provided are a differential amplifier, a method of amplifying a differential input signal, a device including a differential amplifier, and a low voltage differential signaling receiver. | 2013-04-04 |
20130082779 | AMPLIFIER - To suppress the occurrence of distortion. There are included an initial-stage amplifier circuit PREA that receives an input signal IN, a first source-grounded transistor Tr | 2013-04-04 |
20130082780 | ACCURACY POWER DETECTION UNIT - Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection unit is disclosed that includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The first multiplier is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In some embodiments, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together. In some embodiments, the power detection unit is configured to compensate for mismatched transistors by applying offset voltages to bodies of transistors in the first and second transistor pairs. | 2013-04-04 |
20130082781 | VERIFYING OSCILLATION IN AMPLIFIERS AND THE MITIGATION THEREOF - A method is provided for detecting and mitigating oscillation in an amplifier. The amplifier is configured to sample a signal being amplified to determine whether the amplifier is oscillating. In addition, the status of the amplifier can be verified based on the apparent signal levels of the signals being amplified. The gain of the amplifier is then adjusted in accordance with whether the amplifier is oscillating or as necessary to maintain gain that is compatible with the system within which the amplifier is operating. | 2013-04-04 |
20130082782 | Circuit and Power Amplifier - A cascode circuit includes a first transistor and a second transistor. The first transistor and the second transistor are connected to make a cascode. In addition, the circuit has a block capacitance which is connected between a control terminal of the second transistor and a source terminal of the first transistor. In addition, the circuit has a feedback element which is connected between a drain terminal of the second transistor and a control terminal of the first transistor. | 2013-04-04 |
20130082783 | Semiconductor Device - Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits. | 2013-04-04 |
20130082784 | OSCILLATOR CALIBRATION APPARATUS AND OSCILLATOR CALIBRATION METHOD - An oscillator calibration apparatus includes a counter, a comparator and an adjusting unit. The counter is utilized for receiving a first clock signal and a second clock signal, and utilizing the first clock signal to sample the second clock signal to generate at least one counting value, where the first clock signal is generated from a first oscillator, and the second clock signal is generated from a second oscillator different from the first oscillator; the comparator is coupled to the counter, and is utilized for comparing the counting value with a predetermined value to generate at least one calibration signal; and the adjusting unit is coupled to the comparator, and is utilized for adjusting a frequency of the second oscillator according to the calibration signal. | 2013-04-04 |
20130082785 | Tunable signal source - The present disclosure provides a tunable signal source having a plurality of oscillator cores having a coupling input, a coupling output, and a power output that is common to each of the plurality of oscillator cores. Also included is a plurality of tunable phase shifters wherein corresponding ones of the plurality of tunable phase shifters are communicatively coupled between the coupling input and the coupling output of corresponding ones of the plurality of oscillator cores, thereby forming a loop of alternating ones of the plurality of oscillator cores and alternating ones of the plurality of tunable phase shifters. | 2013-04-04 |
20130082786 | CONFIGURABLE SPREAD SPECTRUM OSCILLATOR - A spread spectrum oscillator includes a high frequency oscillator circuit configured to oscillate at a first frequency, and a low frequency oscillator circuit configured to oscillate at a second frequency and resistively coupled to a current summing node of the high frequency oscillator circuit. The first frequency is higher than the second frequency. | 2013-04-04 |
20130082787 | Spin injection layer robustness for microwave assisted magnetic recording - A spin transfer (torque) oscillator (STO) with a non-magnetic spacer formed between a spin injection layer (SIL) and a field generation layer (FGL), and with an interfacial layer comprised of Fe | 2013-04-04 |
20130082788 | LOW NOISE OSCILLATOR HAVING PASSIVE IMPEDANCE NETWORK - Apparatus and methods are disclosed related to an oscillator that includes a sustaining amplifier. One such apparatus includes a resonant circuit configured to operate at a resonant frequency, a sustaining amplifier, and a passive impedance network. The resonant circuit can have a first terminal and a second terminal. The sustaining amplifier can include at least a first switch configured to drive the first terminal of the resonant circuit in response to an input at a first control terminal of the first switch. The passive impedance network can be configured to pass a bias to the first control terminal, such as a gate of a field effect transistor, of the first switch. The passive impedance network can be electrically coupled to the second terminal of the resonant circuit and can include at least one inductor. | 2013-04-04 |
20130082789 | OSCILLATION CIRCUIT AND OPERATING CURRENT CONTROL METHOD THEREOF - An oscillation circuit includes a condenser, a charging/discharging part configured to switch between charging and discharging of the condenser according to a control signal, a comparator configured to compare a voltage of the condenser with a reference voltage and output a comparison result signal, a flip-flop configured to be set or reset according to the comparison result signal, supply an output signal as the control signal to the charging/discharging part, and output the output signal as an oscillation signal, and a current control part configured to control an operating current of the comparator in correspondence with the voltage of the condenser. | 2013-04-04 |