| 14th week of 2014 patent applcation highlights part 26 |
| Patent application number | Title | Published |
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| 20140092643 | ELECTRONIC CONVERTER, AND RELATED LIGHTING SYSTEM AND METHOD OF OPERATING AN ELECTRONIC CONVERTER - An electronic converter may include transformer with a primary winding and a secondary winding, wherein the primary winding is coupled to an input for receiving a power signal, and wherein the secondary winding is coupled to an output including a positive terminal and a negative terminal for providing a power signal. The converter moreover may include an electronic switch arranged between the input and the primary winding, wherein the electronic switch is configured to control the current flow through the primary winding. Specifically, the converter may include a snubber circuit arranged between the secondary winding and the output. | 2014-04-03 |
| 20140092644 | SWITCHING POWER SUPPLY DEVICE AND METHOD FOR CIRCUIT DESIGN OF THE SWITCHING POWER SUPPLY DEVICE - A switching power supply device includes a rectifying circuit configured to rectify an AC voltage and to output a rectified voltage, a smoothing capacitor configured to smooth the rectified voltage and to output a smoothed voltage, a first DC-DC converter configured to convert the smoothed voltage into an intermediate voltage and to output the intermediate voltage, and a second DC-DC converter configured to convert the intermediate voltage into an output voltage and to output the output voltage substantially free of ripple. The first DC-DC converter is configured to perform a step-up operation, a step-up/down operation, and a step-down operation according to the smoothed voltage, and to output the intermediate voltage including a ripple or the intermediate voltage substantially free of ripple. | 2014-04-03 |
| 20140092645 | CONTROL CIRCUIT AND TERMINAL FOR CABLE COMPENSATION AND WAKE-UP OF PRIMARY-SIDE REGULATED POWER CONVERTER - A control circuit of a power converter is provided. It comprises a signal generation circuit generating an oscillation signal in accordance with an output load. A PWM circuit generates a switching signal according to a voltage-loop signal, a current-loop signal and the oscillation signal for regulating an output of the power converter. A regulation circuit receives a compensation signal for an output cable compensation and a wake-up. The compensation signal is coupled to increase a switching frequency of the switching signal once the output of the power converter is lower than a low-voltage threshold. The control circuit reduces the voltage drop of the output when the output load is changed. | 2014-04-03 |
| 20140092646 | Soft Switching Synchronous Quasi Resonant Converter - A switching circuit including a transformer having a primary and a secondary side; a first MOSFET switch coupled with the primary side; a primary current sensing device; a second MOSFET switch coupled with the secondary side; a secondary current sensing device; and a control circuit for driving the first and second MOSFET switches, wherein first and second switch are complementarily driven and wherein switching of the first and second MOSFET switches is controlled by the primary and secondary current sensing devices | 2014-04-03 |
| 20140092647 | FLYBACK CONVERTER AND METHOD FOR CONTROLLING A FLYBACK CONVERTER - A flyback converter includes a transformer and a controller operable for controlling a switch coupled in series with a primary winding of the transformer. The controller is configured to operate in multiple modes including a burst mode and a standby mode. In the burst mode, the controller generates a first plurality of discrete pulse groups to turn on the switch and a duration of each pulse in the first plurality of discrete pulse groups is determined by a first reference signal having a first predetermined voltage. In the standby mode, the controller generates a second plurality of discrete pulse groups to turn on the switch and a duration of each pulse in the second plurality of discrete pulse groups is determined by a second reference signal having a second predetermined voltage which is greater than the first predetermined voltage of the first reference signal. | 2014-04-03 |
| 20140092648 | SWITCH-MODE POWER SUPPLY CONTROL APPARATUS AND FLYBACK SWITCH-MODE POWER SUPPLY INCLUDING THE CONTROL APPARATUS - The present invention discloses a switch-mode power supply control apparatus comprising a PWM controller for outputting a driving signal and a short-circuit protection module coupled to a detection terminal. The detection terminal receives a zero-crossing detection voltage. If the time that the detection voltage input to the detection terminal is lower than a first reference voltage exceeds a predetermined time period, the short-circuit protection module determines that a short-circuit abnormal situation occurs, the short-circuit protection module outputs a short-circuit signal to the PWM controller, and the driving signal output by the PWM controller becomes a turn-off signal. If the short-circuit protection module does not detect the short-circuit abnormal situation, the PWM controller operates normally. The present invention further discloses a flyback switch-mode power supply comprising the switch-mode power supply control apparatus. The flyback switch-mode power supply has a low power consumption when a short-circuit protection is taking place. Also, the transformer will not be saturated, which may otherwise lead to the damage of the power transistor. Further, the present invention makes it easier to test the short-circuit performance. | 2014-04-03 |
| 20140092649 | CONTACTLESS INDUCTIVELY COUPLED POWER TRANSFER SYSTEM - A contactless inductively coupled power transfer system includes a power supply device and a power receiving device. The power supply device includes a primary winding for generating an electromagnetic field (EMF) in response to an AC current flow having an operating frequency. The power receiving device includes a resonant circuit outputting an output voltage to a load and including a secondary winding and a reactance element. The reactance element is capable of forming a parallel resonant LC circuit with the secondary winding that resonates at the operating frequency, and forming a series resonant LC circuit that resonates at the operating frequency, and that is to be connected in series to the load. | 2014-04-03 |
| 20140092650 | POWER TRANSMISSION SYSTEMS - An offshore wind farm includes a plurality of wind turbines connected to an onshore converter station by means of a distributed power transmission system. The power transmission system includes a series of offshore converter platforms distributed within the wind farm. Each converter platform includes a busbar carrying an ac voltage for the converter platform and to which the wind turbines are connected. Each converter platform also includes one or more converter transformers connected to the busbar and a series of one or more converter modules. The power transmission system includes dc transmission lines which deliver generated power back to the onshore converter station. | 2014-04-03 |
| 20140092651 | MICRO-INVERTER WITH IMPROVED CONTROL - The invention concerns an electrical module for adapting a first signal of a first system to a second signal of a second system, including:
| 2014-04-03 |
| 20140092652 | POWER SUPPLY DEVICE AND METHOD OF DETERMINING ABNORMALITY IN POWER SUPPLY DEVICE - A power supply device includes: a first switching element and a flywheel semiconductor element which are connected in series to a first DC power source in this order; and a reactor and a second DC power source which are connected in series in this order to a node between the first switching element and the flywheel semiconductor element. A second switching element and a charge circuit for charging a line between the first switching element and the second switching element are interposed between the reactor and the second DC power source. Abnormality of each element is determined from a voltage of each portion of the power supply device measured when the first and second switching elements and the flywheel semiconductor element are driven and controlled. | 2014-04-03 |
| 20140092653 | ELECTRONIC CIRCUIT OPERATING BASED ON ISOLATED SWITCHING POWER SOURCE - In an electronic circuit, a first circuit region is electrically connected to an input circuit region of an isolated switching power source, and a second circuit region is electrically connected to an output circuit region thereof. A driver of an IC is located in the second circuit region and drives a target device based on output power supplied to the second circuit region via the output circuit region from the isolated switching power source. A transferring module of the IC transfers a value of a parameter indicative of the output power from the second circuit region to the first circuit region while maintaining electrical isolation between the first and second circuit regions. An operating module of the IC performs on-off operations of a switching element to perform feedback control of the value of the parameter indicative of the output power to a target value. | 2014-04-03 |
| 20140092654 | METHOD FOR THE OPERATION OF AN INVERTER, AND INVERTER - The invention relates to a method for operating an inverter ( | 2014-04-03 |
| 20140092655 | Power Converter - A power converter includes an inverter unit that includes a plurality of semiconductor switching elements constituting upper and lower arms and converts DC power into AC power; a gate driving unit that outputs, to the inverter unit, a gate signal used to drive gates of the plurality of semiconductor switching elements; a driving control unit that supplies the gate driving unit with a switching control signal used for the gate driving unit to output the gate signal; a first abnormality detection unit that performs over voltage detection of the DC power and over current detection of the AC power and temperature detection of the upper and lower arms; and a second abnormality detection unit that detects abnormality of the plurality of semiconductor switching elements of the upper arm and lower arms, wherein the driving control unit includes a first protection circuit and a second protection circuit. | 2014-04-03 |
| 20140092656 | POWER SUPPLY CIRCUIT - A power supply circuit is intended to suppress power consumption when a load is not driven and to shorten a required time to be taken until a boosted voltage to be supplied to a high-side MOS transistor is stabilized when the load is changed from a deactivated state to an activated state. | 2014-04-03 |
| 20140092657 | OPERATION CONTROL APPARATUS FOR SOLAR POWER SYSTEM - An operation control apparatus includes a criterion calculator that obtains an operation criterion for the power converter, based on the voltage detected by the above voltage detector on the side of the alternating-current power system, a direct-current voltage detector that detects a direct-current output voltage of the solar battery, and an operation determination device that compares the direct-current output voltage detected by the direct-current voltage detector with the operation criterion obtained by the criterion calculator, and supplies the power converter with an operation command if the direct-current output voltage is greater than the operation criterion. | 2014-04-03 |
| 20140092658 | POWER CONVERSION APPARATUS - A power conversion apparatus includes a power converter and a PWM controller. A first switching element is coupled to a positive pole of a DC power source and one terminal of a load. A second switching element is coupled to a negative pole of the DC power source and another terminal of the load. A third switching element is coupled to the positive pole and the other terminal. A fourth switching element is coupled to the negative pole and the one terminal. The PWM controller PWM-controls the power conversion apparatus to repeat an on-period during which the DC power source outputs a voltage to the load and an off-period during which no voltage is output. The PWM controller alternately controls the first and second switching elements based on a signal set at a high or low level any time during a carrier wave period. | 2014-04-03 |
| 20140092659 | WIRELESS POWER TRANSMISSION DEVICE - A wireless power transmission device includes a power transmitter, a first transmission unit, a power receiver, a feedback regulator, a receive controller, and a second transmission unit. The power transmitter is for generating power, and the first transmission unit is for wirelessly transmitting power generated by the power transmitter. The power receiver is for receiving and rectifying the power from the first transmission unit. The feedback regulator is for receiving a feedback signal from the power receiver to generate an AC control signal. The receive controller is for receiving the control signal to generate a driving signal. The second transmission unit is for wirelessly transmitting the control signal to the receive controller. | 2014-04-03 |
| 20140092660 | MULTILEVEL CONVERTER SYSTEM - A power converter includes at least one leg with a first string including a plurality of controllable semiconductor switches, a first connecting node, and a second connecting node, wherein the first string is operatively coupled across a first bus and a second bus. The at least one leg also includes a second string operatively coupled to the first string via the first connecting node and the second connecting node, wherein the second string includes a plurality of switching units. The first string includes a first branch and a second branch, wherein the second branch is operatively coupled to the first branch via a third connecting node and the third connecting node is coupled to a ground connection. | 2014-04-03 |
| 20140092661 | MULTILEVEL CONVERTER SYSTEM - A power converter is presented. The power converter includes at least one leg, the at least one leg includes a first string, where the first string includes a plurality of controllable semiconductor switches, a first connecting node, and a second connecting node, and where the first string is operatively coupled across a first bus and a second bus. Furthermore, the at least one leg includes a second string operatively coupled to the first string via the first connecting node and the second connecting node, where the second string includes a plurality of switching units. A method for power conversion is also presented. | 2014-04-03 |
| 20140092662 | DC TO AC CONVERSION CIRCUIT - A DC to AC conversion circuit including an inverter, a first inductor, a first capacitor, a second inductor and a second capacitor is provided. The inverter has two input contact points and two output contact points. The input contact points receive a DC signal, and the output contact points output an AC signal. The first terminal of the first inductor is coupled to one of the two output contact points. The first capacitor is coupled to the first inductor in parallel. The first terminal of the second capacitor is coupled to the second terminal of the first inductor, and the second terminal of the second capacitor is coupled to another one of two output contact points. The first terminal of the second inductor is coupled to the first terminal of the second capacitor, and the second terminal of the second inductor is coupled to a load. | 2014-04-03 |
| 20140092663 | ELECTRIC POWER CONVERTER - An electric power converter includes a stacked body in which a plurality of semiconductor modules and a plurality of coolers are stacked. Each of the semiconductor modules is provided with a main body that has semiconductor elements therein, a plurality of power terminals, and control terminals. Among the plurality of the power terminals respectively included in the two semiconductor modules adjoining in a stacking direction of the stacked body, at least parts of the power terminals are configured so as not to overlap each other when viewed from the stacking direction. | 2014-04-03 |
| 20140092664 | Associative Memory Oscillator Array - An embodiment of the invention includes an analog associative memory, which includes an array of coupled voltage or current controlled oscillators, that matches patterns based on shifting frequencies away from a center frequency of the oscillators. The test and memorized patterns are programmed into the oscillators by varying the voltage or current that controls the oscillators. Matching patterns result in smaller shifts of frequencies and enable synchronization of oscillators. Non-matching patterns result in larger shifts and preclude synchronization of oscillators. In one embodiment the patterns each include binary data and the pattern matching is based on discrete shifts. In one embodiment the patterns each include grayscale data and the pattern matching is based on continuously-varied shifts. Other embodiments are described herein. | 2014-04-03 |
| 20140092665 | SEMICONDUCTOR MEMORY DEVICE - A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates. | 2014-04-03 |
| 20140092666 | LOW VOLTAGE EMBEDDED MEMORY HAVING CONDUCTIVE OXIDE AND ELECTRODE STACKS - Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer. | 2014-04-03 |
| 20140092667 | Data storage in memory array with less than half of cells in any row and column in low-resistance states - A method of storing data in a memory array with less than half of memory elements in any row and column in a low-resistance state. The data are arranged in a first portion of an encoding array. High-resistance values are entered in a second portion. A codeword is selected from a covering code for each row in which too many entries have low-resistance values. The selected codeword is used to reduce the number of low-resistance values in that row. A codeword is selected for each column in which too many entries have low-resistance values and the codeword is used to reduce the number of such values in that column. The process is repeated until no row and no column has too many low-resistance values. The array entries are stored in corresponding memory elements. | 2014-04-03 |
| 20140092668 | RESISTIVE SWITCHING DEVICES AND MEMORY DEVICES INCLUDING THE SAME - A resistive switching device includes a first material layer between a first electrode and a second electrode. The first material layer has a first region and a second region parallel to the first region. The first region corresponds to a conducting path formed in the first material layer, and is configured to switch from a low-resistance state to a high-resistance state in response to an applied voltage that is greater than or equal to a first voltage. The second region is configured to switch to a first resistance value that is less than a resistance value of the first region in the high-resistance state when the applied voltage is greater than or equal to a second voltage. The first region remains constant or substantially constant when the second region has the first resistance value. | 2014-04-03 |
| 20140092669 | NON-VOLATILE VARIABLE RESISTIVE ELEMENT, CONTROLLING DEVICE AND STORAGE DEVICE - A non-volatile variable resistive element according to an embodiment comprises a first electrode including a first metal, a second electrode including a second metal, a third electrode placed opposite to the first and second electrodes, and a variable resistive layer placed between the first and second electrodes and the third electrode, a resistance of the variable resistive layer reducing when at least either one of the first metal and the second metal is diffused into the variable resistive layer and the resistance of the variable resistive layer rising when at least either one of the first metal and the second metal diffused into the variable resistive layer is collected by the first electrode or the second electrode. | 2014-04-03 |
| 20140092670 | NON-VOLATILE RESISTIVE MEMORY DEVICES AND METHODS FOR BIASING RESISTIVE MEMORY STRUCTURES THEREOF - The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor. | 2014-04-03 |
| 20140092671 | CROSS-POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE - A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a reference voltage generation circuit which comprises at least the current steering element; a differential amplifier circuit which performs current amplification on an output voltage in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which sets the low voltage side reference voltage to increase with an output of the differential amplifier circuit; and a sense amplifier circuit which determines a resistance state of a selected memory cell according to an amount of current flowing through the selected memory cell. | 2014-04-03 |
| 20140092672 | POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation. | 2014-04-03 |
| 20140092673 | MEMORY CELL - This invention relates generally to a memory cell. The embodiments of the present invention provide a SRAM cell and a SRAM cell array comprising such SRAM cell. The SRAM cell according to the embodiments of the present invention includes a pull-up transistor and a pull-down transistor, such that it is unnecessary to pre-charge a pre-read bit line at the time of performing read operation. By adopting the method of the present invention, generation of leakage current can be suppressed and hence power consumption of SRAM chip can be reduced. | 2014-04-03 |
| 20140092674 | Circuits and Methods of a Self-Timed High Speed SRAM - Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power. | 2014-04-03 |
| 20140092675 | TWO-PORT SRAM WRITE TRACKING SCHEME - A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit. | 2014-04-03 |
| 20140092676 | Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. | 2014-04-03 |
| 20140092677 | DECREASED SWITCHING CURRENT IN SPIN-TRANSFER TORQUE MEMORY - Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell. | 2014-04-03 |
| 20140092678 | INTELLIGENT FAR MEMORY BANDWITH SCALING - Memory bandwidth management. In a two-level memory (2LM) system far memory bandwidth utilization at least a far memory is monitored and the available far memory bandwidth availability is dynamically modified based on monitored far memory bandwidth utilization. The operational state of at least one processing core is dynamically modified in response to modification of available far memory bandwidth. | 2014-04-03 |
| 20140092679 | MEMORY DEVICE AND WRITING METHOD THEREOF - A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability. | 2014-04-03 |
| 20140092680 | MULTIPLE WELL BIAS MEMORY - A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage. | 2014-04-03 |
| 20140092681 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials. | 2014-04-03 |
| 20140092682 | METHOD FOR PROGRAMMING AND READING FLASH MEMORY BY STORING LAST PROGRAMMING PAGE NUMBER - The invention is to provide a method for programming and reading a flash memory, storing the last programming page in a block while programming the flash memory, judging the programming times in the cell of the block by means of the last programming page and the order and distribution of the page in the predefined page distribution list of the block while reading the flash memory, and selecting the predefined voltage based on the judged programming times to implement the reading process for raising reading performance. | 2014-04-03 |
| 20140092683 | ADJUSTABLE READ TIME FOR MEMORY - A method facilitates controlling a read time (tREAD) of an electronic memory device. The method includes implementing a first read time indicative of an array time for a read process for a memory array of the electronic memory device. The first read time relates to the time allocated to make data available at an I/O buffer of the electronic memory device for access by a controller. The method also includes implementing a second read time for the electronic memory device. The second read time has a total duration which is different from the first read time. In this way, different read times can be implemented for read operations at the same electronic memory device. The read times may be changed automatically based on one or more performance parameters (e.g., RBER, P/E count, etc.) of the electronic memory device. | 2014-04-03 |
| 20140092684 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. | 2014-04-03 |
| 20140092685 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. | 2014-04-03 |
| 20140092686 | VERTICALLY-INTEGRATED NONVOLATILE MEMORY DEVICES HAVING LATERALLY-INTEGRATED GROUND SELECT TRANSISTORS - Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines. | 2014-04-03 |
| 20140092687 | METHOD, APPARATUS, AND MANUFACTURE FOR STAGGERED START FOR MEMORY MODULE - A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory. | 2014-04-03 |
| 20140092688 | Non-Volatile Semiconductor Storage Device - In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line. | 2014-04-03 |
| 20140092689 | METHOD FOR PROGRAMMING NON-VOLATILE MEMORY CELL, NON-VOLATILE MEMORY ARRAY AND NON-VOLATILE MEMORY APPARATUS - A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure. | 2014-04-03 |
| 20140092690 | Variable Rate Parallel to Serial Shift Register - A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to I conversion, data is received from an (N×m)-wide parallel data bus in an N by in wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent. | 2014-04-03 |
| 20140092691 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a first data line and is turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line. A second amplifier is coupled to the first data line and amplifies, when activated, the first data signal, and is further coupled to the first signal line and activated in response to a first activation signal that is transferred through a first signal line. A second transistor is coupled to the first signal line and is turned ON in response to the first selection signal to the first signal line. | 2014-04-03 |
| 20140092692 | Variable Rate Serial to Parallel Shift Register - A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data. | 2014-04-03 |
| 20140092693 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device may test a semiconductor memory device by storing a data sample that is sampled from among data requested to be written into a semiconductor memory device and by comparing the data sample with data read from the semiconductor memory device which corresponds to the data sample. | 2014-04-03 |
| 20140092694 | MULTI-BIT RESISTANCE MEASUREMENT - An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell. | 2014-04-03 |
| 20140092695 | HEADER CIRCUIT FOR CONTROLLING SUPPLY VOLTAGE OF A CELL - One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example. | 2014-04-03 |
| 20140092696 | POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation. | 2014-04-03 |
| 20140092697 | READ TIMING GENERATION CIRCUIT - Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add | 2014-04-03 |
| 20140092698 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device may comprise monitoring error handling information corresponding to an address of a semiconductor memory device, setting a refresh period for the address considering the error handling information and requesting a refresh request for the address. | 2014-04-03 |
| 20140092699 | INTERMEDIATE CIRCUIT AND METHOD FOR DRAM - An intermediate circuit and method for hiding refresh confliction. The intermediate circuit includes: a first control circuit configured to generate a Command Output Enable signal CON, a Data Read Enable signal DRN and a Refresh Enable signal REFN based on the second clock, wherein a ration of duration the signal CON is in a first state to duration in a second state equals to CLK | 2014-04-03 |
| 20140092700 | FINE GRANULARITY POWER GATING - Rows of a memory array are segmented into a predetermined number of word line groups. Each row in a word line group has a word line disposed between parallel power supply lines. Each of the power supply lines in a row of a word line group is shared by an adjacent row in the word line group. A row on a boundary of a word line group has a power supply line shared by a row on a boundary of an adjacent word line group. All power supply lines in a word line group are at a full power voltage in response to one of the rows in the word line group being selected by a word line. Most power supply lines in an adjacent word line group are at a full power voltage. All power supply lines in other word line groups are at a power-gated voltage. | 2014-04-03 |
| 20140092701 | MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed. | 2014-04-03 |
| 20140092702 | Blender - A blending device ( | 2014-04-03 |
| 20140092703 | MULTI-COMPARTMENT CONTAINER WITH IN CONTAINER MIXING - A multi-component mixing device comprising an outer container and an inner vessel. The outer container comprises a closed end, a mouth and a peripheral wall between said closed end and said mouth. The inner vessel is disposed within said outer container and the inner vessel comprises a top portion, a bottom portion and a peripheral side wall between said top portion and bottom portion. The peripheral side wall of the inner vessel is defined by first and second sections, which are slidably engaged to one another between a first position and a second position. In the first position, the inner vessel defines an enclosed cavity and in the second position, the inner vessel comprises a first opening corresponding to the enclosed cavity. | 2014-04-03 |
| 20140092704 | MIXING AND DISPENSING CURABLE MULTI-COMPONENT MATERIALS - Methods, apparatus, devices and systems for mixing and dispensing multi-component materials. The mixing and dispensing may be performed using a mobile, enclosed dispenser that can be used to supply a mixed multi-component material at the point of use. In some embodiments, the components to be mixed into the multi-component material may be supplied in cartridges. | 2014-04-03 |
| 20140092705 | ADDITIVE SYSTEM FOR USE WITH POST MIX DISPENSING MACHINE - An additive system is used with a post mix dispensing machine having a liquid inlet, and a supply of an additive for mixing with the liquid from the liquid inlet. A pump, having an additive inlet and an additive outlet, is coupled to a source of power. An additive supply line is coupled to the additive inlet. The additive supply line is coupleable to a source of an additive. A liquid delivery line connects the liquid inlet to a mixture delivery outlet. An additive delivery line connects the additive outlet to a mixing point along the liquid delivery line. An additive flow adjuster is used to control the flow of additive from the pump. Additive flowing through the additive delivery line mixes with liquid flowing through the liquid delivery line for passage to the mixture delivery outlet. | 2014-04-03 |
| 20140092706 | CENTRIFUGAL PROCESSING DEVICE - A centrifugal processing device has structures in which a storage container housing a material is supported such as to rotate freely by a revolving body with a rotating shaft therebetween, and that applies revolution force and rotation force of the storage container to the material by rotating the storage container while revolving the storage container. Rotating shafts and are supported by the revolving body such as to intersect a revolving body center line of the revolving body. | 2014-04-03 |
| 20140092707 | Operational Mode Switching in Seismic Data Acquisition Module via Supply Voltage Polarization - Described herein are various embodiments of methods and corresponding hardware and software that are configured to permit a seismic data acquisition module to switch between a data acquisition operational mode and a USB data downloading mode according to the sensed polarity of an external power supply that is connected to the module. | 2014-04-03 |
| 20140092708 | PLURAL-DEPTH BURIED SEISMIC SENSORS ACQUISITION SYSTEM AND METHOD - A system for collecting seismic data includes plural seismic sensors. The seismic sensors are buried underground. In one application, a first set of seismic sensors are buried at a first depth and a second set of seismic sensors are buried at a second depth. In another application, the sensors alternate along a line, one sensor from the first set and a next sensor from a second set. In still another application, the sensors are randomly distributed below the ground. | 2014-04-03 |
| 20140092709 | PVDF SONAR TRANSDUCER SYSTEM - A sound navigation and ranging (SONAR) transducer system comprises a transmit element and a receive element. The transmit element may be formed from ceramic material and configured to transmit an ultrasonic signal into a body of water. The transmit element may include a first component configured to transmit the ultrasonic signal in a first direction and a second component configured to transmit the ultrasonic signal in a second direction. The receive element may be formed from polyvinylidene difluoride (PVDF) in the shape of a sheet of material and configured to receive a reflection of the ultrasonic signal after the ultrasonic signal is reflected from objects in the body of water. The receive element may include a first section configured to receive reflections from the first direction and a second section configured to receive reflections from the second direction. | 2014-04-03 |
| 20140092710 | METHOD AND SYSTEM FOR LOCATING AN ACOUSTIC SOURCE - A method and a system are provided, in which acoustic signals received by distributed acoustic sensors are processed in order to determine the position of a source or sources of the acoustic signals. The method and system are able to determine the position of several acoustic sources simultaneously, by measuring the corresponding several acoustic signals. Furthermore, the strength of the acoustic signal or signals can be determined. The location of the acoustic source may be overlaid on a map of an area being monitored, or be used to generate an alarm if perceived to correspond to a threat or an intrusion, for example in a pipeline monitoring application. Alternatively, the method and systems can be used to monitor a hydraulic fracturing process. | 2014-04-03 |
| 20140092711 | METHOD FOR IDENTIFYING A SEISMIC EVENT AND A SEISMIC DETECTOR FOR IMPLEMENTING SAME - A method for identifying a seismic even makes it possible to determine the direction to a source of a seismic disturbance both on the surface and in a three-dimensional space and increases the probability of correct identification of a seismic event and the accuracy of the determination of the direction to the source. A compact seismic detector for implementing the method reduces the cost of scanning and servicing a perimeter protection system constructed on the basis of such detectors. In the method, two or three pairs of seismic sensors which are divided by a distance and are oriented at an angle with respect to one another, for example mutually perpendicularly along the axes X, Y or along the axes X, Y, Z, respectively, are combined to form one seismic detector. The resultant seismic data are processed to determine the direction to the source of the seismic disturbance. | 2014-04-03 |
| 20140092712 | Sonotrode with Processing Channel - The present invention relates to an ultrasonic sonotrode with a main sonotrode body and a sealing area arranged on one side of the main sonotrode body. The main sonotrode body has two through-slits extending in or through the main sonotrode body respectively along a slit axis. These through-slits intersect in such a way that a through-channel through the main sonotrode body is formed from the one through-slit into the other through-slit. This creates a slit portion that is formed both by the one through-slit and the other through-slit. Provided in this main sonotrode body is a processing channel, which extends along a processing channel axis from a side area of the main sonotrode body up to the through-channel and is arranged substantially symmetrically about the processing channel axis. | 2014-04-03 |
| 20140092713 | METHOD, DEVICE, SERVER, AND SYSTEM FOR CONFIGURING DAYLIGHT SAVING TIME - The present invention discloses a method, a device, a server, and a system for configuring daylight saving time, belonging to the field of communications. The method includes: receiving, by a CPE, a message carrying a daylight saving time rule parameter; if a daylight saving time enable flag displays that daylight saving time is enabled, extracting, by the CPE, the daylight saving time rule parameter from the message; obtaining the current year of the CPE; and obtaining start time or end time of daylight saving time according to the current year and the daylight saving time rule parameter. The system includes a CPE and a server. The CPE includes a receiving module, an extracting module, a first obtaining module, and a second obtaining module. The server includes a generating module and a sending module. Through the present invention, daylight saving time can be configured in a single attempt and used permanently. | 2014-04-03 |
| 20140092714 | ANALOG ELECTRONIC TIMEPIECE - Disclosed is an analog electronic timepiece including a first pointer which rotates freely with respect to a dial, a driving control unit which controls rotation of the first pointer, and an operation unit which receives an input operation performed by a user. In the analog electronic timepiece, the driving control unit includes an intermittent fast forwarding unit which performs a fast forwarding operation with temporary stops, where the rotation of the first pointer is stopped for a predetermined time period every time the first pointer is rotated by being fast forward for a predetermined number of steps according to a predetermined starting operation performed on the operation unit, the predetermined number of steps being 2 or more steps. | 2014-04-03 |
| 20140092715 | METHOD AND SYSTEM FOR IMPROVING LASER ALIGNMENT AND OPTICAL TRANSMISSION EFFICIENCY OF AN ENERGY ASSISTED MAGNETIC RECORDING HEAD - An EAMR disk drive includes a media, a laser, and a slider coupled with the laser. The laser for provides energy. The slider has an air-bearing surface, a laser input side, an EAMR transducer and an antireflective coating (ARC) layer occupying a portion of the laser input side. The ARC layer is configured to reduce back reflections of the energy. The EAMR transducer includes a write pole, a waveguide optically coupled with the laser and at least one coil. The waveguide has a waveguide input. A portion of the ARC layer resides between the laser and the waveguide input. A method aligns the laser to the ARC layer, and then aligns the laser to the waveguide input. The laser may then be coupled to the slider. | 2014-04-03 |
| 20140092716 | METHOD AND APPARATUS FOR INSPECTING THERMAL ASSIST TYPE MAGNETIC HEAD - An apparatus for inspecting a thermal assist type magnetic head is configured to include a scanning probe microscope unit comprising a cantilever having a probe with a magnetic film formed on the surface of a tip portion thereof; a prober unit which provides an alternating current to a terminal formed on the thermal assist type magnetic head element; a scattered light detection unit which detects scattered light generated from the probe; and a signal process unit which detects defect by using an output signal from the scanning probe microscope unit by scanning the surface of the thermal assist type magnetic head element with the probe in a state that the magnetic field is generated and the near-field light is stopped, and an output signal from the scattered light detection unit by scanning the surface with the probe while near-field light is generated and the magnetic field is off. | 2014-04-03 |
| 20140092717 | METHOD AND APPARATUS FOR INSPECTING THERMAL ASSIST TYPE MAGNETIC HEAD - An apparatus for inspecting a thermal assist type magnetic head is constituted by a scanning probe microscope means including a cantilever having a probe with a magnetic film formed on the surface of a tip portion thereof; a probe unit which provides an alternating current to a terminal formed on the thermal assist type magnetic head element and causes a pulse drive current or pulse drive voltage; a scattered light detection means which scans the near-field light emitting part with the probe to detect the scattered light generated from the probe in the generation region of the near-field light; an imaging means which image the thermal assist type magnetic head element; and a signal process means inspects the thermal assist type magnetic head element and an output signal outputted from the scanning probe microscope means by scanning with the probe while providing an alternating current to the terminal. | 2014-04-03 |
| 20140092718 | METHOD OF WRITING TO AN OPTICAL DATA STORAGE MEDIUM, METHOD OF READING FROM AN OPTICAL DATA STORAGE MEDIUM, AND OPTICAL DATA STORAGE MEDIUM - According to embodiments of the present invention, a method of writing to an optical data storage medium is provided. The method includes receiving a plurality of data elements, each data element having one of a plurality of values, wherein each value of the plurality of values is associated with a wavelength, and forming, for each data element, a nanostructure arrangement on the optical data storage medium, the nanostructure arrangement configured to reflect light of the wavelength associated with the value of the data element in response to a light irradiated on the optical data storage medium. According to further embodiments of the present invention, a method of reading from an optical data storage medium and an optical data storage medium are also provided. | 2014-04-03 |
| 20140092719 | RADIO TRANSCEIVER ON A CHIP - An entire radio transceiver can be compeltely integrated into one IC chip. In order to integrate the IF filters on the chip, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wise are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages. | 2014-04-03 |
| 20140092720 | User equipment optimization for multimedia broadcast multicast service - A technique to receive a Multimedia Broadcast Multicast Service (MBMS) broadcast, in which a plurality of source symbols and repair symbols of a broadcast from a broadcast source are received at a UE. The source symbols and repair symbols are based on fountain codes, so that not all of the repair symbols are used to recover the originally sourced data. An application layer of the UE recovers the sourced data and places the receiver in a power-save mode following the last repair symbol used to recover the sourced data, so that remaining repair symbols are not received by the receiver and subsequently processed. | 2014-04-03 |
| 20140092721 | RECONNECTING DROPPED CALLS USING AN INTERNET PROTOCOL MULTIMEDIA SUBSYSTEM - A Session Initiation Protocol (SIP) system controls an Internet Protocol (IP) communication session between a first communication device and a second communication device. A SIP control server receives a SIP bye message from the first communication device indicating a loss of the IP communication session, and in response, transfers a notification request for the second communication device to a SIP registration server. The SIP registration server processes a SIP registration message from the second communication device, and in response to the notification request and the SIP registration message, transfers a registration notification for the second communication device to the SIP control server. The SIP control server receives the registration notification for the second communication device, and in response, transfers a SIP invite message to re-establish the IP communication session to the first communication device. | 2014-04-03 |
| 20140092722 | SYSTEM AND METHOD PROVIDING STANDBY BYPASS FOR DOUBLE FAILURE PROTECTION IN MPLS NETWORK - A method for providing a Backup Label Switched Path for a specified Bypass Label Switch Path is disclosed. The method for providing a Backup Label Switched Path for a specified Bypass Label Switch Path includes establishing a Bypass LSP having an end-to-end path; obtaining the nodes traversed by the end-to-end path; generating a request to a path calculator which using the nodes provided on the end-to-end path calculates a path disjoint to those nodes; and signaling the calculated disjoint path as a Backup LSP for the Bypass LSP. The method for providing a Backup Label Switched Path for a specified Bypass Label Switch Path provides protection advantages over systems known in the art by providing capability for handling double failure scenarios. | 2014-04-03 |
| 20140092723 | METHODS AND APPARATUS FOR CONTROLLING WIRELESS ACCESS POINTS - In some embodiments, an apparatus comprises of a first Control And Provisioning of Wireless Access Points (CAPWAP) module implemented in at least one of a memory or a processing device that is configured to be designated as a backup control module for a wireless access point during a first time period. The first CAPWAP control module is configured to receive state information associated with the wireless access point during the first time period from a second CAPWAP control module. The second CAPWAP control module is designated as a primary control module for the wireless access point during the first time period. The first CAPWAP control module is configured to be automatically designated as the primary control module during a second time period after the first time period and in response to the second CAPWAP control module not operating according to at least one predefined criterion. | 2014-04-03 |
| 20140092724 | SYSTEM AND METHOD FOR FAIL-SAFE COMMUNICATION ACROSS A COMPROMISED COMMUNICATION CHANNEL OF A NETWORK DEVICE - A system and method for providing communication over a compromised communication channel in a system having a first node and a second node connected via the communication channel is provided. For example, a signaling circuit may be provided. The signaling circuit includes a master signal electrically connected to first and second portions of the communication channel. The first and second portions of the communication channel are employed in the first node. The signaling circuit further includes a slave signal processor arrangement coupled to the master signal processor arrangement and electrically connected to third and fourth portions of the communication channel. The third and fourth portions of the communication channel are employed in the second node. | 2014-04-03 |
| 20140092725 | METHOD AND FIRST NETWORK NODE FOR MANAGING AN ETHERNET NETWORK - A method and a first network node for managing an Ethernet network are disclosed. The Ethernet network comprises the first network node, a second network node and a third network node. The Ethernet network is configured as a Spanning Tree Protocol domain, STP domain. A first root is serving the STP domain. The first network node detects a failure of the first root. Then, the first network node sends a respective first frame indicating a second root to serve the STP domain. The first network node receives, from the second network node, a second frame indicating access to the first root via the third network node. Next, the first network node discards the second frame indicating access to the first root. | 2014-04-03 |
| 20140092726 | METHOD FOR MAPPING A NETWORK TOPOLOGY REQUEST TO A PHYSICAL NETWORK AND COMMUNICATION SYSTEM - A method for mapping a network topology request to a physical network is described. For each of a plurality of primary nodes included in the network topology request a plurality of nodes in the physical network is determined that meet a primary resource requirement associated with the primary node, and from the nodes determined one or more node pairs connected in the physical network by a path are selected that meets a backup connection requirement for a connection between a primary node and its backup node. Then, the paths in the physical network between node pairs associated with interconnected primary nodes are determined. | 2014-04-03 |
| 20140092727 | SCALABLE RELIABLE FAILOVER IN A NETWORK - A method is provided for establishing a reliable communication channel between an encapsulation node and a cluster of decapsulation nodes across a communication network. The method is implemented at the encapsulation node and comprises the following steps. A primary session is initialized with a primary decapsulation node in the cluster of decapsulation nodes during which an assigned address is received. A redundant session is initialized with a redundant decapsulation node in the cluster of decapsulation nodes. Data is transmitted to and received from the decapsulation node until a failure is detected. Once the failure is detected, data is transmitted to and received from the redundant decapsulation node instead of the primary decapsulation node. | 2014-04-03 |
| 20140092728 | FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON A PROCESSOR ARRAY - Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures. | 2014-04-03 |
| 20140092729 | Data Transmission in a Packet Transport Network (PTN) - The present disclosure describes data transmission in a packet transport network (PTN). A multiple stack device facilitates data transmission between a first edge device of a first PTN technology and a second edge device of a second PTN technology. After receiving a first packet of the first PTN technology from the first edge device, the multiple stack device identifies a first connection with the first edge device according to information of the first packet and identifies a second connection with the second edge device from the first connection based on a relationship between the first connection and the second connection. The first packet is de-encapsulated and re-encapsulated into a second packet of the second PTN technology according to the second connection. The second packet is then forwarded to the second edge device via the second connection. | 2014-04-03 |
| 20140092730 | SYSTEMS AND METHODS FOR HYBRID WIRELESS CONTENT DELIVERY - A method comprising transmitting a request, by a mobile device, indicating one or more content items; determining a location for the mobile device, by a processor; establishing a connection with a transmission medium, based at least in part on the indicated one or more content items, if the indicated one or more content items is not on the mobile device, wherein the transmission medium includes a digital radio tower, a long range radio tower and a wireless access point; and activating the indicated one or more content items, if the indicated one or more content items is on the mobile device. | 2014-04-03 |
| 20140092731 | ANDSF PARAMETERS FOR WLAN NETWORK SELECTION - Embodiments describe systems, methods, and apparatuses for identifying, based at least in part on an access network discovery and selection function (ANDSF) quality of service (QoS) policy, a preferred access point (AP) of a wireless local area network (WLAN). In some embodiments, the ANDSF QoS policy may be compared to one or more of an air-interface congestion parameter of the AP, and/or a backhaul congestion parameter of the AP. | 2014-04-03 |
| 20140092732 | ANTI-STARVATION AND BOUNCE-REDUCTION MECHANISM FOR A TWO-DIMENSIONAL BUFFERLESS INTERCONNECT - A slot reservation method is disclosed. The slot reservation method generates slot reservations in two dimensions to address starvation and to reduce bounce of messages transmitted through an interconnect. An interconnect implemented using the slot reservation method is capable of being scaled to larger network-on-chip implementations. | 2014-04-03 |
| 20140092733 | Methods of UE Indicating Traffic-Related Information to Network - A method of user equipment (UE) indication of traffic-related information to network is provided. The method comprises a UE determining a traffic indicator and transmitting the traffic indicator to a base station. In one embodiment, the traffic indicator indicates either that default power consumption is preferred or low power consumption is preferred. For example, when the UE is in background traffic or sparse traffic, low power consumption is preferred. In another embodiment, the traffic indicator indicates a time pattern of the traffic history. From the network perspective, upon receiving and evaluating information contained in the traffic indicator, the network triggers a QoS modification procedure by applying one or more QoS modification algorithms. | 2014-04-03 |
| 20140092734 | NETWORK-CONTROLLED ADAPTIVE TERMINAL BEHAVIOR MANAGING HIGH-NETWORK-LOAD SCENARIOS - A network device may detect a high traffic load for a wireless access network associated with the network device, and broadcast, to mobile terminals in the wireless access network associated with the network device, a signaling message indicating the high traffic load. The signaling message causes a mobile terminal to selectively limit wireless network access requests to the network device. | 2014-04-03 |
| 20140092735 | APPARATUS AND METHOD FOR CONTROLLING CONGESTION IN VEHICULAR COMMUNICATION - An apparatus and method for controlling congestion in a vehicular communication, capable of preventing the network throughput from being lowered due to increase in the number of vehicles, the method including: determining whether a communication channel is in a congestion condition as a message to be transmitted exists; and if determined as the congestion condition, transmitting a message in a transmission section that is determined within a time frame based on a current position. | 2014-04-03 |
| 20140092736 | METHOD AND SYSTEM FOR RADIO SERVICE OPTIMIZATION USING ACTIVE PROBING OVER TRANSPORT NETWORKS - A method and system for determining quality and capacity of a transport monitoring connection between radio service nodes to facilitate local management of subscriber connections are disclosed. One method includes sending first test packets from a first radio service node to a second radio service node via the transport monitoring connection. Second test packets are received from the second radio service node. The second test packets have information added to the first test packets by the second radio service node. The second test packets are analyzed to determine a quality and a bandwidth of the transport monitoring connection. Control and user plane functions are informed when transport monitoring performance is one of degraded and improved based on the quality and bandwidth. The method includes making radio service provisioning decisions based on the quality and bandwidth of the transport monitoring connection. | 2014-04-03 |
| 20140092737 | TRAFFIC CONTROL METHOD AND TRAFFIC CONTROL APPARATUS - The present invention discloses a traffic control method and a traffic control apparatus. The traffic control method comprising the steps of collecting key performance indexes of a system; and determining whether to limit requests entering into the system based on the collected key performance Indexes of the system, and it is determined that the requests entering into the system will be limited when a certain collected key performance Index of the system is inferior to a first threshold for a period of time, According to the invention, traffic control may be effectively, practically and flexibly provided to a system. | 2014-04-03 |
| 20140092738 | MAINTAINING LOAD BALANCING AFTER SERVICE APPLICATION WITH A NETWOK DEVICE - In general, techniques are described for maintaining load balancing after service application. A network device comprising ingress and egress forwarding components and a service card may implement the techniques. An ingress forwarding component receives a packet and, in response to a determination that the service is to be applied to the packet, updates the packet to include an ingress identifier that identifies the ingress forwarding component, thereafter transmitting the updated packet to the service card. The service card applies the service to the updated packet to generate a serviced packet and transmits the serviced packet to the ingress forwarding component identified by the ingress identifier so as to maintain load balancing of packet flows across the plurality of forwarding components. The ingress forwarding component determines a next hop to which to forward the serviced packet and the egress forwarding component forwards the serviced packet to the determined next hop. | 2014-04-03 |
| 20140092739 | FLOW FILTER MAPPING SCHEME WITH PCC FLOW-DIRECTION AVP - Various exemplary embodiments relate to a method performed by a policy and charging rules node (PCRN) device for implementing a PCC procedure with SDF inputs, the method including: receiving a PCC request with a SDF input; determining if the PCC request is from a user equipment (UE); mapping flow direction information from the SDF input request into a unified flow-direction record stored in the PCRN; generating PCC, ADC, and/or QoS rules based upon the unified flow-direction record; determining if flow direction is defined on an output interface; mapping the unified flow-direction record into a flow-information AVP associated with the generated PCC, ADC, and/or QoS rules. | 2014-04-03 |
| 20140092740 | ADAPTIVE PACKET DEFLECTION TO ACHIEVE FAIR, LOW-COST, AND/OR ENERGY-EFFICIENT QUALITY OF SERVICE IN NETWORK ON CHIP DEVICES - Methods and apparatus for provision of adaptive packet deflection to achieve fair, low-cost, and/or energy-efficient Quality of Service (QoS) in Network-on-Chip (NoC) devices are described. In some embodiments, it is determined whether a target port of a packet has reached a threshold utilization value and the packet is routed to an alternate port in response to a deflection probability value that is to be determined based on a utilization value of the target port and a priority level value of the packet. Other embodiments are also claimed and/or disclosed. | 2014-04-03 |
| 20140092741 | SYSTEM AND METHOD FOR A TCP MAPPER - A system for congestion control of traffic in a network that uses Transmission Control Protocol (TCP) includes a plurality of TCP congestion control programs having one or more parameters, a plurality of TCP congestion control units running the TCP congestion control programs, and a TCP mapper adapted to map incoming TCP traffic flow from a plurality of incoming TCP traffic flows to the TCP congestion control units based on at least one of (a) the type of application program from which the incoming TCP traffic flow originated (b) the type of network for which the incoming TCP traffic flow is destined, (c) parameters related to network performance (d) network constraints (e) source of the incoming TCP traffic flow, and (f) destination of the incoming TCP traffic flow. | 2014-04-03 |
| 20140092742 | MANAGEMENT APPARATUS AND METHOD TO SUPPORT WLAN OFFLOADING - Embodiments of systems and techniques are described for supporting WLAN offloading. In some embodiments, a network management system (NMS) for WLAN offloading may include a network manager (NM); a first element manager (EM), coupled to the network manager, to communicate with the network manager and one or more WLANs; and a second EM, coupled to the NM, to communicate with the NM and one or more base stations of a cellular network. Coverage areas of at least one access point (AP) of the one or more WLANs are overlaid with at least one cell of the cellular network to support a WLAN offloading operation. Further, the NM is to activate the WLAN offloading operation based at least in part on at least one indicator received from the one or more WLANs. Other embodiments may be described and claimed. | 2014-04-03 |
