| 14th week of 2015 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20150091006 | Thin Film Transistor Substrate Having Metal Oxide Semiconductor and Method for Manufacturing the Same - The present disclosure relates to a thin film transistor substrate with a metal oxide semiconductor layer that has enhanced characteristics and stability. The present disclosure also relates to a method for manufacturing a thin film transistor substrate in which a thermal treatment is conducted for the metal oxide semiconductor layer and the damages to the substrate by the thermal treatment are minimized | 2015-04-02 |
| 20150091007 | METHOD FOR PRODUCING A MICROSYSTEM HAVING A THIN FILM MADE OF LEAD ZIRCONATE TITANATE - A method for producing a micro system, said method comprising: providing a substrate ( | 2015-04-02 |
| 20150091008 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A transistor which includes an oxide semiconductor and is capable of high-speed operation and a method of manufacturing the transistor. In addition, a highly reliable semiconductor device including the transistor and a method of manufacturing the semiconductor device. The semiconductor device includes an oxide semiconductor layer including a channel formation region, and a source and drain regions which are provided so that the channel formation region is interposed therebetween and have lower resistance than the channel formation region. The channel formation region and the source and drain regions each include a crystalline region. | 2015-04-02 |
| 20150091009 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes. | 2015-04-02 |
| 20150091010 | METHOD FOR FORMING LOW-TEMPERATURE POLYSILICON THIN FILM, THIN FILM TRANSISTOR AND DISPLAY DEVICE - A method for forming low-temperature polysilicon thin film, a thin film transistor and a display device are provided. The method for forming low-temperature polysilicon thin film comprises: depositing an amorphous silicon thin film on a base substrate; covering the amorphous silicon thin film with an anti-reflective optical film; performing photolithography and etching on the anti-reflective optical film such that light condensing structures are provided in an array on the anti-reflective optical film; and irradiating the amorphous silicon thin film with the anti-reflective optical film covered by laser light such that the amorphous silicon film is converted into the low-temperature polysilicon thin film. The method may improve the grain size and uniformity of the low-temperature polysilicon thin film, make full use of the energy of the incident laser light, facilitate the reduction of the production cost of the low-temperature polysilicon thin film, and improve the performance of the low-temperature polysilicon thin film transistor. | 2015-04-02 |
| 20150091011 | DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A display device and a method for fabricating a display device are provided. According to one embodiment of the present invention, a display device includes a substrate, an insulating layer arranged on the substrate, a wiring pattern arranged on the insulating layer, an organic layer arranged on the wiring pattern, and a contact hole penetrating the organic layer to expose at least a portion of the wiring pattern. The side wall of the organic layer that defines the contact hole includes a first side wall portion and a second side wall portion, and a value obtained by dividing a vertical distance of the first side wall portion by a horizontal distance of the first side wall portion is different from a value obtained by dividing a vertical distance of the second side wall portion by a horizontal distance of the second side wall portion. | 2015-04-02 |
| 20150091012 | DISPLAY APPARATUS - A display apparatus includes: a flexible display panel including: a base substrate including a display area and a non-display area; a pixel at the display area of the base substrate; and signal lines at the non-display area of the base substrate; and a protective film coupled to the flexible display panel and including: a first portion under the flexible display panel; and a second portion extending from the first portion and configured to be bent to overlap with the signal lines and to overlap with the first portion, wherein the display apparatus is configured to be bent along a folding line crossing an area of the display apparatus in which the first portion and the second portion are configured to be overlapped with each other. | 2015-04-02 |
| 20150091013 | DISPLAY PANEL AND DISPLAY DEVICE HAVING THE SAME - A display panel includes a base substrate including a display area and a peripheral area, a pixel at the display area of the base substrate, a signal line coupled to the pixel and configured to apply a signal to the pixel, and a pad part including a plurality of pads at the peripheral area. The pad part being electrically coupled to the signal line, and the plurality of pads includes at least two pads having widths different from each other. | 2015-04-02 |
| 20150091014 | Display Device and Method of Manufacturing the Same - A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel and thus thickness and manufacturing cost are reduced. | 2015-04-02 |
| 20150091015 | Display Device and Method of Manufacturing the Same - A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel unlike the related art and thus thickness and manufacturing cost are reduced. | 2015-04-02 |
| 20150091016 | Flexible Display - A flexible display has a display layer, a thin-film transistor (TFT) layer and a flexible substrate. The display layer has a plurality of display units. The TFT layer has a plurality of pixel control circuits and a plurality of sensing circuits. The pixel control circuits are configured to control operations of the plurality of display units. Each of the sensing circuits is configured to generate a deformation signal according to deformation of the flexible display. The flexible substrate and the TFT layer are stacked. | 2015-04-02 |
| 20150091017 | Semiconductor Device and Fabrication Method Thereof - A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an inter-layer insulation film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks. | 2015-04-02 |
| 20150091018 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPARATUS - To prevent an electrostatic damage on a display device formed with a driving circuit. Protective circuits are provided not only at input terminal parts, but also at intermediate parts of a circuit or at the ends of wiring lines. Otherwise, the protective circuits are provided at the ends of the wiring lines and at the places immediately before and after the input terminals, respectively, and then the circuit is interposed therebetween. Further, the protective circuits are provided around a circuit with a large current consumption. | 2015-04-02 |
| 20150091019 | WHITE LED CHIP AND WHITE LED PACKAGING DEVICE - A white LED chip includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first material layer, the active layer includes a second material layer, and the second barrier layer includes a third material layer. The N-type layer is disposed over the tunneling structure. An energy gap of the second material layer is lower than an energy gap of the first material layer and an energy gap of the third material layer. Each of the first material layer, the second material layer and the third material layer is a metal oxide layer, a metal nitride layer or a metal oxynitride layer. | 2015-04-02 |
| 20150091020 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device includes: a gate oxide film formed on a surface of a semiconductor substrate; a gate electrode formed on the gate oxide film; and a high concentration impurity layer connected to a main electrode and formed on the surface of the semiconductor substrate, wherein an impurity species doped in the high concentration impurity layer comprises a first impurity species of phosphorous and a second impurity species of at least one of argon and nitrogen, a concentration of the second impurity species is higher than a concentration of the first impurity species in a surface of the high concentration impurity layer, and a peak position of a concentration distribution of the first impurity species in a depth direction in the high concentration impurity layer is deeper than a peak position of a concentration distribution of the second impurity species in the depth direction. | 2015-04-02 |
| 20150091021 | Method of Manufacturing Semiconductor Device and the Semiconductor Device - A method of manufacturing a semiconductor device includes: forming a gate electrode material layer made of a material configuring a gate electrode and a barrier material layer made of a silicon nitride film; forming an upper barrier layer configured to an upper surface of the gate electrode with the barrier material layer and forming the gate electrode from the gate electrode material later by etching the barrier material layer and the gate electrode material layer with a same mask pattern; forming a sidewall barrier layer configured to cover a side surface of the gate electrode by forming again the barrier material layer after the forming of the gate electrode; forming an interlayer insulation layer configured to cover a surface-side of the semiconductor substrate including the upper surface barrier layer and the sidewall barrier layer; and opening the interlayer insulation layer and forming the silicide electrode. | 2015-04-02 |
| 20150091022 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device having a main electrode connected to a first semiconductor region and a second semiconductor layer on a semiconductor substrate so that a pn-junction diode is formed with the first semiconductor region being interposed and a Schottky barrier diode is formed with the second semiconductor layer being interposed on a surface of the semiconductor substrate, the semiconductor device includes a first electrode configured to ohmic-contact the first semiconductor region; a second electrode configured to Schottky-contact the second semiconductor layer and not having a portion directly contacting the first electrode; and a conductive reaction suppression layer to suppress a reaction between a material configuring the first electrode and a material configuring the second electrode are provided on the surface of the semiconductor substrate, and the main electrode is electrically connected to the first electrode and the second electrode. | 2015-04-02 |
| 20150091023 | Semiconductor Device and Method of Manufacturing - A diode comprising a reduced surface field effect trench structure, the reduced surface field effect trench structure comprising at least two trenches formed in a substrate and separated from one another by a joining region of the substrate, the joining region comprising an electrical contact and a layer of p-doped semiconductor material. | 2015-04-02 |
| 20150091024 | PACKAGE STRUCTURE OF OPTICAL MODULE - A package structure of an optical module includes: a substrate defined with a light-emitting region and a light-admitting region; a light-emitting chip disposed at the light-emitting region of the substrate; a light-admitting chip disposed at the light-admitting region of the substrate; two encapsulants for enclosing the light-emitting chip and the light-admitting chip, respectively; and a shielding layer formed on the substrate and the encapsulants and having a light-emitting hole and a light-admitting hole, wherein the light-emitting hole and the light-admitting hole are positioned above the light-emitting chip and the light-admitting chip, respectively. Accordingly, the optical module package structure simplifies a packaging process and cuts manufacturing costs. | 2015-04-02 |
| 20150091025 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a sheet-shaped die bonding material on a substrate including a wiring, and a plurality of light-emitting elements fixed onto the die bonding material. A method of manufacturing the light-emitting device includes applying the die bonding material in a paste form to the substrate such that the die bonding material is shared by the plurality of light-emitting elements, placing the plurality of light-emitting elements on the die bonding material in the paste form, and curing the die bonding material after placing the plurality of light-emitting elements so as to fix the plurality of light-emitting elements onto the bonding material. | 2015-04-02 |
| 20150091026 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - A light emitting diode package structure is provided. The light emitting diode package structure includes at least one light emitting diode unit, an encapsulating body and at least one isolation film. The encapsulating body includes a plurality of surfaces and at least one light-emitting surface, wherein one of the surfaces supports the light emitting diode unit, the other surfaces are exposed. The at least one isolation film is formed on the exposed surfaces. Wherein the isolation film blocks or reflects a portion of light emitted from the light emitting diode unit. | 2015-04-02 |
| 20150091027 | LIGHT EMITTING DEVICE - A light emitting device of the invention includes a substrate; a light emitting element mounted on the upper surface of the substrate; a wire that is electrically connected to the light emitting element; and a plate-shaped light-transmissive member that covers the light emitting element. The wire has a stack structure in which a first bonding ball, a bonding wire, and a second bonding ball are stacked in that order, the stack structure is disposed on the upper surface of the light emitting element, and the plate-shaped light-transmissive member is disposed above the stack structure. | 2015-04-02 |
| 20150091028 | DISPLAY DEVICE INCLUDING FLUORIDE PHOSPHOR - A display device having a superior color reproduction in the ranges of green and red colors by using a fluoride phosphor is disclosed. The display device includes a light emitting diode (LED) package having a light emitting diode, a wavelength converting member to convert a wavelength of light output from the light emitting diode, and a light guide panel to reflect, refract and scatter the light having a converted wavelength, wherein the wavelength converting member includes a fluoride phosphor and a curing resin. | 2015-04-02 |
| 20150091029 | LED LIGHT EMITTING APPARATUS - The purpose of the present invention is to provide an LED light emitting apparatus, which has both the high reliability with respect to connection of the LED elements, and improved light extraction efficiency. This LED light emitting apparatus includes a mounting substrate having an element mounting region, in which a reflection layer is formed; a plurality of LED elements mounted in the element mounting region; a pair of facing electrodes, which have gold plating layers formed thereon, respectively, which are provided around the element mounting region, and which are connected to the LED elements by wire bonding; and a sealing frame, which is disposed around the element mounting region so as to cover the pair of facing electrodes. The inner circumference of the sealing frame is provided at a position where the inner circumference of the sealing frame covers the outer circumference of the reflection layer. | 2015-04-02 |
| 20150091030 | DISPLAY DEVICES AND METHODS OF MANUFACTURING DISPLAY DEVICES - A display device includes a substrate including a display region and a peripheral region, display structures at the display region of the substrate, a plurality of blocking structures at the peripheral region of the substrate wherein the blocking structures have heights different from each other, an organic layer on the display structures and the blocking structures, and an inorganic layer on the organic layer. | 2015-04-02 |
| 20150091031 | LOCATING OPTICAL STRUCTURES TO LEDS - An optical device and a method of making an optical device are disclosed. A printed wiring board is formed that includes coupling elements at selected locations. The coupling elements are formed using a printed wiring board manufacturing technique. A light source may be coupled to the printed wiring board at one of the coupling elements. An optical structure for directing light from the light source may be coupled to the printed wiring board at another coupling element. A tolerance for a distance between the optical structure and the light source is thus controlled using the manufacturing technique. | 2015-04-02 |
| 20150091032 | Nickel-Titanium and Related Alloys as Silver Diffusion Barriers - Diffusion of silver from LED reflector layers is blocked by 10-50 nm barrier layers of nickel-titanium (NiTi) alloys. Optionally, the alloys also include one or more of tungsten (W), niobium (Nb), aluminum (Al), vanadium (V), tantalum (Ta), or chromium (Cr). These barriers may omit the noble-metal (e.g., platinum or gold) cap used with silver barriers based on other materials. | 2015-04-02 |
| 20150091033 | LIGHT ENHANCING STRUCTURE FOR A LIGHT EMITTING DIODE - A light enhancing structure includes a light emitting diode in it and at least one coating layer. The light emitting diode unit includes a plurality of surfaces and a light-emitting surface. The light-emitting surface is for allowing a plurality of lights generated inside the light emitting diode unit to emit through. The coating layer is formed on the surfaces for blocking or reflecting one of the lights generated inside the light emitting diode unit, and to light intensity of the light emitting diode unit is enhanced. | 2015-04-02 |
| 20150091034 | LIGHT EMITTING DIODE PACKAGE - A light-emitting diode (LED) package structure includes a lead frame, a LED chip, a package body, N opaque spacer and N+1 encapsulating glues. The LED chip is disposed on the lead frame; the package body covers the lead frame and exposes the LED chip. The package body has an accommodation space, divided by the N opaque spacers disposed on the LED chip into N+1 chambers. The N+1 encapsulating glues are filled into the N+1 chambers, where N is a natural number. | 2015-04-02 |
| 20150091035 | SEMICONDUCTOR DEVICE STRUCTURE - The present disclosure relates to a method for manufacturing a semiconductor device structure, comprising the steps of: securing the position of a semiconductor device on a plate; securing the positions of electrodes such that the electrodes face the plate; covering the semiconductor device with an encapsulating material; and separating, from the plate, the semiconductor device covered with the encapsulating material. | 2015-04-02 |
| 20150091036 | LIGHT EMITTING DIODE - Disclosed herein is a light emitting diode. The light emitting diode includes a substrate, an n-type semiconductor layer placed on the substrate, an active layer placed on the n-type semiconductor layer, a p-type semiconductor layer placed on the active layer, a reflective layer placed on the p-type semiconductor layer, an n-type electrode electrically connected to the n-type semiconductor layer, a p-type electrode placed on the reflective layer; and a first patterned magnetic structure placed on the reflective layer, and separated from the p-type electrode. The light emitting diode can provide improved internal quantum efficiency using the patterned magnetic structure. | 2015-04-02 |
| 20150091037 | LIGHT EMITTING DEVICE - A light emitting device includes a semiconductor structure layer including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. A plurality of lower refractive layers is provided on an outer surface of the semiconductor structure layer. The lower refractive layers includes a first lower refractive layer having a first refractive index lower than a refractive index of the semiconductor structure layer on a surface of the semiconductor structure layer, and a second lower refractive layer having a second refractive index lower than the first refractive index on an outer surface of the first lower refractive layer. The second refractive index of the second lower refractive layer is 1.5 or less, and the second lower refractive layer is provided on an outer surface thereof with a plurality of protrusions. The second lower refractive layer includes a plurality of metallic oxide powders. | 2015-04-02 |
| 20150091038 | LIGHT EMITTING DIODE - A light emitting diode including a lower semiconductor layer formed on a substrate; an upper semiconductor layer disposed above the lower semiconductor layer, exposing an edge region of the lower semiconductor layer; a first electrode formed on the upper semiconductor layer; an insulation layer interposed between the first electrode and the upper semiconductor layer, to supply electric current to the lower semiconductor layer; a second electrode formed on another region of the upper semiconductor layer, to supply electric current to the upper semiconductor layer. The first electrode includes an electrode pad disposed on the upper semiconductor layer and an extension extending from the electrode pad to the exposed lower semiconductor layer. The insulation layer may have a distributed Bragg reflector structure. | 2015-04-02 |
| 20150091039 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes a semiconductor stack part that includes a light emitting layer, a diffractive face to which light emitted from the light emitting layer is incident, and convex portions or concave portions formed in a period which is longer than an optical wavelength of the light and is shorter than a coherent length of the light. The diffractive face reflects incident light in multimode according to Bragg's condition of diffraction and transmits the incident light in multimode according to the Bragg's condition of diffraction. The semiconductor stack part is formed on the diffractive face. The convex portions or the concave portions include a side surface and a curved portion which curves and extends to a center side of the convex portions or the concave portions from an upper end of the side surface. | 2015-04-02 |
| 20150091040 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region. | 2015-04-02 |
| 20150091041 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING APPARATUS INCLUDING THE SAME - A semiconductor light emitting device includes a substrate, a first structure, a second structure, first and second n-electrodes, and first and second p-electrodes. The first structure is disposed on the substrate and includes a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer. The second structure is spaced apart from the first structure on the substrate and includes a second n-type semiconductor layer, a second active layer and a second p-type semiconductor layer. The first n-electrode and the first p-electrode are connected to the first n-type semiconductor layer and the first p-type semiconductor layer, respectively. The second n-electrode and the second p-electrode are connected to the second n-type semiconductor layer and the second p-type semiconductor layer, respectively. The second n-electrode is spaced apart from the second active layer to encompass the second active layer. | 2015-04-02 |
| 20150091042 | LIGHT EMITTING DIODE CHIP AND LIGHT EMITTING DEVICE HAVING THE SAME - A light emitting diode (LED) chip can include: a first pattern region having one or more curved parts; and a second pattern region at least partially surrounding the first pattern region. The first pattern region can include a first conductive type nitride-based semiconductor layer, an active layer, a second conductive type nitride-based semiconductor layer, a top electrode layer, and a top bump layer stacked over a substrate, the second pattern region can include a first conductive type nitride-based semiconductor layer, a bottom electrode layer, and a bottom bump layer stacked over the substrate, and the first pattern region can include one or more protrusion patterns formed in the one or more curved part. | 2015-04-02 |
| 20150091043 | Heterostructure Including Anodic Aluminum Oxide Layer - A semiconductor structure including an anodic aluminum oxide layer is described. The anodic aluminum oxide layer can be located between a semiconductor layer and another layer of material. The anodic aluminum oxide layer can include a plurality of pores extending to an adjacent surface of the semiconductor layer. The layer of material can penetrate at least some of the plurality of pores and directly contact the semiconductor layer. In an illustrative embodiment, the layer of material is a conductive material and the anodic aluminum oxide is located at a p-type contact. | 2015-04-02 |
| 20150091044 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface. | 2015-04-02 |
| 20150091045 | DISPLAY PANEL, DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY PANEL - A display panel includes a first substrate and a second substrate sealed by sealant, and an inorganic material thin film is also formed outside the sealant. The display panel possesses a better characteristic of water and oxygen isolation in a lateral direction. A manufacturing method of a display panel and a display device including the display panel are further disclosed. | 2015-04-02 |
| 20150091046 | HIGH-EFFICIENCY AlGaInP LIGHT-EMITTING DIODE GROWN DIRECTLY ON TRANSPARENT SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present invention relates to a high-efficiency AlGaInP light-emitting diode directly grown on a transparent substrate and a method of manufacturing the same, and, more particularly, to a high-efficiency AlGaInP light-emitting diode grown on a sapphire substrate and a method of manufacturing the same. According to the present invention, an AlGaInP light-emitting diode is manufactured using an inexpensive sapphire substrate having high transmittance to ultraviolet rays, infrared rays and visible rays. The AlGaInP light-emitting diode according to the present invention can emit light with high efficiency because a lower substrate does not absorb light, and can be effectively manufactured because a process of removing a GaAs or a process of bonding a sapphire substrate is not conducted. | 2015-04-02 |
| 20150091047 | METHOD OF GROWING NITRIDE SEMICONDUCTOR, METHOD OF MANUFACTURING TEMPLATE FOR SEMICONDUCTOR FABRICATION AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE SAME - Disclosed are a method of growing a nitride semiconductor, a method of manufacturing a template for semiconductor fabrication and a method of manufacturing a semiconductor light emitting device using the same. The method of manufacturing a semiconductor light emitting device includes: preparing a growth substrate having a defect aggregation region; growing a first nitride semiconductor layer over the growth substrate; growing a second nitride semiconductor layer over the first nitride semiconductor layer; growing a third nitride semiconductor layer over the second nitride semiconductor layer; growing an active layer over the third nitride semiconductor layer; and forming a second conductive type semiconductor layer over the active layer. Accordingly, semiconductor layers grown on the template can have excellent crystallinity. | 2015-04-02 |
| 20150091048 | OPTICALLY-TRIGGERED SILICON CONTROLLED RECTIFIER AND METHOD OF FABRICATION OF THE SAME - A device includes a semiconductor substrate having a plurality of doped layers forming first and second junctions. The semiconductor substrate includes a first surface and a second surface opposite the first surface. The device includes a plurality of waveguides defined by a plurality of glass inlaid channels defined within the first surface. Each of the plurality of glass inlaid channels extends through the second junction. The device includes a pattern of reflective elements associated with sidewalls of the plurality of glass inlaid channels to reflect light into the plurality of waveguides. A first electrically-conductive layer is disposed on the first surface and covers the plurality of glass inlaid channels. | 2015-04-02 |
| 20150091049 | TRIODE - A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a p+ doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region. | 2015-04-02 |
| 20150091050 | TRIODE - A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel. | 2015-04-02 |
| 20150091051 | Semiconductor Device and Method for Forming a Semiconductor Device - A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement. The IGBT arrangement includes a carrier confinement reduction region laterally arranged between a cell region and a sensitive region. The IGBT arrangement is configured or formed so that the cell region has a first average density of free charge carriers in an on-state of the IGBT arrangement, the carrier confinement reduction region has a second average density of free charge carriers in the on-state of the IGBT arrangement and the sensitive region has a third average density of free charge carriers in the on-state of the IGBT arrangement. The first average density of free charge carriers is larger than the second average density of free charge carriers and the second average density of free charge carriers is larger than the third average density of free charge carriers. | 2015-04-02 |
| 20150091052 | Semiconductor Device and Method for Forming a Semiconductor Device - A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement. The IGBT arrangement includes a first configuration region of emitter-side insulated gate bipolar transistor structures and a second configuration region of emitter-side insulated gate bipolar transistor structures. The first configuration region and the second configuration region are arranged at a main surface of a semiconductor substrate of the semiconductor device. Further, the IGBT arrangement includes a collector layer and a drift layer. The collector layer is arranged at a backside surface of the semiconductor substrate and the drift layer is arranged between the collector layer and the emitter-side IGBT structures of the first configuration region and the second configuration region. Additionally, the collector layer includes at least a first doping region laterally adjacent to a second doping region. The first doping region and second doping region include different charge carrier life times, different conductivity types or different doping concentrations. | 2015-04-02 |
| 20150091053 | IGBT with Reduced Feedback Capacitance - An IGBT includes at least one first type transistor cell, including a base region, a first emitter region, a body region, and a second emitter region. The body region is arranged between the first emitter region and the base region. The base region is arranged between the body region and the second emitter region. The IGBT further includes a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a base electrode adjacent the base region and dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A doping concentration of the first base region section is higher than a doping concentration of the second base region section. | 2015-04-02 |
| 20150091054 | SCRs with Checker Board Layouts - An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips. | 2015-04-02 |
| 20150091055 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first region of a first conductivity type, a collector electrode electrically connected to a first side of the first region, first and second gate electrodes and first and second conductor electrodes, each of the gate and conductor electrodes extending into the first region from a second side thereof that is opposite to the first side, an emitter electrode electrically connected to the conductor electrodes, and a second region of the first conductivity type, that is adjacent to the gate electrodes, electrically connected to the emitter electrode, and spaced from the first and second conductor electrodes. | 2015-04-02 |
| 20150091056 | SEMICONDUCTOR DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION - Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly. | 2015-04-02 |
| 20150091057 | SEMICONDUCTOR STRUCTURE AND DEVICE AND METHODS OF FORMING SAME USING SELECTIVE EPITAXIAL PROCESS - Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques. | 2015-04-02 |
| 20150091058 | VERTICAL TRANSISTOR DEVICES FOR EMBEDDED MEMORY AND LOGIC TECHNOLOGIES - Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate. | 2015-04-02 |
| 20150091059 | PROCESS FOR FABRICATING FIN-TYPE FIELD EFFECT TRANSISTOR (FinFET) STRUCTURE AND PRODUCT THEREOF - A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fm together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer. | 2015-04-02 |
| 20150091060 | SEMICONDUCTOR DEVICE HAVING HIGH MOBILITY CHANNEL - In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel | 2015-04-02 |
| 20150091061 | PASSIVATION TECHNIQUE FOR WIDE BANDGAP SEMICONDUCTOR DEVICES - A method of protecting a semiconductor structure from water and a semiconductor structure formed by the method. The semiconductor structure includes a wide-bandgap semiconductor material in which at least one semiconductor device is formed. The method includes heating the semiconductor structure in a vacuum to a temperature of at least 200° C. to remove water from the semiconductor structure. The method also includes, after the heating of the semiconductor structure, forming a layer comprising a hydrophobic material over the semiconductor structure. The semiconductor structure is kept in the vacuum between the heating of the semiconductor structure and the forming of the layer comprising the hydrophobic material. | 2015-04-02 |
| 20150091062 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor element includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a control electrode, a pad unit, an insulating layer, and a conductor. The second semiconductor layer is provided on the first semiconductor layer. The first electrode is provided on the second semiconductor layer. The second electrode is provided on the second semiconductor layer. The control electrode is provided on the second semiconductor layer. The pad unit is provided on the second semiconductor layer. The pad unit is electrically connected to the control electrode. The insulating layer is provided on the second semiconductor layer. The insulating layer has an opening. The conductor is provided on the insulating layer. The conductor covers at least a part of the opening. | 2015-04-02 |
| 20150091063 | SEMICONDUCTOR ELEMENT - A semiconductor element includes a collector contact layer of a high concentration N-type semiconductor layer. An N-type collector layer, a base layer, being a high concentration P-type semiconductor layer with a top surface, laminated on the collector layer, and an N-type emitter layer laminated on a part of the top surface, are laminated on the collector contact layer. A base-collector layer junction is located on a bonded surface, between the base layer and the collector layer. An inactive portion is located outside an outside end of a base electrode on the top surface, in a plan view. The inactive portion is formed by implanting ions of one of helium and argon into the first and second semiconductor layers. The inactive portion extends from the top surface to a position below the base-collector layer junction. | 2015-04-02 |
| 20150091064 | 3D SEMICONDUCTOR DEVICE AND 3D LOGIC ARRAY STRUCTURE THEREOF - A 3D semiconductor device and a 3D logic array structure thereof are provided. The 3D semiconductor device includes an array structure, a periphery line structure and a 3D logic array structure. The array structure has Y contacts located at a side of the array structure. Y is within M | 2015-04-02 |
| 20150091065 | PIXEL STRUCTURES OF CMOS IMAGING SENSORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a pixel structure of a CMOS transistor. The method includes providing a semiconductor substrate doped with first type doping ions; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The method also includes forming isolation layers on side surfaces of the trench to prevent dark current from laterally transferring; and forming an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type doping ions in the trench. Further, the method includes forming a pinning layer on a top surface of the epitaxial layer; and forming a gate structure on a surface of the semiconductor substrate at one side of the epitaxial layer. Further, the method also includes forming a floating diffusion region in the semiconductor substrate at one side of the gate structure far from the epitaxial layer. | 2015-04-02 |
| 20150091066 | Double Sided NMOS/PMOS Structure and Methods of Forming the Same - A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric. | 2015-04-02 |
| 20150091067 | HYBRID PHASE FIELD EFFECT TRANSISTOR - An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side. | 2015-04-02 |
| 20150091068 | GATE ELECTRODE WITH A SHRINK SPACER - A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm. | 2015-04-02 |
| 20150091069 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer. | 2015-04-02 |
| 20150091070 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines. | 2015-04-02 |
| 20150091071 | Memory Devices and Method of Fabricating Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 2015-04-02 |
| 20150091072 | Memory Devices and Method of Forming Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 2015-04-02 |
| 20150091073 | NONVOLATILE MEMORY STRUCTURE AND FABRICATION METHOD THEREOF - According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer. | 2015-04-02 |
| 20150091074 | NONVOLATILE MEMORY STRUCTURE - A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel. | 2015-04-02 |
| 20150091075 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device is provided. The element isolation insulating bodies form active areas extending in one direction along a surface of a semiconductor substrate in a surface region of the semiconductor substrate, and partition the surface region into the active areas. The tunnel insulating films are formed on the active areas respectively. The floating gate electrodes are formed on the tunnel insulating films respectively. The inter-gate insulating films are formed on the floating gate electrodes. The control gate electrodes are provided on the inter-gate insulating films. The source regions and drain regions are formed in the active areas respectively. Each of the active areas has steps at side surfaces. A width of a portion of each of the active areas deeper than the steps is larger than that of a portion of each of the active areas shallower than the steps. | 2015-04-02 |
| 20150091076 | ISOLATION FORMATION FIRST PROCESS SIMPLIFICATION - A method for manufacturing a memory device includes providing a substrate having a plurality of active layers, forming a plurality of holes through the plurality of active layers including a first row of holes and a second row of holes, and filling the plurality of holes with an isolation material. The method includes etching the plurality of active layers to form first and second sets of interdigitated stacks of active strips, where the first set includes strips extending from pads in a first stack of pads and terminating at isolation strips remaining from corresponding filled holes in the first row, and the second set includes strips extending from pads in a second stack of pads and terminating at isolation strips remaining from corresponding filled holes in the second row. | 2015-04-02 |
| 20150091077 | Method of fabricating a non-volatile memory - A structure of a memory cell includes a substrate, a well, two source/drain doped regions, a stacked layer and a metal gate. The stacked layer includes a tunneling layer, and a charge trapping layer. A method of fabricating the memory cell may vary with the change in sequence of performing steps. The difference in sequence of fabrication may yield different characteristic variations for the formed components of the memory cell. | 2015-04-02 |
| 20150091078 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern. | 2015-04-02 |
| 20150091079 | NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-FIRST METHODOLOGY - A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate. | 2015-04-02 |
| 20150091080 | Method of forming and structure of a non-volatile memory cell - A structure of a memory cell includes a substrate, a well, three source/drain doped regions, two bottom dielectric layers, two charge trapping layers, a blocking layer and two gates to form a storage transistor and a select transistor of the memory cell. A bottom dielectric layer and a charge trapping layer may be used to provide the dielectric of the gate of the select transistor with enough thickness but without any additional fabrication process. | 2015-04-02 |
| 20150091081 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate including a plurality of pillars, a gate electrode formed to surround a lower portion of the pillar and having a top surface lower than a top surface of the pillar, a salicide layer formed to cover the top surface of the pillar and surround an upper portion of the pillar, and an electrode formed to cover a top surface and a lateral surface of the salicide layer. | 2015-04-02 |
| 20150091082 | Semiconductor Device - A semiconductor device includes a semiconductor substrate, a surface of which is provided with: a source region having a first conductivity type is formed in a body region having a second conductivity type opposite to the first conductivity type; a main electrode connected to the source region and the body region; and a gate electrode, to which a voltage for controlling a current flowing through the main electrode is applied, and the semiconductor device includes: a recess formed in the surface of the semiconductor substrate, wherein the source region is exposed on an inner surface of the recess and the main electrode is connected to the source region at the inner surface of the recess. | 2015-04-02 |
| 20150091083 | Semiconductor Device and Method of Manufacturing a Semiconductor Device with Lateral FET Cells and Field Plates - A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections. | 2015-04-02 |
| 20150091084 | POWER MOSFET DEVICES INCLUDING EMBEDDED SCHOTTKY DIODES AND METHODS OF FABRICATING THE SAME - A semiconductor device can include first and second vertical channel power MOSFET transistors that are arranged in a split-gate configuration in a semiconductor substrate. A groove can be in an active region between the first and second vertical channel power MOSFET transistors and a conductive pattern can be in the groove on the active region, where the conductive pattern can include a source contact for the first and second vertical channel power MOSFET transistors. A vertical Schottky semiconductor region can be embedded in the groove beneath the conductive pattern between the vertical channels. | 2015-04-02 |
| 20150091085 | MOS DEVICE WITH ISOLATED DRAIN AND METHOD FOR FABRICATING THE SAME - A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type. | 2015-04-02 |
| 20150091086 | Raised Epitaxial LDD in MuGFETs and Methods for Forming the Same - Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction. | 2015-04-02 |
| 20150091087 | METAL OXIDE SEMICONDUCTOR (MOS) DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a metal oxide semiconductor (MOS) device and a manufacturing method thereof. The MOS device is formed in a substrate with an upper surface and it includes: an isolation region, a well region, a gate, a lightly-doped-source (LDS), a lightly-doped-drain (LDD), a source, and a drain. The isolation region defines an operation region. The gate includes: a dielectric layer, a stack layer, and a spacer layer, wherein the stack layer separates the operation region to a first side and a second side. The LDS with a first conductive type, is formed in the substrate beneath the upper surface, and at least part of the LDS overlaps the stack layer from a top view. The source with a second conductive type overlaps the spacer layer at the first side. The conductive types of the LDS and the source are different to mitigate the threshold voltage roll-off. | 2015-04-02 |
| 20150091088 | Integrated Circuit and Method of Manufacturing an Integrated Circuit - An integrated circuit includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode. | 2015-04-02 |
| 20150091089 | AIR-SPACER MOS TRANSISTOR - A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers. | 2015-04-02 |
| 20150091090 | MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure and a method of fabricating a semiconductor device structure are provided. A first device layer is formed over a substrate, where an alignment structure is patterned in the first device layer. A dielectric layer is provided over the first device layer. The dielectric layer is patterned to include an opening over the alignment structure. A second device layer is formed over the dielectric layer. The second device layer is patterned using a mask layer, where the mask layer includes a structure that is aligned relative to the alignment structure. The alignment structure is visible via the opening during the patterning of the second device layer. | 2015-04-02 |
| 20150091091 | JUNCTION-LESS TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a junction-less transistor. The method includes providing a semiconductor substrate having a dielectric layer; and forming a semiconductor layer including a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer. The method also includes etching the semiconductor layer and the dielectric layer to form trenches to expose side surfaces of a portion of the semiconductor layer and a portion of the dielectric layer; and removing the portion of the dielectric layer between the adjacent trenches to form a chamber. Further, the method includes forming a gate structure around the portion of the semiconductor layer between the adjacent trenches; and forming a source region and a drain region in the semiconductor layer at both sides of the gate structure. | 2015-04-02 |
| 20150091092 | Dynamic Threshold MOS and Methods of Forming the Same - A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode. | 2015-04-02 |
| 20150091093 | INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME - Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal. | 2015-04-02 |
| 20150091094 | DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION - Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate. | 2015-04-02 |
| 20150091095 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a circle or polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode. | 2015-04-02 |
| 20150091096 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a pipe channel layer formed on a semiconductor substrate, a first channel layer, a second channel layer and a third channel layer, connected with the pipe channel layer, first conductive layers stacked while surrounding the first channel layer, second conductive layers stacked while surrounding the second channel layer, and third conductive layers stacked while surrounding the third channel layer, wherein the first to third conductive layers are separately controlled. | 2015-04-02 |
| 20150091097 | HARDMASK FOR A HALO/EXTENSION IMPLANT OF A STATIC RANDOM ACCESS MEMORY (SRAM) LAYOUT - Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor. | 2015-04-02 |
| 20150091098 | SEMICONDUCTOR DEVICE HAVING A MONOLITHIC INTER-TIER VIA (MIV), AND METHOD OF MAKING SAME - A three dimensional semiconductor device includes a first memory device, a second memory device and a via. The via connects the first memory device to the second memory device. | 2015-04-02 |
| 20150091099 | FinFETs with Gradient Germanium-Containing Channels - A method includes forming a semiconductor fin, forming a dummy gate on a top surface and sidewalls of the semiconductor fin, and removing the dummy gate to form a recess. The semiconductor fin is exposed to the recess. After the dummy gate is removed, an oxidation is performed on the semiconductor fin to form a condensed germanium-containing fin in the recess, and a silicon oxide layer on a top surface and sidewalls of the condensed germanium-containing fin. The method further includes forming a gate dielectric over the condensed germanium-containing fin, and forming a gate electrode over the gate dielectric. | 2015-04-02 |
| 20150091100 | METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure. | 2015-04-02 |
| 20150091101 | DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a display device that may include a gate electrode and a first metal pattern on a substrate, the gate electrode being formed on a first region of the substrate and the first metal pattern being formed on a second region of the substrate; an insulating film formed on the gate electrode and the first metal pattern and provided with a first hole for exposing at least a part of the first metal pattern; source and drain electrodes formed on the insulating film in the first region and a second metal pattern formed on the insulating film in the second region; a pixel electrode formed on the source and drain electrodes, the pixel electrode electrically connected with the drain electrode, and a first protection electrode formed on the second metal pattern, the first protection electrode electrically connected with the second metal pattern and at least partially covering the second metal pattern; a passivation film formed on an entire surface of the substrate including the pixel electrode and the first protection electrode and provided with a second hole for exposing at least a part of the first metal pattern and a third hole for exposing at least a part of the first protection electrode; and a connection electrode formed on the passivation film, the connection electrode connected with the first metal pattern through a first contact hole formed by a combination of the first hole and the second hole, and connected with the first protection electrode through a second contact hole formed of the third hole, wherein the first protection electrode is formed of the same material as that of the pixel electrode. | 2015-04-02 |
| 20150091102 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction. | 2015-04-02 |
| 20150091103 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate stack, an isolation structure and a strained feature. The gate stack is over a substrate. The isolation structure is in the substrate. The strained feature is disposed between the gate stack and the isolation structure and disposed in the substrate. The strained feature includes an upper surface adjacent to the isolation structure having a first crystal plane and a sidewall surface adjacent to the gate stack having a second crystal plane. The first crystal plane is different from the second crystal plane. | 2015-04-02 |
| 20150091104 | SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME - The invention provides a semiconductor structure and a semiconductor device having such semiconductor structure. The semiconductor structure includes: a substrate; a first well having a first conductivity type, which is provided on the substrate; a second well having a second conductivity type and contacting the first well at a boundary in between in a lateral direction; and a plurality of mitigation regions having the first conductivity type or the second conductivity type, provided in the first well and being close to the boundary in a lateral direction and penetrating the first well in a vertical direction. | 2015-04-02 |
| 20150091105 | CONTINUOUS TUNING OF ERBIUM SILICIDE METAL GATE EFFECTIVE WORK FUNCTION VIA A PVD NANOLAMINATE APPROACH FOR MOSFET APPLICATIONS - Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nano-laminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack. | 2015-04-02 |
