14th week of 2009 patent applcation highlights part 55 |
Patent application number | Title | Published |
20090089532 | Serial Buffer Supporting Virtual Queue To Physical Memory Mapping - A serial buffer having a plurality of virtual queues, which can be allocated to include various combinations of on-chip dual-port memory blocks, on-chip internal memory blocks and/or off-chip external memory blocks. The virtual queues are allocated and accessed in response to configuration bits and size bits stored on the serial buffer. Relatively large external memory blocks can be allocated to virtual queues used for data intensive operations, while relatively small and fast dual-port memory blocks can advantageously be allocated to virtual queues used for passing command and status information. The serial buffer provides an efficient and flexible manner for utilizing available memory, which not only minimizes the access latency but also provides a large amount of buffer space to meet different application needs. | 2009-04-02 |
20090089533 | Image Forming Apparatus and Computer-Readable Medium - Disclosed is an image forming apparatus including a communication section connected to a data processing apparatus through a communication line to perform image formation on the basis of data transmitted from the data processing apparatus through the communication section, the apparatus including: a plurality of storage sections each of which has a different free storage capacity and a different access speed; and a control section to obtain data size information of an XPS file from the XPS file including the data size information thereof in a head of a file data, frame, the XPS file being received from the data processing apparatus through the communication section, to select a storage section to store the XPS file from the plurality of storage sections on the basis of the data size information, and to allow the selected storage section to store the XPS file. | 2009-04-02 |
20090089534 | Thin Provisioning Migration and Scrubbing - A method for migrating data to a mass storage system, including receiving an incoming data partition for storage in the mass storage system and allocating logical storage for the incoming data partition in the mass storage system. The method further includes making a determination that the incoming data partition includes only zero data, and, in response to the determination, inhibiting physical storage of the incoming data partition in the mass storage system while maintaining the allocated logical storage for the incoming data partition. | 2009-04-02 |
20090089535 | MEDIA CONTAINER FILE MANAGEMENT - The invention teaches a media container file comprising media data organized into media source blocks. The media source blocks are partitioned into source symbols that can be processed by a forward error correction (FEC) algorithm for generation of FEC redundancy data. Information of this source block partitioning is included in the file in addition to the source blocks. The container file also comprises meta data providing an association between the media source blocks and the partitioning information. The container file can be employed by a media server in a media session for compiling media data packets to be transmitted to requesting clients without the need of extensive data processing before calculating FEC data. | 2009-04-02 |
20090089536 | METHOD FOR ASSIGNING ADDRESSES TO MEMORY DEVICES - A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations. | 2009-04-02 |
20090089537 | APPARATUS AND METHOD FOR MEMORY ADDRESS TRANSLATION ACROSS MULTIPLE NODES - A method for translating memory addresses in a plurality of nodes, that includes receiving a first memory access request initiated by a processor of a first node of the plurality of nodes, wherein the first memory access request comprises a process virtual address and a first memory operation, translating the process virtual address to a global system address, wherein the global system address corresponds to a physical memory location on a second node of the plurality of nodes, translating the global system address to an identifier corresponding to the second node, and sending a first message requesting the first memory operation to the second node based on the identifier, wherein the second node performs the first memory operation on the physical memory location. | 2009-04-02 |
20090089538 | Synchronous Address And Data Multiplexed Mode For SRAM - A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode. | 2009-04-02 |
20090089539 | SYSTEM AND METHOD FOR DETECTING EMAIL CONTENT CONTAINMENT - Systems and methods for detecting email content containment are disclosed. In one embodiment, a method comprises generating a first set of hash values corresponding to a first email document, wherein the first set includes a respective hash value corresponding to each of a plurality of character sequences of the first email document. The method further comprises generating a second set of hash values corresponding to a second email document, wherein the second set include a respective hash value corresponding to each of a plurality of character sequences of the second email document, and determining whether the first set of hash values is a subset of the second set of hash values. | 2009-04-02 |
20090089540 | Processor architecture for executing transfers between wide operand memories - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2009-04-02 |
20090089541 | MULTIPROCESSING DEVICE AND INFORMATION PROCESSING DEVICE - Instructions executed by a plurality of processors including a specific processor and the other processors connected to the specific processor are stored in an instruction storage memory. The instructions stored in the instruction storage memory are transferred to and retained in an instruction execution memory, and when an instruction is executed by one of the plurality of processors, a required instruction is retrieved by the processor. A leading address of a position where the required instruction of the other processors is retained in the instruction execution memory is stored in an address storage memory. A memory control circuit coordinates access to the instruction execution memory by the plurality of processors and controls access to the address storage memory by the specific processor. | 2009-04-02 |
20090089542 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PERFORMING A SCAN OPERATION - A system, method, and computer program product are provided for efficiently performing a scan operation. In use, an array of elements is traversed by utilizing a parallel processor architecture. Such parallel processor architecture includes a plurality of processors each capable of physically executing a predetermined number of threads in parallel. For efficiency purposes, the predetermined number of threads of at least one of the processors may be executed to perform a scan operation involving a number of the elements that is a function (e.g. multiple, etc.) of the predetermined number of threads. | 2009-04-02 |
20090089543 | INTEGRATED CIRCUIT PERFORMANCE IMPROVEMENT ACROSS A RANGE OF OPERATING CONDITIONS AND PHYSICAL CONSTRAINTS - Methods and apparatus to improve integrated circuit (IC) performance across a range of operating conditions and/or physical constraints are described. In one embodiment, an operating parameter of one or more of processor cores may be adjusted in response to a change in the activity level of processor cores (e.g., the number of active processor cores) and/or a comparison of one or more operating conditions and one or more corresponding threshold values. Other embodiments are also described. | 2009-04-02 |
20090089544 | Infrastructure for parallel programming of clusters of machines - GridBatch provides an infrastructure framework that hides the complexities and burdens of developing logic and programming application that implement detail parallelized computations from programmers. A programmer may use GridBatch to implement parallelized computational operations that minimize network bandwidth requirements, and efficiently partition and coordinate computational processing in a multiprocessor configuration. GridBatch provides an effective and lightweight approach to rapidly build parallelized applications using economically viable multiprocessor configurations that achieve the highest performance results. | 2009-04-02 |
20090089545 | MULTI PROCESSOR SYSTEM HAVING MULTIPORT SEMICONDUCTOR MEMORY WITH PROCESSOR WAKE-UP FUNCTION - A multiport semiconductor memory device having a processor wake-up function and multiprocessor system employing the same is provided. The multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including: a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, the wake-up signal generator being coupled to the first processor and the second processor. | 2009-04-02 |
20090089546 | Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache - In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads. | 2009-04-02 |
20090089547 | SYSTEM AND METHOD FOR MONITORING DEBUG EVENTS - A system has a pipelined processor for executing a plurality of instructions by sequentially fetching, decoding, executing and writing results associated with execution of each instruction. Debug circuitry is coupled to the pipelined processor for monitoring execution of the instructions to determine when a debug event occurs. The debug circuitry generates a debug exception to interrupt instruction processing flow. The debug circuitry has control circuitry for indicating a number of instructions, if any, that complete instruction execution between an instruction that caused the debug event and a point in instruction execution when the exception is taken. | 2009-04-02 |
20090089548 | METHOD FOR PRELOADING DATA IN A CPU PIPELINE - A method for preloading data in a CPU pipeline is provided, which includes the following steps. When a hint instruction is executed, allocate and initiate an entry in a preload table. When a load instruction is fetched, load a piece of data from a memory into the entry according to the entry. When a use instruction which uses the data loaded by the load instruction is executed, forward the data for the use instruction from the entry instead of from the memory. When the load instruction is executed, update the entry according to the load instruction. | 2009-04-02 |
20090089549 | H.264 Video Decoder CABAC Core Optimization Techniques - A device employing techniques to optimize Context-based Adaptive Binary Arithmetic Coding (CABAC) for the H.264 video decoding is provided. The device includes a processing circuit operative to implement a set of instructions to decode multiple bins simultaneously and renormalize an offset register and a range register after the multiple bins are decoded. The range register and offset registers may be 32 or 64 bits. The use of a larger range register allows renormalization to be skipped when enough bits are still in the range register. | 2009-04-02 |
20090089550 | JEK DYNAMIC INSTRUMENTATION - A method and system for performing dynamic instrumentation. At least some of the illustrative embodiments are methods comprising setting at least one monitor value (wherein the at least one monitor value is associated with a software monitoring handler), detecting a value within a register equal to the at least one monitor value, and executing the software monitoring handler based on the detecting. | 2009-04-02 |
20090089551 | Apparatus and method of avoiding bank conflict in single-port multi-bank memory system - Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict. | 2009-04-02 |
20090089552 | Dependency Graph Parameter Scoping - A number of tasks are defined according to a dependency graph. Multiple parameter contexts are maintained, each associated with a different scope of the tasks. A parameter used in a first of the tasks is bound to a value. This binding includes identifying a first of the contexts according to the dependency graph and retrieving the value for the parameter from the identified context. | 2009-04-02 |
20090089553 | MULTI-THREADED PROCESSING - A system includes a multi-threaded processor that executes an instruction of a process of an executing program. The multi-threaded processor includes at least a first and a second thread. First and second sets of source registers are respectively allocated to the first and second threads, and first and second sets of destination registers are respectively allocated to the first and second threads. A resource prefix configuration register includes mappings between each of the source and destination registers and the threads. The multi-threaded processor, during execution of the instruction by one of the first or the second threads of execution, accesses the source and destination registers based on the mapping, wherein at least one of the accessed registers is allocated to the other of the first or the second thread of execution. | 2009-04-02 |
20090089554 | METHOD FOR TUNING CHIPSET PARAMETERS TO ACHIEVE OPTIMAL PERFORMANCE UNDER VARYING WORKLOAD TYPES - A method, system, and computer program product for tuning a set of chipset parameters to achieve optimal chipset performance under varying workload characteristics. A set of workload characteristics of a current workload type is determined. An instruction stream is generated using weighted parameters derived from the set of workload characteristics of the current workload type. A set of chipset parameters is generated and integrated within the instruction stream. The instruction stream is loaded to one or more processors and executed to collect and analyze performance data relating to the chipset's performance. The analysis includes comparing the set of performance data of a plurality of different instruction streams having the same set of workload characteristics. Each executed instruction stream is executed with at least one different combination of chipset parameters. A determination is made regarding which combination of chipset parameters provides the best performance data for the current workload. | 2009-04-02 |
20090089555 | Methods and apparatus for executing or converting real-time instructions - In one embodiment, a computer processor is configured to execute a plurality of instructions defined by an instruction set including at least one real-time instruction. Each of the at least one real-time instruction specifies an execution timing of a respective one of the at least one real-time instruction. Each execution timing is tied to a common real-time measurement system. Other embodiments are also described. | 2009-04-02 |
20090089556 | High-Speed Add-Compare-Select (ACS) Circuit - A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay. | 2009-04-02 |
20090089557 | UTILIZING MASKED DATA BITS DURING ACCESSES TO A MEMORY - Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted. | 2009-04-02 |
20090089558 | ADJUSTMENT OF DATA COLLECTION RATE BASED ON ANOMALY DETECTION - Systems and methods that vary multiple data sampling rates, to collect sets of data with different levels of granularity for an industrial system. The data for such industrial system includes sets of data from the “internal” data stream(s) (e.g., history data collected from an industrial unit) and sets of data from an “external” (e.g., traffic data on network services) data stream(s), based in part on the criticality/importance criteria assigned to each collection stage. Each set of data can be assigned its own unique data collection rate. For example, a higher sample rate can be employed when collecting data from the network during an operation stage that is deemed more critical (e.g., dynamic attribution of predetermined importance factors) than the rest of the operation. | 2009-04-02 |
20090089559 | METHOD OF MANAGING DATA MOVEMENT AND CELL BROADBAND ENGINE PROCESSOR USING THE SAME - A method of managing data movement in a cell broadband engine processor, comprising: determining one or more idle synergistic processing elements among multiple SPEs in the cell broadband engine processor as a managing SPE, and informing a computing SPE among said multiple SPEs of a starting effective address of a LS of said managing SPE and an effective address for a command queue; and said managing SPE managing movement of data associated with computing of said computing SPE based on the command queue from the computing SPE. | 2009-04-02 |
20090089560 | INFRASTRUCTURE FOR PARALLEL PROGRAMMING OF CLUSTERS OF MACHINES - GridBatch provides an infrastructure framework that hides the complexities and burdens of developing logic and programming application that implement detail parallelized computations from programmers. A programmer may use GridBatch to implement parallelized computational operations that minimize network bandwidth requirements, and efficiently partition and coordinate computational processing in a multiprocessor configuration. GridBatch provides an effective and lightweight approach to rapidly build parallelized applications using economically viable multiprocessor configurations that achieve the highest performance results. | 2009-04-02 |
20090089561 | VISUALIZING CHANGES TO CONTENT OVER TIME - A processing device and method are provided for visualizing changes to dynamic content. Dynamic content may be obtained from a content source and a state of the content may be saved. The saved state of the content may be compared with a previously saved state of the content to produce difference data, indicating differences between the saved state of the content and the previously saved state of the content. The obtained content may be presented to a user and may include visual indications pointing out added portions of the content, deleted portions of the content, and/or unchanged portions of the content. In some embodiments, a scheduler may be configured to obtain content and save a state of the content at particular times or upon occurrences of particular events. In various embodiments, aged states of the content may be degraded. | 2009-04-02 |
20090089562 | Methods and apparatuses for reducing power consumption of processor switch operations - Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions. | 2009-04-02 |
20090089563 | METHOD AND SYSTEM OF PERFORMING THREAD SCHEDULING - A method and system of performing thread scheduling. At least some of the illustrative embodiments are computer-readable mediums storing a program that, when executed by a processor of a host system, causes the processor to instantiate a CPU object that represents a processor abstraction, create a CPU context object that represents a thread abstraction (wherein the CPU context object is associated to a method, and wherein the CPU context object is mapped onto the CPU object), and execute the method within the CPU object. | 2009-04-02 |
20090089564 | Protecting a Branch Instruction from Side Channel Vulnerabilities - Embodiments of an invention to protection a branch instruction from side channel vulnerabilities are described. In one embodiment, a method includes receiving a request to modify the operation of a processor to protect against side channel attacks, and modifying branch prediction operation in response to the request. | 2009-04-02 |
20090089565 | Method and Apparatus for Configuring a Device Based on Proximity to Another Device - Methods and apparatus are provided for configuring a device based on proximity to another device. A user device is configured by obtaining one or more configuration rules that establish one or more configuration parameters of the user device based on a proximity to one or more additional general purpose devices; determining whether one or more of the configuration rules are satisfied; and configuring the user device based on the satisfied one or more configuration rules. The configuration rules can be configured by an authorized user of the user device. The proximity comprises a predefined physical relationship between devices that is based on distance, such as a radius around a given device, or a physical relationship, such as in the same room or building, or within a communication range of a device. | 2009-04-02 |
20090089566 | SUPPORTING ADVANCED RAS FEATURES IN A SECURED COMPUTING SYSTEM - Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand. | 2009-04-02 |
20090089567 | Applying Firmware Updates To Servers In A Data Center - Applying firmware updates to servers in a data center, the servers including one or more active servers and a standby server, each server mapped to separate remote computer boot storage, including applying the firmware updates to the standby server; selecting an active server for firmware updating; powering off the selected active server by the system management server; remapping the standby server to the remote computer boot storage for the selected active server; rebooting the standby server from the remote computer boot storage for the selected active server, designating the standby server as an active server; remapping the selected active server to the remote computer boot storage formerly mapped to the standby server; and rebooting the selected active server from the remote boot storage formerly mapped to the standby server, designating the selected active server as a standby server. | 2009-04-02 |
20090089568 | Securely Launching Encrypted Operating Systems - Tools and techniques for securely launching encrypted operating systems are described herein. The tools may provide computing systems that include operating systems (OSs) that define boot paths for the systems. This boot path may include first and second OS loader components. The first loader may include instructions for retrieving a list of disk sectors from a first store, and for retrieving these specified sectors from an encrypted second store. The first loader may also store the sectors in a third store that is accessible to both the first and the second loader components, and may invoke the second loader to try launching the OS using these sectors. In turn, the second loader may include instructions for retrieving these sectors from the third store, and for unsealing a key for decrypting these sectors. The second loader may then decrypt these sectors, and attempt to launch the OS from these sectors. | 2009-04-02 |
20090089569 | MULTI-OS (OPERATING SYSTEM) BOOT VIA MOBILE DEVICE - A system that facilitates different levels of operating system (OS) boot so as to provide users with rapid access to certain mobile device functionalities, security, applications, etc. is provided. An OS can be loaded in phases or stages commensurate with policies, preferences, actions, context, etc. Similarly, a particular OS or group of OSs can be loaded to address a particular scenario or requirement. | 2009-04-02 |
20090089570 | Method, system and apparatus for providing a boot loader of an embedded system - A method, system and apparatus for executing a boot loader for an embedded system including a system-on-chip (SOC) processor coupled to a memory including first boot loader code for implementing a first boot loader stored in a first sector and second boot loader code for implementing a second boot loader stored in a second sector determines which of the first boot loader code and second boot loader code is younger; if the second boot loader code is determined to be younger than the first boot loader code, a swapping operation is performed so that the second boot loader code is associated with the first sector and the first boot loader code is associated with a different sector, and the boot loader code associated with the first sector is executed. | 2009-04-02 |
20090089571 | MOTHERBOARD AND START-UP METHOD THEREOF - A motherboard comprises a first unit which includes most components that are common in a group of motherboards which have a same chip set, a second unit which includes components that are different in the group of motherboards, and a BIOS Bin file which is loaded in the first unit. The BIOS Bin file comprises a share module, a loading module unit which includes a plurality of loading modules each corresponding to one type of motherboard, and a startup module which identifies the type of the motherboard according to a voltage of pre-selected GPIO Pins, and reads one of the loading modules corresponding to that type of motherboard to identify and initiate the second unit, and reads the share module to identify and initiate the first unit. | 2009-04-02 |
20090089572 | BOOTING SYSTEM, IMAGE FORMING APPARATUS HAVING THE SYSTEM AND CONTROL METHOD THEREOF - A booting system including a boot code transmission control unit to sequentially execute a booting operation concurrently with storing boot codes stored in a NAND flash memory in an internal memory. The boot code transmission control unit includes storage units to store addresses of the boot codes stored in the internal memory and an address of a boot code to be accessed by a CPU core for the execution of the booting operation, respectively. These addresses are checked by monitoring a memory interface and a bus interface. When the boot code addresses are the same, the boot code transmission control unit transmits a boot code corresponding to the same address, among the boot codes stored in the internal memory, to the CPU core so that the CPU core can sequentially execute the booting operation. | 2009-04-02 |
20090089573 | MULTI PROCESSOR SYSTEM HAVING DIRECT ACCESS BOOT AND DIRECT ACCESS BOOT METHOD THEREOF - A multiprocessor system having a direct access boot operation and a direct access boot method are provided to substantially reduce a boot error of processor that does not provide a memory link architecture in the multiprocessor system. In an embodiment of the invention, a multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including at least one shared memory area, the multiport semiconductor memory device configured to provide access to the at least one shared memory area by the first processor and the second processor; and a non-volatile memory device coupled to the first processor and the second processor, the non-volatile memory device storing a first boot code associated with the first processor and a second boot code associated with the second processor, the multiprocessor system configured to provide the first processor direct access to the non-volatile memory area during a boot operation and indirect access to the non-volatile memory area otherwise. | 2009-04-02 |
20090089574 | SYSTEM, METHOD AND PROGRAM FOR PROTECTING COMMUNICATION - A system, method and program product for transferring data between a first computer and a second computer. A first request to start a session is received. An encrypted hash value in the first request is decrypted and a hash value for the information in the first request is independently determined. The independently determined hash value is compared to the decrypted hash value, and if there is match, a session with the first computer is started. Subsequently, a second request is received and the encrypted hash value in the second request is decrypted. A hash value for the information in the second request is independently determined. The independently determined hash value is compared to the decrypted hash value, and if there is match, the second computer processes a request to at least partially download or upload a file. | 2009-04-02 |
20090089575 | Service Providing System, Outsourcer Apparatus, Service Providing Method, and Program - When an entrustor entrusts an outsourcer with the supply of a service for members, member information managed by the entrustor is kept secret from the outsourcer, and users can receive the service without communicating with the entrustor. For using the service, user apparatus | 2009-04-02 |
20090089576 | TECHNIQUES FOR COMMUNICATING INFORMATION OVER MANAGEMENT CHANNELS - Techniques for communicating information over management channels are described. An apparatus may comprise a classifier module operative to classify management information for a wireless communications network as media access control security management information or media access control management information. The apparatus may further comprise a wireless transceiver to couple to the classifier module, the wireless transceiver operative to communicate the media access control security management information over an insecure management connection and the media access control management information over a secure management connection. Other embodiments are described and claimed. | 2009-04-02 |
20090089577 | MAC FRAME PROVISION METHOD AND APPARATUS CAPABLE OF ESTABLISHING SECURITY IN IEEE 802.15.4 NETWORK - A medium access control (MAC) frame provision method establishes security in an IEEE 802.15.4 network. A MAC frame is generated, which includes a MAC header, a payload field, and a frame check sequence (FCS) field, the payload field including relevant main data according to a frame type defined in the MAC header. A disguised decoy data sequence number (DSN) is generated and inserted into the MAC header. A real DSN, which is a corresponding transmission sequence number of the MAC frame, is generated and inserted into the payload field. The MAC frame is transmitted, including the encrypted payload field, to a counterpart node. A MAC ACK frame acknowledges reception of the transmitted MAC frame; and a DSN is compared in the received MAC ACK frame with the real DSN. An authentication of the counterpart node is performed when the received MAC ACK frame is equal to the real DSN. | 2009-04-02 |
20090089578 | DIGEST GENERATION FROM INSTRUCTION OP-CODES - In general, in one aspect, a computer-implemented method includes determining a digest value based on hash operations on values of, at least, a set op-codes of multiple instructions of a program during execution of the program by a processor. | 2009-04-02 |
20090089579 | Secure Policy Differentiation by Secure Kernel Design - A method, computer program product, and data processing system are disclosed for ensuring that applications executed in the data processing system originate only from trusted sources are disclosed. In a preferred embodiment, a secure operating kernel maintains a “key ring” containing keys corresponding to trusted software vendors. The secure kernel uses vendor keys to verify that a given application was signed by an approved vendor. To make it possible for users to execute software from independent software developers, an administrative user may disable the above-described vendor key-checking as an option. | 2009-04-02 |
20090089580 | WIRELESS COMMUNICATION DEVICE, PORTABLE TERMINAL, COMMUNICATION CONTROL PROGRAM AND COMMUNICATION SYSTEM - A wireless communication device, comprising: a wireless communication unit which communicates with other communication device located at a prescribed range; a first identification information generator which generates first identification information including a service name of available service and inherent information; an encryption unit configured to encrypt said first identification information by using a prescribed encryption key to generate encryption data; a second identification information generator which generates second identification information including the service name, the inherent information and the encryption data; and an inherent information transmitter which transmits the second identification information for an other communication device which has requested transmission of the inherent information. | 2009-04-02 |
20090089581 | System and Method for Securing Data Through a PDA Portal - Consumers may utilize computing devices to assist in the purchase and/or loyalty process, and in particular, the consumer may utilize a PDA to facilitate the purchase and/or loyalty process. During the purchase and/or loyalty process, the consumer may need to insure that any content downloaded or used in association with the PDA is secure in how it is collected, assembled, and delivered to the PDA device. This system and method secures the data from its source to when it is actually viewed or used by the authorized user. The PDA may have direct access to an Internet web site portal that offers secure personal content from a content provider, such as, for example, an on-line banking or financial institution. Using the web site portal, the content provider may offer personal or confidential data, such as financial information, to PDA users in a secure (e.g., encrypted) environment. The exemplary system and method may establish a PDA portal link to the web site for collecting specified information for a user and transmitting the information to the remote device. To receive the information, the PDA contacts the portal and establishes a connection, authenticates itself to the network and allows the user to complete secured transactions or transmissions over the network. | 2009-04-02 |
20090089582 | METHODS AND APPARATUS FOR PROVIDING UPGRADEABLE KEY BINDINGS FOR TRUSTED PLATFORM MODULES - A processing system with a trusted platform module (TPM) supports migration of digital keys. For instance, an application in the processing system may create a first configuration key as a child of a TPM storage root key (SRK) when the processing system has a first configuration. The application may also create an upgradable root user key associated with an upgrade authority as a child of the first configuration key. The application may also create a user key as a child of the upgradable root user key. When the processing system has a second configuration, the application may create a second configuration key as a child of the SRK. The application may request migration approval from the upgrade authority. In response to receiving the approval from the upgrade authority, the application may migrate the root user key to be a child of the second configuration key. Other embodiments are described and claimed. | 2009-04-02 |
20090089583 | Method of establishing authentication keys and secure wireless communication - A method of establishing authentication keys at both a network and mobile equipment are provided. The authentication key generated by the mobile equipment is based on both mobile keys and network keys, which are each calculated by the mobile equipment. The authentication key generated by the network is based on both mobile keys and network keys, which are each calculated by the network. The mobile keys are calculated from a challenge generated by the mobile equipment and the network keys generated by the mobile based on a challenge generated by network. | 2009-04-02 |
20090089584 | SYSTEMS, DEVICES, AND METHODS FOR OUTPUTTING ALERTS TO INDICATE THE USE OF A WEAK HASH FUNCTION - Systems, devices, and methods for outputting an alert on a mobile device to indicate the use of a weak hash function are disclosed herein. In one example embodiment, the method comprises receiving data (e.g. from a server) that identifies at least one first hash function, identifying a hash digest generated using a second hash function, determining if the second hash function is weak using the received data, and outputting an alert indicating that the second hash function is weak if it is determined that the second hash function is weak. | 2009-04-02 |
20090089585 | DIGITAL WATERMARK EMBEDDING APPARATUS AND DIGITAL WATERMARK DETECTING APPARATUS - A digital watermark embedding apparatus includes: an extractor configured to extract a specific frequency component from each of N kinds of scaled images about an input image signal to generate N kinds of extracted signals; a generator configured to compress the amplitude of the respective extracted signals on the basis of N kinds of to-be-embedded information corresponding to the N kinds of extracted signals to generate watermark image signals by shifting the predetermined phases; and a superimposer configured to add the N kinds of watermark image signals to the input image signal to generate an output image signal. | 2009-04-02 |
20090089586 | Methods, Apparatus and Programs for Generating and Utilizing Content Signatures - The presently claimed invention generally relates to deriving and/or utilizing content signatures (e.g., so-called “fingerprints”). One claim recites a method of generating a fingerprint associated with a content item including: pseudo-randomly selecting a segment of the content item; and utilizing a processor or electronic processing circuitry, fingerprinting the selected segment of content item as at least an identifier of the content item. Of course, other claims and combination are provided as well. | 2009-04-02 |
20090089587 | Methods, Apparatus and Programs for Generating and Utilizing Content Signatures - The presently claimed invention generally relates to deriving and/or utilizing content signatures (e.g., so-called “fingerprints”). One claim recites a method comprising: obtaining a sequence of content identifiers, the sequence of content identifiers corresponding to one or more segments of a media signal; and utilizing at least a processor or electronic processing circuitry, carrying out a convolution operation based on the sequence of content identifiers and content signatures housed or stored in a database to identify the media signal. Of course, other claims and combination are provided as well. | 2009-04-02 |
20090089588 | METHOD AND APPARATUS FOR PROVIDING ANTI-THEFT SOLUTIONS TO A COMPUTING SYSTEM - A manageability engine (ME) may be used to authenticate a user for a computer system. A data collection module may be coupled to the ME to collect data (e.g., fingerprint image, facial images, speech, etc.) from a user. The ME processes the collected data to authenticate the user. If the authentication is successful, the system may boot, resume from a sleep state, or become re-accessible by the user; otherwise, the user is prevented from using the system or accessing data stored therein. | 2009-04-02 |
20090089589 | INFORMATION PROCESSING APPARATUS FOR PROTECTED DATA FILES AND INFORMATION PROCESSING METHOD THEREOF - According to one embodiment, a processing environment of protected file data is improved by an inspection module which inspects whether file ARF protected in a predetermined format is usable or unusable, an information table in which usable/unusable data of the ARF is set based on the inspection result of the inspection module, a file cache which stores the ARF, the usable/unusable data of which is set in this table, and a decryption processor which decrypts resource data as the contents of an encrypted data object using the ARF stored in this cache. | 2009-04-02 |
20090089590 | MERGING EXTERNAL NVRAM WITH FULL DISK ENCRYPTION - Methods and arrangements for managing a flash drive, hard disk, or connection between the two, in a manner to ensure that sensitive data is not decrypted at any time when it would be vulnerable. Accordingly, in a first implementation, the data may preferably be encrypted as it first goes into a flash drive and decrypted when it comes out of the flash drive. In another implementation, the flash drive may be logically bound to the hard disk, so that they would both use the same encryption key. In yet another implementation, if a hard disk is moved to another system, then the flash drive may also preferably be simultaneously moved. | 2009-04-02 |
20090089591 | Data security in a disconnected environment - Systems and methods are provided for the detection and prevention of intrusions in data at rest systems such as file systems and web servers. The systems and methods regulate access to sensitive data with minimal dependency on a communications network. Data access is quantitatively limited to minimize the data breaches resulting from, e.g., a stolen laptop or hard drive. | 2009-04-02 |
20090089592 | INFORMATION PROCESSING DEVICE, LOG MANAGEMENT APPARATUS, AND LOG MANAGEMENT PROGRAM PRODUCT - Technology is provided, which allows to easily find tampering of event logs created by an information processing device and transmitted to a log management apparatus, without increasing communication load. A printer (i.e. information processing device) creates a hash value from the event log of an event every time the event occurs. The printer generates a digital signature by encrypting the hash value with its own private key. The printer transmits the signature-bound event log obtained by binding the digital signature with the event log to a server (i.e. log management apparatus). The server decrypts the hash value from the event log of the received signature-bound log information using a device public key. The server also generates a new hash value from the event log. The server verifies the coincidence of the decrypted hash value and the new hash value, and authenticates signature-bound event logs for which this coincidence has been verified. The server stores signature-bound event logs that have been authenticated. Every time an event occurs, the printer transmits an event log bound with a digital signature that is created using its private key. Only signature-bound event logs are communicated between the printer and the server. Event log tampering can easily be discovered from the signature-bound event logs. Thus, tampering of event logs can easily be discovered without increasing the communication load between the printer and server. | 2009-04-02 |
20090089593 | Recording system, information processing apparatus, storage apparatus, recording method, and program - Disclosed herein is a recording system including a storage apparatus incorporating a storage medium, and an information processing apparatus which is connectable to the storage apparatus and which holds a content to be recorded to the storage apparatus. | 2009-04-02 |
20090089594 | Method and System to Validate Physical and Logical System Connectivity of Components in a Data Processing System - A method, system, and computer program product are provided for validating a connection of powered elements within a data processing system. A request for data is issued to a set of powered elements using a set of communication channels. The set of communication channels comprises one or more alternating current power lines. The request is sent as a set of instructions injected onto the communication channels to the set of powered elements. Data received from the set of powered elements using the set of communication channels includes physical connection information for the set of powered elements. A determination is made as to whether each powered element in the set of powered elements is connected in a predetermined configuration. A notification is presented to a user identifying each powered element in the set of powered elements that is not connected in the predetermined configuration. | 2009-04-02 |
20090089595 | Managing Computer Power Among A Plurality Of Computers - Methods, systems, and computer program products are provided for managing computer power among a plurality of computers so that the aggregate power consumption does not exceed a maximum subscription amount, the maximum subscription amount comprising the maximum amount of power that can be supplied to the plurality of computers. Embodiments include monitoring, by a central power management module, aggregate power consumption of the plurality of computers; the central power management module and the computers coupled for data communications through a power management network; determining, by the central power management module, whether the aggregate power consumption exceeds a predetermined maximum aggregate power threshold, the maximum aggregate power threshold less than the maximum subscription amount; if the aggregate power consumption exceeds the predetermined maximum aggregate power threshold, throttling-down the plurality of computers, reducing the aggregate power consumption to a level below the predetermined maximum aggregate power threshold. Typical embodiments also include determining, by a central power management module, whether the aggregate power consumption is below a predetermined minimum aggregate power threshold; and if the aggregate power consumption is below a predetermined minimum aggregate power threshold, throttling-up the plurality of computers increasing the aggregate power consumption to a level that exceeds the predetermined minimum threshold. | 2009-04-02 |
20090089596 | Method and Apparatus for Mitigating Current Drain in a Low-Power Hand-Held Device - An authentication device or other type of low-power hand-held device comprises a processor, an external button alternately configurable in an unpressed state and a pressed state, and current drain mitigation circuitry coupled to the external button and a corresponding input of the processor. The current drain mitigation circuitry is configured to connect the input of the processor to a first potential when the external button is in the unpressed state and to connect the input of the processor to a second potential different than the first potential when the external button is in the pressed state, thereby limiting current drain arising from the external button being stuck in the pressed state. | 2009-04-02 |
20090089597 | INFORMATION PROCESSING DEVICE, METHOD OF CONTROLLING THE DEVICE, COMPUTER READABLE MEDIUM, AND SECURITY SYSTEM - An information processing device includes a power control section and a function-suppressing section. The power control section switches between a predetermined mode and a low-power mode on the basis of a pre-specified setting condition relating to power consumption of the information processing device. The low-power mode is lower in electricity consumption quantities than the predetermined mode. When switching from the low-power mode to the predetermined mode in a period of operation of an external security apparatus, the function-suppressing section suppresses a part of functions of the device in the predetermined mode. | 2009-04-02 |
20090089598 | SYSTEM AND METHOD FOR SELECTING OPTIMAL PROCESSOR PERFORMANCE LEVELS BY USING PROCESSOR HARDWARE FEEDBACK MECHANISMS - An embodiment of the present invention is a system and method relating to adaptive power management using hardware feedback to select optimal processor frequencies and reduce power/watt. In at least one embodiment, the present invention is intended to optimize processor frequency and power/watt usage based on the hardware feedback and processor stall behavior. | 2009-04-02 |
20090089599 | POWER SUPPLY SYSTEM FOR LOW POWER MCU - A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors. | 2009-04-02 |
20090089600 | Power supply efficiency optimization - Methods and apparatus operative in a portable electronic device having a processor and a switching mode power supply detect entry of the processor into a power saving mode during active operations and signal the switching mode power supply that the processor has entered a power saving mode. In response to the signaling the switching mode power supply optimizes its operating state in order to increase power supply efficiency. | 2009-04-02 |
20090089601 | Network system - Power consumption on GMPLS controlled networks can be reduced by cutting power consumption on spare paths that are not normally used. To achieve power consumption reduction, in the path setting process, a path is calculated while taking the power saving capability of each interface into account, and the applicable interface is set to the power-saving state when setting the spare path. When the spare path was set to the operating state, then the power-saving state on the applicable interface was canceled so that interface could operate normally. | 2009-04-02 |
20090089602 | METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT - A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system. | 2009-04-02 |
20090089603 | STORAGE DEVICE MAINTENANCE IN A PORTABLE DEVICE BASED ON A POWER EVENT - The disclosure is related to monitoring a portable electronic device to detect an occurrence of a power event. A command can be sent to a data storage device to initiate a maintenance procedure on the data storage device. In a particular embodiment, a method includes monitoring a portable electronic device to detect an occurrence of a power event. The method also includes selectively sending a command to a data storage device to initiate a maintenance procedure on the data storage device when the occurrence of the power event is detected. | 2009-04-02 |
20090089604 | APPARATUS, SYSTEM, AND METHOD FOR EVENT, TIME, AND FAILURE STATE RECORDING MECHANISM IN A POWER SUPPLY - An apparatus, system, and method are disclosed for event, time, and failure state recording in a power supply. Disclosed is a power supply that receives AC voltage as an input and provides regulated DC voltage as an output; a microcontroller integrated into the power supply that regulates output voltage and monitors, records, and reports operating conditions of the power supply; and a non-volatile solid-state storage that can be repeatedly read from, written to, and erased by the microcontroller and integrated within the microcontroller such that only a single address is needed to access both the microcontroller and the solid-state storage, the solid-state storage configured to store operating data received from the microcontroller, the operating data including the recorded operating conditions of the power supply. | 2009-04-02 |
20090089605 | POWER SUPPLY VOLTAGE MONITORS - The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. A power management unit controls power operations of the processing unit, the analog circuitry and the digital circuitry. Power monitoring circuitry provides power control signals to the power management unit. The power monitoring circuitry further includes a system voltage monitoring circuit for generating a system voltage control signal responsive to a system voltage level with respect to a predetermined level. The power monitoring circuitry also includes a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level. | 2009-04-02 |
20090089606 | Opportunistic initiation of data traffic - A method for trafficking data based at least in part on a power condition of a system resource. In one embodiment of the invention, a data trafficking device initiates data traffic in response to a detecting of an indication of the power condition. In another embodiment of the invention, the detected indication is independent of any data traffic of the data trafficking device. | 2009-04-02 |
20090089607 | Systems and methods for voltage regulator communication - Systems and method for providing a regulated voltage supply to an integrated circuit. In an embodiment of the invention, a voltage regulator in a system provides an integrated circuit in the system with information related to the voltage regulator providing a supply voltage to the integrated circuit. In another embodiment of the invention, the integrated circuit makes determinations about the operating characteristic of the system using information from the voltage regulator. | 2009-04-02 |
20090089608 | SYSTEMS AND METHODS FOR POWER SWING AND OUT-OF-STEP DETECTION USING TIME STAMPED DATA - A first intelligent electric device (IED) may be placed at a first location in an electrical power system and a second IED may be placed at a second location in the electrical power system. Voltage measurements may be received from the first and second IEDs. The measurements may be time aligned and used to calculate an angle difference between the first location and the second location in the electrical power system. A slip frequency and acceleration may be derived from the angle difference. The angle difference, slip frequency, and acceleration may be used to detect an out-of-step (OOS) condition in the electrical power system and/or a power swing between the first location and the second location in the electrical power system. The angle difference, slip frequency, and acceleration may also be used to predicatively detect OOS conditions. | 2009-04-02 |
20090089609 | CLUSTER SYSTEM WHEREIN FAILOVER RESET SIGNALS ARE SENT FROM NODES ACCORDING TO THEIR PRIORITY - A failover method for a cluster computer system in which a plurality of computers sharing a resource are connected by a heartbeat path for providing each computer with lines for monitoring operations of the other computers and a reset path. Resetting may be conducted based upon a registered priority for resetting the computers. | 2009-04-02 |
20090089610 | RAPID CRASH RECOVERY FOR FLASH STORAGE - Recovery is expedited for crashes involving flash memory. Rather than requiring an entire flash memory to be read to reconstruct lost information, only a subset of the memory need be read thereby reducing system down, among other thing. In particular, state information such as a logical to physical mapping is captured via a checkpoint operation periodically. Moreover, a deterministic usage pattern is employed to facilitate recovery of actions performed after a checkpoint. | 2009-04-02 |
20090089611 | METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR COORDINATING ERROR REPORTING AND RESET UTILIZING AN I/O ADAPTER THAT SUPPORTS VIRTUALIZATION - A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting of a physical I/O adapter that supports virtualization. The physical I/O adapter is virtualized by generating virtual I/O adapters that each represent a portion of the physical I/O adapter. Each one of the virtual I/O adapters is assigned to a different one of client logical partitions. A determination is made regarding whether the physical I/O adapter may have experienced an error. If the physical I/O adapter has experienced an error, all of the client logical partitions are notified about the error and a recovery of the physical I/O adapter is coordinated among all of the client logical partitions by waiting for each client logical partition to acknowledge the error notification before the physical I/O adapter is reset. | 2009-04-02 |
20090089612 | SYSTEM AND METHOD OF REDUNDANTLY STORING AND RETRIEVING DATA WITH COOPERATING STORAGE DEVICES - A system and method for data storage in an array. A system includes a client coupled to a storage subsystem. The storage subsystem comprises data storage locations addressable as rows and columns in an array. Each column comprises a separate storage device. Each row includes redundant data. For a given row, a coordinating storage device receives data from the client, coordinates computation and storage of redundant data, and forwards data to other storage devices. In response to receiving data targeted for storage in a given storage location, a non-volatile, temporary storage device that is associated with the separate storage device that includes the given storage location buffers the received data. The coordinating storage device conveys a write completion message to the client in response to detecting that the data has been buffered in the non-volatile, temporary storage devices. At least two storage devices are coordinating storage devices in separate rows. | 2009-04-02 |
20090089613 | REDUNDANCY SYSTEM HAVING SYNCRONIZATION FUNCTION AND SYNCRONIZATION METHOD FOR REDUNDANCY SYSTEM - A redundancy system that can perform synchronization even if a failure occurs to an application. According to the redundancy system of the present invention, a synchronization data memory area, a management bit map table having a flag created for each segment of the synchronization data memory area, and a management memory area for storing the starting address of the segment are set in each device. In the service application process, a service is performed using one or more segments, a flag corresponding to the segment is set, and synchronization information is written to the management memory each time the segment is written or overwritten. In the read process, each flag in the management bit map table is checked, and if a flag being set exists, the synchronization data is read from the segment corresponding to the synchronization information stored in the management memory, and the flag is reset. | 2009-04-02 |
20090089614 | DATA RESTORING METHOD AND AN APPARATUS USING JOURNAL DATA AND AN IDENTIFICATION INFORMATION - A host and a storage system each keep a shared identifier indicating a state of a system. The storage system acquires, at update of data, a data pair including data for a change through processing of the host and data before the update. The storage system relates the data pair to a shared identifier. When the host indicates an identifier, the storage system restores data using the data pair. | 2009-04-02 |
20090089615 | FIELD REPAIRABLE LOGIC - A state matcher for a logic circuit may detect at least one of a buggy state of the logic circuit, a precursor to a buggy state of the logic circuit and a verified state of the logic circuit based on a plurality of signal values indicative of a state of the logic circuit. A recovery controller for a microprocessor may reconfigure the microprocessor to a trusted feature mode in response to receiving a signal indicating that the microprocessor is in a predefined state and operate the microprocessor in the trusted feature mode for a predetermined period of time. | 2009-04-02 |
20090089616 | OFFLINE HARDWARE DIAGNOSTIC ENVIRONMENT - A computer configured to operate in diagnostic mode during which the operating system is suspended. During the diagnostic mode, tests can be performed on the computer system, including hardware, and the tests do not disrupt the operating system and are not disrupted by the operating system. When diagnostic mode is triggered, execution of the operating system is suspended. When the diagnostic tests are completed, the operating system may resume operation and test data may be made available within the operating system environment. Upon resuming, the state of the computer prior to entering diagnostic mode may be restored, preventing any changes made during diagnostic mode from interfering with operation of the operating system or application components. | 2009-04-02 |
20090089617 | METHOD AND APPARATUS FOR TESTING MATHEMATICAL ALGORITHMS - A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2 | 2009-04-02 |
20090089618 | System and Method for Providing Automatic Test Generation for Web Applications - In accordance with a particular embodiment of the present invention, a method is offered that includes generating an automatic test case generation using model checking for web applications, the automatic test case generation including: developing a specification; verifying a property using model checking on the specification; obtaining a counterexample, whereby the counterexample is mapped to a web test case; and executing the web test case on an implementation. In more specific embodiments, the method includes generating counterexamples by negating a desirable property and then model checking the specification, whereby the counterexamples represent a set of witnesses that are mapped to the web test case; and executing the web test case on the implementation. In still other specific embodiments, the generating step and the executing step are repeated on available properties and on their available counterexamples. The witnesses can be mapped to the web test case through selected framework technology. | 2009-04-02 |
20090089619 | AUTOMATIC DETECTION OF FUNCTIONAL DEFECTS AND PERFORMANCE BOTTLENECKS IN NETWORK DEVICES - A network device, such as a router or switch, has a CPU and a memory operable to receive, store and output computer code. The code includes device configuration files, traffic pattern files, and standard-behavior-output template files adapted for detecting network device functional defects and bottlenecks. The device is operable in a testing mode to act as either a Device Testing Doctor (DTD) or a Device Under Test (DUT), in which it loads into or accepts from a related, interconnected and similarly configured and operable network device selected ones of the device configurations, transmits to or receives from the other device selected ones of the input traffic patterns, compares its own output or that of the other device in response to the input traffic pattern with selected ones of the standard-behavior-output templates, and detects a network device defect or bottleneck in itself or in the other device based on the comparison. | 2009-04-02 |
20090089620 | Internet connectivity evaluation - Internet connectivity evaluation provides for easy, efficient and effective testing of the Internet connectivity behavior between an operating system hosted on a computing device and an IGD (Internet Gateway Device) interacting with the computing device. With a user's computing device communicating with one or more servers, or server-type devices, interacting with, or otherwise communicating with, the Internet, Internet connectivity evaluation can quickly and cost-effectively be performed to identify known major issues in the interaction between the operating system hosted on the user's computing device and an IGD. | 2009-04-02 |
20090089621 | Application crash resist method and apparatus - Embodiments of an application crash resist method and apparatus including an abnormal application termination service and an exception handler are disclosed herein. The service is configured to broadcast messages to cause the exception handler to be loaded by applications, and the exception handler is configured to stall abnormal termination of an application having loaded an instance of the exception handler. In various embodiments, the exception handler instances further report abnormal terminations to the service, and to receive instructions on how long to stall from the service. In various embodiments, the method and apparatus further includes a tray application through which the service obtains user inputs on how long to stall an abnormal termination from a user. | 2009-04-02 |
20090089622 | Providing Customizable, Process-Specific Just-In-Time Debugging in an Operating System - A method and a system for providing customizable, process-specific Just-In-Time debugging in operating system is provide in this invention. The method comprises the following steps: obtaining process-specific JIT debugging information, in response to the occurrence of an trap event in operating system; invoking the debugger corresponding to the process according to the obtained process-specific JIT debugging information. This method and system supports per-process JIT debugging configuration. | 2009-04-02 |
20090089623 | EVENT TIMING ANALYZER FOR A SYSTEM OF INSTRUMENTS AND METHOD OF ANALYZING EVENT TIMING IN A SYSTEM OF INTRUMENTS - An arrangement and method for analyzing the timing of events in a test system including a device under test and a plurality of test instruments connected together by one or more communication connections: time-stamps events in a test routine executed by the test instruments under control of a test program to generate time-stamped event data; communicates the time-stamped event data to a central processor; and processes the time-stamped data to output information about the timing of the events. | 2009-04-02 |
20090089624 | MECHANISM TO REPORT OPERATING SYSTEM EVENTS ON AN INTELLIGENT PLATFORM MANAGEMENT INTERFACE COMPLIANT SERVER - The exemplary embodiments provide a computer-implemented method, apparatus, and computer-usable program code for reporting operating system faults on an Intelligent Platform Management Interface compliant server. In response to receiving an alert for an operating system fault, the alert for the operating system fault is converted into an IPMI event. The IPMI event is stored in an internal event log. An IPMI system event record is created for the IPMI event. The IPMI event is sent to a host management controller in order to enable monitoring of the operating system fault. | 2009-04-02 |
20090089625 | Method and Apparatus for Multi-Domain Identity Interoperability and certification - A method and apparatus to provide identity management deployment interoperability and compliance verification. In one embodiment, the system also provides on-demand services including automated certification, monitoring, alerting, routing, and translation of tokens for federated identity related interactions between multi-domain identity management systems is provided. | 2009-04-02 |
20090089626 | Techniques for generating a trace stream for a data processing apparatus - Trace circuitry, and a method of operating such trace circuitry, are provided for generating a trace stream indicative of activities of monitored circuitry of a data processing apparatus. The monitored circuitry produces data elements indicative of those activities, and the trace circuitry comprises trace element generation circuitry which is responsive to at least some of the data elements produced by the monitored circuitry to generate trace elements representative of those data-elements, with the trace elements generated being dependent on a selected trace mode of operation of the trace circuitry. Compression circuitry is then arranged to apply an encoding operation to a sequence of trace elements in order to produce a packet whose bit pattern represents the sequence of trace elements, and to cause that packet to be output in the trace stream, the encoding operation applied being dependent on a current compression scheme associated with the compression circuitry. Whilst in the selected trace mode of operation, the compression circuitry is responsive to a compression change stimulus to change the current compression scheme from a first compression scheme to a second compression scheme whose bit pattern encoding space overlaps the bit pattern encoding space of the first compression scheme, such that following the change of compression scheme any further packets produced whilst in the selected trace mode of operation are produced in accordance with the second compression scheme. Such an approach has been found to provide improved compression efficiency thereby reducing the volume of trace data produced. | 2009-04-02 |
20090089627 | Distributed Control System - There is provided a distributed system having a plurality of nodes connected by a network. Each of the nodes includes: a common-parameter-value determining unit for determining a common-parameter-value from values of a parameter (each value being possessed by a corresponding one of the nodes); a common-operation execution unit for executing a common-operation using, as its input, a value of the parameter or the common-parameter-value; a send/receive unit for exchanging, via the network, the parameter values used for the determination of the common-parameter-value and the results of the common-operation execution with the other nodes; and a fault identification unit that compares the common-operation execution results collected from all the nodes and determines that an error occurs if not all the results are the same. | 2009-04-02 |
20090089628 | FILE SYSTEM ERROR DETECTION AND RECOVERY FRAMEWORK - Methods, systems and machine readable media for file system error detection and protection are described. In one aspect, an embodiment of a method includes collecting first data identifying at least one error in performing at least one of reading or writing data to a storage device and determining, through an association between the first data and file identifiers, a set of files which are effected by the at least one error. The collecting may be performed automatically as a background process. In another aspect, an embodiment of a method includes detecting at least one error in file system metadata for a storage device, the detecting being performed automatically as a background process, and storing state information automatically in response to the detecting; the state information indicates that upon next mounting of the storage device, the data processing system will automatically cause the running of a file system check of the file system metadata. | 2009-04-02 |
20090089629 | CAPTURING DIAGNOSTICS IN WEB BROWSER APPLICATIONS - The present invention extends to methods, systems, and computer program products for capturing diagnostics for Web browser applications. Embodiments of the present invention can capture errors in client-side code for a Web application and automatically report them a Web Service. Diagnostics code can be automatically injected into client code to capture client-side diagnostic information, including but not limited to errors in Web application code (script code, managed code, etc) that runs in a Web browser. The client-side diagnostic information can be automatically forwarded to a Web service under the control of the Web application. The Web application operator can use this information to improve the quality and hence customer satisfaction of their Web application. | 2009-04-02 |
20090089630 | METHOD AND SYSTEM FOR ANALYSIS OF A SYSTEM FOR MATCHING DATA RECORDS - Embodiments disclosed herein provide a system and method for analyzing an identity hub. Particularly, a user can connect to the identity hub, load an initial set of data records, create and/or edit an identity hub configuration locally, analyze and/or validate the configuration via a set of analysis tools, including an entity analysis tool, a data analysis tool, a bucket analysis tool, and a linkage analysis tool, and remotely deploy the validated configuration to an identity hub instance. In some embodiments, through a graphical user interface, these analysis tools enable the user to analyze and modify the configuration of the identity hub in real time while the identity hub is operating to ensure data quality and enhance system performance. | 2009-04-02 |
20090089631 | MEMORY DIAGNOSIS APPARATUS - A memory diagnosis apparatus include an intra-word testing unit that tests for a coupling fault in each bit in each word in a memory, an inter-word testing unit that tests for a coupling fault between words in each sub-array each being plural words in the memory, and an inter-block testing unit that tests for a coupling fault between sub-arrays in the memory. | 2009-04-02 |