14th week of 2009 patent applcation highlights part 54 |
Patent application number | Title | Published |
20090089432 | INFORMATION PROCESSING SYSTEM AND CONTROL METHOD THEREOF - According to one embodiment, a control method of an information processing system including a service receiving apparatus connected to a network and a plurality of service providing apparatuses which provide services to the service receiving apparatus via the network, includes causing each of the plurality of service providing apparatuses to transmit service information stored in a nonvolatile memory disposed at each service providing apparatus to the service receiving apparatus, causing the service receiving apparatus to detect service providing apparatuses which can provide predetermined services on the basis of the service information transmitted from the service providing apparatus, transmitting the start commands for starting the service providing apparatuses to the detected service providing apparatuses, and causing the service providing apparatuses having received the start commands to start. | 2009-04-02 |
20090089433 | Media-on-demand network, and a method of storing a media asset in a streaming node of the network - A method is provided of storing a media asset in a streaming node of a media-on-demand network. The network comprises a library node connected to a plurality of streaming nodes. The method comprises determining a popularity estimate for the asset at each of a plurality of the streaming node. The popularity estimates are aggregated to provide an aggregate popularity estimate for the asset over multiple streaming nodes. A determination is made whether the aggregate popularity estimate exceeds a predetermined threshold. Upon the threshold being exceeded, the asset is stored in one of the streaming nodes for use in addressing a request for the asset. | 2009-04-02 |
20090089434 | METHOD AND SYSTEM FOR SAVING AND RETRIEVING CLIENT-SPECIFIC INFORMATION IN AN INTERNET PROTOCOL MULTIMEDIA SUBSYSTEM - A method of saving and retrieving client-specific information in an Internet Protocol (IP) Multimedia Subsystem (IMS). A Serving Call Session Control Server (S-CSCF) receives information from a first client initiating a call to a second client. The information includes identification information corresponding to the first client and a Session Initiation Protocol (SIP) invite to the second client. If a profile of the first client in a Home Subscriber Server (HSS) includes a trigger value, the S-CSCF forwards the SIP invite to an Application Server (AS). If a local AS archive does not include valid profile information corresponding to the first client, the AS fetches valid profile information from the HSS, and the AS stores the profile information in the local archive. The AS sends the profile information corresponding to the first client from the local archive to the second client by embedding the profile information within the SIP invite. | 2009-04-02 |
20090089435 | Method for initiating IMS based communications - A method of initiating an IP Multimedia Sub-system communication for a user that is not registered a priori with the IP Multimedia Subsystem. The method comprises receiving a communication request from said user at a Session Initiation Protocol Application Server via an interface to an external network or receiving an internally or externally generated stimulus requiring the establishment of an IP Multimedia Subsystem communication, allocating a Serving Call/State Control Function to the user, forwarding a SIP request from the Application Server to the allocated Serving Call/State Control Function, and establishing the requested communication. | 2009-04-02 |
20090089436 | Policy information in multiple PDFs - The invention proposes a method for establishing sessions in a network comprising a user entity, a network control node and a plurality of network nodes storing subscriber specific information, the method comprising the steps of receiving a session establishing request at the network control node, forwarding a policy request message from the network control node to each network node of the plurality of network nodes storing subscriber specific information comprising policy information required for the session to be established, processing the policy request message to generate a policy decision message and sending the policy decision message to the network control node from each of the network nodes having received the policy request message, generating a single policy decision confirmation message based on the received policy decision messages in the network control node, and sending the single policy decision message to the user entity. | 2009-04-02 |
20090089437 | SYSTEMS AND MEDIA FOR SHARING SESSION DATA ON A NETWORK - Systems and media for sharing session data on a network are disclosed. More particularly, hardware and/or software for sharing user session data between different servers on a network are disclosed. Embodiments include a data processing system for sharing session data on a network, where the network includes an application server and an enterprise server, each providing at least part of an application to a user on the network. In some embodiments, the application server includes a session transport component for recording changes to user session data with the application server and the enterprise server includes a session transport component for requesting updated user session data from the application server. In further embodiments, the enterprise server may establish a user session based on the updated user session data received from the application server. | 2009-04-02 |
20090089438 | INTELLIGENT NETWORK ADDRESS LOOKUP SERVICE - An intelligent lookup service for a network is provided for clients of a network requesting services of the network that intelligently determines, based on a service requirement of the requested service, optimal service endpoint(s) for providing the requested service. The intelligent lookup service can incorporate predetermined mapping policy and traffic measurements into the determination. In addition, a feedback loop is provided from clients and/or service endpoints to the lookup service concerning measurements about prior connections in the network. The lookup service can include a set of beacons distributed in the network and against which measurements about the network are recorded. A client receives, from the lookup service in response to a request for a network address, a set of candidate service endpoints that pertain to the requested network address and the client connects to one of the candidate service endpoints based on policy or context. | 2009-04-02 |
20090089439 | COMMUNICATION BETWEEN A REAL WORLD ENVIRONMENT AND A VIRTUAL WORLD ENVIRONMENT - Gateway systems and methods are disclosed for allowing for communication between a real world environment and a virtual world environment. A gateway system in one embodiment is implemented between the virtual world environment and the real world environment. For a session being initiated from a real world user to a virtual world user, the gateway system receives a signaling message from the real world user to initiate the session with the virtual world user, and processes the signaling message to identify a virtual world identifier assigned to the virtual world user. The gateway system converts the signaling message to a communication request message in a protocol used in the virtual world environment, and transmits the communication request message to the virtual world user to establish the session. When the session is established, the virtual world user and the real world user may communicate via voice and/or data. | 2009-04-02 |
20090089440 | PROTOCOL FOR LEASING SOCKETS - A system for establishing a communication session in a networked deployment includes a negotiation between a client application and a service regarding the duration of the communication session. A client application sends a packet or datagram having a load and a request for a communication link. The request for a communication link includes a first proposed interval for a lease term between the client application and the service. The service may accept the first proposed interval and begin processing the load. Alternatively, the service may deny the request or counter-propose a second proposed interval for the communication link. Substantially concurrently with sending the second proposed interval, the service may begin processing the load. | 2009-04-02 |
20090089441 | SYSTEMS & METHODS FOR PROXY RESOLUTION OF DOMAIN NAME SERVICE (DNS) REQUESTS - Systems and methods are provided for resolving domain name services (DNS) queries for address information about hosts on a network. The queries are posited from remote users across a satellite or other remote link to a network. In response to a domain name services request from the client containing a name of the server, a placeholder address is generated and provided in response to the client. After a subsequent request for a connection to the server is received, the name of the server is re-associated with the placeholder address and the connection request containing the proper host name is forwarded across the data link. A hub processor receives the request for connection, resolves the name of the server to an address on the network, and establishes a connection between the client and the server using the address on the network. | 2009-04-02 |
20090089442 | Method of transmitting data in a communication system - A method of transmitting data from a first terminal to a second terminal in a communication network comprising: receiving at the first terminal an data signal determining an identity of the peripheral device; supplying to a data store the identity of the peripheral device; selecting from the data store at least one parameter for processing the data signal based on the identity of the peripheral device; transmitting the data signal from the first terminal to the second terminal; and processing the data signal, wherein the data signal is processed based on the selected parameter. | 2009-04-02 |
20090089443 | MANAGEMENT SYSTEM, MANAGEMENT METHOD AND MANAGEMENT PROGRAM - A management system including a management apparatus and a managed apparatus connected with each other by a communications network, the system having a registration controller, wherein in an initial registration phase where the managed apparatus sends a registration request notice to the management apparatus, and the management apparatus returns a registration permission notice to the managed apparatus; in cases where a first communications method is utilized that enables immediate mutual communication, the registration controller determines that a final registration has completed when the managed apparatus has received the registration permission notice; and in cases where a second communications method via a server is utilized, the registration controller determines that a temporary registration has completed when connection between the managed apparatus and the server has been established, and when the managed apparatus has acquired the registration permission notice, the registration controller determines that the final registration has completed. | 2009-04-02 |
20090089444 | METHOD, DEVICE AND SYSTEM FOR CONNECTING TO URL RESOURCE - A method, device, and system for connecting to a URL resource is disclosed. The method includes: receiving a connection request carrying a URL number from a User Equipment; resolving the URL number to obtain a corresponding URL and returning the corresponding URL to the User Equipment; and connecting, by the User Equipment, to a corresponding URL resource, upon receiving the URL. The invention enables an existing User Equipment with a poor input capability to connect to a URL resource, and improves the efficiency of the User Equipment to access the URL resource. | 2009-04-02 |
20090089445 | Client-Controlled Adaptive Streaming - A client determines the transmission of a data stream from a server and transmits to the server a Real-Time Streaming Protocol (RTSP) header having either RTSP Speed or both RTSP Scale and RTSP Speed values where the values are formed based at least on the determined transmission rate of the data stream received by the client and a reference data stream rate. An RTSP server responsive to the Speed value or the Speed and Scale value may adjust properties of the data stream being transmitted in response to the RTSP header values sent by the client. | 2009-04-02 |
20090089446 | METHODS AND APPARATUS FOR ADAPTING COMPRESSION TECHNIQUES OVER DATA BASED ON EXTERNAL CONTEXT - Techniques for selecting a new compression technique or altering the currently instantiated compression technique employed over a data stream in data collection system are provided. At least one change to at least one external contextual condition is detected. One or more modifications to a defined compression technique is generated, either independently or in conjunction with one or more modifications to the event processing operators that operate on the data stream and whose output provides the values that are compressed by the defined compression technique, in response to the at least one change to the at least one external contextual condition. The defined compression technique of the at least one client device is altered in accordance with the one or more modifications to form a modified compression technique through which the unmodified or processed data stream will be compressed before being sent to the server. | 2009-04-02 |
20090089447 | Proxy-driven content rate selection for streaming media servers - Methods for proxy-driven content rate selection for streaming media servers are provided. In one method, one or more maximum transmission rate parameters from a network controller are stored at a proxy server in response to a receiver report message from the client. A target rate for the media session is generated based on the stored maximum transmission rate parameters, and the target rate is transmitted to a media server in a proxy-to-server feedback message. The media server selects the content rate from among a plurality of supported content rates in response to the proxy-to-server feedback message from the proxy server, and streams streaming multimedia frames to the client at the selected content rate. | 2009-04-02 |
20090089448 | MOBILE BROWSER WITH ZOOM OPERATIONS USING PROGRESSIVE IMAGE DOWNLOAD - A method and mobile device for providing fast rendering of a web page and zoom capability using progressive image download. A data server requests the web page and converts images within the webpage into a progressive format before forwarding the web page data to the mobile device. The initial fully zoomed-out view of the web page is rendered using initial low resolution image data first received at the device. As additional progressive resolution data is received, the device is capable of zooming in to portions of the web page using the higher resolution data. If interpolations are used in rendering an image at a particular zoom level, then the image is repainted in higher resolution as additional progressive resolution data is received. | 2009-04-02 |
20090089449 | Mutiplexing and congestion control - Methods, systems and devices for network congestion control exploit the inherent burstiness of network traffic, using a wave-based characterization of network traffic and corresponding multiplexing methods and approaches. | 2009-04-02 |
20090089450 | System and method providing secure access to a computer system - A system and method for providing secure access to a computer system. An access device divides the password into multiple segments and places them in data packets. In one embodiment, an authentication server has multiple addresses, and each packet is sent to a different address. The server then reassembles the password. In another embodiment, when the server receives a password, the server sends an index value back to the access device, which then accesses the server on another address indicated by the index value. Alternatively, the password is sent to multiple addresses for the server, and the server determines whether any of the received packets have been altered. The multiple password packets may be forced to follow different paths to the server, thereby denying hackers the ability to intercept all of the password characters or determine the inter-packet timing factor. The system is effective against passive and active hackers, Trojans, and phishing techniques. | 2009-04-02 |
20090089451 | System and Apparatus for Pre-Routing Network Events - A pre-routing software system for treating incoming network events according to event importance prior to agent-level routing in a communication center network is disclosed. The system includes at least one network interface for receiving incoming events, a parsing engine for parsing electronic messages and documents, at least one communication interface for enabling communication with connected routing, queuing, and automated response systems, and a determination module for determining pre-treatment of received events. In preferred application, incoming network events are parsed according to a rules set and determination of pre-treatment is made for each event according to the rules set. In some embodiments, the system is used in conjunction with one or more virtual, priority-based queuing systems. | 2009-04-02 |
20090089452 | SYSTEM AND METHOD FOR MANAGING DEVICES CONNECTED TO A COMPUTER NETWORK - According an aspect of the embodiment, there is provided a method for managing management target devices each connected to a computer network and managed by one of a plurality of management servers. A management server list storing IP addresses of the plurality of management servers is provided. A hop count defined as the number of hops, in the computer network, from the management target device to the each of the plurality of management servers is obtained and a management server having the smallest hop count among the plurality of management servers is selected as an optimum management server. Then, the management target device is managed under the control of the selected optimum management server. | 2009-04-02 |
20090089453 | REMOTE VISUALIZATION OF A GRAPHICS APPLICATION - Many embodiments provide a technique to allow the automatic conversion between the operating system specific interfaces of OpenGL based graphics applications. Embodiments comprise logic such as hardware and/or code related to the display of a graphics application using OpenGL functions executing on a local computer system and displayed on the screen or screens of one or more remote computer systems. The described embodiments may work regardless of the types of OS running on the local computer system and the remote computer system(s). In some embodiments, the OS-specific interface calls to OpenGL, in addition to the platform independent OpenGL calls, are translated into an OS-independent wire protocol. As a result, many embodiments provide automatic conversion between the OpenGL OS-specific interfaces at the local and remote computer systems. | 2009-04-02 |
20090089454 | Network packet payload compression - Methods and apparatus relating to network packet payload compression/decompression are described. In an embodiment, an uncompressed packet payload may be compressed before being transferred between various components of a computing system. For example, a packet payload may be compressed prior to transfer between network interface cards or controllers (NICs) and storage devices (e.g., including a main system memory and/or cache(s)), as well as between processors (or processor cores) and storage devices (e.g., including main system memory and/or caches). Other embodiments are also disclosed. | 2009-04-02 |
20090089455 | Image Forming Apparatus and Computer Readable Medium - Disclosed is an image forming apparatus including a communication section connected to a data processing apparatus through a communication line, the apparatus including: a plurality of storage sections each of which has a different free storage capacity and a different access speed; and a control section to obtain data size information of a data-decompressed XPS file from the XPS file which includes the data size information in a head of a file data frame, the XPS file being received from the data processing apparatus through the communication section, to select a storage section to store the file data of the data-decompressed XPS file from the plurality of storage sections on the basis of the data size information, to perform data decompression of the XPS file, and to allow the selected storage section to store the file data of the data-decompressed XPS file. | 2009-04-02 |
20090089456 | SYSTEM AND METHOD FOR SYNCHRONIZING SIMULTANEOUS MEDIA STREAM PLAYBACK ACROSS NONSYNCHRONIZED NETWORK TIMING/CLOCK ISLANDS - A system and method for synchronizing simultaneous media stream playback across disjoint network timing/clock islands. An embodiment of a method includes determining a closest device to a source device in a network communications path between the source device and one or more target devices. Here, clocks of the closest device and the one or more target devices are synchronized and a clock of the source device is not necessarily synchronized with the clocks of the closest device and the one or more target devices. A current time for the closest device is then determined. A start time is assigned to at least the current time plus a maximum latency across the network communications path. A data stream and the start time are sent to the one or more target devices for rendering. Other embodiments are described and claimed. | 2009-04-02 |
20090089457 | RECONNECTING A HOST COMPUTER WITH A NETWORKED PRINTER HAVING A DYNAMIC NETWORK ADDRESS - Methods and apparatus for reconnecting a host computer with a networked printer having a dynamic network address without manually entering the printer's network address. In a first method, when a user presses a reconnect button on the printer, the printer broadcasts a reconnection event containing the printer's network address over the network. The host receives the event, extracts the network address and reconnects the printer accordingly. In a second method, the host obtains the network addresses of candidate printers, displays a list of them on a UI, and sends a flash signal to the candidate printers to cause them to generate an alarm one by one. The user observes the desired printer and correlates its alarm with the timing of the flash signals sent by the host. Based on the observation, the user selects one of the candidate printers on the UI and the host reconnects it. | 2009-04-02 |
20090089458 | STORAGE APPARATUS, PROCESS CONTROLLER, AND STORAGE SYSTEM - A storage apparatus comprises: a memory for storing a processing ratio/upper limit table, which stores an upper limit number per prescribed time for input/output processing in accordance with the processing of a processing type for each of a plurality of processing types executed by a host computer; and a processor which receives an input/output request from the host computer, and executes input/output processing corresponding to the input/output request, such that input/output processing corresponding to the processing of each processing type per prescribed time falls within the upper limit number. According to this constitution, the input/output processing count per prescribed time can be properly controlled in accordance with the processing type. | 2009-04-02 |
20090089459 | Schedule and data caching for wireless tranmission - A method and apparatus for schedule and data caching for wireless transmissions. An embodiment of a method may include generating a schedule of queues for a wireless controller, the schedule being generated at a driver on a host system. In some embodiments schedule data may be cached at the wireless controller from the host system, where the cache may include active queues and page list entries for the active queues. The wireless controller may be operated using the cached queues. | 2009-04-02 |
20090089460 | STORAGE DEVICE AND STORAGE DEVICE ACCESS CONTROL METHOD - A storage device is removably connectable to a host computer. The storage device includes: a storage unit on which one or more storage areas are allocatable to a plurality of users; and a control unit. The control unit is operable to, when the storage deice receives authentication success information indicating that authentication for one of the users is succeeded from the host computer or other external device, simulatively mount the storage area allocated to the authenticated user and unmount the storage area allocated to another user. | 2009-04-02 |
20090089461 | Image input/output switching method for a notebook computer and related notebook computer - A notebook computer includes a display module, a processing unit, an image input/output module and a detecting unit. The processing unit is electrically connected to the display module. The image input/output module is electrically connected to the processing unit and includes an image switch and at least one image connector. The detecting unit is electrically connected to the display module and the image input/output module. The detecting unit is capable of detecting whether a signal transmitted via the image input/output module is an input or output signal, and notifies the display module and the image input/output module accordingly to switch to the input/output image. | 2009-04-02 |
20090089462 | OPTIMISATION OF THE SELECTION OF STORAGE DEVICE PORTS - A port optimisation component and method for selecting a pair of ports, each port having predetermined operating parameters, for connecting to a storage device in a storage area network, the port optimisation component comprising: a determination component for requesting configuration data and policy data pertaining to a storage device in response to a request to configure access to the storage device; and the determination component for comparing the configuration data to the policy data to determine a difference in operating parameters for each storage device port located on the storage device and in dependence on the detected difference, selecting a pair of ports having a preferred operating parameter. | 2009-04-02 |
20090089463 | Information Processing Device, Device Access Control Method, and Device Access Control Program - An information processing device, a device access control method, and a device access control program are provided. When a device built in or mounted on the information processing device is controlled, the OS manages access to the device driver, so as to restrict the use of the device. When issuing a control instruction to a device driver ( | 2009-04-02 |
20090089464 | MODULAR I/O VIRTUALIZATION FOR BLADE SERVERS - An apparatus includes a server comprising n operating system images and an IOV aware root complex; a plurality of physical I/O devices comprising n virtual I/O functions; and a PCI Express bus operatively connected to the server and the plurality physical I/O devices via the root complex, wherein the root complex is operable to provide communication between the n operating system images and the n virtual I/O function, and wherein the server and the plurality of physical I/O devices are modules in a chassis. | 2009-04-02 |
20090089465 | Plug and Play Display Device Over Ultra Wideband Link - A method for conveying display device data over an ultra wideband wireless link that provides an information handling system with an information handling system ultra wideband communication link. The method also provides a display device with a display device ultra wideband communication link and transmits display data between the information handling system ultra wideband communication link and the display device ultra wideband communication link. | 2009-04-02 |
20090089466 | PROXIMITY COMMUNICATION PACKAGE FOR PROCESSOR, CACHE AND MEMORY - A “sombrero” bridge transports signal communication between a processor and one or more cache memories. The bridge surrounds the processor's perimeter, and includes an aperture opposite the processor through which power and data can be provided to the processor from another device. The bridge exchanges signals with the cache memories via capacitively coupled proximity connections. The bridge communicates with the processor via conductive (e.g. wire) connections and optionally proximity connections. Spacing between opposing pads of the proximity connection(s) between the bridge and the cache memories can be provided by recesses in a surface of the cache memory, corresponding recesses in an opposing surface of the bridge, and a ball for each matching pair of corresponding cache memory and bridge recesses. The ball fits in and between the recesses of the matching pair. The recess depths and ball diameter(s) constrain a minimum distance between opposing pads of the proximity connection(s). | 2009-04-02 |
20090089467 | BUS COMMUNICATION EMULATION - Provided are a method, system, and program for initializing a processor of a computer system, to enumerate a remote bus and remote devices coupled to the remote bus, as operating components of the computer system. In another embodiment, a controller stores a message containing a directive in a memory shared by a processor of a computer system and the controller which may be operated independently of the state of said processor and said operating system. The processor may read a message stored in the shared memory by the controller and process the message. In addition, the processor may store a message intended for the controller to provide, for example, status information to be forwarded to another computer system. Other embodiments are described and claimed. | 2009-04-02 |
20090089468 | COHERENT INPUT OUTPUT DEVICE - According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described. | 2009-04-02 |
20090089469 | Parallel burunig system and method - A parallel burning system and method is for burning chips of various different bus types in parallel. A computer compiles configuration information according to corresponding connection relations between the chips and the micro controller units, and transmits the configuration information, burning command and burning data to a master micro controller unit of the micro controller units. The master micro controller unit distributes the burning data to slave micro controller units of the micro controller units based on the analyzed configuration information, and controls each slave micro controller unit to activate its burning operation. Then, the slave micro controller units burn the burning data onto the chips connected thereto, and transmit the burning results back to the master micro controller unit after completion of the burning operations. Finally, the master micro controller unit transmits the burning results back to the computer after completion of all the burning operations. | 2009-04-02 |
20090089470 | INTERRUPT BALANCING FOR MULTI-CORE AND POWER - A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of interrupt handling is selected. During the performance mode, interrupts and/or interrupt sources are distributed among multiple physical sockets, i.e. multiple physical processors. However, if the interrupt activity is below a threshold for a number of periods, which denotes low interrupt activity, then a power save mode is selected. Here, interrupts and/or sources are primarily assigned to a single processor to allow other physical processors to save power. Furthermore, after interrupts are assigned to a physical processor, the interrupts may be further distributed among cache domains of the processor. In addition, high activity classes, interrupt sources, interrupts, or categories may be further assigned to specific processing elements for servicing. | 2009-04-02 |
20090089471 | Process Suspension Through Process Model Design - Various implementations are disclosed for designing a process model that includes a task, the task associated with a potential suspension, e.g., in response to an error or other exception. At least one suspension task may be provided in parallel with the task to form a parallel combination thereof within the process model. A first control task, e.g., an AND split task, may be provided prior to the parallel combination, and a second control task, e.g., a synchronize/merge task, may be provided subsequent to the parallel combination, the first control task and the second control task configured to activate and join, respectively, the task and the at least one suspension task during execution of the process model. | 2009-04-02 |
20090089472 | Program memory test access collar - A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations. | 2009-04-02 |
20090089473 | Data transmission system and method thereof - The invention uses a SGPIO bus as an optional route for the communication between the two SAS expanders to guarantee high communication performance. Furthermore, two GPIO buses are used respectively as receiver and transmitter of the SGPIO so as to achieve synchronous data transmission between two SAS expanders. | 2009-04-02 |
20090089474 | MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORY - An exemplary motherboard for supporting different types of memory includes a driving module, a first slot, a second slot, and a transmission line connected the driving module, the first slot and the second slot in turn. The first slot is arranged for mounting a first type of memory. The second slot is arranged for mounting a second type of memory. The first memory and the second memory are alternatively mounted on the motherboard. The transmission line is grounded via a capacitor for eliminating echo signals generated by the first and second type memories. The motherboard for supporting different memory modes satisfies different type memories, and maintains integrality of signals transmitted therein. | 2009-04-02 |
20090089475 | Low latency interface between device driver and network interface card - Methods and apparatus relating to a low latency interface between a device driver and a network interface device are described. In one embodiment, a network interface card (NIC) and a processor may be coupled through a coherent interconnection, e.g., to allow for coherent communication of data between buffers in the NIC and the processor. Other embodiments are also disclosed. | 2009-04-02 |
20090089476 | WIRELESS UNIVERSAL SERIAL BUS SYSTEM AND DRIVING METHOD THEREOF - A wireless universal serial bus system (WUSB) includes a device, a first host, and a second host. The first host communicates with the device through a first superframe according to a wireless USB protocol. The first host sets a host-adding bit in the first superframe when the second host transfers a second superframe to the first host according to the wireless USB protocol to enable communication between the second host and the device. | 2009-04-02 |
20090089477 | DEADLOCK AVOIDANCE IN A BUS FABRIC - Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock. | 2009-04-02 |
20090089478 | Crossbar channel router having a distributed arbitration scheme - A router is provided that includes a plurality of lanes to receive inbound data from a plurality of different input ports. The router may further include a shared crossbar channel coupled to each of the lanes and to a plurality of output ports, the crossbar channel to receive inbound data from the plurality of lanes and to provide outbound data to the plurality of output ports. Each lane may include a local lane arbiter, a global lane arbiter and a port arbiter associated with each port. | 2009-04-02 |
20090089479 | Method of managing memory, and method and apparatus for decoding multi-channel data - A memory management method is provided. In the method, a spatial parameter included in an encoding result is represented as a vector of a time slot and a frequency band in a first domain, a temporary matrix is calculated in the first domain by using the difference between vectors of a current time slot and a previous time slot at the same frequency band and then is stored in a memory, and then a matrix needed to decode the encoding result is represented as a matrix for a time slot and a frequency band in a second domain by using the temporary matrix, thereby reducing the load on the memory for storing matrices on which a decoding operation is performed. | 2009-04-02 |
20090089480 | SUPPORTING UN-BUFFERED MEMORY MODULES ON A PLATFORM CONFIGURED FOR REGISTERED MEMORY MODULES - A RDIMM enabled memory controller may support a UDIMM by way of a register chip and a PLL chip being implemented in operational relationship with a memory slot and a memory controller configured to support a RDIMM. The memory controller may drive address and control signals from the memory controller to the register chip, and the address and control signals may be provided from the register chip to the memory slot after one clock cycle, in response to the register chip latching onto the address and control signals from the memory controller on a rising clock edge. | 2009-04-02 |
20090089481 | Leveraging Portable System Power to Enhance Memory Management and Enable Application Level Features - A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window. Additionally, in a data write operations, where the memory device receives data from a host, stores the data in volatile memory, and then writes the data into the non-volatile memory, the memory device sends the host an acknowledgment of the data having been written into the non-volatile memory after it has been store in the volatile memory, but before the write into the non-volatile memory is complete. | 2009-04-02 |
20090089482 | DYNAMIC METABLOCKS - A nonvolatile block erasable memory array links erase blocks together for programming with high parallelism as a metablock. Erase blocks are operated in banks, with each bank having a dedicated bus and controller. Sub-metablocks of different metablocks, in different banks, are accessed in parallel allowing different metablocks to be updated at the same time. | 2009-04-02 |
20090089483 | Storage device and deduplication method - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area. | 2009-04-02 |
20090089484 | DATA PROTECTION METHOD FOR POWER FAILURE AND CONTROLLER USING THE SAME - A data protection method suitable for a plurality of physical blocks mapped to a logical block in a non-volatile memory is provided. The data protection method includes recording data update information in each of the physical blocks for identifying an update relationship of the physical blocks and re-establishing the update relationship of the physical blocks according to the data update information. The data update information is composed of a plurality of words having a circular relationship, and the number of these words is greater than the number of the physical blocks. The data update information is sequentially recorded in each of the physical blocks according to the update relationship and the circular relationship. | 2009-04-02 |
20090089485 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for a non-volatile memory is provided. The non-volatile memory is substantially divided into a plurality of blocks, and these blocks are grouped into at least a data area, a spare area, a substitute area, and a temporary area. The wear leveling method includes selecting blocks from the spare area according to different purposes and executing a wear leveling procedure. | 2009-04-02 |
20090089486 | PORTABLE DATA STORAGE DEVICE INCORPORATING MULTIPLE FLASH MEMORY UNITS - A portable data storage device is disclosed which includes an Interface for enabling the portable data storage device to be used for data transfer with a host Computer, and an Interface controller for controlling the interface. There is also a master control unit for controlling the writing of data to and reading data from a non-volatile memory. The non-volatile memory includes at least one single layer cell flash memory and at least one multiple layer cell flash memory. Upon receiving a write instruction, the master control unit determines which of the memories data contained in the instruction should be written to, and writes the data as appropriate similarly, upon receiving a read instruction, the master control unit reads the data from the appropriate one of the memories and transmits the data out of the device. | 2009-04-02 |
20090089487 | MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME - A multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a specification related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array. | 2009-04-02 |
20090089488 | MEMORY SYSTEM, MEMORY READ METHOD AND PROGRAM - According to one embodiment, there is disclosed a memory system comprising a flash memory unit which suspends a write operation to execute a read operation when receiving a suspend command during a write operation, a CPU, an OS which includes a device driver, a TLB which has a page table for conversion from a virtual address to a physical address, and an application program which makes a TLB setting request with respect to the device driver when receiving a read command under the control of the CPU and the OS, acquires address information read from the page table of the TLB by the device driver in response to the setting request, and executes read directly with respect to the flash memory unit using the acquired address information without using the device driver. | 2009-04-02 |
20090089489 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND CONTROL METHOD OF FLASH MEMORY - The memory controller updates a count number based on a new assignment of a logical block to a physical block, and writes count information in the physical block to which the logical block is newly assigned. The count information is defined by the count number. The memory controller decides, based on the count number and the count information stored in each physical block, whether or not to transfer stored data in a physical block to another physical block. | 2009-04-02 |
20090089490 | MEMORY SYSTEM - A memory system including a nonvolatile memory, a first controller connected to a host equipment, the first controller controlling the entire memory system, a second controller connected to the first controller and also connected to the nonvolatile memory, the second controller controlling an access process to said nonvolatile memory, the second controller receives a command via the first controller and carries out the access process to the nonvolatile memory according to the command, the command being input from the host equipment. | 2009-04-02 |
20090089491 | SEMICONDUCTOR MEMORY DEVICE AND DATA MANAGEMENT METHOD USING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory part which has a plurality of memory blocks having a memory cell capable of storing a plurality of different kinds of data which require a memory area having different characteristics, and a memory controller which has a function of treating each of the memory blocks as a deletion unit in order to manage the memory part and converting a logic address of the memory part to a physical address identifying the memory block, and which replaces the memory block with a preregistered free block in rewriting the memory block. The memory controller manages the different kinds of data to be stored in the memory part so as to store the same kind of data as before, even after each of the memories and free blocks in the memory part are rewritten. | 2009-04-02 |
20090089492 | FLASH MEMORY CONTROLLER - Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device. | 2009-04-02 |
20090089493 | SEMICONDUCTOR MEMORY, OPERATING METHOD OF SEMICONDUCTOR MEMORY, AND SYSTEM - Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the second operation in response to a termination command to terminate operations of the plurality of memory cores. For example, the semiconductor memory is mounted on a system together with a controller accessing the semiconductor memory. The termination of the operation in response to the termination command is judged in accordance with an operation state of the memory core. Accordingly, it is possible to terminate the operation of the memory core requiring the termination of operation without specifying the memory core from outside. | 2009-04-02 |
20090089494 | Memory control apparatus, memory control method, and computer program - Disclosed herein is a memory control apparatus including a plurality of memory control sections, each of which has connected thereto one or more memories that require periodic refresh and is configured to perform data write, data read, and refresh operations on the one or more memories. The memory control sections issue, to each of the one or more memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other. | 2009-04-02 |
20090089495 | NON-BLOCKING VARIABLE SIZE RECYCLABLE BUFFER MANAGEMENT - Buffer management system. A ring buffer may be implemented. The ring buffer includes a number of zones. Each of the zones includes state fields. The state fields include a filled indicator indicating whether the zone is full. The state fields for the zone further include a committed indicator indicating whether data in the zone is readable. The state fields for the zone also include a recycling indicator indicating whether the zone can be recycled. The ring buffer includes entries in the zones. Each of the entries includes state information. The entry state information includes a zone offset indication indicating a memory offset into the zone. The entry state information further includes a size indicating the size of the entry. The entry state information also includes a committed indicator indicating that the entry is readable | 2009-04-02 |
20090089496 | Dual-interface data storage apparatus - The present invention discloses a dual interface data storage apparatus, including: a memory module, a first interface and a second interface connected with the memory module, a housing, and a movable carriage for carrying the memory module, the first interface, and the second interface. The housing accommodates the memory module, the first interface and the second interface, and has a first opening at one end and a second opening at the other end for either allowing the first interface or the second interface to pass through the first opening or the second opening. | 2009-04-02 |
20090089497 | METHOD OF DETECTING PRE-OPERATING SYSTEM MALICIOUS SOFTWARE AND FIRMWARE USING CHIPSET GENERAL PURPOSE DIRECT MEMORY ACCESS HARDWARE CAPABILITIES - In some embodiments, a method of detecting pre-operating system malicious software and firmware using chipset general purpose direct memory access hardware capabilities is presented. In this regard, a security agent is introduced to access system memory used by instructions executing on a host processor or microcontroller, to copy contents from the system memory to an internal chipset memory, and to scan the internal memory with an embedded processor for a malicious software pattern. Other embodiments are also disclosed and claimed. | 2009-04-02 |
20090089498 | Transparently migrating ongoing I/O to virtualized storage - A method, medium and apparatus for transparently virtualizing storage in an operating computer system. The method includes a computer's recognizing a storage device connected to the computer through a physical connection, a storage virtualizing device's virtualizing the storage device, the computer's relating the storage device and the virtualized storage device and, finally, the computer's failing over to the virtualized storage device on the computer. While virtualizing, the storage virtualizing device, the physical connection and the first recognition maybe maintained through the step of virtualizing. While virtualizing, the method may recognize the storage device through a physical connection, virtualize the storage device and expose the virtualized storage device. In an further form of the method, from the time of recognition through the time of failing over, no I/O is interrupted by the method. | 2009-04-02 |
20090089499 | METHOD OF MANAGING STORAGE CAPACITY IN A STORAGE SYSTEM, A STORAGE DEVICE AND A COMPUTER SYSTEM - A capacity management method of managing a capacity of a storage unit of each storage in a computer system having a plurality of storage devices each having one or more storage units each providing one or more storage areas. The method includes the steps of: detecting a storage area relation between a first storage area and a second storage area; and calculating an estimated capacity necessary for the storage unit in accordance with a detection result. | 2009-04-02 |
20090089500 | MEMORY CACHE SHARING IN HYBRID HARD DISK - A system allows one or more hybrid hard disks or any other storage devices to share a logical nonvolatile device formed by one or more non-volatile memory devices. The system comprises a control logic to reserve on a hybrid hard disk a space that corresponds to a non-volatile memory device in the hybrid hard disk and to use a space access instruction to access the non-volatile memory device. The control logic accesses the logical non-volatile memory device in an event that a content of a storage device is stored in the logical non-volatile memory device in response to an instruction to access the storage device. | 2009-04-02 |
20090089501 | METHOD OF PREFETCHING DATA IN HARD DISK DRIVE, RECORDING MEDIUM INCLUDING PROGRAM TO EXECUTE THE METHOD, AND APPARATUS TO PERFORM THE METHOD - A method of prefetching data in a hard disk drive includes searching for a logic block address (LBA) of data requested by an external apparatus in a history of a non-volatile cache of the hard disk drive, and if the LBA of the data is stored in the history, storing data recorded in a LBA stored after the LBA of the data requested by the external apparatus from among LBAs stored in the history in a buffer of the hard disk drive. | 2009-04-02 |
20090089502 | Rotating parity redundant array of independant disk and method for storing parity the same - A rotating parity redundant array of independent disk (RAID) and a method for storing parity of the same are provided. The rotating parity RAID comprises a first˜a third disk. The first disk has A | 2009-04-02 |
20090089503 | DISK ARRAY APPARATUS, COMPUTER-READABLE RECORDING MEDIUM HAVING DISK ARRAY APPARATUS CONTROL PROGRAM RECORDED THEREON, AND DISK ARRAY APPARATUS CONTROL METHOD - A disk array apparatus has a plurality of disks constituting a mounted RAID group and controls access from an upper-level device to each of the disks. The disk array apparatus also has a performance information collector for collecting a piece of performance-related information of each of the disks, and a suspected disk detector for comparing the pieces of information collected for the disks by the performance information collector among disks constituting a single one of the RAID group and detecting a suspected disk suspected of being abnormal in performance based on a result of the comparison. | 2009-04-02 |
20090089504 | Virtual Disk Drive System and Method - A disk drive system and method capable of dynamically allocating data is provided. The disk drive system may include a RAID subsystem having a pool of storage, for example a page pool of storage that maintains a free list of RAIDs, or a matrix of disk storage blocks that maintain a null list of RAIDs, and a disk manager having at least one disk storage system controller. The RAID subsystem and disk manager dynamically allocate data across the pool of storage and a plurality of disk drives based on RAID-to-disk mapping. The RAID subsystem and disk manager determine whether additional disk drives are required, and a notification is sent if the additional disk drives are required. Dynamic data allocation and data progression allow a user to acquire a disk drive later in time when it is needed. Dynamic data allocation also allows efficient data storage of snapshots/point-in-time copies of virtual volume pool of storage, instant data replay and data instant fusion for data backup, recovery etc., remote data storage, and data progression, etc. | 2009-04-02 |
20090089505 | STEERING DATA UNITS TO A CONSUMER - A computer system may comprise a second device operating as a producer that may steer data units to a first device operating as a consumer. A processing core of the first device may wake-up the second device after generating a first data unit. The second device may generate steering values after retrieving a first data unit directly from the cache of the first device. The second device may populate a flow table with a plurality of entries using the steering values. The second device may receive a packet over a network and store the packet directly into the cache of the first device using a first steering value. The second device may direct an interrupt signal to the processing core of the first device using a second steering value. | 2009-04-02 |
20090089506 | STRUCTURE FOR CACHE FUNCTION OVERLOADING - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a system that includes a cache that stores information in a cache line for processing, wherein the cache line includes at least a first field configured to store an instruction or data and at least a second field configured to store parity information, a parity register that include a parameter indicative a whether parity generation and checking is disabled for the information in the cache line, and a processor that sets the second field in the cache line to include a value, which indicates a corresponding action to be performed, when the parameter in the parity register indicates that parity generation and checking is disabled for the cache line. | 2009-04-02 |
20090089507 | OVERLAY INSTRUCTION ACCESSING UNIT AND OVERLAY INSTRUCTION ACCESSING METHOD - The present invention provides an overlay instruction accessing unit and method, and a method and apparatus for compressing and storing a program. The overlay instruction accessing unit is used to execute a program stored in a memory in the form of a plurality of compressed program segments, and compresses: a buffer; a processing unit for issuing an instruction reading request, reading an instruction from the buffer, and executing the instruction; and a decompressing unit for reading a requested compressed instruction segment from the memory in response to the instruction reading request of the processing unit, decompressing the compressed instruction segment, and storing the decompressed instruction segment in the buffer, wherein while the processing unit is executing the instruction segment, the decompressing unit reads, according to a storage address of a compressed program segment to be invoked in a header corresponding to the instruction segment, a corresponding compressed instruction segment from the memory, decompresses the compressed instruction segment, and stores the decompressed instruction segment in the buffer for later use by the processing unit. | 2009-04-02 |
20090089508 | METHOD FOR REDUCING NUMBER OF WRITES IN A CACHE MEMORY - Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a set of data of the plurality of the data in the cache memory to be flushed to a hard disk, wherein the hard disk is operatively coupled to the cache memory; flushing the set of data of the plurality of data to the hard disk from the cache memory; and writing a clean-marker to the cache memory specifying which of the plurality of the data has been flushed to the disk. | 2009-04-02 |
20090089509 | CACHE LINE REPLACEMENT MONITORING AND PROFILING - Systems and methods for cache replacement monitoring (CRM) are provided. The system includes a monitored cache comprising a monitored cache line set, the monitored cache line set comprising at least one cache line capable of holding data of a monitored address; and a CRM mechanism operatively associated with the monitored cache. The CRM mechanism collects CRM information for the monitored address. The method includes the steps of collecting CRM information for a monitored address in a monitored cache; and recording the CRM information for the monitored address, when at least one of (1) the monitored address is cached in the monitored cache, (2) the monitored address is replaced in the monitored cache, (3) any cache line in a cache line set corresponding to the monitored address is cached in the monitored cache, and (4) any cache line in a cache line set corresponding to the monitored address is replaced in the monitored cache. | 2009-04-02 |
20090089510 | SPECULATIVE READ IN A CACHE COHERENT MICROPROCESSOR - A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory. | 2009-04-02 |
20090089511 | HYBRID CACHE COHERENCE USING FINE-GRAINED HARDWARE MESSAGE PASSING - Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware. | 2009-04-02 |
20090089512 | Adaptive Snoop-and-Forward Mechanisms for Multiprocessor Systems - In a network-based cache-coherent multiprocessor system, when a node receives a cache request, the node can perform an intra-node cache snoop operation and forward the cache request to a subsequent node in the network. A snoop-and-forward prediction mechanism can be used to predict whether lazy forwarding or eager forwarding is used in processing the incoming cache request. With lazy forwarding, the node cannot forward the cache request to the subsequent node until the corresponding intra-node cache snoop operation is completed. With eager forwarding, the node can forward the cache request to the subsequent node immediately, before the corresponding intra-node cache snoop operation is completed. Furthermore, the snoop-and-forward prediction mechanism can be enhanced seamlessly with an appropriate snoop filter to avoid unnecessary intra-node cache snoop operations. | 2009-04-02 |
20090089513 | ADDRESSING MULTI-CORE ADVANCED MEMORY BUFFERS - In some embodiments a method of addressing advanced memory buffers identifies whether a dual inline memory module includes more than one advanced memory buffer. If the dual inline memory module includes more than one advanced memory buffer, then each of the advanced memory buffers of the dual inline memory module is addressed separately, and an address is computed for a next dual inline memory module. Other embodiments are described and claimed. | 2009-04-02 |
20090089514 | Implementing Asynchronous Request for Forcing Dynamic Memory into Self Refresh - In some embodiments a memory controller receives a signal indicating a power condition of a system. In response to the received signal the memory controller controls a clock enable signal to a memory, allows only already issued memory controller signals to finish, and forces the memory into a self refresh. A transition is made such that power is only provided to the memory controller and to the memory, and no power is provided to any other components in the system. Other embodiments are described and claimed. | 2009-04-02 |
20090089515 | Memory Controller for Performing Memory Block Initialization and Copy - A memory controller and methods for performing memory block initialization and copy functions with reduced bus traffic are disclosed. The memory controller can perform the memory initialization by receiving a start address of a memory, an end address of the memory and a fill value. The fill value is then written from the memory controller to the memory in a fill range of arbitrary length defined by the start address and end address. | 2009-04-02 |
20090089516 | Reclaiming storage on a thin-provisioning storage device - A method, medium and apparatus for managing storage in a thin-provisioning storage device. The method includes ceasing to use storage on thinly provisioned storage delivered by a thin-provisioning storage device and notifying the thin-provisioning storage device of the unused storage. The method may further include reclaiming the unused storage in response to the notification. Alternatively, the notification may include recognizing the storage being freed and communicating the recognition to the storage device. In another form, the invention is a method, medium and apparatus for managing storage in a thin-provisioning storage device. This method includes delivering thinly provisioned storage and receiving notification that part of the thinly provisioned storage is no longer in use. The method may further include reclaiming that part of the thinly provisioned storage in response to the notification. Between receiving and reclaiming, the method may wait for a time to pass. | 2009-04-02 |
20090089517 | MEMORY CONTROL DEVICE AND SEMICONDUCTOR PROCESSING APPARATUS - The present invention provides a memory control device and a semiconductor processing apparatus which can be flexibly made adapted to a plurality of kinds of semiconductor memories. An SDRAM controller has: a register unit to which a command to be issued and a minimum interval (wait time) between issue of the command and issue of the next command are written by a CPU; and a command issuing unit that stops issue of the next command until the minimum interval written in the register elapses since issue of the command written in the register. Therefore, by changing software for the CPU, the SDRAM controller can be flexibly adapted to a plurality of kinds of SDRAMs. | 2009-04-02 |
20090089518 | SOLID STATE STORAGE RECLAMATION APPARATUS AND METHOD - A method and apparatus are disclosed for reclaiming solid state storage with limited write cycles such as flash memory. Through the use of shared storage for common data patterns, physical space may be conserved or reclaimed in a solid state device. The apparatus may use internal mappings and/or external device drivers to handle the reclamation of unused space. By enabling reclamation of physical space, the disclosed systems, apparatus, and methods may provide more efficient read and write access and improved wear leveling. | 2009-04-02 |
20090089519 | Method for memory management and chip cars associated therewith - A method for the processor controlled administering of a memory of a chip card. Initially, available free memory capacity is determined. Then, the memory is released for storing data. The data in the memory can be deleted. The memory can also be used by new data. A stored indication of the actual amount of free memory space is adapted to the current free memory space. The free memory space is reorganized and allocated. Furthermore, the invention relates to a chip card. The chip card comprises a chip with a memory wherein the memory is managed by a processor-controlled memory management system. Means for identifying used and unused memory are provided. The actual free memory space is displayed by means for displaying. | 2009-04-02 |
20090089520 | Hardware acceleration of strongly atomic software transactional memory - In accordance with some embodiments, software transactional memory may be used for both managed and unmanaged environments. If a cache line is resident in a cache and this is not the first time that the cache line has been read since the last write, then the data may be read directly from the cache line, improving performance. Otherwise, a normal read may be utilized to read the information. Similarly, write performance can be accelerated in some instances to improve performance. | 2009-04-02 |
20090089521 | SELF-ORGANIZING HETEROGENEOUS DISTRIBUTED STORAGE SYSTEM - The state of a computing environment is captured and heterogeneously stored on a network using self-organizing data portions. Altered portions of data of a captured computing state are replicated a plurality of times and each are embedded with a rule set that governs the distribution of the data. The rule set of each portion directs that data portion to relocate itself and remain as distant as possible from other replicated copies of that particular captured state and stored on a heterogeneous storage medium. Simultaneously, data portions that are associated with a similar file or other data structure are directed to maintain proximity with each other within a replicated copy forming a self-organized distribution of data portions. | 2009-04-02 |
20090089522 | System and method for dynamic storage device reconfiguration - A system and method provides for recovery of a backup process that has been interrupted by an address change for a connected backup storage device. A backup server may manage a data backup process from client computers to backup storage devices, each device having a unique address. Devices may be managed by storage node computers, which may occasionally reorganize its associated devices, causing some device address changes. This will interrupt the backup process since the server will not be able to match reorganized devices to known addresses. The present invention provides a method for querying the backup storage device, updating the server with the new address change, and continuing with the backup process. The present invention also provides a method for disabling the device from the backup process if the problem cannot be solved, then resuming the backup process. | 2009-04-02 |
20090089523 | TECHNIQUES FOR VIRTUAL ARCHIVING - Techniques for virtual archiving are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for performing virtual archiving comprising applying archiving rules to a backup catalog, generating a virtual archive catalog based at least in part on a result of applying archiving rules to the backup catalog, determining a backup image associated with the virtual archive catalog becoming expired and converting the backup image into an archive image. | 2009-04-02 |
20090089524 | Storage Device Controlling Apparatus and Method - A storage area, among multiple storage areas, which meets a predetermined requirement is determined to be a target for access. In a controller for controlling a multi-tiered storage subsystem, the following components operate under the control of a file write unit and a file read unit. First, a list acquiring unit obtains a list of tiers that can meet file access requirements. A requisite energy calculating unit calculates an additional energy amount necessary to satisfy file access requirements for each tier, an allowable energy calculating unit calculates an allowable additional energy amount, and a path retrieving unit determines a path to a target tier based on the energy amounts. An identifier acquiring unit obtains a file identifier, and an access point generating unit determines a file access point based on the path and the file identifier. A method for controlling a multi-tiered storage subsystem is also described. | 2009-04-02 |
20090089525 | REMOTE COPY WITH WORM GUARANTEE - In the case in which data in a storage system A is remotely copied to a storage system B, it is not taken into account whether the data of the remote copy is WORM data. In the case in which a setting is made such that data stored in a volume in the storage system A is copied to a volume in the storage system B, storage system A judges whether an attribute to the effect that data can be referred to and can be updated or to the effect that data can be referred to but cannot be updated is added to the volume in the storage system A. Then, if the volume is a volume to which the attribute to the effect that data can be referred to but cannot be updated is added, such attribute is added to the volume in the storage system B. | 2009-04-02 |
20090089526 | MEMORY DEVICES WITH DATA PROTECTION - A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device. | 2009-04-02 |
20090089527 | EXECUTING A PROTECTED DEVICE MODEL IN A VIRTUAL MACHINE - Embodiments of apparatuses, methods, and systems for executing a protected device model in a virtual machine are disclosed. In one embodiment, an apparatus includes recognition logic, memory management logic, control logic, and execution logic. The recognition logic is to recognize an indication, during execution of first code on a virtual machine, that the first code is attempting to access a device. The memory management logic is to prevent the virtual machine from accessing a portion of memory during execution of the first code, and to allow the virtual machine to access the portion of memory in response to the indication. The control logic is to transfer control of the apparatus from the first code to second code stored in the portion of memory, without exiting the virtual machine. The execution logic is to execute the second code to model the device. | 2009-04-02 |
20090089528 | STORAGE SYSTEM AND METHOD OF CONTROLLING THE SAME - A storage system is utilized to its fullest storage capacity by setting a write inhibitive attribute to a desired storage area of the storage system. The storage system has a logical volume in which data is stored and a control device which controls access to the data stored in the logical volume. A first area of a desired size is set in the logical volume, and an access control attribute is set to the first area. In response to a request made by a computer to perform access to the logical volume, the control device notifies the computer that the control device does not perform the access when an area designated by the access request contains at least a part of the first area and the access control attribute set to the first area inhibits the type of the access requested. | 2009-04-02 |
20090089529 | METHOD AND APPARATUS TO CONTROL ACCESS TO DEVICE ENABLE FEATURES - An integrated circuit device includes a first plurality of non-volatile memory locations such as fuses that supply programmed values corresponding to initially selected device features such as voltage, frequency, clock speed, and cache parameters. The device is programmed with a lock value in a second plurality of non-volatile memory locations. That lock value may be a randomly generated number that is unique for each device. After initial programming of the device, access to the device is prevented by appropriately programming access control. In order to unlock the device and modify device features, an unlock key value is supplied to the device. If the unlock key value correctly corresponds to the lock value, the device features can be modified. In that way device features can be modified, but security is maintained to prevent unauthorized modification to device features. | 2009-04-02 |
20090089530 | APPARATUS AND METHOD FOR ACCESSING A SYNCHRONOUS SERIAL MEMORY HAVING UNKNOWN ADDRESS BIT FIELD SIZE - An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a transition detector. The pull circuit causes the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory. The data out control circuit has an output terminal for providing the read command and a first predetermined number of address bits to the output terminal. The transition detector is coupled to an input terminal for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits. The transition detector will detect a transition of the input terminal when a correct number of address bits have been provided. | 2009-04-02 |
20090089531 | METHOD AND SYSTEM FOR MEMORY MANAGEMENT - A method for memory management that includes receiving a request for memory space, identifying a first memory module from a plurality of memory modules based on a first memory power management policy, wherein the first memory power management policy specifies how to allocate memory space in the plurality of memory modules to satisfy a power consumption criteria, and allocating the memory space on the first memory module. | 2009-04-02 |