| 14th week of 2009 patent applcation highlights part 11 |
| Patent application number | Title | Published |
|---|
| 20090085126 | Hybrid metal fully silicided (FUSI) gate - A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer. | 2009-04-02 |
| 20090085127 | NON-VOLATILE SEMICONDUCTOR MEMORY BASED ON ENHANCED GATE OXIDE BREAKDOWN - A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming. | 2009-04-02 |
| 20090085128 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate including a plurality of device regions and a device isolation region defining the device regions, and a semiconductor element located in a major surface of the semiconductor substrate and formed in at least one of the device regions. The device isolation region has a DTI (deep trench isolation) structure and has a bottom exposed to a backside of the semiconductor substrate. | 2009-04-02 |
| 20090085129 | DEFECT-FREE SOURCE/DRAIN EXTENSIONS FOR MOSFETS HAVING GERMANIUM BASED CHANNEL REGIONS - A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers. | 2009-04-02 |
| 20090085130 | Semiconductor device - The present invention relates to a semiconductor device comprising a semiconductor substrate ( | 2009-04-02 |
| 20090085131 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes: a semiconductor substrate; a diffusion layer provided in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate; a gate electrode provided on the gate insulation film; and a Ni silicide layer selectively provided on the diffusion layer, and a metal cap film having Co as a main component is selectively provided on the Ni silicide layer. | 2009-04-02 |
| 20090085132 | MRAM Cell Structure with a Blocking Layer for Avoiding Short Circuits - A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit. | 2009-04-02 |
| 20090085133 | On Chip Antenna And Method Of Manufacturing The Same - An antenna with air-filled trench is integrated with a radio frequency (RF) circuit. The trench locates directly under the metal lines that made up the antenna and is formed by etching from the back side of the semiconductor substrate until all the substrate material in the trench is removed. The air-filled trench greatly reduces the losses due to the semiconductor substrate; therefore the performance of the antenna improves greatly. When the antenna is a large planar spiral inductor, the air-filled trench means the semiconductor substrate inside the spiral inductor is untouched; hence integrated circuit can be built inside the antenna and on that substrate. Therefore the RF integrated circuit has a smaller size. Air-filled trench can also be used to reduce the semiconductor substrate noise coupling between digital circuit block and analog/RF circuit block. This air-filled trench and the air-filled trench under the antenna are formed at the same time. | 2009-04-02 |
| 20090085134 | Wafer-level image sensor module, method of manufacturing the same, and camera module - Provided is a wafer-level image sensor module including a wafer; an image sensor mounted on the wafer; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of vias formed in the wafer so as to be positioned outside the transparent member; a plurality of upper pads formed on the upper ends of the respective vias; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the lower ends of the respective vias. | 2009-04-02 |
| 20090085135 | Image Sensor and Manufacturing Method Thereof - Provided are embodiments of an image sensor. The image sensor can comprise a first substrate including a transistor circuit, a lower interconnection layer, an upper interconnection layer, and a second substrate including a vertical stacked photodiode. The lower interconnection layer is disposed on the first substrate and comprises a lower interconnection connected to the transistor circuit. The upper interconnection layer is disposed on the lower interconnection layer and comprises an upper interconnection connected with the lower interconnection. The vertical stacked photodiode can be disposed on the upper interconnection layer and connected with the upper interconnection through, for example, a single plug connecting a blue, green, and red photodiode of the vertical stack or a corresponding plug for each of the blue, green, and red photodiode of the vertical stack. | 2009-04-02 |
| 20090085136 | Image sensor and method for manufacturing the same - An image sensor and method of manufacturing the same are provided. The image sensor can comprise a photodiode region an interlayer dielectric, and a microlens. The interlayer dielectric can have a trench over the photodiode region, and the microlens can be disposed in the trench such that the microlens fills the trench. | 2009-04-02 |
| 20090085137 | SOLID-STATE IMAGING DEVICE - In a solid-state imaging device of the present invention, light-sensitive elements | 2009-04-02 |
| 20090085138 | GLASS CAP MOLDING PACKAGE, MANUFACTURING METHOD THEREOF AND CAMERA MODULE - The present invention is to reduce a manufacturing cost and improve productivity by manufacturing a small module in comparison with a conventional module and simplifying a process. | 2009-04-02 |
| 20090085139 | SOLID-STATE IMAGE SENSING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state image sensing element includes an effective pixel section in a central area of a light receiving surface thereof, and a ridge-shaped protruding portion is provided around the effective pixel section. A liquid transparent adhesive is applied on the effective pixel section, and a light transparent substrate is placed thereon. The light transparent substrate is in contact with the protruding portion, and is therefore prevented from sliding with the liquid adhesive serving as a lubricant. Thus, the light transparent substrate can be fixed at a predetermined position. | 2009-04-02 |
| 20090085140 | FINGER TYPE PHOTODIODE AND METHOD OF MANUFACTURING THE SAME - Provided are a finger type photodiode and a method of manufacturing the same, which can reduce noise by forming a shallow doping layer. The finger type photodiode includes a bottom substrate supporting layers to be formed thereon, an epitaxial layer formed on the bottom substrate, a finger doping layer formed in a finger shape on a top surface of the epitaxial layer, and a shallow doping layer formed with a shallow depth on an externally exposed top surface of the epitaxial layer and a top surface of the finger doping layer. Since the dangling bond generated on the epitaxial layer and the finger doping layer is reduced, noise can be reduced, thereby improving the light efficiency and reliability of the photodiode. | 2009-04-02 |
| 20090085141 | PIXEL MATRIX WITH COMPENSATION OF OHMIC DROPS ON THE POWER SUPPLIES - A matrix microelectronic device comprising:
| 2009-04-02 |
| 20090085142 | SOLID-STATE IMAGING DEVICE AND METHOD FOR FABRICATING SAME - A solid-state imaging device includes a plurality of pixels two-dimensionally arrayed in a well region disposed on a semiconductor substrate, each pixel including a photoelectric conversion section having a charge accumulation region which accumulates signal charge; an element isolation layer which is disposed on the surface of the well region along the peripheries of the individual charge accumulation regions and which electrically isolates the individual pixels from each other; and a diffusion layer which is disposed beneath the element isolation layer and which electrically isolates the individual pixels from each other, the diffusion layer having a smaller width than that of the element isolation layer. Each charge accumulation region is disposed so as to extend below the element isolation layer and be in contact with or in close proximity to the diffusion layer. | 2009-04-02 |
| 20090085143 | Image sensor and method of manufacturing the same - Image sensors and methods of fabricating the same are provided. An image sensor may include a substrate, a first pad provided on a front side of the substrate, a second pad provided on a backside of the substrate, one or more contacts, each of the contacts passing through the substrate and electrically connecting the first pad with the second pad, and one or more guard rings, each of the guard rings surrounding one or more contacts and having insulating characteristics. | 2009-04-02 |
| 20090085144 | PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE, AND IMAGE PICKUP SYSTEM - A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C | 2009-04-02 |
| 20090085145 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a semiconductor substrate. A layer of an electrically insulating material is formed over the semiconductor substrate. An electrically conductive feature is formed in the layer of electrically insulating material. A first layer of a semiconductor material is formed between the electrically conductive feature and the layer of electrically insulating material. | 2009-04-02 |
| 20090085146 | SEMICONDUCTOR DEVICE - A semiconductor device | 2009-04-02 |
| 20090085147 | MULTI-DIRECTIONAL TRENCHING OF A DIE IN MANUFACTURING SUPERJUNCTION DEVICES - A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die. | 2009-04-02 |
| 20090085148 | MULTI-DIRECTIONAL TRENCHING OF A PLURALITY OF DIES IN MANUFACTURING SUPERJUNCTION DEVICES - A method of manufacturing a superjunction device includes providing a semiconductor wafer having a plurality of dies. A first plurality of trenches having a first orientation are formed in a first die. A second plurality of trenches having a second orientation are formed in a second die. The second orientation is different from the first orientation. | 2009-04-02 |
| 20090085149 | SEMICONDUCTOR DEVICE AND METHOD OF PROCESSING THE SAME - Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers. | 2009-04-02 |
| 20090085150 | Semiconductor device having silicon-on-insulator (SOI) structure and method of forming semiconductor device - A semiconductor device includes a substrate, an insulating layer formed on the substrate, an active layer formed on the insulating layer, and a metal layer formed on a back surface of the substrate, the substrate and the metal layer being in ohmic contact. By bringing the substrate and the metal layer into ohmic contact, the resistance difference between the substrate and the metal layer can be reduced. | 2009-04-02 |
| 20090085151 | SEMICONDUCTOR FUSE STRUCTURE AND METHOD - An electrical structure and method of forming. The electrical structure includes a semiconductor substrate, an insulator layer formed over and in contact with the semiconductor substrate, and a semiconductor fuse structure formed over the insulator layer. The fuse structure includes a silicon layer and a continuous metallic silicide layer. The continuous metallic silicide layer includes a first section formed over and in contact with a first horizontal section of a top surface of the silicon layer, a second section formed over and in contact with a second horizontal section of the top surface of the silicon layer, and a third section formed within an opening within the top surface of the silicon layer. | 2009-04-02 |
| 20090085152 | THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME - Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto. | 2009-04-02 |
| 20090085153 | DIODE ARRAY AND METHOD OF MAKING THEREOF - A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface. | 2009-04-02 |
| 20090085154 | VERTICAL DIODE BASED MEMORY CELLS HAVING A LOWERED PROGRAMMING VOLTAGE AND METHODS OF FORMING THE SAME - In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided. | 2009-04-02 |
| 20090085155 | METHOD AND APPARATUS FOR PACKAGE-TO-BOARD IMPEDANCE MATCHING FOR HIGH SPEED INTEGRATED CIRCUITS - A method of package-to-board impedance matching for high speed integrated circuits (ICs). Multiple solder balls are attached to an IC package. The IC package includes multiple conductive interconnect layers, where one of the conductive interconnect layers is coupled to one or more of the multiple solder balls. Multiple vias are coupled between different conductive interconnect layers. An inductive element is coupled between an interconnect lead and a via land in the conductive interconnect layer within the IC package. The physical layout dimensions of the inductive element are configured such that the inductive element provides an inductance value that is sufficient to offset a parasitic capacitance provided by the conductive interconnect layers and the solder balls. The inductive element may be a bond wire, an inductive interconnect, or a spiral interconnect. | 2009-04-02 |
| 20090085156 | METAL SURFACE TREATMENTS FOR UNIFORMLY GROWING DIELECTRIC LAYERS - A fabrication process for a MIM capacitor comprises providing a substrate, depositing a first metal layer on a dielectric layer of the substrate, forming an interfacial layer on the first metal layer, wherein the interfacial layer has a hydroxyl terminated surface, depositing a capacitor dielectric layer on the interfacial layer using an ALD process, and depositing a second metal layer on the capacitor dielectric layer. The interfacial layer may be formed by depositing a thin layer of a metal oxide, by oxidizing a surface of the first metal layer with an oxygen plasma, or by evaporating a thin metal oxide onto the surface of the first metal layer. | 2009-04-02 |
| 20090085157 | Manufacturing method for an integrated circuit, corresponding intermediate integrated circuit structure and corresponding integrated circuit - The present invention provides a method of manufacturing integrated circuit including a plurality of pillars, comprising the steps of: forming a plurality of first trenches in a first layer comprising a first material, thereby leaving a plurality of fins of the first material between said trenches; forming an infill comprising a second material in said first trenches; forming a plurality of second trenches in said first layer and said infill, the second trenches having sidewalls, walls, wherein first portions of said sidewalls expose the first material, and second portions of said sidewalls expose the second material; and removing either the first or the second material selectively to the respective other material, thereby leaving said pillars of the remaining material. The invention also provides a corresponding intermediate integrated circuit structure. | 2009-04-02 |
| 20090085158 | Package with improved connection of a decoupling capacitor - A package ( | 2009-04-02 |
| 20090085159 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes cylinder type bottom electrodes connected to a contact plug formed over a semiconductor substrate, and a supporting pattern formed between the cylinder type bottom electrodes, wherein a portion of sidewalls of the bottom electrodes is higher than the supporting pattern and the other portion of the sidewalls of the bottom electrode is lower than the supporting pattern. | 2009-04-02 |
| 20090085160 | Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System - Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode. | 2009-04-02 |
| 20090085161 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints. | 2009-04-02 |
| 20090085162 | SEMICONDUCTOR DEVICE AND INTEGRATED SEMICONDUCTOR CIRCUIT DEVICE - The present invention provides a semiconductor device that includes a plurality of transistor cells and makes it possible to achieve higher degree of integration and lower cost of an integrated semiconductor circuit device as the first object, and provide an integrated semiconductor circuit device of high density integration and compact construction at a low cost. | 2009-04-02 |
| 20090085163 | VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH - Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus. | 2009-04-02 |
| 20090085164 | WIRING BOARD - There is provided a wiring board. The wiring board includes: a semiconductor substrate having a through hole and covered with an insulating film; a through electrode formed in the through hole; a first wiring connected to one end of the through electrode; and a second wiring connected to the other end of the through electrode. The semiconductor substrate includes: a semiconductor element and a first guard ring formed to surround the through hole. The semiconductor element includes a first conductivity-type impurity diffusion layer having a different conductivity-type from that of the semiconductor substrate and is electrically connected to the first wiring and the second wiring. | 2009-04-02 |
| 20090085165 | Group 3-5 Nitride Semiconductor Multilayer Substrate, Method for Manufacturing Group 3-5 Nitride Semiconductor Free-Standing Subtrate, and Semiconductor Element - A group 3-5 nitride semiconductor multilayer substrate ( | 2009-04-02 |
| 20090085166 | GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A gallium nitride semiconductor device is disclosed that can be made by an easy manufacturing method. The device includes a silicon substrate, buffer layers formed on the top surface of the silicon substrate, and gallium nitride grown layers formed thereon. The silicon substrate has trenches | 2009-04-02 |
| 20090085167 | Methods for Forming Metal-Germanide Layers and Devices Obtained Thereby - The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO | 2009-04-02 |
| 20090085168 | Semiconductor device and method for manufacturing same - When a photoresist or the like is spin-coated on a semiconductor chip comprising a seal ring is formed, striation due to corners of the seal ring is suppressed. A wiring metal layer and a contact are layered, and a seal structure ( | 2009-04-02 |
| 20090085169 | METHOD OF ACHIEVING ATOMICALLY SMOOTH SIDEWALLS IN DEEP TRENCHES, AND HIGH ASPECT RATIO SILICON STRUCTURE CONTAINING ATOMICALLY SMOOTH SIDEWALLS - A high aspect ratio silicon structure comprises a silicon substrate ( | 2009-04-02 |
| 20090085170 | INTERFACIAL ROUGHNESS REDUCING FILM, WIRING LAYER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An interfacial roughness reducing film which is in contact, on one side thereof, with an insulating film and in contact, on a side opposite from the one side, with wiring comprises a Si—O bond, and is formed using a composition containing a silicon compound that comprises at least one bond of Si—N bonds and Si—Cl bonds wherein the number of Si—N bonds and Si—Cl bonds combined per molecule of the compound is at least two. An interfacial roughness between the interfacial roughness reducing film and the wiring is smaller than that between the interfacial roughness reducing film and the insulating film. | 2009-04-02 |
| 20090085171 | OXIDE FILM FORMATION METHOD AND IMAGE SENSING APPARATUS - An oxide film formation method comprises steps of: generating a plasma from a gas mixture containing an inert gas and an oxidizing gas whose mixing ratio to the inert gas is higher than 0, and is 0.007 or lower; and forming an oxide film on a surface of a silicon substrate by using the plasma. | 2009-04-02 |
| 20090085172 | Deposition Method, Deposition Apparatus, Computer Readable Medium, and Semiconductor Device - A deposition method includes steps of placing a substrate on a susceptor in a process chamber; supplying to the process chamber a source gas including an organic compound and a plasma gas for facilitating activation of the source gas into plasma; evacuating the process chamber to a reduced pressure; generating plasma of the plasma gas and the source gas in the process chamber to deposit a barrier film including carbon on the substrate; and applying high frequency bias electric power to the susceptor during the plasma generating step. | 2009-04-02 |
| 20090085173 | SIDEWALL PROTECTION LAYER - The present disclosure generally relates to forming a metallization layer in a semiconductor device. In particular, this disclosure concerns the damascene inlay technique in low-k dielectric layers. Etching trenches and vias in low-k dielectric materials leads to uneven and porous sidewalls of the trenches and vias due to the porous nature of the low-k dielectric materials. Thus, smooth and dense sidewalls cannot be achieved, which is a prerequisite for an effective barrier layer, which prevents copper from being diffused into the low-k dielectric material. As a consequence, process tolerances are high and the reliability of the semiconductor device is reduced. The present disclosure overcomes these drawbacks by a surface treatment of the sidewalls of trenches and vias in order to densify the surface such that the following barrier layer may more effectively prevent copper from diffusing into the low-k or ultra high-k dielectric material. | 2009-04-02 |
| 20090085174 | STRUCTURAL BODY AND MANUFACTURING METHOD THEREOF - The present invention includes a substrate structural body having a high electrostatic chuck force at a low voltage even when an insulated board is used, and a method for manufacturing the substrate structural body. As the substrate structural body, there is provided a substrate structural body for attaining its fixing by an electrostatic chuck mechanism, comprising at least a first polycrystalline silicon film formed on the back surface of a substrate comprised of an insulating material or its back and side surfaces, wherein a top layer of part of the back surface or the back and side surfaces is of a first silicon insulating film. | 2009-04-02 |
| 20090085175 | SEMICONDUCTOR DEVICE CONTAINING A BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYER AND METHOD OF FORMING - A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described. | 2009-04-02 |
| 20090085176 | GLASS-BASED SOI STRUCTURES - Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer ( | 2009-04-02 |
| 20090085177 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME ARRAY - An integrated circuit package system includes providing an integrated circuit die; attaching the integrated circuit die over a lead grid having lead blocks; and connecting a die interconnect to the integrated circuit die and the lead blocks. | 2009-04-02 |
| 20090085178 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BASE STRUCTURE DEVICE - An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device. | 2009-04-02 |
| 20090085179 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a first and second die pads arranged side by side; a plurality of inner leads arranged around the first and second die pads; first and second chips mounted on the first and second die pads; a bar provided between the first and second chips and the plurality of inner leads, extending in an array direction of the first chip and the second chip; a plurality of wires that connect the first and second chips and the plurality of inner leads and connect the first chip and the second chip; and resin that seals the first and second die pads, the plurality of inner leads, the first and second chips, the plurality of wires and the bar, wherein the bar comprises a mark provided at a position corresponding to an area between the first chip and the second chip in an array direction of the first chip and the second chip. | 2009-04-02 |
| 20090085180 | Packaging carrier with high heat dissipation and method for manufacturing the same - The present invention relates a packaging carrier with high heat dissipation for packaging a chip, comprising: a carrier body, an interfacial metal layer, at least one diamond-like carbon thin film, a plated layer, and an electrode layer. Herein, the packaging carrier further comprises through holes. The present invention further discloses a method for manufacturing the aforementioned packaging carrier, comprising: providing a carrier body; forming an interfacial metal layer on the upper surface of the carrier body; forming a diamond-like carbon thin film on the interfacial metal layer; forming a plated layer on the diamond-like carbon thin film; forming an electrode layer on the lower surface of the carrier body; and forming through holes extending through all or part of the aforementioned elements. The present invention uses a diamond-like carbon thin film and through holes for heat dissipation in three dimensions to improve heat dissipation of an electronic device. | 2009-04-02 |
| 20090085181 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DIE - An integrated circuit package system includes providing die; forming leads adjacent the die; forming a die paddle adjacent the leads with the die thereover; and forming a cavity for isolating one of the die and a die attach segment of the die paddle. | 2009-04-02 |
| 20090085182 | Semiconductor device and method for manufacturing the same - A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 10 | 2009-04-02 |
| 20090085183 | INTEGRATED-CIRCUIT PACKAGE FOR PROXIMITY COMMUNICATION - Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die. | 2009-04-02 |
| 20090085184 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same, and more particularly, a semiconductor package and a method of fabricating the semiconductor package. The semiconductor package includes a first package that comprises a first substrate, at least one first semiconductor chip stacked on the first substrate, and first conductive pads exposed on a top surface of the first substrate; a second package disposed below the first package such that the second package comprises a second substrate, at least one second semiconductor chip, and second conductive pads exposed on a bottom surface of the second substrate; and a connection unit that extends from the first conductive pads to the second conductive pads such that the connection unit covers a side surface of the first package and a side surface of the second package in order to electrically connect the first package to the second package. | 2009-04-02 |
| 20090085185 | STACK-TYPE SEMICONDUCTOR PACKAGE, METHOD OF FORMING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME - A stack-type semiconductor package, a method of forming the same, and an electronic system including the same are provided. The stack-type semiconductor package includes: a lower printed circuit board having a plurality of connection bumps disposed on an upper surface of the lower printed circuit board and a plurality of lower interconnections; at least one first lower chip sequentially stacked on the lower printed circuit board and electrically connected to the plurality of lower interconnections; a lower molding resin compound disposed on the lower printed circuit board and covering the first lower chips; a double-sided wiring board bonded to the lower molding resin compound and electrically connected to the connection bumps; and an upper chip package bonded to the double-sided wiring board and having upper bumps electrically connected to an interconnection pattern of the double-sided wiring board. | 2009-04-02 |
| 20090085186 | Semiconductor Device and Methods of Manufacturing Semiconductor Devices - This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements. | 2009-04-02 |
| 20090085187 | LOADING MECHANISM FOR BARE DIE PACKAGES AND LGA SOCKET - Methods and associated apparatus of reducing stress in a package Those methods may comprise providing a package comprising a die coupled to a substrate, wherein the substrate is disposed on an LGA socket, and wherein a TIM is disposed on a top surface of the die, and then attaching a thermal solution to the TIM, wherein at least one standoff is attached between the thermal solution and the substrate. | 2009-04-02 |
| 20090085188 | POWER SEMICONDUCTOR MODULE - A power semiconductor module comprising: a power semiconductor element; a case for receiving the power semiconductor element; a control terminal which is connected to a control electrode of the power semiconductor element, the control terminal is installed in a state of protruding from an upper surface of the case; and a conductive spring which is inserted into the control terminal so that an inner surface of the spring makes contact with at least a part of the side surface of the control terminal, the conductive spring is electrically connected to a printed substrate placed as opposed to the upper surface of the case by making pressurization contact with the printed substrate. | 2009-04-02 |
| 20090085189 | POWER SEMICONDUCTOR MODULE - One embodiment provides a semiconductor module with an electrically insulating substrate. A conductor track is arranged on the substrate. A semiconductor chip and sleeve member are arranged on the substrate and electrically connected to the conductor track. The sleeve member includes a rim with a maximum inner diameter. The module further includes a contact element. The contact element includes a first end arranged within and electrically connected to the sleeve member, a second end providing an external contact of the module, and a section arranged between the first end and the second end. The section includes a maximum outer diameter that is larger than the maximum inner diameter of the rim. The contact element is in mechanical contact with the sleeve member such that the section between both ends of the contact element is arranged outside the sleeve member and borne on the rim of the sleeve member. | 2009-04-02 |
| 20090085190 | Semiconductor Device and Method for Making Same - A method for making a semiconductor device includes creating conductive structures on a substrate. Contact pads of a semiconductor die are connected to first ends of conductive structures. The semiconductor die is encapsulated or embedded and the substrate is removed such that second ends of the conductive structures are exposed to the exterior. | 2009-04-02 |
| 20090085191 | Environment-Resistant Module, Micropackage And Methods Of Manufacturing Same - An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams. | 2009-04-02 |
| 20090085192 | Packaging substrate structure having semiconductor chip embedded therein and fabricating method thereof - The present invention relates to a packaging substrate structure having an semiconductor chip embedded therein and a method for manufacturing the same. The structure comprises: a substrate body having a through cavity, wherein the substrate body is a multilayer board which comprises a core board and a first built-up structure disposed on each of the opposite surfaces of the core board; an semiconductor chip disposed and fixed in the cavity, wherein the active surface of the semiconductor chip has a plurality of electrode pads thereon; and a second built-up structure disposed on at least one surface of the substrate body as well as the surface of the semiconductor chip, wherein the second built-up structure has a plurality of conductive vias conducting to the first built-up structure. The present invention can reduce the stress imposed on the surface of the semiconductor chip and increase the reliability of the whole package structure. | 2009-04-02 |
| 20090085193 | Heat-releasing printed circuit board and semiconductor chip package - A heat-releasing printed circuit board and semiconductor chip package are disclosed. The heat-releasing printed circuit board includes an insulation layer, on a surface of which a circuit pattern is formed, and a solder resist, which is stacked on the insulation layer, where the solder resist contains carbon nanotubes. The heat-releasing printed circuit board allows the heat generated in a semiconductor chip to be dispersed in several directions of the board or package, to improve heat-releasing property. | 2009-04-02 |
| 20090085194 | WAFER LEVEL PACKAGED MEMS DEVICE - An apparatus and method for sensor architecture based on bulk machining of silicon wafers and fusion bond joining which provides a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device. An example device includes a device sensor mechanism formed in an active semiconductor layer and separated from a handle layer by a dielectric layer, and a silicon cover plate having a handle layer with a dielectric layer being bonded to portions of the active layer. Pit are included in one of the handle layers and corresponding dielectric layers to access electrical leads on the active layer. Another example includes set backs from the active components formed by anisotropically etching the handle layer while the active layer has been protectively doped. | 2009-04-02 |
| 20090085195 | Method of Making Microelectronic Package Using Integrated Heat Spreader Stiffener Panel and Microelectronic Package Formed According to the Method - A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel; mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel; and singulating the combination to yield a plurality of microelectronic packages, each of the packages including: an IHS component of the IHS panel, one of the plurality IC dies bonded and thermally coupled to said IHS component and one of the plurality of package substrates, said IHS component and said one of the plurality of IC dies being mounted to said one of the plurality of package substrates to form said each of the packages. | 2009-04-02 |
| 20090085196 | INTEGRATED CIRCUIT CHIP MANUFATURING METHOD AND SEMICONDUCTOR DEVICE - This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region. | 2009-04-02 |
| 20090085197 | Method of Fabrication of On-Chip Heat Pipes and Ancillary Heat Transfer Components - The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture. | 2009-04-02 |
| 20090085198 | NANOTUBE BASED VAPOR CHAMBER FOR DIE LEVEL COOLING - The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap. | 2009-04-02 |
| 20090085199 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD LOCK SUBASSEMBLY - An integrated circuit package system includes: providing a substrate; attaching an integrated circuit over the substrate; attaching an integrated circuit subassembly system having a perforated interposer over the substrate with the perforated interposer having a slot; and forming a package encapsulation over the integrated circuit subassembly system, the perforated interposer, the integrated circuit, and the substrate with the slot filled with the package encapsulation. | 2009-04-02 |
| 20090085200 | LOW LOSS RADIO FREQUENCY SIGNAL COMMUNICATION WITHIN A PACKAGE, A BOARD AND/OR A WAVE GUIDE - In some embodiments an integrated circuit package includes a coaxial arrangement of one or more ground via surrounding a signal via. The one or more ground via and the signal via extend through the package to allow transmission of signals between an integrated circuit and a board. Other embodiments are described and claimed. | 2009-04-02 |
| 20090085201 | DIRECT DEVICE ATTACHMENT ON DUAL-MODE WIREBOND DIE - A dual-mode integrated circuit comprises wirebondable and solderable electrical connectors. | 2009-04-02 |
| 20090085202 | Methods and Apparatus for Assembling Integrated Circuit Device Utilizing a Thin Si Interposer - Methods of assembling an integrated circuit are provided. An interposer supported by an integrated handler is solder bumped onto one or more bond pads on a substrate. The integrated handler is removed from the interposer. A side of the interposer opposite that of the substrate is solder bumped to one or more bond pads on a chip. | 2009-04-02 |
| 20090085203 | Method for Exchanging Semiconductor Chip of Flip-Chip Module and Flip-Chip Module Suitable Therefor - A process for replacing a semiconductor chip of such a flip-chip module and a suitable flip-chip module and an apparatus for implementing the method are disclosed. The flip-chip module comprises at least one semiconductor chip and a substrate. The semiconductor chip comprises contact posts on a surface that are disposed at right angles to the surface. With these contact posts it is connected with contact points of the substrate via a soldered connection. The contact posts completely cover the contact points with their end faces. Due to this it is possible to completely press the solder between the contact posts and contact points out of the intermediate area between the contact points and the contact posts after a renewed heating. This permits a renewed attachment of a further semiconductor chip. | 2009-04-02 |
| 20090085204 | Wafer-level package and method of manufacturing the same - Provided is a wafer-level package including a wafer-level semiconductor chip having a plurality of integrated circuits (ICs) and pads formed on the top surface thereof; a molding material of which the outer portion is supported by the top surface of the semiconductor chip such that a cavity is provided on the semiconductor chip; and a conducive member filled in a plurality of vias which are formed in arbitrary positions of the molding material so as to pass through the molding material, the conductive member being connected to the pads. | 2009-04-02 |
| 20090085205 | METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC COMPONENT PACKAGE - A manufacturing method of an electronic component package, includes: forming electrode pads on a main surface of a first electronic component; forming first bonding wires shaped in loop so as to be electrically connected with the electrode pads and elongated upward from the electrode pads and such that both ends of the first bonding wires are on the electrode pad, respectively; forming a resin layer over the main surface of the first electronic component so as to embed the first bonding wires; removing the resin layer so as to expose ends of the first bonding wires from the resin layer and removing the end of each of the first bonding wires so that two wires are elongated from on each of the electrode pads; and forming a metallic layer on the surface of the resin layer after removing so that the first bonding wires are electrically connected with the metallic layer. | 2009-04-02 |
| 20090085206 | METHOD OF FORMING SOLDER BUMPS ON SUBSTRATES - A method of forming solder bumps on a substrate is disclosed. The method includes forming a plurality of contact points on the substrate. The method further includes depositing a layer of surface finish material on the plurality of contact points. Furthermore, the method includes disposing a plurality of solder balls on the layer of surface finish material. Each solder ball of the plurality of solder balls has conductive material including a solder alloy and Phosphorus. Thereafter, the method includes applying a solder reflow process to the plurality of solder balls to configure a plurality of solder bumps on the substrate layer. The concentration of the Phosphorus in the solder material is based on target performance characteristic of the substrate having the plurality of solder bumps. | 2009-04-02 |
| 20090085207 | Ball grid array substrate package and solder pad - The invention provides ball grid array assemblies and methods for their manufacture, with improved characteristics favoring the formation of secure metallurgical solder pad to solder ball joints. In disclosed preferred embodiments of ball grid array assemblies, substrates, and methods according to the invention, solder pads are provided with metal blocks comprising a layer primarily of nickel plated with an outer metal layer comprising primarily gold. | 2009-04-02 |
| 20090085208 | Semiconductor device - A semiconductor device ( | 2009-04-02 |
| 20090085209 | SEMICONDUCTOR DEVICE WITH COPPER WIREBOND SITES AND METHODS OF MAKING SAME - Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer. | 2009-04-02 |
| 20090085210 | STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer. | 2009-04-02 |
| 20090085211 | ELECTRICAL CONTACTS FOR INTEGRATED CIRCUITS AND METHODS OF FORMING USING GAS CLUSTER ION BEAM PROCESSING - Embodiments of the invention describe electrical contacts for integrated circuits and methods of forming using gas cluster ion beam (GCIB) processing. The electrical contacts contain a fused metal-containing layer formed by exposing a patterned structure to a gas cluster ion beam containing a transition metal precursor or a rare earth metal precursor. | 2009-04-02 |
| 20090085212 | CLADDED SILVER AND SILVER ALLOY METALLIZATION FOR IMPROVED ADHESION ELECTROMIGRATION RESISTANCE - In semiconductor integrated circuit and device fabrication interconnect metallization is accomplished by a clad Ag deposited on a SiO2 level on a Si surface. The clad Ag has a layer of an alloy of Ag and Al (5 atomic %) contacting the SiO2, a layer of substantially pure Ag and an outer layer of the Ag and Al alloy. The alloy improves adhesion to the SiO2, avoids agglomeration of the Ag, reduces or eliminates diffusion at the SiO2 surface, reduces electromigration and presents a passive exterior surface. | 2009-04-02 |
| 20090085213 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si | 2009-04-02 |
| 20090085214 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member. | 2009-04-02 |
| 20090085215 | Semiconductor component comprising copper metallizations - A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy. | 2009-04-02 |
| 20090085216 | Semiconductor device - The present invention provides a semiconductor device excellent in the reliability of connection between the semiconductor device and a mounting board. The semiconductor device has external connecting terminals. Each of the external connecting terminals includes a Cu electrode, intermetallic compounds containing Cu, each formed over the Cu electrode, stopper portions which cover surfaces of the intermetallic compounds at intervals, and a solder alloy comprising Bi and an impurity containing Sn formed over the stopper portions and the intermetallic compounds. | 2009-04-02 |
| 20090085217 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a semiconductor chip formed on the carrier, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip. | 2009-04-02 |
| 20090085218 | FLASH MEMORY DEVICE AND FABRICATING METHOD THEREOF - A flash memory device may include a first insulating layer on a base insulating layer on a substrate, a lower wire layer that fills a trench in the first insulating layer, a first insulating interlayer and a second insulating layer stacked in sequence on the first insulating layer and the lower wire layer, a middle wire layer that fills a trench in the second insulating layer, and a second insulating interlayer and an upper wire layer stacked in sequence on the middle wire layer, wherein the lower wire layer. The middle wire layer and the upper wire layer may be electrically connected to each other and the first insulating layer may include a low-k layer in contact with the base insulating layer. In addition, each of the first insulating interlayer, the second insulating layer, and the second insulating interlayer may include an FSG layer. | 2009-04-02 |
| 20090085219 | POWER SEMICONDUCTOR ARRANGEMENT - A power semiconductor arrangement is provided that includes a power semiconductor chip being electrically connected to a set of plug-like elements with at least two plug-like elements and further including a sheet metal strip line including a set of openings receiving the first set of plug-like elements, where the set of openings in the sheet metal strip line and the set of plug-like elements establish a press fit connection. | 2009-04-02 |
| 20090085220 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING - A semiconductor component and a method of manufacturing is disclosed. One embodiment provides a semiconductor chip with a chip pad and a support pad and a substrate with a substrate pad. The support pad is connected by wire bonding to the chip pad and the support pad. | 2009-04-02 |
| 20090085221 | Multi-host interface controller with USB PHY/analog functions integrated in a single package - In a first embodiment, an apparatus and a method of fabrication thereof includes a substrate, a controller formed on a first integrated circuit (IC) die and disposed on the substrate, a second IC die embodying circuitry configured to enable communication between the controller and an external device, first I/O pads disposed on the first IC die, second I/O pads disposed on the second IC die, wire bonding interconnections coupling at least one of the first I/O pads with at least one of the second I/O pads, and a memory array formed on a third IC die and configured to enable communication with the controller. In a second embodiment the memory array is alternatively integrated into the first IC die. | 2009-04-02 |
| 20090085222 | ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF - There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed. | 2009-04-02 |
| 20090085223 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements. | 2009-04-02 |
| 20090085224 | STACK-TYPE SEMICONDUCTOR PACKAGE - Provided is a stack-type semiconductor package including a base chip having a circuit formed on one of its surfaces, at least one stack chip having a circuit stacked on the base chip, an adhesive interposed between the base chip and the stack chip, and signal transmission members formed along a lateral surface of the stack chip. The fabrication process of this stack-type semiconductor package may be simplified and the number of process operations may be lessened, thereby reducing the production time and cost. Also, a state of electrical contact of a terminal with a signal transmission member may be solidified, thereby improving the reliability of the stack-type semiconductor package. Furthermore, new post-type signal transmission members are adopted instead of wires or electrodes so that the structural stability and productivity of the stack-type semiconductor package may be markedly enhanced. | 2009-04-02 |
| 20090085225 | Semiconductor packages having interposers, electronic products employing the same, and methods of manufacturing the same - A semiconductor package and methods for manufacturing the same are provided. The semiconductor package includes a substrate, first and second semiconductor chips stacked on the substrate. An interposer is disposed between the first and second semiconductor chips. The interposer has a non-planar top surface. | 2009-04-02 |
