| 14th week of 2009 patent applcation highlights part 10 |
| Patent application number | Title | Published |
|---|
| 20090085026 | STRUCTURE AND METHOD FOR MANIPULATING SPIN QUANTUM STATE THROUGH DIPOLE POLARIZATION SWITCHING - Disclosed herein is a structure and method for manipulating a spin state, regarded as important in the field of spintronics, by which the distribution of spin-up and spin-down states of carriers in a hybrid double quantum disk structure, composed of a diluted magnetic semiconductor and a ferroelectric compound semiconductor, is manipulated through dipole polarization switching of the ferroelectric compound semiconductor without a change in bias. Giant Zeeman splitting properties of the diluted magnetic semiconductor and polarization properties of the ferroelectric compound semiconductor are applied in conjunction with the Pauli exclusion principle, thus enabling the combination or separation of carriers in spin-up and spin-down states in the hybrid double quantum disk structure. The spin relaxation time in the structure is on the order of microseconds, during which the spin state is well-defined, and therefore, the structure can be applied to microprocessors having gigahertz clock speeds. | 2009-04-02 |
| 20090085027 | THREE DIMENSIONAL STRAINED QUANTUM WELLS AND THREE DIMENSIONAL STRAINED SURFACE CHANNELS BY GE CONFINEMENT METHOD - The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment. | 2009-04-02 |
| 20090085028 | HYBRID MATRICES FOR THIN-LAYER TRANSISTORS - The invention relates to a hybrid semiconductor material and to a device containing same. | 2009-04-02 |
| 20090085029 | Photoelectric conversion element and imaging device - A photoelectric conversion element is provided and includes: a conductive thin layer; an organic photoelectric conversion layer including a compound represented by formula (I); and a transparent conductive thin layer, in this order: | 2009-04-02 |
| 20090085030 | INCREASED RELIABILITY FOR A CONTACT STRUCTURE TO CONNECT AN ACTIVE REGION WITH A POLYSILICON LINE - By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria. | 2009-04-02 |
| 20090085031 | Wafer-Shaped Measuring Apparatus and Method for Manufacturing the Same - The present invention provides a temperature measuring apparatus with favorable temperature measuring performance and a method of manufacturing the same. A temperature measuring apparatus ( | 2009-04-02 |
| 20090085032 | PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A method of fabricating a pixel structure is provided. First, a semiconductor material layer and a first conductive layer are sequentially formed on a substrate. Next, a first patterned photoresist layer with a fillister is formed on the first conductive layer by a first mask. A semiconductor layer, a drain, and a source are formed by the first patterned photoresist layer. After removing the first patterned photoresist layer, a dielectric material layer covering the source, the drain, and the semiconductor layer is formed. A second conductive layer is formed on the dielectric material layer. Then, a second patterned photoresist layer with a salient is formed on the second conductive layer by a second mask. A gate and a dielectric layer are formed by the second patterned photoresist layer. After removing the second patterned photoresist layer, a pixel electrode electrically connected to the drain is formed above the substrate. | 2009-04-02 |
| 20090085033 | THIN FILM TRANSISTOR, PIXEL STRUCTURE AND FABRICATION METHODS THEREOF - A thin film transistor including a gate, a gate insulator layer, a doped semiconductor layer, a channel layer, a source, and a drain is provided. The gate is disposed on a substrate, and the gate insulator layer is disposed on the substrate and covers the gate. The doped semiconductor layer is disposed on the gate insulator layer above the gate. Furthermore, the channel layer is disposed on the doped semiconductor layer. The source and the drain are disposed separately on two sides of the channel layer. | 2009-04-02 |
| 20090085034 | THIN FILM TRANSISTOR ARRAY SUBSTRATE - The present invention relates to a thin film transistor array substrate comprising a gate line and a data line that are separated by an insulting layer and intersecting each other to define a pixel, wherein a data auxiliary line is disposed adjacent to an intersection portion between the data line and the gate line, and both ends of the data auxiliary line are on two sides of the intersection portion and connected with the data lines, respectively. | 2009-04-02 |
| 20090085035 | Method of Producing a Semiconductor Element in a Substrate and a Semiconductor Element - A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities and carbide precipitates in the substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, annealing the substrate such that at least a part of the crystallographic defects are eliminated using the micro-cavities and the carbide precipitates, and wherein the semiconductor element is formed using the doping atoms. | 2009-04-02 |
| 20090085036 | LIGHT SENSOR - A light sensor includes an intrinsic layer, a first ion doping area disposed one side of the intrinsic layer, a second ion doping area disposed at the other side of the intrinsic layer, an oxide insulating layer on the intrinsic layer, and a gate metal on the oxide insulating layer. The first and second ion doping areas have the same P type or N type doped ions. The intrinsic layer further includes a first light sensing region close to the first ion doping area. The first light sensing region is used for generating electron-hole pairs based on luminance of incident light. | 2009-04-02 |
| 20090085037 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME - A method for fabricating an array substrate for a liquid crystal display (LCD) is provided. A semiconductor layer and a transparent lower electrode formed on a substrate is provided and covered by a first dielectric layer serving as a gate dielectric layer and a capacitor dielectric layer. A gate electrode and an upper electrode comprising a transparent electrode portion and a metal electrode portion are formed on the first dielectric layer and covered by a second dielectric layer. A source/drain electrode, a planarization layer, and a pixel electrode are sequentially formed on the second dielectric layer, in which the source/drain electrode is electrically connected to the semiconductor layer through the first and second dielectric layers and the pixel electrode is electrically connected to the source/drain electrode through the planarization layer. An array substrate for an LCD is also disclosed. | 2009-04-02 |
| 20090085038 | SUBSTRATE FOR DISPLAY DEVICE, MANUFACTURING METHOD FOR SAME AND DISPLAY DEVICE - The present invention provides the substrate for a display device, comprising a scan line, a signal line and a switching element on an insulating substrate, and further comprising an interlayer insulation film and a pixel electrode, the switching element is provided at an intersection of the scan line and the signal line, and have a gate electrode connected to the scan line, a source electrode connected to the signal line, and a drain electrode connected to the pixel electrode, the interlayer insulation film has a contact hole for connecting the drain electrode of the switching element to the pixel electrode, and a protective layer is provided above the scan line and/or the signal line in the substrate for a display device. | 2009-04-02 |
| 20090085039 | Image display system and fabrication method thereof - The invention provides a method for fabricating a low-temperature polysilicon (LTPS) driving circuit and thin film transistor. The method includes: providing a substrate, forming an active layer, forming a gate insulating layer, forming a dielectric layer having an extending portion and forming a gate electrode. The extending portion of the dielectric layer and the gate electrode are formed during the same step, and they can serve as a mask during a later doping process so that a lightly doped source/drain region and a source/drain region are formed during the same time without forming extra masks. | 2009-04-02 |
| 20090085040 | Liquid crystal display device and fabricating method thereof - A thin film transistor substrate and a fabricating method simplify a process and enlarge a capacitance value of a storage capacitor without any reduction of aperture ratio. A transparent first conductive layer and an opaque second conductive layer of a double-layer structured gate line are formed having a step coverage. A pixel electrode is provided on the gate insulating film within a pixel hole of said pixel area passing through the passivation film to be connected to the thin film transistor. A storage capacitor overlaps with the pixel electrode with having the gate insulating film therebetween and has a lower storage electrode protruded from the first conductive layer. | 2009-04-02 |
| 20090085041 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A method of manufacturing a thin film transistor array panel is provided, which includes: forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate; forming a first passivation layer on the drain and the source electrodes; forming a transparent conductive layer on the first passivation layer; etching the transparent conductive layer using a photoresist as an etch mask to expose the portion of the first passivation layer and to form a pixel electrode connected the drain electrode; ashing the first passivation layer and the photoresist; and removing the photoresist. | 2009-04-02 |
| 20090085042 | Display device having thin film semiconductor device and manufacturing method of thin film semiconductor device - A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm. | 2009-04-02 |
| 20090085043 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor light emitting device, which can improve characteristics of the semiconductor light emitting device such as a forward voltage characteristic and a turn-on voltage characteristic, increase light emission efficiency by lowering an input voltage, and increase reliability of the semiconductor light emitting device by a low-voltage operation, and a method of manufacturing the same. The semiconductor light emitting device includes: an n-type GaN semiconductor layer; an active layer formed on a gallium face of the n-type GaN semiconductor layer; a p-type semiconductor layer formed on the active layer; and an n-type electrode formed on a nitrogen face of the n-type GaN semiconductor layer and including a lanthanum (La)-nickel (Ni) alloy. | 2009-04-02 |
| 20090085044 | SILICON CARBIDE SEMICONDUCTOR SUBSTRATE AND SILICON CARBIDE SEMICONDUCTOR DEVICE BY USING THEREOF - A manufacturing method is provided for a silicon carbide semiconductor substrate adapted for reduced basal plane dislocations in a silicon carbide epitaxial layer. Between a silicon carbide epitaxial layer for device fabrication (i.e., a drift layer) and a base substrate formed of a silicon carbide single-crystal wafer, a highly efficient dislocation conversion layer through which any basal plane dislocations in the silicon carbide single-crystal wafer are converted into threading edge dislocations very efficiently when the dislocations propagate into the layer epitaxially grown is provided by epitaxial growth. Assigning to the dislocation conversion layer a donor concentration lower than that of the drift layer, therefore, allows the above conversion of a larger number of basal plane dislocations than the case where the drift layer exists alone (without the dislocation conversion layer). | 2009-04-02 |
| 20090085045 | METHOD FOR PRODUCING A MATRIX OF INDIVIDUAL ELECTRONIC COMPONENTS AND MATRIX PRODUCED THEREBY - The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by forming trenches in the active layer at least until the substrate emerges. The method comprises steps of depositing a layer of functional material on the active layer, depositing a photosensitive resin on the layer of material in such a way as to fill said trenches and to form a thin film on the upper face of the components, at least partially exposing the resin to radiation while underexposing the portion of resin in the trenches, developing the resin in such a way as to remove the properly exposed portion thereof, removing the functional material layer portion that shows through after the development step, and removing the remaining portion of resin. | 2009-04-02 |
| 20090085046 | METHODS AND SYSTEMS RELATING TO SOLID STATE LIGHT SOURCES FOR USE IN INDUSTRIAL PROCESSES - Methods and systems relating to solid state light sources for use in industrial processes. | 2009-04-02 |
| 20090085047 | Integrated multi-colored LED light source with heatsink and collimator - A LED light source is integrated with a heatsink and a collimator. Four isolated heatsinks form an optical taper in which a single color LED is mounted. The LEDs are arranged to form a reflective light recycling cavity. Up to four different colors can be combined inside the light recycling cavity to form a uniform and homogenous mixing of the colors at the exit aperture of the light recycling cavity and/or the exit aperture of the collimator/heatsink. | 2009-04-02 |
| 20090085048 | AC LIGHT EMITTING DIODE - Disclosed is a light emitting diode (LED) operated by being directly connected to an AC power source. An AC LED according to the present invention comprises a plurality of light emitting cells two-dimensionally arranged on a single substrate; and wires electrically connecting the light emitting cells; wherein the light emitting cells are connected in series by the wires to form a serial array, the single substrate is a non-polar substrate, and the light emitting cells have non-polar GaN-based semiconductor layers grown on the non-polar substrate. | 2009-04-02 |
| 20090085049 | Phosphor down converting element for an LED package and fabrication method - There is provided a phosphor down converting element based on fluoropolymer resin and a method for fabricating the same. There is further provided a method for using said phosphor down converting element to generate white light from a radiation source. The method for fabricating phosphor down converting element includes preparing an appropriate phosphor powder mixture that is capable of absorbing a first band of wavelengths and emitting a second band of wavelengths being greater in length than the first bands, incorporating the phosphor powder mixture into or on a phosphor carrier element comprising a fluoropolymer material, and molding the phosphor down converting elements into useful shapes. Fluoropolymers are the most chemically inert of all plastics, can withstand both extremely high and low temperatures, and show a resistance to weavering and UV degradation, making fluoropolymers optimal for use as a phosphor carrier. | 2009-04-02 |
| 20090085050 | ISLAND SUBMOUNT AND A METHOD THEREOF - An island submount used for carrying at least one light-emitting element having at least one electrical contact. The island submount includes a substrate, at least one island structure having a top surface and an inclined surface, and a conductive layer. The island structure is located on the substrate and corresponds to the electrical contact. The conductive layer is formed on the surface of the island structure and at least covers the top surface, so as to be electrically connected with the electrical contact. The island submount is capable of enhancing the light extraction efficiency of the light-emitting element, and avoids the energy loss due to re-absorption when the light emerging from below the light-emitting element is reflected back to the light-emitting element. | 2009-04-02 |
| 20090085051 | Light emitting diode device - A light emitting diode device includes a light emitting diode chip, a thermal conducting part, two electric conducting parts and two first conducting wires. The light emitting diode chip has a surface and two electrodes disposed on the surface. The thermal conducting part is electrically insulated to the electrodes. The thermal conducting part includes a core bearing the light emitting diode chip, and four outward lead-frames connected to the core. The electric conducting parts are electrically insulated to the thermal conducting part. The first conducting wires have ends electrically connected to the electrodes. | 2009-04-02 |
| 20090085052 | GAN TYPE LIGHT EMITTING DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a GaN type LED device and a method of manufacturing the same. More particularly, there are provided a GaN type LED device including an LED chip; and a submount eutectic-bonded with the LED chip through an adhesive layer, wherein the adhesive layer is configured by soldering a plurality of metallic layers in which a first metallic layer and a second metallic layer are sequentially stacked, and the second metallic layer is formed in a paste form. | 2009-04-02 |
| 20090085053 | Light emitting diode package with large viewing angle - A light emitting diode package with large viewing angle includes a substrate, a LED chip, transparent housing body, and phosphor matrix. The substrate has an upper surface with a first electrode and a second electrode and a lower surface opposite to the upper surface. The LED chip with a positive electrode and an opposite electrode, the LED chip is mounted on the upper surface of the substrate, and connected from the positive electrode to the first electrode of the substrate by wire, and connected from the negative electrode to the second electrode by wire. The transparent housing body is arranged on the upper surface of the substrate, and is formed with a cavity together with the substrate, so that the LED chip is within the cavity. And the phosphor matrix is inserted in the cavity to coat the LED chip, so that the light emitted from the LED chip may turn into white light through the phosphor matrix, and the white light from the LED chip may penetrate the laterals of the transparent housing body. | 2009-04-02 |
| 20090085054 | III-Nitride Semiconductor Light Emitting Device - The present disclosure relates to a III-nitride semiconductor light emitting device, and more particularly, to a III-nitride semiconductor light emitting device which can facilitate current spreading and improve electrostatic discharge characteristic by providing an undoped GaN layer with a thickness over 300 Å in an n-side contact layer. | 2009-04-02 |
| 20090085055 | Method for Growing an Epitaxial Layer - A method for growing an epitaxial layer and devices obtained by that method are disclosed. The method starts by providing a growth substrate having a top surface characterized by a first thermal expansion coefficient (TEC). A mask having a plurality of openings therein is formed on the top surface of the growth substrate. The top surface of the growth substrate is exposed through the openings in the mask. A first epitaxial layer of a first material is grown on the exposed top surface of the openings to form discrete islands of the first material. The discrete islands from adjacent openings in the mask do not contact one another. The first epitaxial layer is characterized by a second TEC. The first and second TECs differ by more than 5 percent. The mask includes a mask material on which the first material will not nucleate. | 2009-04-02 |
| 20090085056 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - According to an aspect of the present invention, there is provided an optical semiconductor device, comprising, a first AlN clad-layer, a first nitride semiconductor guide-layer formed on the first AlN clad-layer, refractive index of the first nitride semiconductor guide-layer being larger than refractive index of the first AlN clad-layer, a nitride semiconductor core-layer formed on the first nitride semiconductor guide-layer, refractive index of the nitride semiconductor core-layer being larger than refractive index of the first AlN clad-layer and smaller than refractive index of the first nitride semiconductor guide-layer, a second nitride semiconductor guide-layer formed on the nitride semiconductor core-layer, refractive index of the second nitride semiconductor guide-layer being larger than refractive index of the nitride semiconductor core-layer, a second AlN clad-layer formed on the second nitride semiconductor guide-layer. | 2009-04-02 |
| 20090085057 | III-Nitride Semiconductor Light Emitting Device - The present disclosure relates to a III-nitride semiconductor light emitting device, and more particularly, to a III-nitride semiconductor light emitting device which can facilitate current spreading and improve electrostatic discharge characteristic by providing an undoped GaN layer with a thickness over 100 Å in an n-side contact layer. | 2009-04-02 |
| 20090085058 | ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE - A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer. | 2009-04-02 |
| 20090085059 | SEMICONDUCTOR DEVICE INCLUDING ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - A SGPMOS transistor includes a base, a P-type diffusion layer, a gate electrode, and a LOCOS oxide film. The base includes at least one of a N-type semiconductor substrate, a P-type semiconductor substrate, and a N-type well. The P-type diffusion layer includes a P-type source and a P-type drain. At least the P-type drain includes a double diffusion structure including first and second P-type drain diffusion layers. The LOCOS oxide film is provided on the first P-type drain diffusion layer and covered by an end of the gate electrode. The first and the second P-type drain diffusion layers satisfy a relation of Y| 2009-04-02 | |
| 20090085060 | SEMICONDUCTOR DEVICE - In a high-voltage semiconductor switching element, in addition to a first emitter region that is necessary for switching operations, a second emitter region, which is electrically connected with the first emitter region through a detection resistor in current detection means and is electrically connected with the current detection means, is formed. No emitter electrode is formed on the second emitter region, while an emitter electrode is formed on a part of a base region that is adjacent to the second emitter region. | 2009-04-02 |
| 20090085061 | HIGH-VOLTAGE SEMICONDUCTOR SWITCHING ELEMENT - In a base region of a first conductivity type, at least one emitter region of a second conductivity type and at least one sense region of the second conductivity type, spaced away from the emitter region, are selectively formed. The emitter region and the sense region are located so as to be aligned in a second direction perpendicular to a first direction going from a collector region of the first conductivity type, which is formed so as to be spaced away from the base region, toward the base region. The width of the sense region, the width of the emitter region, the width of a part of the base region that is adjacent to the sense region, and the width of a part of the base region that is adjacent to the emitter region in the second direction are set in such a manner that a sense ratio varies in a desired manner in accordance with variation in collector current. | 2009-04-02 |
| 20090085062 | METHOD TO INTRODUCE UNIAXIAL STRAIN IN MULTIGATE NANOSCALE TRANSISTORS BY SELF ALIGNED SI TO SIGE CONVERSION PROCESSES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region. | 2009-04-02 |
| 20090085063 | COMPOUND SEMICONDUCTOR DEVICE WITH T-SHAPED GATE ELECTRODE AND ITS MANUFACTURE - A method for manufacturing a compound semiconductor device forms an EB resist layer on first SiN film, performs EB exposure at high dose for recess forming opening and at low dose for eaves removing opening, develops the high dose EB resist pattern to etch the first SiN film, selectively etches the cap layer to form a recess wider than the opening of the first SiN film leaving eaves of SiN, develops the low dose EB resist pattern to form the eaves removing opening, etches the first SiN film to extinguish the eaves, forms second SiN film on the exposed surface, forms a resist pattern having a gate electrode opening on the second SiN film to etch the second SiN film, forms a metal layer to form a gate electrode by lift-off. The SiN film in eaves shape will not be left. | 2009-04-02 |
| 20090085064 | HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a lower band-gap than the first band-gap material. A heterojunction is formed between the first semiconductor substrate and the second semiconductor substrate substantially in a first plane. The semiconductor device further includes, in a cross-section which is perpendicular to the first plane, a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type both of which extend from the second semiconductor substrate at least partially into the first semiconductor substrate. The first and second semiconductor regions are spaced in the first semiconductor substrate from each other in a direction parallel to the first plane by a first distance which is arranged in an area proximate to the heterojunction and which is larger than a second distance which is arranged in an area distal to the heterojunction. | 2009-04-02 |
| 20090085065 | METHOD TO FABRICATE III-N SEMICONDUCTOR DEVICES ON THE N-FACE OF LAYERS WHICH ARE GROWN IN THE III-FACE DIRECTION USING WAFER BONDING AND SUBSTRATE REMOVAL - A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces. | 2009-04-02 |
| 20090085066 | Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure - According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector in the high speed transistor region of the substrate. The method further includes forming a first high energy implant region in the high voltage transistor region of the substrate, where the first high energy implant region extends to a depth greater than a depth of a peak dopant concentration of the buried subcollector, thereby increasing a collector-to-emitter breakdown voltage of the high voltage transistor. The collector-to-emitter breakdown voltage of the high voltage transistor can be greater than approximately 5.0 volts. The high speed bipolar transistor can have a cutoff frequency of greater approximately 200.0 GHz. | 2009-04-02 |
| 20090085067 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD THEREFOR - A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active regions of the gate electrodes, in positions in parallel with and a fixed distance apart from the gate electrodes arranged at both ends in a gate length direction on active regions of the transistors and, when the transistors have plural gate electrodes with different gate widths, extending the projected parts to the outside of the active regions by a necessary length, a gate connecting step of, when gate patterns and contact regions are connected to the gate electrodes of the transistors, connecting the gate electrodes and the dummy gates according to a positional relation between the gate electrodes and the dummy gates, and a wiring step of wiring a metal layer. It is possible to design a semiconductor device having a smaller area than that in the past and with a less design man-hour. | 2009-04-02 |
| 20090085068 | Semiconductor integrated circuit having output buffer circuit - Provided is a semiconductor integrated circuit capable of preventing switching noise due to on/off switching of an output buffer transistor from being transmitted to circuits other then the output buffer transistor via power supply lines, wells, and a substrate. A semiconductor integrated circuit according to the present invention includes: a first power supply line connected to a source electrode of an output buffer transistor provided in a well formed on a semiconductor substrate; and a second power supply line connected to a well tap provided to correspond to the output buffer transistor, the first power supply line and the second power supply line being separately provided in different paths. | 2009-04-02 |
| 20090085069 | NAND-type Flash Array with Reduced Inter-cell Coupling Resistance - In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of the inter-cell coupling region. The diffusion zone includes a shallow implant region and a deep implant region. In one embodiment, the shallow implant region defines shallow source/drain regions for floating gate transistors of the memory cells. The size of the metal silicide insets are controlled to not compromise isolation PN junctions defined by the shallow and deep implant region. In one embodiment, the metal silicide insets include nickel. | 2009-04-02 |
| 20090085070 | Solid-state image pickup device, method of manufacturing solid-state image pickup device, and image pickup device - Disclosed herein is a solid-state image pickup device including, a plurality of light receiving units, a transfer channel, a first transfer electrode, a second transfer electrode, first wiring, and second wiring. | 2009-04-02 |
| 20090085071 | SENSOR DEVICE COMPRISING ELONGATED NANOSTRUCTURES - A sensor device is provided for determining the presence and/or amount of at least one component in a fluid. The sensor device comprises at least one sensor unit, the at least one sensor unit comprising at least one elongated nanostructure and a dielectric material surrounding the at least one elongated nanostructure. The dielectric material is such that it is selectively permeable for one of the at least one component and is capable of sensing the component permeated through the dielectric material. The sensor device according to preferred embodiments shows good sensitivity and good mechanical strength. The present invention furthermore provides a method for manufacturing such a sensor device and a method for determining the presence and/or amount of at least one component in a fluid using such a sensor device. | 2009-04-02 |
| 20090085072 | Biosensor using nanoscale material as transistor channel and method of fabricating the same - Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time. | 2009-04-02 |
| 20090085073 | MOSFET STRUCTURE AND METHOD OF MANUFACTURE - A method of forming a portion ( | 2009-04-02 |
| 20090085074 | TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING FOUR MASKS - In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device. | 2009-04-02 |
| 20090085075 | METHOD OF FABRICATING MOS TRANSISTOR AND MOS TRANSISTOR FABRICATED THEREBY - A method of fabricating a MOS transistor, and a MOS transistor fabricated by the method. The method can include forming a gate pattern on a semiconductor substrate. The gate pattern can be formed by sequentially stacking a gate electrode and a capping layer pattern. The capping layer pattern is formed to have a lower capping layer pattern and an upper capping layer pattern. The lower capping layer pattern is formed to a smaller width than the upper capping layer pattern. | 2009-04-02 |
| 20090085076 | Photo Sensor and a Method for Manufacturing Thereof - According to a method of manufacturing photo sensor, a diode can be formed by one lithography step. In addition, the source/drain is arranged on a gate dielectric layer to avoid the conventional plug structure. Moreover, a diode stack is formed on one of the source/drain to simplify the structure of the photo sensor. | 2009-04-02 |
| 20090085077 | Photo Sensor and a Method for Manufacturing Thereof - A photo sensor has an insulator layer for covering a diode stack, and the insulator layer is made of phtoresist to reduce a side leakage current. | 2009-04-02 |
| 20090085078 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor includes a pixel array including a photodiode, a peripheral region including a logic circuit, and an isolation region formed between the pixel array and the peripheral region and formed under the peripheral region to electrically isolate the pixel array from the peripheral region. | 2009-04-02 |
| 20090085079 | Image Sensor and Method for Manufacturing The Same - An image sensor and method of manufacturing the same are disclosed. A semiconductor substrate can be prepared comprising a photodiode region, a transistor region, and a floating diffusion region. A gate dielectric can be disposed under a surface of the semiconductor substrate in the transistor region. A first dielectric pattern can be provided having a portion above and a portion below the surface of the semiconductor substrate in the photodiode and the floating diffusion regions. A second dielectric can be disposed under the gate dielectric. The second dielectric can extend the depth of the gate dielectric into the semiconductor substrate to space the movement path of photoelectrons from the photodiode region to the floating diffusion region. | 2009-04-02 |
| 20090085080 | Image Sensor and Method for Manufacturing The Same - Disclosed is an image sensor. The image sensor includes a semiconductor substrate including unit pixels, an interlayer dielectric layer including metal interconnections formed on the semiconductor substrate, a plurality of bottom electrodes formed on the interlayer dielectric layer in correspondence with the unit pixels, the plurality of bottom electrodes includes bottom electrodes having at least two different sizes, a photodiode formed on the interlayer dielectric layer including the bottom electrodes, and color filters formed on the photodiode in correspondence with the unit pixels. | 2009-04-02 |
| 20090085081 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device with high response speed and high reliability. In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed. | 2009-04-02 |
| 20090085082 | CONTROLLED INTERMIXING OF HFO2 AND ZRO2 DIELECTRICS ENABLING HIGHER DIELECTRIC CONSTANT AND REDUCED GATE LEAKAGE - Controlled deposition of HfO | 2009-04-02 |
| 20090085083 | Semiconductor memory device and method of forming the same - Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried contact plug that extends in a lower portion of the bit line from one side of the bit line and connected to the buried contact pad. A width of the buried contact plug near a top surface of the buried contact pad may be greater than a width of the buried contact plug adjacent to the bit line. | 2009-04-02 |
| 20090085084 | Integrated Circuit and Methods of Manufacturing the Same - A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned. | 2009-04-02 |
| 20090085085 | DRAM CELL WITH CAPACITOR IN THE METAL LAYER - A DRAM cell includes a substrate, a transistor, and a capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the capacitor is formed in a metal layer. The transistor includes a source region and a drain region formed at the main surface of the substrate. The transistor also includes a control gate placed between the source region and the drain region, and separated from the substrate by a thin control dielectric. The capacitor includes a first electrode layer, a dielectric layer formed on the surface of the first electrode layer, and a second electrode layer formed on the surface of the dielectric layer. The DRAM cell increases the density and simplifies the manufacturing process. A DRAM cell with the capacitor formed in multiple layers is also provided. | 2009-04-02 |
| 20090085086 | CAPACITIVE ELECTRODE HAVING SEMICONDUCTOR LAYERS WITH AN INTERFACE OF SEPARATED GRAIN BOUNDARIES - The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased. | 2009-04-02 |
| 20090085087 | LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY - A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off. | 2009-04-02 |
| 20090085088 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME AS WELL AS DATA PROCESSING SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes low voltage and high voltage transistors over a substrate. The low voltage transistor is configured by at least one unit transistor. The high voltage transistor is configured by a greater number of the unit transistors than the at least one unit transistor that configures the low voltage transistor. Each of the unit transistors may include a vertically extending portion of semiconductor providing a channel region and having a uniform height, a gate insulating film extending along a side surface of the vertically extending portion of semiconductor, a gate electrode separated by the gate insulating film from the vertically extending portion of semiconductor, and upper and lower diffusion regions being respectively disposed near the top and bottom of the vertically extending portion of semiconductor. The greater number of the unit transistors are connected in series to each other and have gate electrodes eclectically connected to each other. | 2009-04-02 |
| 20090085089 | TWO-BIT FLASH MEMORY - A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced. | 2009-04-02 |
| 20090085090 | Non-volatile semiconductor memory device having an erasing gate - A non-volatile semiconductor memory device includes a semiconductor substrate; a floating gate formed above the semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a first silicide film formed on an upper surface of the erasing gate; and a second silicide film formed on an upper surface of the control gate, in which a height of the upper surface of the control gate is flush with/or lower than a height of the upper surface of the erasing gate. With such a device structure, the distance between the upper surface of the erasing gate and the upper surface of the control gate is large, and hence the probability of occurrence of the silicide short between the first silicide film formed on the upper surface of the erasing gate and the second silicide film formed on the upper surface of the control gate may be extremely lowered. Thus, further high speed, operation, miniaturization, and the lower voltage operation of the non-volatile semiconductor memory device having an erasing gate may be achieved. | 2009-04-02 |
| 20090085091 | Non-volatile semiconductor memory device having an erasing gate - A non-volatile semiconductor memory device includes a floating gate formed above a semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a first diffusion layer formed on the semiconductor substrate at a position corresponding to another lateral side of the floating gate and the erasing gate; a plug formed above the first diffusion layer, the plug coupled to the first diffusion layer; and a second diffusion layer formed on the semiconductor substrate at a position adjacent to the control gate. With such a device structure, the first diffusion layer and the plug connected thereto are formed in a self-alignment method, thereby contributing to a size reduction of the memory cells. Thus, further miniaturization of the non-volatile semiconductor memory device having an erasing gate may be achieved. | 2009-04-02 |
| 20090085092 | Non-volatile semiconductor memory device having an erasing gate - A non-volatile semiconductor memory device includes: a floating gate formed above the semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a diffusion layer formed on the semiconductor substrate at a position corresponding to another lateral side of the floating gate and the erasing gate; a plug formed above the diffusion layer, the plug coupled to the diffusion layer; a first silicide film formed on an upper surface of the erasing gate; and a second silicide film formed on an upper surface of the plug, in which a height of the upper surface of the plug is flush with/or lower than a height of the upper surface of the erasing gate. | 2009-04-02 |
| 20090085093 | SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device fabricating method includes forming a nitride layer pattern over a semiconductor substrate, forming a trench by etching the semiconductor substrate using the nitride layer pattern as a mask, forming a first insulation layer over an entire face of the semiconductor substrate, forming a device isolation pattern by polishing the first insulation layer to expose the nitride layer pattern, removing the nitride layer pattern, forming a first polysilicon layer over an entire face of the semiconductor substrate, etching the first polysilicon layer to expose the device isolation pattern and thus forming a floating gate electrode between the device isolation patterns, forming a second insulation layer covering the floating gate electrode, forming a second polysilicon layer over the insulation layer, and patterning the second polysilicon layer and the second insulation layer and thus forming a control gate electrode and a second insulation layer pattern. | 2009-04-02 |
| 20090085094 | Floating gate having multiple charge storing layers, method of fabricating the floating gate, non-volatile memory device using the same, and fabricating method thereof - Provided is a floating gate having multiple charge storing layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storing layers using metal nano-crystals of nano size is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-crystal film which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of metal nano-crystals for trapping charges are deposited. The floating gate is made by self-assembling the metal nano-crystals on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature. | 2009-04-02 |
| 20090085095 | Profile Engineered Thin Film Devices and Structures - The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch. | 2009-04-02 |
| 20090085096 | Nonvolatile Memory Devices and Methods of Forming the Same - Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion. | 2009-04-02 |
| 20090085097 | METHODS OF FORMING NITRIDE STRESSING LAYER FOR REPLACEMENT METAL GATE AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include removing residual dielectric material from a metal gate structure, and then forming a stress relief layer on a top surface and on a sidewall region of the metal gate structure. A stress is introduced into a channel region disposed beneath the metal gate structure. | 2009-04-02 |
| 20090085098 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL MOS TRANSISTORS - A semiconductor device includes: a plurality of vertical MOS transistors sharing a gate electrode ( | 2009-04-02 |
| 20090085099 | TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING THREE MASKS - In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device. | 2009-04-02 |
| 20090085100 | SEMICONDUCTOR DEVICE - A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device. | 2009-04-02 |
| 20090085101 | Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance - A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region. | 2009-04-02 |
| 20090085102 | SEMICONDUCTOR DEVICE HAVING VERTICAL SURROUNDING GATE TRANSISTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars. | 2009-04-02 |
| 20090085103 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and production method is disclosed. In one embodiment, the semiconductor device includes a first electrode and a second electrode, located on surfaces of a semiconductor body, and an insulated gate electrode. The semiconductor body has a contact groove for the first electrode in an intermediate oxide layer. Highly doped zones of a first conduction type are located in edge regions of the source connection zone. Below the highly doped zones of the first conduction type, there are highly doped zones of a body zone with a complementary conduction type. In a central region of the source connection zone, the body zone has a net charge carrier concentration with a complementary conduction type which is lower than the charge carrier concentration in the edge regions of the source connection zone. | 2009-04-02 |
| 20090085104 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first surface and a second surface which is arranged opposite to the first surface. The semiconductor substrate includes a plurality of trench structures extending from the first surface into the semiconductor substrate. The thickness of the semiconductor substrate is then reduced by removing semiconductor material at the second surface to obtain a processed second surface with exposed bottom portions of the trench structures. At least a first mask is formed on the processed second surface in a self-aligned manner with respect to the bottom portions of the trench structures, and doping regions are formed in the semiconductor substrate between the trench structures. | 2009-04-02 |
| 20090085105 | TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING TWO MASKS - A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks. | 2009-04-02 |
| 20090085106 | Semiconductor device and semiconductor device manufacturing method - A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed. | 2009-04-02 |
| 20090085107 | Trench MOSFET with thick bottom oxide tub - A semiconductor power device includes a plurality of trenched gates. The trenched gates include a thin dielectric layer padded sidewalls of the trenched gate and a tub-shaped thick dielectric layer below a bottom of the trenched gates having a width narrower than the trenched gate. In an exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further includes a local deposition of silicon oxide (LOCOS) filling in a tub-shaped trench having a narrower width than the trenched gate. In another exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further comprising a high density plasma (HDP) chemical vapor deposition (CVD) silicon oxide filled in a tub-shaped trench having a narrower width than the trenched gate. | 2009-04-02 |
| 20090085108 | SEMICONDUCTOR DEVICE HAVING CELL TRANSISTOR WITH RECESS CHANNEL STRUCTURE - The present invention provides a semiconductor device comprising: a dual-gate peripheral transistor having a transistor structure of surface channel nMOSFET and a transistor structure of surface channel pMOSFET; and a cell transistor having an nMOSFET structure with a recess channel structure, a gate electrode of the cell transistor having an N-type polysilicon layer which contains of N-type impurities at an approximately constant concentration. | 2009-04-02 |
| 20090085109 | Semiconductor device and method of manufacturing semiconductor device - A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a trench dug from the surface of the semiconductor layer to penetrate the body region; a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode embedded in the trench through the gate insulating film and so formed that the surface thereof is lower by one stage than the surface of the source region; and a peripheral wall film formed on a peripheral edge portion of the surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench. | 2009-04-02 |
| 20090085110 | SEMICONDUCTOR DEVICE EMPLOYING PRECIPITATES FOR INCREASED CHANNEL STRESS - A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target depth, and forming a source region and a drain region in the substrate such that a channel region there between is positioned above the band of precipitates, wherein the desired target depth is such that a desired separation distance is achieved between the channel region and the band of precipitates, and wherein an average lattice constant of the band of precipitates is different from the average lattice constant of the silicon substrate so as to cause a stress in the channel region. | 2009-04-02 |
| 20090085111 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device and a method of manufacturing a semiconductor device. In the semiconductor device, high-concentration n type impurity regions are formed respectively below gate electrodes. By setting a gate length to be smaller than a depth of channel regions, pn junction interfaces formed of adjacent side faces of the n type impurity regions and the channel regions can be substantially vertical to a top surface of a base. With this configuration, even when reduction in size is achieved in a super junction structure, a distance between the channel regions (i.e. a current path below the gate electrode) is not reduced unnecessarily. Accordingly, an increase in resistance can be prevented. In addition, depletion layers uniformly expand in the n type semiconductor regions, and impurity concentration of the regions can be increased consequently. Accordingly, reduction in resistance can be achieved. | 2009-04-02 |
| 20090085112 | LATERAL DIFFUSION METAL-OXIDE-SEMICONDUCTOR STRUCTURE - A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms. | 2009-04-02 |
| 20090085113 | Semiconductor device - A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; an annular deep trench penetrating the semiconductor layer in the depth direction to surround an element forming region; a drain region of a second conductivity type formed in a surface layer portion of the semiconductor layer in the element forming region; a drift region of the second conductivity type formed in the surface layer portion of the semiconductor layer to come into contact with the drain region in the element forming region; a body region of the first conductivity type formed in the surface layer portion of the semiconductor layer at an interval from the drift region in the element forming region; a source region of the second conductivity type formed in a surface layer portion of the body region; and a first high-concentration buried region, formed in the semiconductor layer between a portion opposed to the source region in the depth direction and the deep trench, having a higher impurity concentration than that of the semiconductor layer. | 2009-04-02 |
| 20090085114 | Semiconductor Structure - A semiconductor structure includes a substrate, an undoped GaP insulating layer formed over the substrate, and a semiconductor layer formed over the GaP layer. | 2009-04-02 |
| 20090085115 | TRANSISTOR AND IN-SITU FABRICATION PROCESS - A method of fabricating semiconductor components in-situ and in a continuous integrated sequence includes the steps of providing a single crystal semiconductor substrate, epitaxially growing a first layer of rare earth insulator material on the semiconductor substrate, epitaxially growing a first layer of semiconductor material on the first layer of rare earth insulator material, epitaxially growing a second layer of rare earth insulator material on the first layer of semiconductor material, and epitaxially growing a second layer of semiconductor material on the second layer of rare earth insulator material. The first layer of rare earth insulator material, the first layer of semiconductor material, the second layer of rare earth insulator material, and the second layer of semiconductor material form an in-situ grown structure of overlying layers. The in-situ grown structure is etched to define a semiconductor component and electrical contacts are deposited on the semiconductor component. | 2009-04-02 |
| 20090085116 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device | 2009-04-02 |
| 20090085117 | LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR DEVICE THEREOF - A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning. | 2009-04-02 |
| 20090085118 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first active region formed having a first portion extending laterally and second portion extendedly vertically upward from a central portion of the first portion; a second active region formed spaced from the first active region, the second active region having a third portion extending laterally, fourth and fifth portions extending vertically downwardly at distal end portions of the third portion, and a sixth portion extending vertically downwardly at a central portion of the third portion; a first gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a second gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a third gate formed extending in a direction perpendicular to the first and second gates and overlapping of the fourth and fifth portions of the second active region; and a plurality of contacts spaced apart predetermined distances from the gates. | 2009-04-02 |
| 20090085119 | DOUBLE-GATE TRANSISTOR STRUCTURE EQUIPPED WITH A MULTI-BRANCH CHANNEL - Double gate transistor microelectronic device comprising:
| 2009-04-02 |
| 20090085120 | Method for Reduction of Resist Poisoning in Via-First Trench-Last Dual Damascene Process - Fabrication of interconnects in integrated circuits (ICs) use low-k dielectric materials, nitrogen containing dielectric materials, copper metal lines, dual damascene processing and amplified photoresists to build features smaller than 100 nm. Regions of an IC with low via density are subject to nitrogen diffusion from nitrogen containing dielectric materials into low-k dielectric material, and subsequent interference with forming patterns in amplified photoresists, a phenomenon known as resist poisoning, which results in defective interconnects. Attempts to solve this problem cause lower IC circuit performance or higher fabrication process cost and complexity. This invention comprises a dummy via and a method of placing dummy vias in a manner that reduces resist poisoning without impairing circuit performance or increasing fabrication process cost or complexity. | 2009-04-02 |
| 20090085121 | Condensed Memory Cell Structure Using a FinFET - An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure. | 2009-04-02 |
| 20090085122 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 2009-04-02 |
| 20090085123 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first sidewall formed on a side surface of a first gate electrode, and including a first inner sidewall having an L-shaped cross-section and a first outer sidewall. The second MIS transistor includes a second sidewall formed on a side surface of a second gate electrode, and including a second inner sidewall having an L-shaped cross-section and a second outer sidewall, a trench provided in a region outside the second sidewall in a second active region, and a silicon mixed-crystal layer formed in the trench, for causing first stress in a gate length direction of a channel region in the second active region. A height of an upper end of the second inner sidewall is lower than a height of an upper end of the first inner sidewall. | 2009-04-02 |
| 20090085124 | Semiconductor storage device and manufacturing method of the same - A semiconductor storage device includes: a storage circuit, an access control circuit, a ground voltage supplying region, and a polysilicon portion. The storage circuit stores data. The access control circuit includes a first access transistor and a second access transistor and controls reading and writing of the data. The ground voltage supplying region supplies a ground voltage to the storage circuit and the access control circuit. The polysilicon portion connects a first gate electrode included in the first access transistor and a second gate electrode included in the second access transistor, and is composed of a semiconductor of a second conductive type. The ground voltage supplying region is connected to a ground voltage supplying contact which supplies the ground voltage, and includes: a first portion composed of a semiconductor of the second conductive type, and a second portion composed of a semiconductor of a first conductive type. | 2009-04-02 |
| 20090085125 | MOS transistor and CMOS transistor having strained channel epi layer and methods of fabricating the transistors - Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS transistor may include at least one active region defined by an isolation structure formed in a substrate. At least one channel trench may be formed in a part of the at least one active region. At least one strained channel epi layer may be in the at least one channel trench. At least one gate electrode may be aligned on the at least one strained channel epi layer. Sources/drains may be arranged in the at least one active region along both sides of the at least one strained channel epi layer. | 2009-04-02 |
