| 13th week of 2010 patent applcation highlights part 54 |
| Patent application number | Title | Published |
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| 20100082836 | Content Delivering Method and System for Computer Network - A content delivering method for computer network and system are provided. The present invention classifies nodes participating in content transmission into a transmitting group and a receiving group, and uses the groups to manage the nodes dynamically entering or quitting, and the management includes grouping, monitoring and reflecting update of CDS of group controlling information. Real time management for nodes is achieved through CDS, and the nodes in the transmitting group communicate information according to nodes recorded in the CDS. Multiple nodes in the transmitting group cooperate with each other in transmitting content. Firstly, transmission tasks are assigned to nodes in the transmitting group, and then, nodes in the transmitting group divide assigned content into many blocks and package them and transmit to nodes in the receiving group, and nodes in the receiving group which have received content packages exchange the content packages in the group according to the control data set. Therefore, the content is simultaneously transmitted from a plurality of nodes to other a plurality of nodes, and content transmission speed is improved, compared to the prior art. | 2010-04-01 |
| 20100082837 | METHOD AND APPARATUS FOR COMMUNICATIONS ACCELERATOR ON CIP MOTION NETWORKS - An apparatus for accelerating communications over the Ethernet between a first processor and a second processor where the communications include CIP messages, the apparatus comprising a network accelerator that includes memory locations, the accelerator associated with the first processor and programmed to, when the second processor transmits a data packet to the first processor over the Ethernet, intercept the data packet at a first processor end of the Ethernet, extract a CIP message from the data packet, parse the CIP message to generate received data, store the received data in the memory locations and provide a signal to the first processor indicating that data for the first processor in stored in the memory locations. | 2010-04-01 |
| 20100082838 | ISP-FRIENDLY RATE ALLOCATION FOR P2P APPLICATIONS - An ISP-friendly rate allocation system and method that reduces network traffic across ISP boundaries in a peer-to-peer (P2P) network, Embodiments of the system and method continuously solve a global optimization problem and dictate accordingly how much bandwidth is allocated on each connection. Embodiments of the system and method minimize load on a server in communication with the P2P network, minimize ISP-unfriendly traffic while keeping the minimum server load unaffected, and maximize peer prefetching. Two different techniques are used to compute rate allocation, including a utility function optimization technique and a minimum cost flow formulation technique. The utility function optimization technique constructs a utility function and optimizes that utility function. The minimum cost flow formulation technique generates a minimum cost flow formulation using a bipartite graph have a vertices set and an edges set. A distributed minimum cost flow formulation is solved using Lagrangian multipliers. | 2010-04-01 |
| 20100082839 | SMART LOAD BALANCING FOR CALL CENTER APPLICATIONS - Methods, devices, and systems for smart load balancing are provided. SIP Requests destined for a particular AOR are delivered to one of several registered contact addresses according to associated availability score stored in routing element's contact resolution table. The availability score is periodically updated by the contact entity itself using the SIP PUBLISH mechanism to push the score to the routing element. | 2010-04-01 |
| 20100082840 | USING LINK SEND AND RECEIVE INFORMATION TO SELECT ONE OF MULTIPLE LINKS TO USE TO TRANSFER DATA FOR SEND AND RECEIVE OPERATIONS - Provided are a method, system, and article of manufacture for using link send and receive information to select one of multiple links to use to transfer data for send and receive operations. Link information for a plurality of links to at least one target node indicates for each link a send throughput for sending data, a receive throughput for received data, a state of the link indicating whether the link is online, offline or degraded. A send operation is processed to transfer data to a receiving node comprising one of the target nodes. A determination is made of the states of the links to the receiving node in response to the send operation. The send throughput of the links having the online state is processed to select one of the links to the receiving node in response to determining that more than one of the links has the online state. The data of the send operation is sent using the selected link to the receiving node. A retrieve operation to access data from a sending node comprising one of the target nodes is processed. A determination is made of the state of the links to the sending node in response to the retrieve operation. The receive throughput is processed to select one of the links having the online state to the sending node in response to determining that more than one of the links has the online state. The data of the receive operation is received using the selected link to the sending node. | 2010-04-01 |
| 20100082841 | UPDATING MACHINES WHILE DISCONNECTED FROM AN UPDATE SOURCE - Disclosed are exemplary embodiments for updating a networked machine having at least a dormant state and an active state. In various embodiments, when the machine it is a dormant state, it listens to a network for candidate updates, that is, updates that may be applicable to the machine. In some embodiments, determining the candidate update is an applicable update for the machine may be based at least in part on a variety of reasons, including testing if it has already been applied, does not actually update some aspect of the machine, conflicts with an existing configuration of the machine, conflicts with a policy of the machine, etc. The machine may cache some or all of the candidate updates or applicable updates, where a variety of rationales or policies may be used to control update retention. When the machine enters an active state, such as a power on or non-sleep mode, or other active state, the machine may validate integrity of an applicable update if not done while the machine was dormant, and optionally choose to install it. | 2010-04-01 |
| 20100082842 | COMPUTER PROGRAM PRODUCT, SYSTEM AND METHOD FOR FIELD MANAGEMENT AND MOBILE INSPECTION - Disclosed herein is a computer program product, system and method to provide field management and mobile inspection via an online platform web-application for use by construction and capital projects management and property management firms and their subcontractors/vendors. More particularly, in an aspect, use of an automated field management process includes a terminal-based solution (i.e., a Tablet-PC) for field-based personnel that synchronizes with a server for office personnel and dynamically generates field management documents, reports and other information. In further aspects, field management resources may be generated that are context-specific. A visual punch list may be generated using area plans and special codes to facilitate automated field management processes. Rules may be pre-established by users to expedite field management processes. Data records may be synchronized among multiple mobile terminals and at least one server. | 2010-04-01 |
| 20100082843 | Method and System for Implementing Automatic Installation of Key Device - The invention discloses a method and system for implementing automatic installation of a key device, and relates to the field of smart card. The method includes steps of: establishing, by the key device, a connection with a computer; declaring to the computer that the key device itself is a compound device containing a USB keyboard device; sending a predefined first keyboard message sequence to the computer, wherein the first keyboard message sequence is used for starting an operation environment of the computer; converting, after the operation environment is started, a pre-stored script instruction for running an installation program into a second keyboard message sequence, and sending the second keyboard message sequence to the computer; sending a predefined third keyboard message sequence to the computer, wherein the third keyboard message sequence is used for running the installation program. The system includes a key device and a computer. According to the invention, by way of interaction between the key device and the computer, the technical problem that the key device can not be installed automatically in the case that the autorun function of the Windows system is shielded is solved, thereby facilitating automatic installation of the key device. | 2010-04-01 |
| 20100082844 | FIELD DEVICE CONTROLLER ADAPTER - A controller adapter including a controller interface configured to interface with a controller for a legacy field device of an electrical power distribution system, wherein the controller communicates based on a first protocol, a network interface configured to interface with a network common to a plurality of assets of the electrical power distribution system, wherein the network interface communicates based on a second protocol, a mapper that maps information received from the legacy field device controller about the legacy device that to the second protocol, and storage that stores at least one logic function, wherein at least one input and/or output of the logic function is connected to the mapped information. | 2010-04-01 |
| 20100082845 | DISPLAY APPARATUS OPERATED IN MULTIPLE MODES AND MODE CHANGING METHOD THEREOF - A display apparatus operable in plural modes and a mode changing method thereof are disclosed. The display apparatus includes a storage unit which stores information about a final mode, and a controller which changes a mode of the display apparatus to the final mode and displays a corresponding screen if the display apparatus is connected to a host device. | 2010-04-01 |
| 20100082846 | USB DEVICE AND METHOD FOR CONNECTING THE USB DEVICE WITH USB HOST - A method for connecting a universal serial bus (USB) device to a USB host is disclosed. The method for connecting the USB device to a USB host includes detecting a connection to the USB host; controlling the USB host not to recognize the connection of the USB device; selecting one of USB modes provided by the USB device; and controlling the connection so as to allow the USB host to recognize the selected USB mode. | 2010-04-01 |
| 20100082847 | PERIPHERAL DEVICE MANAGEMENT SYSTEM - The peripheral device management system includes a server, a peripheral device, a data processing device. The data processing device includes an attempting unit, a confirming unit, a notifying unit, a first setting unit, and a second setting unit. The attempting unit attempts to acquire, from the peripheral device, firmware data. The confirming unit confirms, to the server, whether a newer firmware than the firmware installed on the peripheral device is available for downloading from the server. The notifying unit notifies that the newer firmware is available for downloading from the server. The first setting unit sets a first confirmation time as the confirmation time if a result of the attempting unit satisfies a prescribed condition. The second setting unit sets a second confirmation time that precedes the first confirmation time as the confirmation time if the result of the attempting unit does not satisfy the prescribed condition. | 2010-04-01 |
| 20100082848 | INCREASING AVAILABLE FIFO SPACE TO PREVENT MESSAGING QUEUE DEADLOCKS IN A DMA ENVIRONMENT - Embodiments of the invention may be used to manage message queues in a parallel computing environment to prevent message queue deadlock. A direct memory access controller of a compute node may determine when a messaging queue is full. In response, the DMA may generate an interrupt. An interrupt handler may stop the DMA and swap all descriptors from the full messaging queue into a larger queue (or enlarge the original queue). The interrupt handler then restarts the DMA. Alternatively, the interrupt handler stops the DMA, allocates a memory block to hold queue data, and then moves descriptors from the full messaging queue into the allocated memory block. The interrupt handler then restarts the DMA. During a normal messaging advance cycle, a messaging manager attempts to inject the descriptors in the memory block into other messaging queues until the descriptors have all been processed. | 2010-04-01 |
| 20100082849 | Data filtering using central DMA mechanism - A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device. | 2010-04-01 |
| 20100082850 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING SAME - Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected. | 2010-04-01 |
| 20100082851 | BALANCING USAGE OF HARDWARE DEVICES AMONG CLIENTS - Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time. | 2010-04-01 |
| 20100082852 | Querying a device for information - In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed. | 2010-04-01 |
| 20100082853 | Implementing System to System Communication in a Switchless Non-IB Compliant Environment Using Infiniband Multicast Facilities - A method and apparatus are provided for implementing system to system communication in a switchless non-InfiniBand (IB) compliant environment. IB architected multicast facilities are used to communicate between HCAs in a loop or string topology. Multiple HCAs in the network subscribe to a predetermined multicast address. Multicast messages sent by one HCA destined to the pre-determined multicast address are received by other HCAs in the network. Intermediate TCA hardware, per IB architected multicast support, forward the multicast messages on via hardware facilities, which do not require invocation of software facilities thereby providing performance efficiencies. The messages flow until picked up by an HCA on the network. Architected higher level IB connections, such as IB supported Reliable Connections (RCs) are established using the multicast message flow, eliminating the need for an IB Subnet Manager (SM). | 2010-04-01 |
| 20100082854 | Real-Time/Batch Interface Arbiter - One embodiment of an interface request arbitration system comprises a queue for holding individual processing requests from at least one application process and an interface request arbiter which dynamically chooses to pass a request at the head of the queue to either a real-time interface of an external system that handles the request or a batch interface to the external system. | 2010-04-01 |
| 20100082855 | ASSOCIATING PROCESS PRIORITY WITH I/O QUEUING - Input/output (I/O) requests generated by processes are typically stored in I/O queues. Because the queued I/O requests may not be associated with the processes that generated them, changing a process' priority may not affect the priority of the I/O requests generated by the process. Therefore, after the process' priority has been increased, it may be forced to wait for an I/O handler to service its I/O request, which may be stuck behind an I/O request generated by a lower priority process. Functionality can be implemented to associate the processes' priorities with the I/O requests generated by the processes. Also, reordering the queued I/O requests to reflect changes in the processes' priorities can ensure that the I/O requests from high priority processes are serviced before the I/O requests from low priority processes. This can ensure efficient processing and lower wait times for high priority processes. | 2010-04-01 |
| 20100082856 | Managing Command Request Time-outs In QOS Priority Queues - In one embodiment a storage controller comprises a processor, a computer readable storage medium coupled to the processor, and logic instructions in the memory module which, when executed by the processor, configure the processor to receive, in a quality of service module, a first command request from a host initiator port, associate a time-out threshold with the first command request, determine, in the quality of service module, whether an available priority queue can release the first command request for execution by a scheduling module within the time-out threshold; and in response to a determination that an available priority queue can release the first command request for execution within the time-out threshold, assign the first command request to the available priority queue. | 2010-04-01 |
| 20100082857 | SOLID STATE STORAGE DEVICE CONTROLLER WITH PARALLEL OPERATION MODE - Solid state storage devices and methods for operation of solid state storage devices are disclosed. In one such method, a master memory controller is comprised of a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller. | 2010-04-01 |
| 20100082858 | METHOD TO IMPROVE OPERATING PERFORMANCE OF A COMPUTING DEVICE - The system includes a microprocessor, a first buffer, a second buffer, and a control circuit. The control circuit includes a memory and an interface. The control circuit is configured to determine a first buffer value and compare the first buffer value to a predetermined value to obtain a result. The control circuit is further configured to control a read issue rate of the first buffer based on the result. The memory is configured to store at least one of the first buffer value, the result, the read issue rate, and the TAG. | 2010-04-01 |
| 20100082859 | DISPLAYPORT I2C SPEED CONTROL - Circuits, methods, and apparatus that allow a DisplayPort compatible host device to control data transactions over an I | 2010-04-01 |
| 20100082860 | SYSTEM AND METHOD FOR UPDATING THE STATUS OF AN ASYNCHRONOUS, IDEMPOTENT MESSAGE CHANNEL - The present invention provides systems and methods for an abstraction layer for an asynchronous, idempotent message channel useful for performing status updates between communicating processes via a protocol that reduces overhead. The system comprises a sink endpoint that is operative to send a status message, a data path that is operative to transmit the status message over a message channel, a source endpoint that is operative to receive the status message sent by the sink endpoint over the data path, and an abstraction layer that is operative to provide an interface between the sink endpoint and the source endpoint over the message channel, relaying the status message from the sink endpoint to the source endpoint according to an optimized algorithm. | 2010-04-01 |
| 20100082861 | MEMORY SYSTEM AND METHOD - In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component. | 2010-04-01 |
| 20100082862 | UNIVERSAL SERIAL BUS ENDPOINT CONTEXT CACHING - According to some embodiments, an apparatus may be capable of exchanging information with t potential universal serial bus endpoints, where t is an integer greater than 1. Moreover, x endpoint state machines may be established, where x is an integer greater than 1 and less than t. A first endpoint state machine may then be assigned to a first potential endpoint having a pending work item. Before the apparatus has completed the pending work item associated with the first potential endpoint, the first endpoint state machine may be flushed, and the first endpoint state machine may be re-assigned to a second potential endpoint. | 2010-04-01 |
| 20100082863 | I/O AND MEMORY BUS SYSTEM FOR DFPs AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES - A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading). | 2010-04-01 |
| 20100082864 | SELECTION CIRCUIT AND PACKET PROCESSING APPARATUS - An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit. | 2010-04-01 |
| 20100082865 | Access Grants - Provided are, among other things, systems, methods, apparatuses and techniques for storing access grants. In one implementation, a blinding factor and access information for accessing a restricted object are obtained; blinded access information is generated for the restricted object based on the access information and the blinding factor; and an anchor node is stored into a data store, with the anchor node being accessible by submission of an identifier, the anchor node at least one of containing or referring to sufficient information to obtain access to the blinding factor and the blinded access information, and the identifier for the anchor node being independent of the blinding factor. | 2010-04-01 |
| 20100082866 | Providing a set aside mechanism for posted interrupt transactions - In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so routing it to a first queue, and otherwise routing it to a second queue. Other embodiments are described and claimed. | 2010-04-01 |
| 20100082867 | Multi-thread processor and its interrupt processing method - A first exemplary aspect of an embodiment of the present invention is a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, and an interrupt controller that determines whether or not an input interrupt request signal is associated with one or more than one of the plurality of hardware threads, and when the input interrupt request signal is associated, assigns the interrupt request to an associated hardware thread. | 2010-04-01 |
| 20100082868 | METHODS AND SYSTEMS FOR A PORTABLE, INTERACTIVE DISPLAY DEVICE FOR USE WITH A COMPUTER - A portable, interactive display device is disclosed. The device presents to a user the graphical interface of a host computer. The host is separate from the display device and sits in a fixed location. The invention allows a user to carry with him the user interface capability of the host, limited only by the capabilities of a wireless communications channel to the host. The host provides processing, storage, and access to its own peripheral devices. The display device need only provide the amount of processing necessary to communicate with the host, to run the client side of the hosting software, and to provide security functions. The host provides a docking station that accommodates the display device. When in the docking station, the display device continues to operate but communicates with the host through the docking station rather than through the wireless channel. This allows for a higher quality video connection. | 2010-04-01 |
| 20100082869 | STACKABLE I/O MODULES APPEARING AS STANDARD USB MASS STORAGE DEVICES - An industrial automation device is provided that includes a universal serial bus interface and an I/O module coupled to the industrial automation device via the universal serial bus interface, wherein the I/O module is configured to connect as one of a plurality of universal serial bus device classes. An I/O module is provided that includes a plurality of inputs, a plurality of outputs, a universal serial bus connection configured to couple to the industrial automation device, a memory configured to store one of a plurality of universal serial bus device class information. A method for connecting the I/O module to the industrial automation device is also provided. | 2010-04-01 |
| 20100082870 | Tape-form communication sheet and information processing device using the tape-form - It is an object to provide a transmission system that is more suitable for transmission of a large volume of data than a cable or an optical fiber is and capable of coupling a transmission path and an electronic device easily without using a connector. A tape-form communication sheet is configured by a sheet body, plural coupling nodes regularly arranged in line and fitted in the sheet body, and a signal transmission wiring, wherein an interface of a computer having the interface similar to this coupling node is connected to the coupling node of the tape-form communication sheet for transmitting a signal. The coupling nodes are configured by an arrayed antenna and a communication circuit unit including a signal In/Out unit, a memory, a signal reception/output unit, and a CPU connected to the signal In/Out unit, the memory, and the signal reception/output unit, wherein the signal transmission wiring is connected to the signal In/Out unit of the respective coupling nodes. | 2010-04-01 |
| 20100082871 | Distributed Command and Address Bus Architecture - Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions. | 2010-04-01 |
| 20100082872 | METHOD AND APPARATUS TO OBTAIN CODE DATA FOR USB DEVICE - A method and apparatus are provided that include creating an image of a page descriptor at a universal serial bus (USB) device, transferring the image of the page descriptor to a main memory, modifying a schedule list in a main memory based on the transferred image, identifying an active transaction in the modified schedule list, and providing code data to the USB device from the main memory based on the identified active transaction. | 2010-04-01 |
| 20100082873 | Ship Rudder Control (Autopilot) with a CAN Bus - Ship rudder control, so-called autopilot, includes a multiplicity of components connected with a bus interface to a CAN bus and via this also to each other. A further bus interface on each component of the control system is coupled to a separate, second bus, with the components being provided with unambiguous addresses and further information being assigned that mark the components as monitorable or non-monitorable. A device for emitting telegrams of component addresses and monitorability. A first comparator on all monitorable components start or switch off their own property as a monitoring component using the addresses of other components in received telegrams by comparison, and a second comparator on all monitorable components that use the number of received telegrams by comparison with the number of telegrams received on the other channel causing a change of the channel to that with the higher number of received telegrams under certain circumstances. | 2010-04-01 |
| 20100082874 | COMPUTER SYSTEM AND METHOD FOR SHARING PCI DEVICES THEREOF - In order to provide an inexpensive way to share an I/O device loaded in an I/O drawer among a plurality of blades, in a server system including a plurality of servers, a PCI device, and a manager for initializing a PCI switch, the PCI device has a plurality of virtual functions (VFs). The PCI switch, which has VF allocation information which indicates association between the servers and the VFs, is configured to: receive a transaction from one of the servers or from the PCI device; when the received transaction is a transaction sent from the one of the servers, remove a server identifier with which a sender server is identified and transfer the received transaction to the PCI device; and when the received transaction is a transaction sent from the PCI device, attach a server identifier that is determined based on the VF allocation information. | 2010-04-01 |
| 20100082875 | TRANSFER DEVICE - A transfer device includes: a first input port operatively connected to a first apparatus; a second input port operatively connected to a second apparatus which is to run in parallel to the first apparatus; an output port operatively connected to a third apparatus; and a controller for controlling a data synchronization in accordance with a process including: receiving first and second data packets from the first and second apparatus, respectively, each of the first and second data packets including a check code; comparing one of the check codes in the first and second data packet with the other; and transferring at least the data of one of the first and second data packets upon determining coincidence of the check codes of the first and second data packets to the third apparatus via the output port. | 2010-04-01 |
| 20100082876 | System and method of use of fast updatable counters using dynamic random access memories - A system and method for enabling one or more memories to maintain, update, and provide counter values. In a first version a dynamic random access memory, or DRAM, is bi-directionally communicatively coupled with a processor. The DRAM is divided into a plurality of banks. In the first version a set of subcounters is established, wherein each subcounter element is separately and singly located within a different DRAM bank. The value of a counter can be derived by reading and processing, e.g., adding, all of the values of each of an assigned set of subcounter subvalues maintained within the plurality of banks. Conversely, a counter value may be updated by updating a single assigned subcounter of a single bank. The first method allows a hosting computer to select a subcounter having a shortest access time, where the subcounter is an element of a set of subcounters assigned to maintain a given counter value. | 2010-04-01 |
| 20100082877 | MEMORY ACCESS CONTROL APPARATUS - A memory access control apparatus includes an arbiter and a sub-arbiter receiving and arbitrating access requests from a plurality of memory masters; a memory controller; and a memory having a plurality of banks. When a bank of the memory used by an access request allowed by the arbiter and currently being executed and a bank of the memory to be accessed by an access request by the sub-arbiter are different and the type of access request allowed by the arbiter and currently being executed and the type of memory access to be performed by the sub-arbiter are identical, then it is decided that access efficiency will not decline, memory access by the arbiter is suspended and memory access by the sub-arbiter is allowed to squeeze in (FIG. | 2010-04-01 |
| 20100082878 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND DATA WRITING METHOD - Used is a nonvolatile memory such as a multi-level NAND flash memory having memory cells for holding data of a plurality of pages. When the data is to be written in the nonvolatile memory | 2010-04-01 |
| 20100082879 | PRIORITY COMMAND QUEUES FOR LOW LATENCY SOLID STATE DRIVES - A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device. | 2010-04-01 |
| 20100082880 | PRE-CODE DEVICE, AND PRE-CODE SYSTEM AND PRE-CODING METHOD THEREROF - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 2010-04-01 |
| 20100082881 | SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device. | 2010-04-01 |
| 20100082882 | SEMICONDUCTOR DISK DEVICES AND RELATED METHODS OF RANDOMLY ACCESSING DATA - A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register. | 2010-04-01 |
| 20100082883 | Hybrid density memory system and control method thereof - A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table. | 2010-04-01 |
| 20100082884 | MEMORY CELL OPERATION - The present disclosure includes memory devices and systems having memory cells, as well as methods for operating the memory cells. One or more methods for operating memory cells includes determining age information for a portion of the memory cells and communicating a command set for the portion of the memory cells, the command set including the age information. | 2010-04-01 |
| 20100082885 | METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES - Bits are stored by attempting to set parameter value(s) of (a) cell(s) to represent some of the bits. In accordance with the attempt, an adaptive mapping of the bits to value ranges is provided and the value(s) is/are adjusted accordingly as needed. Or, to store (a) bit(s) in (a) cell(s), a default mapping of the bit(s) to a predetermined set of value ranges is provided and an attempt is made to set the cell value(s) accordingly. If, for one of the cells, the attempt sets the value such that the desired range is inaccessible, an adaptive mapping is provided such that the desired range is accessible. Or, to store (a) bit(s) in (a) cell(s), several mappings of the bit(s) to a predetermined set of ranges is provided. Responsive to an attempt to set the cell value(s) according to one of the mappings, the mapping to actually use is selected. | 2010-04-01 |
| 20100082886 | VARIABLE SPACE PAGE MAPPING METHOD AND APPARATUS FOR FLASH MEMORY DEVICE - Disclosed is a method and apparatus embodying a flash translation layer (FTL) in a storage device including a flash memory. The FTL may classify a block into a sequential group and a fusion group based on a locality of a write request. The FTL may store data in blocks of the fusion group by using a page mapping scheme, and sequentially store data by using a block mapping scheme. The FTL may improve efficiency of garbage collection operation that is performed by using limited redundant blocks and also may increase efficiency of a non-sequential reference operation. | 2010-04-01 |
| 20100082887 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - The memory controller forms temporary virtual blocks each composed of a plurality of physical blocks, whose physical addresses are the same value, each of which is included in each of flash memories, extracts temporary virtual block to which at least one defective block belongs from the temporary virtual blocks, generates a second temporary virtual block to which a defective block does not belong by replacing a defective block belonging to one temporary virtual block with a normal block belonging to another temporary virtual block among temporary virtual blocks extracted, and allocates temporary virtual blocks not extracted and second temporary virtual blocks generated to available virtual blocks. | 2010-04-01 |
| 20100082888 | Memory controller, flash memory system with memory controller, and method of controlling flash memory - In a case where at least one of physical blocks composing the virtual block becomes a defective block, use of the virtual block to which the defective block belongs is forbidden and the virtual block of which use is forbidden is managed as a defective virtual block. Replacing the defective block with a normal block is performed among the defective virtual blocks so as to generate the virtual block to which the defective block does not belong. Then use of the virtual block generated is allowed. | 2010-04-01 |
| 20100082889 | Memory controller, flash memory system with memory controller, and method of controlling flash memory - First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data. | 2010-04-01 |
| 20100082890 | Method of managing a solid state drive, associated systems and implementations - A solid state drive may include one or more memory cell arrays divided into a plurality of blocks. A first portion of the blocks may be designated for storing user data and a second portion of the blocks may be designated as reserved blocks for replacing defective blocks in the first portion. In one embodiment, the method includes reformatting, by a memory controller, the solid state drive to convert one or more blocks in the first portion into reserved blocks. | 2010-04-01 |
| 20100082891 | APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES - A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface. | 2010-04-01 |
| 20100082892 | Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input— output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 2010-04-01 |
| 20100082893 | Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 2010-04-01 |
| 20100082894 | COMMUNICATION SYSTEM AND METHOS BETWEEN PROCESSORS - A system communicating processors is provided. The system comprises a first processor, a second processor, a SRAM and a DMA unit. The DMA unit further comprises a detection unit to determine whether the SRAM is accessed by the second processor, wherein when the SRAM is not accessed by the second processor, the access control of the SRAM is transferred to the DMA unit, and data communication between the first processor and the second processor is transmitted by the DMA unit. | 2010-04-01 |
| 20100082895 | MULTI-LEVEL CONTENT ADDRESSABLE MEMORY - A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM. | 2010-04-01 |
| 20100082896 | Storage system for controlling assignment of storage area to virtual volume storing specific pattern data - A storage system comprises a storage medium including a plurality of physical storage areas. The storage system controls a host computer to recognize a logical volume having a plurality of virtual storage areas, reads the data from the physical storage area assigned to the virtual storage area of the logical volume, determines whether or not the read data includes only the specific pattern data, and cancels the assignment of the physical storage area to the virtual storage area if the read data includes only the specific pattern data. | 2010-04-01 |
| 20100082897 | Load sharing method and system for computer system - The invention is directed to a load sharing method in a computer system including a first storage subsystem, a host computer, and a management computer. In the computer system, the first storage subsystem creates a plurality of first logical units from a storage area of a disk drive group, and the host computer creates a logical storage area configured by a plurality of virtual logical units respectively corresponding to the first logical units. A communications path is set between the host computer and each of the first logical units configuring the logical storage area. The load sharing method includes the steps of: monitoring, by the first storage subsystem, a load of its own; and changing, by the first storage subsystem, the communications paths between the host computer and the first logical units based on the monitoring result of the load. With such a configuration, provided is a computer system high in extensibility not deteriorating the performance at the limit of the system after load sharing among the storage subsystems. | 2010-04-01 |
| 20100082898 | Methods to securely bind an encryption key to a storage device - Embodiments of methods to securely bind a disk cache encryption key to a cache device are generally described herein. Other embodiments may be described and claimed. | 2010-04-01 |
| 20100082899 | MANAGEMENT COMPUTER AND OPERATING METHOD THEREOF - Implementing migration of a computer or data in consideration of the performance of an entire computer system is disclosed. A management computer is coupled to a computer | 2010-04-01 |
| 20100082900 | MANAGEMENT DEVICE FOR STORAGE DEVICE - The present invention provides effective use of a storage resource in a system where a storage area of a logical volume is dynamically extended and reduced. In an information processing system including a management device communicably connected to a storage device that can dynamically change a storage capacity of a virtual volume allocated to a host computer, when a used amount of a certain storage pool exceeds a threshold set in the storage pool, the management device sends to the storage device, an instruction to migrate a predetermined number of virtual volumes, sequentially selected in ascending order of capacity increasing rate, so that another storage pool different from the certain storage pool may be used as a creation source. At this time, as a migration destination, the management device uses, the storage pool having, for example, an attribute of the storage resource identical to that of the certain storage device. | 2010-04-01 |
| 20100082901 | STORAGE SYSTEM WITH LU-SETTING FUNCTION - In a storage system, an operator makes an input only of minimum-required information, and when an LU setting command including the information is accepted, in response to the LU setting command, any internal process is executed using configuration management information about an LU and a plurality of physical storage devices. After completion of the internal process, the processing result is forwarded back. Herein, the configuration management information is about the LU and the physical storage devices, including information about a free area and a free capacity in a storage space of each of the physical storage devices, and information about the LU based on the storage spaces. The free area is an address area occupied by the free space not used as the LU. The free capacity is the capacity of the free space. Accordingly, an LU setting technology with a reduced level of the operator's load of work can be favorably provided. | 2010-04-01 |
| 20100082902 | SECURITY FOR LOGICAL UNIT IN STORAGE SUBSYSTEM - Mapping tables are for stipulating information for primarily identifying computers, information for identifying a group of the computers and a logical unit number permitting access from the host computer inside storage subsystem, in accordance with arbitrary operation method by a user, and for giving them to host computer. The invention uses management table inside the storage subsystem and allocates logical units inside the storage subsystem to a host computer group arbitrarily grouped by a user in accordance with the desired form of operation of the user, can decide access approval/rejection to the logical unit inside the storage subsystem in the group unit and at the same time, can provide the security function capable of setting interface of connection in the group unit under single port of storage subsystem without changing existing processing, limitation and other functions of computer. | 2010-04-01 |
| 20100082903 | NON-VOLATILE SEMICONDUCTOR MEMORY DRIVE, INFORMATION PROCESSING APPARATUS AND DATA ACCESS CONTROL METHOD OF THE NON-VOLATILE SEMICONDUCTOR MEMORY DRIVE - According to one embodiment, a non-volatile semiconductor memory drive stores an address table in a non-volatile semiconductor memory in predetermined units that are storage units of data in the non-volatile semiconductor memory, manages a second address table associating a logical address with a physical address with respect to each part of the address table stored in the non-volatile semiconductor memory, and temporarily stores each part of the address table which has been read in the predetermined units from the non-volatile semiconductor memory in the cache memory based on the second address table. | 2010-04-01 |
| 20100082904 | Apparatus and method to harden computer system - In some embodiments, a non-volatile cache memory may include a segmented non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the segmented non-volatile cache memory, wherein the controller is configured to control utilization of the segmented non-volatile cache memory. The segmented non-volatile cache memory may include a file cache segment, the file cache segment to store complete files in accordance with a file cache policy, and a block cache segment, the block cache segment to store one or more blocks of one or more files in accordance with a block cache policy, wherein the block cache policy is different from the file cache policy. The controller may be configured to utilize the file cache segment in accordance with information related to the block cache segment and to utilize the block cache segment in accordance with information related to the file cache segment. Other embodiments are disclosed and claimed. | 2010-04-01 |
| 20100082905 | DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS - Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed. | 2010-04-01 |
| 20100082906 | Apparatus and method for low touch cache management - In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed. | 2010-04-01 |
| 20100082907 | System For And Method Of Data Cache Managment - The present invention provides a system for and a method of data cache management. In accordance with an embodiment, of the present invention, a method of cache management is provided. A request for access to data is received. A sample value is assigned to the request, the sample value being randomly selected according to a probability distribution. The sample value is compared to another value. The data is selectively stored in the cache based on results of the comparison. | 2010-04-01 |
| 20100082908 | Access control and computer system - An access control method for a computer system in which a plurality of clusters share a storage unit, includes predefining an access instruction with exclusive right in addition to an access instruction that is issued with respect to the storage unit from the plurality of clusters, and monitoring, in the storage unit, based on the access instruction with exclusive right transferred from an arbitrary cluster, an access state of an other cluster and executing access instructions with exclusion if a region accessed by an access instruction from the other cluster overlaps a region accessed by the access instruction with exclusive right. | 2010-04-01 |
| 20100082909 | MEMORY SYSTEM AND CONTROL METHOD - A control method for a memory system includes a plurality of processing apparatuses each having a comparison data holding area and a replacement data holding area, and a plurality of storage units each having a readout data holding area rewritably holding readout data and a memory unit shared by the plurality of processing apparatuses. The control method includes issuing an exclusive control instruction to exclusively access to one of the memory units from one of the processing apparatuses, sending comparison data to one of the plurality of storage units from the comparison data holding area of the one of the processing apparatuses when the exclusive control instruction is executed, and comparing the comparison data sent from the one of the processing apparatuses with the readout data in the storage unit. | 2010-04-01 |
| 20100082910 | SKIP BASED CONTROL LOGIC FOR FIRST IN FIRST OUT BUFFER - A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, and a read pointer for pointing to a read address of the storage for a read operation. Further, the FIFO buffer system includes a control logic for incrementing the read pointer based on a skip parameter of a skip register. The skip parameter is used to characterize a validity of the data for the read operation. | 2010-04-01 |
| 20100082911 | LOW POWER TERMINATION FOR MEMORY MODULES - An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE. | 2010-04-01 |
| 20100082912 | SYSTEMS AND METHODS FOR RESOURCE ACCESS - Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged. | 2010-04-01 |
| 20100082913 | STORAGE DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICE - A storage device includes: a printed circuit board; a semiconductor memory package mounted on the printed circuit board via solder joints, the semiconductor memory package incorporating semiconductor memories; a sensor configured to measure a physical quantity relating to a state of the storage device; a database including a damage estimation model base to be used for estimating damage of the solder joints from the physical quantity measured by the sensor; a damage estimating module configured to calculate a damage estimation value of the solder joints from the physical quantity using the damage estimation model base; and a controller configured to control writing, reading, and erasure of electronic data to or from the semiconductor memories based on the damage estimation values calculated by the damage estimating module. | 2010-04-01 |
| 20100082914 | RECORDING MEDIUM, DRIVE DEVICE, AND MOUNTING METHOD - A recording medium coupled to a drive device includes a management information storage area and a master boot record. Management information used for a mounting process of the recording medium by the drive device is stored in the management information storage area and a starting location and an area size of a drive area is stored in the master boot record. | 2010-04-01 |
| 20100082915 | Method and system for accessing storage via the internet - Embodiments of the present invention set forth methods and systems for accessing storage via the Internet. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of automatically establishing a connection to the Internet, automatically logging into a first account and a second account, wherein first storage space is allocated to the first account and second storage space is allocated to the second account, aggregating the first storage space and the second storage space to formulate an aggregated storage space, and mapping the aggregated storage space into a set of contiguous memory locations. | 2010-04-01 |
| 20100082916 | Highly Reliable Disk Controller - Provided is a unit for protecting data with respect to data transfer between memories of a disk controller. The disk controller for controlling data transfer between a host computer and a disk drive includes: a channel unit having a channel memory; a cache unit having a cache memory, and a control unit for controlling the data transfer. The data transferred to/from the host computer is transferred in a packet between the channel memory and the cache memory, and The control unit for verifying consistency of information included in a header of the packet to be transferred to decide whether transfer can be permitted when the packet is transferred. | 2010-04-01 |
| 20100082917 | SOLID STATE STORAGE SYSTEM AND METHOD OF CONTROLLING SOLID STATE STORAGE SYSTEM USING A MULTI-PLANE METHOD AND AN INTERLEAVING METHOD - A solid state storage system includes a memory area configured to include a plurality of chips, and a micro controller unit (MCU) configured to perform a control operation, such that continuous logical block addresses are allocated using a multi-plane method or an interleaving method to different chips, and a read/write operation is performed in the logical block address unit in response to a read/write command. | 2010-04-01 |
| 20100082918 | LOG MANAGER FOR AGGREGATING DATA - A processing device and a machine-implemented method may be provided for sequentially aggregating, or writing, data to a log included in a data store. The log may store multiple log entries. Each of the log entries may include an entry metadata portion, describing a respective log entry, and an entry payload data portion. The entry metadata portion may include a log sequence number, corresponding to a log entry at a particular position in the log. A library of log-related processes may be provided, along with an application program interface to permit a calling application program to call any of the log related processes. The log-related processes may be called during a boot mode, a user mode, and a kernel mode. | 2010-04-01 |
| 20100082919 | DATA STREAMING FOR SOLID-STATE BULK STORAGE DEVICES - Methods and apparatus facilitate data streaming in bulk storage devices by generating linked lists containing entries for both user data and metadata. These linked lists containing mixed data types facilitate receiving and outputting user data, and to insert or ignore, respectively, metadata corresponding to that user data without interrupting flow of the user data. | 2010-04-01 |
| 20100082920 | Tracking Metadata Changes During Data Copy In A Storage System - Embodiments include methods, apparatus, and systems for tracking metadata changes during copying in a storage system. One embodiment includes a method that uses a bitmap and two fences to track changes to metadata while a copy of the metadata is being transferred from a source disk array to a destination disk array. | 2010-04-01 |
| 20100082921 | Systems And Methods For Data Snapshot Replication - Systems and methods for data snapshot replication are disclosed. In an exemplary implementation, a method for data snapshot replication may include inserting a token into a replication link when a data snapshot is generated at a source. The method may also include generating the data snapshot on a target in an order that the token is received. | 2010-04-01 |
| 20100082922 | VIRTUAL MACHINE MIGRATION USING LOCAL STORAGE - A method, apparatus, and system of virtual machine migration using local storage are disclosed. In one embodiment, a method includes creating a current snapshot of an operating virtual machine on a source physical server, storing a write data on a low-capacity storage device accessible to the source physical server and a destination physical server during a write operation on the destination physical server, and launching the operating virtual machine on the destination physical server when a memory data is copied from the source physical server to the destination physical server. The current snapshot may be a read-only state of the operating virtual machine frozen at a point in time. A time and I/O that may be needed to create the current snapshot that may not increase with a size of the operating virtual machine. | 2010-04-01 |
| 20100082923 | DEVICE FOR CONTROL OF SWITCHING OF STORAGE SYSTEM - A storage system includes a controller that controls switching from a system before switching to a system after switching. The controller includes a check unit that checks whether a connection between the system before switching and the system after switching is enabled, or not, a determination unit that determines whether switching from the system before switching to the system after switching is enabled, or not, a fail-over information migration unit that migrates fail-over information included in the system before switching to the system after switching, a user data migration unit that migrates user data in the system before switching to the system after switching, and a switching execution unit that enables the system after switching to receive I/O from a host. | 2010-04-01 |
| 20100082924 | Storage controller having virtual volume - To shorten time necessary for performing backup of data in a virtual volume managed by a storage controller to a backup destination storage device. A secondary volume including storage areas of the same number as the number of first primary virtual areas is created with respect to a primary virtual volume (a virtual logical volume to be an I/O destination from an external device) including plural primary virtual areas. The first primary virtual areas are primary virtual areas to which actual areas are allocated. Data copy is performed from the primary virtual volume to the secondary volume. At the time of backup to the backup destination storage device, data backup is performed from the secondary volume to the backup destination storage device. | 2010-04-01 |
| 20100082925 | MANAGEMENT COMPUTER USED TO CONSTRUCT BACKUP CONFIGURATION OF APPLICATION DATA - According to the present invention, it is possible to construct a backup configuration of a particular application data, without influencing data of another application. A management computer is coupled to a host computer on which an application operates, and to a storage apparatus that includes a plurality of volume groups each having one or more logical volumes. At least one of the logical volumes is allocated to the application. The management computer includes a volume group overlapping use determination part and a backup policy determination part. When the backup of the volume group to which one logical volume belongs is configured, the volume group overlapping use determination part determines whether there is another application that uses the volume group. The backup policy determination part determines whether there is set, for another volume group, backup policy information same as that set for the application. | 2010-04-01 |
| 20100082926 | Restricted Component Access to Application Memory - Embodiments of the present disclosure provide methods, systems, and articles for restricting access to memory of an application by a component of the application, for example, pluggable code modules. Other embodiments may also be described and claimed. | 2010-04-01 |
| 20100082927 | Secure memory interface - A secure memory interface includes a reader block, a writer block, and a mode selector for detecting fault injection into a memory device when a secure mode is activated. The mode selector activates or deactivates the secure mode using memory access information from a data processing unit. Thus, the data processing unit flexibly specifies the amount and location of the secure data stored into the memory device. | 2010-04-01 |
| 20100082928 | Secure Manufacturing of Programmable Devices - According to an embodiment, a programmable logic device includes a plurality of logic blocks and a logic unit. The logic blocks are grouped into one or more partitions. The logic unit controls external access to the one or more partitions, controls programming of the one or more partitions and controls interconnection and operation of the one or more partitions during operation of the programmable logic device. | 2010-04-01 |
| 20100082929 | MEMORY PROTECTION METHOD, INFORMATION PROCESSING APPARATUS, AND COMPUTER-READABLE STORAGE MEDIUM THAT STORES MEMORY PROTECTION PROGRAM - A memory protection method for protecting a memory from an unauthorized access by a program, includes: executing area definition processing for dividing an undivided address space on the memory into a plurality of areas; executing combining processing for temporarily combining the divided areas before calling a procedure of the program across the divided areas; executing calling processing for calling the procedure after the areas are combined; and executing restoring processing for restoring the combined areas to a state before the combining processing after execution of the called procedure. | 2010-04-01 |
| 20100082930 | GPU ASSISTED GARBAGE COLLECTION - A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) sends a garbage collection request and a first log to a special processing unit (SPU). The first log includes an address and a data size of each allocated data object stored in a heap in memory corresponding to the CPU. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU efficiently performs operations of a garbage collection algorithm due to its architecture on a local representation of the data objects stored in the memory. The SPU records a list of changes it performs to remove dead data objects and compact live data objects. This list is subsequently sent to the CPU, which performs the included operations. | 2010-04-01 |
| 20100082931 | INTELLIGENT EXTENT INITIALIZATION IN STORAGE ENVIRONMENT - A method, apparatus, and computer program product for initializing a plurality of extents in a computing storage environment is provided. A plurality of states for each of the plurality of extents is defined to include either an initialized state or a modified state. The plurality of extents is initialized at an advance time, designating the plurality of extents as having the initialized state. Upon a first occurrence of a destage operation of a first extent of the plurality of extents, the first extent is designated as having the modified state. | 2010-04-01 |
| 20100082932 | HARDWARE AND FILE SYSTEM AGNOSTIC MECHANISM FOR ACHIEVING CAPSULE SUPPORT - Methods and apparatus relating to a hardware and file system agnostic mechanism for achieving capsule support are described. In one embodiment, content associate with a capsule are stored in a non-volatile memory prior to a cold reset. A capsule descriptor may also be constructed, prior to the reset, which includes information about the physical location of the capsule content on the non-volatile memory. Other embodiments are also described and claimed. | 2010-04-01 |
| 20100082933 | AUTOMATED METHOD TO CONFIGURE A DATA STORAGE SYSTEM - An automated, computer-implemented method to configure a data storage system comprising a host computer, a storage controller in communication with said host computer, and a plurality of data storage media in communication with said storage controller, wherein the method provides a configuration algorithm encoded as computer readable program code, and executes that computer readable program code. The configuration algorithm creates a command procedure comprising a plurality of physical configuration commands to establish a physical configuration for the data storage system. The configuration algorithm further creates a command procedure comprising a plurality of logical configuration commands to establish a logical configuration for the data storage system. | 2010-04-01 |
| 20100082934 | COMPUTER SYSTEM AND STORAGE SYSTEM - In order to manage and operate Pool created in storage system A and a virtual volume using Pool in storage system B, it is required to copy the virtual volume of storage system A into a virtual volume of storage system B and new storage regions for copy of virtual volume into storage system B are needed. Storage system B acquires configuration information of Pool and a virtual volume of storage system A and inputs a logical volume included in Pool of storage system A to storage system B based on the acquired configuration information. Storage system B transforms the acquired configuration information for use in storage system B and creates Pool and a virtual volume from the input logical volume based on the transformed configuration information. | 2010-04-01 |
| 20100082935 | COMPUTER SYSTEM AND CAPACITY MANAGEMENT METHOD OF COMPUTER SYSTEM - It is necessary to install a program called an agent in order to keep track of how much a file system on a computer uses a disk. On this account, loads might be applied to a server due to installation work or the agent program to increase primary costs. In addition, software inside a storage device determines and records a target block for data input/output and keeps track of capacity utilization, which might degrade the input/output performance of the storage device. A computer system is provided in which configuration information and operating information are acquired from a storage device, when data input/output is made from a computer to a logical unit, it is determined that the computer uses the logical unit to which input/output is made, and capacity used by the computer is computed. | 2010-04-01 |
