13th week of 2010 patent applcation highlights part 26 |
Patent application number | Title | Published |
20100080029 | Multiple phase power supply having current shared power factor correction - A multi-phase (N) power supply is presented having current shared power factor correction, comprising. This includes N input rectifier filters each receiving a respective different one of an N phase AC input signal and providing therefrom one of N rectified signals. N single phase power factor correction pre-regulators receives a respective different one of the rectified signals and provide therefrom a regulated signal. A current sharing N way to single way multiplexing switch network for receiving the N regulated signals and provides therefrom a single output signal. | 2010-04-01 |
20100080030 | LOW-MASS, BI-DIRECTIONAL DC-AC INTERFACE UNIT - A DC-AC converter includes a DC-DC converter providing bi-directional conversion between a first DC power signal and a second DC power signal, the first DC power signal being on a first DC bus and the second DC power signal being on a second DC bus. The DC-AC converter also includes an inverter providing bi-directional DC-AC conversion between a third DC power signal and a first AC power signals the third DC power signal being on the second DC bus and the first AC power signal being on a first AC bus. | 2010-04-01 |
20100080031 | POWER FREQUENCY CONVERTER - A current control circuit (active element) is provided that is connected between a rectifier of a DC power source and a smoothing capacitor in a power frequency converter and that controls a variation in the rectified current caused by a variation in the instantaneous power consumption of the load device. When the rectified current increases, the current control circuit limits the current to have a reference current value or lower and, when the rectified current decreases, the current control circuit increases the current to have a value close to the reference current to thereby suppress the rectified current from the rectifier to a substantially-constant value. This consequently mitigates the influence on the primary power source by the variation in the instantaneous power consumption of the load device, thus clearing the Load Demand Variation specification required for the power source to be used in an aircraft. | 2010-04-01 |
20100080032 | SEMICONDUCTOR DEVICE - A semiconductor device is provided in which two adjacent cell lines extending in a word line direction are connected by one word line. Additionally, A semiconductor device comprising: word lines; bit lines which are disposed to cross the word lines; a plurality of cell lines extending in a word line direction; and a word line provided to share one cell line and the other cell line, of a pair of cell lines comprising two adjacent cell lines, wherein a distance between two adjacent cell lines in the pair of cell lines is smaller than a distance between two adjacent cell lines between one pair of cell lines and the other pair of cell lines. | 2010-04-01 |
20100080033 | VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments. | 2010-04-01 |
20100080034 | MAGNETIC SHIFT REGISTER AND OPERATION METHOD THEREOF - A magnetic shift register includes at least a magnetic memory track of which several magnetic walls separate the memory track into multiple magnetic domains to serve as magnetic binary memory cells. The magnetic memory track includes multiple data regions. Each data region has multiple of the magnetic binary memory cells for storing bit data at a quiescent state and registering at least one of the bit data shifted from the adjacent data region at a shifting state. Wherein, the bit data of the magnetic binary memory cells is shifted between the adjacent two data region under an operation current. | 2010-04-01 |
20100080035 | SRAM BASED ONE-TIME-PROGRAMMABLE MEMORY - Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state. | 2010-04-01 |
20100080036 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 2010-04-01 |
20100080037 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device comprises: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes. | 2010-04-01 |
20100080038 | SEMICONDUCTOR MEMORY DEVICE - An inexpensive nonvolatile memory having high performance which makes random write and readout possible an unlimited number of times is provided. A unit memory cell is formed of a MISFET having a channel body that is electrically isolated from a semiconductor substrate and a resistance change element having a two-terminal structure with one end electrically connected to a drain of the MISFET. The MISFET functions as a volatile memory element, and the resistance change element functions as a nonvolatile memory element, so that information stored in the MISFET is copied to the resistance change element before the power is turned OFF and information stored in the resistance change element is transferred to the MISFET when the power is turned ON, and thus, the MISFET is used as a volatile memory which makes random write and readout possible. | 2010-04-01 |
20100080039 | Nonvoltile memory device and method of driving the same - A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors. | 2010-04-01 |
20100080040 | Nonvolatile memory device and method of driving the same - A nonvolatile memory and a method of driving the same are provided, which adopt an improved write verify operation. The method of driving a nonvolatile memory device having variable resistance memory cells, bit lines coupled to the variable resistance memory cells, and column selection transistors coupled between the variable resistance memory cells and the bit lines to receive a first control voltage being applied to their gates, includes making the first control voltage at a first level, and changing a resistance of the variable resistance memory cells by providing a write bias to the variable resistance cells; verifying and reading whether the changed resistance enters into a specified resistance window; and changing the first control voltage to a second level that is different from the first level, and changing the resistance of the variable resistance memory cells by providing the write bias to the variable resistance memory cells. | 2010-04-01 |
20100080041 | Semiconductor device - A semiconductor device includes a comparison unit for comparing a resistance value of a memory element selectively connected to an input terminal with a resistance value of a reference resistance, and a resistance reference unit capable of selecting one of a plurality of resistance values and capable of being selectively connected to the input terminal. | 2010-04-01 |
20100080042 | INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES - A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device. | 2010-04-01 |
20100080043 | APPARATUS FOR THE DYNAMIC DETECTION, SELECTION AND DESELECTION OF LEAKING DECOUPLING CAPACITORS - Embodiments of the invention generally related to arrangements of decoupling capacitor arrays in an integrated circuit. A decoupling capacitor array may include a plurality of bit lines that are electrically coupled to each other, a plurality of word lines that are electrically coupled to each other, and a plurality of decoupling capacitors, each decoupling capacitor coupled to a respective bit line and word line. The decoupling capacitor array may further include an access circuit electrically coupled to the plurality of word lines and a power grid, the access circuit being configured to either connect or disconnect the decoupling capacitor array to the power grid based on a control signal. | 2010-04-01 |
20100080044 | SEMICONDUCTOR MEMORY DEVICE HAVING BALANCING CAPACITORS - According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers. | 2010-04-01 |
20100080045 | ROBUST 8T SRAM CELL - This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line. | 2010-04-01 |
20100080046 | SEMICONDUCTOR DEVICE - A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current. | 2010-04-01 |
20100080047 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 2010-04-01 |
20100080048 | STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL - A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell. | 2010-04-01 |
20100080049 | THERMALLY ASSISTED MULTI-BIT MRAM - Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation. | 2010-04-01 |
20100080050 | MAGNETORESISTIVE EFFECT DEVICE AND MAGNETIC MEMORY - A magnetic memory includes a magnetoresistive effect device comprising: a first ferromagnetic layer that has magnetic anisotropy in a direction perpendicular to a film plane thereof; a first nonmagnetic layer that is provided on the first ferromagnetic layer; a first reference layer that is provided on the first nonmagnetic layer, has magnetic anisotropy in a direction perpendicular to a film plane thereof, has magnetization antiparallel to a magnetization direction of the first ferromagnetic layer, and has a film thickness that is 1/5.2 to 1/1.5 times as large as a film thickness of the first ferromagnetic layer in the direction perpendicular to the film plane; a second nonmagnetic layer that is provided on the first reference layer; and a storage layer that is provided on the second nonmagnetic layer, has magnetic anisotropy in a direction perpendicular to a film plane thereof, and has a magnetization direction varied by spin-polarized electrons caused by flowing the current to the magnetoresistive effect device. | 2010-04-01 |
20100080051 | BIT-ERASING ARCHITECTURE FOR SEEK-SCAN PROBE (SSP) MEMORY STORAGE - An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. | 2010-04-01 |
20100080052 | ARRANGEMENT AND METHOD FOR CONTROLLING A MICROMECHANICAL ELEMENT - The invention concerns an arrangement for controlling a non-volatile memory arrangement for a circuit comprising: a micromechanical element coupled to a substrate; the micromechanical element being responsive to deflection means arranged on the substrate to control the movement of the micromechanical element between one or more stable states. In addition, the invention concerns a method for controlling a non-volatile memory device arrangement comprising: applying one or more signals to a deflection means for moving a micromechanical element between one or more stable states. To enhance the efficacy of the invention there is further provided a shorting circuit for use in the non-volatile memory arrangement. | 2010-04-01 |
20100080053 | STATIC SOURCE PLANE IN STRAM - The present disclosure relates to a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A transistor is electrically between the magnetic tunnel junction cell and the source line. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions. | 2010-04-01 |
20100080054 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS READING METHOD - A reading method includes: selecting the memory cell; performing a read operation on the selected memory cell to supply the read voltage, amplifying a first voltage read out from the selected memory element, outputting a second voltage obtained by amplifying the first voltage, and storing the second voltage as a first read state; performing a write operation on the selected memory cell to supply one of the first and second write voltages, regarding a third voltage appearing on the second line during the write operation as a second read state, comparing the first read state with the second read state, and deciding a state stored in the memory element before the read operation, as a read logic state on the basis of a result of the comparison; and writing the decided read logic state into the memory element if a logic state written in the write operation is different from the decided read logic state. | 2010-04-01 |
20100080055 | SEMICONDUCTOR MEMORY DEVICE - Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory device includes a plurality of memory banks, a plurality of second bit lines, a plurality of selector circuits, a voltage supply circuit. Each of the memory banks includes a plurality of first bit lines, a plurality of word lines, and a plurality of memory banks which are installed between the first bit lines and the word lines. The voltage supply circuit holds non-select bit lines of the first bit lines at the GND level at all times. | 2010-04-01 |
20100080056 | SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data. The memory cells that share one of word lines and can be written or read at a time are configured to store multiple pages of data therein. A total amount of data stored in the multiple pages is set to a power-of-two number of bits, and the redundant data is stored in a residual portion of the multiple pages. | 2010-04-01 |
20100080057 | Providing A Capacitor-based Power Supply To Enable Backup Copying Of Data From Volatile Storage To Persistent Storage - A system includes a volatile storage, a persistent storage, a capacitor-based power supply, and a controller coupled to the capacitor-based power supply. The controller detects interruption of main power, and in response to detecting the interruption of main power, begins backup copying of data from the volatile storage to the persistent storage. After beginning the backup copying of data, the controller checks whether the main power has resumed prior to depletion of the capacitor-based power supply. In response to detecting that main power has resumed prior to depletion of the capacitor-based power supply, the controller resumes operation using content of the volatile storage without restoring data from the persistent storage. | 2010-04-01 |
20100080058 | SEMICONDUCTOR DEVICE - The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved. | 2010-04-01 |
20100080059 | PAGE BUFFER USED IN A NAND FLASH MEMORY AND PROGRAMMING METHOD THEREOF - A page buffer used in a NAND flash memory comprises a first latch circuit, a second latch circuit, a bit line voltage supply circuit and a verification circuit comprising a first verification path, a second verification path and a third verification path. The first latch circuit and the second latch circuit latch the data programmed into and read from the NAND flash memory. The bit line voltage supply circuit supplies bit line voltages to the corresponding bit line of the NAND flash memory. The verification circuit verifies the programming operations of the NAND flash memory. The first verification path is for the verification of a first LSB programming operation. The second verification path is for the verification of a second LSB programming operation before the first LSB programming operation is verified. The third verification path is for the verification of the second LSB programming operation after the first LSB programming operation is verified. | 2010-04-01 |
20100080060 | DETERMINING MEMORY PAGE STATUS - The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry. | 2010-04-01 |
20100080061 | NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors. | 2010-04-01 |
20100080062 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - A nonvolatile semiconductor memory device includes: a semiconductor substrate including a first channel, and a source region and a drain region provided on both sides of the first channel; a first insulating film provided on the first channel; a charge retention layer provided on the first insulating film; a second insulating film provided on the charge retention layer; and a semiconductor layer including a second channel provided on the second insulating film, and a source region and a drain region provided on both sides of the second channel. | 2010-04-01 |
20100080063 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell group, transfer transistor, and switching circuit. The memory cell group has a plurality of memory cells each including a floating gate and control gate, and the current paths of the plurality of memory cells are connected in series. The transfer transistor transfers a write voltage to at least one memory cell in the memory cell group. The switching circuit applies a voltage to the gate of the transfer transistor. In a write operation, when a first voltage higher than a power supply voltage and lower than the write voltage is applied to the control gate of an unselected memory cell, the switching circuit applies an intermediate voltage higher than the first voltage and equal to or lower than the write voltage to the gate of the transfer transistor. | 2010-04-01 |
20100080064 | BIT LINE BIAS FOR PROGRAMMING A MEMORY DEVICE - Bit line bias for programming a memory device is generally described. In one example, circuitry for bit line bias programming comprises a word line, one or more bit lines coupled with the word line, and one or more cells to be programmed to a target threshold voltage coupled with the word line and the one or more bit lines wherein a program speed of the one or more cells is increased by selectively pre-charging the one or more bit lines such that a single program pulse raises individual threshold voltages of the one or more cells to or above the target threshold voltage. | 2010-04-01 |
20100080065 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile semiconductor memory device includes a memory cell and a driving unit. The a memory cell has a semiconductor layer having, a channel, and a source region and a drain region provided on both sides of the channel; a first insulating film provided on the channel; a charge retention layer provided on the first insulating film; and a gate electrode provided on the charge retention layer. The driving unit applies a burst signal having a constant amplitude and a constant frequency between the gate electrode and the semiconductor layer and performs at least one of operations of programming and erasing charge on the charge retention layer. | 2010-04-01 |
20100080066 | MEMORY, MEMORY OPERATING METHOD, AND MEMORY SYSTEM - A memory includes a plurality of memory cells each of which includes a memory transistor and a selection transistor; a control gate line; a selection gate line; a source line; a bit line; a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation; a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage; and a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed. | 2010-04-01 |
20100080067 | MEMORY AND READING METHOD THEREOF - A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period. | 2010-04-01 |
20100080068 | MEMORY CELL, AND METHOD FOR STORING DATA - The invention relates, among other things, to a memory cell for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals and a semiconductor structure with a band curve (EL) that has at least one potential well. The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure. The semiconductor heterostructure and the space charge region are spatially arranged relative to one another in such a way that the semiconductor heterostructure is located within the space charge region when the maintaining voltage is applied, at the edge of or outside the space charge region when the supply voltage is applied, and within the space charge region when the discharge voltage is applied. | 2010-04-01 |
20100080069 | SEMICONDUCTOR MEMORY DEVICE - A NAND type flash memory for erasing data every block including plural memory cell transistors that are provided every block and have floating gates formed through first gate insulating film above a well formed in a semiconductor substrate and control gates formed through second gate insulating film above the floating gates, data in the memory cell transistors being rewritable by controlling charge amounts accumulated in the floating gates, and a row decoder having a plurality of MOS transistors having drains that are respectively connected to corresponding word lines connected to the control gates of the plurality of memory cell transistors, the row decoder controlling gate and source voltages of the MOS transistors. | 2010-04-01 |
20100080070 | Method for Reducing Power Consumption in a Volatile Memory and Related Device - A method for reducing power consumption in a volatile memory includes switching off a bitline voltage provider according to a leakage control signal when a bitline array corresponding to the bitline voltage provider is dysfunctional due to a wordline to bitline short, controlling connections between a plurality of first bitline arrays corresponding to the bitline voltage provider and a plurality of sense amplifiers according to an access control signal, controlling connections between a plurality of second bitline arrays corresponding to the plurality of first bitline arrays and the plurality of sense amplifiers according to the access control signal, and providing power to the plurality of corresponding sense amplifiers according to the access control signal. | 2010-04-01 |
20100080071 | DATA STORAGE USING READ-MASK-WRITE OPERATION - Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns. | 2010-04-01 |
20100080072 | METHODS AND SYSTEMS TO WRITE TO SOFT ERROR UPSET TOLERANT LATCHES - Methods and systems to write to redundant storage latches, or storage cells, including soft error upset tolerant latches and feedback-interlocked redundant storage cells, including to write a logic value to one of a plurality of same sense storage nodes, and to write a complementary logic value to a selected one of a plurality of opposite sense storage nodes responsive to the logic value. Remaining storage nodes may be written to through circuitry within the storage cell. Logic values may be output substantially simultaneously with corresponding write operations. A system may include a multiple logic level write circuit to write to the first same sense storage node, and first and second single logic level write circuits to write to the first and second opposite sense storage nodes, respectively. | 2010-04-01 |
20100080073 | SEMICONDUCTOR MEMORY - A semiconductor memory includes: a plurality of regular memory cells; a first redundant memory cell; a second redundant memory cell; a first redundancy program circuit, first defect position information indicating a position of a first defective regular memory cell being programmed into the first redundancy program circuit; a second redundancy program circuit, second defect position information indicating a position of a second defective regular memory cell being programmed into the second redundancy program circuit; a redundancy switch circuit which couples signal lines to the regular memory cell, the first redundant memory cell, and the second redundant memory cell; and a redundancy signal switch circuit which replaces the first defect position information and the second defect position information with each other when the second defective regular memory cell is located between the first defective regular memory cell and the first redundant memory cell. | 2010-04-01 |
20100080074 | SEMICONDUCTOR MEMORY DEVICE - Easy and fast memory access with correcting defects is to be realized. In a spare memory in a semiconductor memory device, a redundant memory cell array that stores the number of correcting defects is provided. When a signal from the outside is received, the signal is switched to the redundant memory cell array, and the number of correcting defects is judged. Then, based on the result of the judgment, it is determined the judgment of a defective memory cell is continued or the judgment is finished to write data to a main memory cell. By providing the redundant memory cell array that stores the number of correcting defects, a state of correcting defects can be observed fast in such a manner. | 2010-04-01 |
20100080075 | Memory Device Refresh Method and Apparatus - In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address and addresses a row of memory cells included in each of the sections using a second portion of the row address. The refresh controller also successively selects two or more different groups of the banks during different time intervals each time a different one of the sections is identified. The refresh controller refreshes the addressed row of memory cells included in the most recently identified section of each bank for the most recently selected group of banks. | 2010-04-01 |
20100080076 | COMMON MEMORY DEVICE FOR VARIABLE DEVICE WIDTH AND SCALABLE PRE-FETCH AND PAGE SIZE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM. | 2010-04-01 |
20100080077 | PROCESS AND APPARATUS FOR MIXING A FLUID WITHIN A VESSEL - This invention relates to a process and an apparatus for mixing a fluid or a liquid within a vessel or a tank. The invention includes an apparatus with an inlet device and a mixer. The invention mixes crude oils and/or other hydrocarbon materials to a homogenous state with surprising and unexpected high efficiency. The invention includes methods of using the apparatus to mix the contents of the vessel and/or two stratified materials. The invention includes the ability to mix materials having disparities in density and/or viscosity. | 2010-04-01 |
20100080078 | METHOD AND APPARATUS FOR HOMOGENIZING A GLASS MELT - The present invention is directed toward a method of reducing contamination of a glass melt by volatilized precious metal oxides that may condense on the stirrer shaft of a stirring vessel and fall back into the glass melt, by heating the shaft. In one embodiment, the stirrer shaft includes an interior cavity and a heating element disposed within the cavity. The heating element heats the shaft to a temperature sufficient to prevent volatilized materials from condensing on the surfaces of the shaft. | 2010-04-01 |
20100080079 | DRUM MIXER - The invention relates to a drum mixer comprising a drum ( | 2010-04-01 |
20100080080 | PROCEDURE FOR ELIMINATING GHOST SOURCES FROM PASSIVE SONAR COMPRISING SEVERAL LINEAR ANTENNAS - This invention concerns the field of passive sonar systems simultaneously processing several linear antennas. This invention includes a method to eliminate ghost sources for a passive sonar having at least two linear antennas A and B, the method including: An initial acquisition step during which the signal received is measured at different moments t | 2010-04-01 |
20100080081 | METHOD AND APPARATUS FOR SEISMIC EXPLORATION - The disclosure identifies method and apparatus for seismic exploration which may be used to provide improved positioning of land-based seismic sources in an array. Also described are methods which make use of the improved positioning to allow, in some examples, improved direction or distribution of the energy beam resulting from actuation of the sources. Some methods make use of the described techniques to steer the energy beam; and in some cases at each source or a distribution location, multiple shots will be taken to distribute the beam in multiple orientations relative to the central source point. | 2010-04-01 |
20100080082 | SIDE SCAN SONAR IMAGING SYSTEM - A system for use with a boat to provide underwater sonar images includes a GPS receiver for providing GPS position data, a left side scan sonar transducer for transmitting left side scan sonar pulses and for receiving left side scan sonar return signals, and a right side scan sonar transducer for transmitting right side scan sonar pulses and for receiving right side scan sonar return signals. The system further includes signal processing circuitry for processing the left and right side scan sonar return signals to produce side scan image data and a digital processor for causing a display to display an underwater image based upon the side scan image data, wherein the digital processor associates GPS position and side scan image data. | 2010-04-01 |
20100080083 | Time-Dependant Gain Control For An Amplifier Used In Receiving Echoes - An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system. | 2010-04-01 |
20100080084 | MICROPHONE PROXIMITY DETECTION - A mobile communications device contains at least two microphones. One microphone is located away from the handset receiver and serves to pick up voice of a near end user of the device for transmission to the other party during a call. Another microphone is located near the handset receiver and serves to pick up acoustic output of the handset receiver (a far end signal). A signal processor measures the frequency response of the receiver. The signal processor performs spectral analysis of the receiver frequency response to determine whether or not the device is being held at the ear of the user. On that basis, the device automatically changes its operating mode, e.g., turns on or off a touch sensitive display screen during the call. Other embodiments are also described. | 2010-04-01 |
20100080085 | FORCED ACOUSTIC DIPOLE AND FORCED ACOUSTIC MULTIPOLE ARRAY USING THE SAME - Provided is a forced acoustic dipole capable of regulating phases and acoustic pressures of first and second acoustic signals output from first and second pole speakers to freely steer the direction of an acoustic lobe. In addition, a forced acoustic multipole array is constituted by a plurality of forced acoustic dipoles. When the phases and acoustic pressures of the first and second acoustic signals output from the forced acoustic dipoles are regulated to steer an acoustic lobe in a specific direction, sound can be heard from a desired direction only without disturbing others. | 2010-04-01 |
20100080086 | ACOUSTIC FINGERPRINTING OF MECHANICAL DEVICES - A method and device are presented for identifying machines, such as vehicles, based on acoustic machine signatures. An acoustic sensor generates machine-acoustic data about the machine. A machine-signature identifier receives the machine-acoustic data, determines a machine signature from the machine-acoustic data, and identifies the machine based on the machine signature. A machine-signature database, configured to store multiple machine signatures and/or machine-signature templates, may receive and process queries about machine signatures for machine identification. The machine-signature identifier may generate and send an instruction based on the identified machine. The instruction may instruct application of electronic countermeasures or may permit a vehicle to enter a secured area. An acoustic modulator may generate the machine-acoustic data to act as a machine signature. The acoustic modulator may generate the machine signature using an ultrasonic carrier. | 2010-04-01 |
20100080087 | Multifunction Sports and Recreation Device - A multifunction sports and recreation device includes a sports whistle, a detachable measuring lanyard, a laser pointer, and a multimode digital electronic stopwatch that displays date, time, and advanced stopwatch information, with daily and segmented alarms. The device is also capable of displaying temperature, relative humidity, and heat index information (along with a heat index alarm). In other embodiments, particularly those with an outdoor recreation influence, the device includes a digital compass; radio frequency transmitters and receivers for locating a base camp; and means for monitoring or indicating wind speed, barometric pressure, and lunar tide cycles. The device may also incorporate an outdoor light and fire-starting flint. | 2010-04-01 |
20100080088 | TIME BASE DEVICE FOR A WATCH - The time base device for a watch includes at least one electric motor coil ( | 2010-04-01 |
20100080089 | Storage medium reproducing apparatus or storage medium recording/reproducing apparatus - In a recording/reproducing apparatus, a pair of detection sliders, in which pins coming into contact with an outer peripheral edge of a storage medium being inserted are formed and which approach and are separated from each other, are disposed in the vicinity of a storage medium insert port, and a detection lever coupled with one of the pins is rotatably and slidably attached to a frame. Further, the recording/reproducing apparatus has a support member, which is slid by being pressed by the outer peripheral edge of the storage medium being inserted, and an intermediate guide lever rotated in association with a sliding operation of the support member. Two select grooves are formed in the detection lever, and a first projecting piece, which is selectively fit into the select grooves, is disposed in the intermediate guide lever. | 2010-04-01 |
20100080090 | STORAGE SYSTEMS AND METHODS FOR PUBLISHING DEVICE ADDRESSES - Storage systems and methods for publishing device addresses are disclosed. An exemplary method may include receiving addresses for a plurality of device objects in the storage system over an out-of-band path to each of the device objects. The method may also include storing the addresses for the plurality of device objects in the storage system. The method may also include returning the addresses for the plurality of device objects in the storage system over another out-of-band path to an interface manager for the storage system. | 2010-04-01 |
20100080091 | PASS-THROUGH ACCESSOR COMPRISING A FIXTURING APPARATUS FOR STORING A PLURALITY OF PORTABLE DATA STORAGE CASSETTES - A pass-through accessor comprising a fixturing apparatus that can store a plurality of portable data storage cassettes. The pass-through accessor comprises a moveable gripper assembly comprising a plurality of gripping members. The gripper assembly releaseably attaches to a portable data storage cassette disposed in a storage slot, pulls that portable data storage cassette outwardly from the storage slot, and releaseably attaches that portable data storage cassette to one of a plurality of fixturing assemblies disposed on the fixturing apparatus. | 2010-04-01 |
20100080092 | Optical disc apparatus - A simple circuit configuration allows an optical disc apparatus to reduce a problem of sound skips occurring due to damage on an optical disc. To this end, an LPF extracts a low-frequency component from a tracking actuator drive signal obtained by a tracking actuator driver. When the optical disc apparatus reads and writes information to and from the optical disc, a sled drive signal supplier outputs a sled pulse signal, as a drive signal for a sled motor, for a set-up predetermined time within each interval of a predetermined length, the sled pulse signal having a level corresponding to a level of the low-frequency component obtained by the LPF. On the other occasions, the sled drive signal supplier outputs the low-frequency component obtained by the LPF as the drive signal for the sled motor. | 2010-04-01 |
20100080093 | OPTIMIZING FOCUS POINT FOR OPTICAL DISC - An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate status signals and an error signal in response to accessing a storage medium. The error signal provides a first value based on an accuracy of accessing the storage medium. The second circuit may be configured to offset the first value of the error signal to a second value to increase the accuracy of accessing said storage medium. The status signals include one or more of a data signal and a differential signal. In a first mode, an offset signal is generated in response to the data signal. In a second mode, the offset signal is generated in response to the differential signal. | 2010-04-01 |
20100080094 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - Disclosed are a display apparatus and a control method thereof. The display apparatus includes a memory which stores contents with voice information; a voice output unit which outputs a voice; a voice storage which receives and stores a voice of a user; and a controller which controls the voice output unit to selectively output one of the voice information stored in the memory or the voice of a user stored in the voice storage when reproducing the contents. | 2010-04-01 |
20100080095 | RECORDING CONTROL METHOD, RECORDING/REPRODUCTION METHOD, RECORDING CONTROL APPARATUS AND RECORDING/REPRODUCTION APPARATUS - Information is recorded on an information recording medium by classifying recording conditions by data pattern, including at least one recording mark and at least one space, of a data stream to be recorded; wherein the classification of the recording conditions by data pattern is performed using a combination of the length of a first recording mark included in the data stream and the length of a first space located adjacently previous or subsequent to the first recording mark, and then further performed using the length of a second recording mark which is not located adjacent to the first recording mark and is located adjacent to the first space. Alternatively, the classification of the recording conditions by data pattern is performed using a combination of the length of a first recording mark included in the data stream and the length of a first space located adjacently previous or subsequent to the first recording mark, and then further performed using the length of a second space which is not located adjacent to the first space and is located adjacent to the first recording mark. | 2010-04-01 |
20100080096 | HIGHER PERFORMACNE DVD WRITING CURRENT CIRCUIT - A writing current circuit ( | 2010-04-01 |
20100080097 | Medium Processor and Medium Processing Method - According to one embodiment, a medium processor includes a detector, an acquiring module, a storage module, and an output module. The detector detects a data storage medium. The acquiring module acquires a use period that is set as a period during which data recorded on the data storage medium is supposed to be intact. The storage module stores identification information that identifies the data storage medium in association with the use period. The output module outputs the identification information and the use period stored in the storage module in association with each other. | 2010-04-01 |
20100080098 | BASEPLATE FOR USE IN PARTICLE ANALYSIS - A test baseplate is configured to support and expose at least one storage device component to particle evacuation and particle analysis. The test baseplate includes a base having an upper surface that extends between an outer peripheral wall and an inner peripheral wall and having a lower surface defined by the inner peripheral wall. The test baseplate also includes a top clamp configured to be fastened to the upper surface of the base to secure the at least one storage device component to the base. | 2010-04-01 |
20100080099 | DEVICE AND METHOD FOR REPRODUCING INFORMATION, AND COMPUTER PROGRAM - An information reproducing apparatus ( | 2010-04-01 |
20100080100 | TRACKING ERROR SIGNAL DETECTION APPARATUS AND OPTICAL DISC APPARATUS - A DPD tracking error signal detection apparatus includes the following. Four differentiators remove DC components and differentiate four signal with varying differential phases. The signals are then sampled and quantized by four A/D converters, and output to a non-inverting unit and an inverting unit. A phase inverter/compositor then leaves as-is or phase-inverts the output signals, according to a control signal. The non-inverting and the inverting unit each include two Hilbert transformers that phase-shift the output from the A/D converters, two delay units that delay the output of the other A/D converters to match the delay of the Hilbert transformers, two cross-correlators that calculate the cross-correlation between pairs of Hilbert transformers and delay units, and an adding unit that combines the cross-correlator results and outputs the combined result to the phase inverter/compositor. | 2010-04-01 |
20100080101 | SYSTEM AND METHOD FOR ANALYZING MAGNETIC MEDIA SURFACES FOR THERMAL ERASURES AND OTHER CHARACTERISTICS - Analyzing magnetic media surfaces for thermal erasures and other characteristics is described. The system includes a drive channel module configured to measure servo automatic gain control values for a magnetic media surface that represent the amount of gain applied by the drive channel module to a preamble signal recorded on the magnetic media surface. The gain control values are then acquired according to certain measurement parameters. The gain control values are then arranged by proximity to each other and organized to generate images that represent changes in the characteristics of the magnetic media surface. Analysis of the images then detects patterns that represent changes in the characteristics of the media surface and determines measurement parameters that coincide with the change in the characteristic. | 2010-04-01 |
20100080102 | INFORMATION REPRODUCING APPARATUS AND METHOD, AND COMPUTER PROGRAM - An information reproducing apparatus ( | 2010-04-01 |
20100080103 | Information recording apparatus, information reproducing apparatus and recording media - An apparatus for recording information in an optical-information recording media by holography includes a signal-light irradiation unit, a reference-light irradiation unit, a reference light angle adjustment unit, and a positioning unit for positioning irradiation positions of the signal light and the reference light. The optical-information recording media is divided into N (N≧2) recording regions, M multiplexed information can be recorded in the respective recording regions by the reference light angle adjustment unit which changes the angle of the reference light at M angles (θ | 2010-04-01 |
20100080104 | Information recording/reproducing apparatus, apparatus for manufacturing optical information recording medium, and optical information recording medium - An optical information recording/reproducing apparatus equipped with a mechanism for moving an optical pickup to an arbitrary radial position of an optical information recording medium using holography. A total sum signal of signals is generated at the photodetector for receiving signals reproduced from the optical information recording medium, and a radial position of the pickup is obtained from the number of pulses in the total sum signal to thereby allow the pickup to move to an arbitrary radial position. | 2010-04-01 |
20100080105 | Optical Pickup Device and Optical Disk Driver Using the Same - A light source, an objective lens, and an astigmatism generation element producing for light for focus control, and an optical receiver are provided. The astigmatism generation element is interposed between the objective lens and the optical receiver and produces focal points in front of and behind the optical receiver within two mutually orthogonal cross-sectional planes including an optical axis of the reflected light. The astigmatism generation element is a Fresnel mirror that has a plurality of orbicular zones and steps connecting adjacent orbicular zones to each other and that takes the orbicular zones as reflecting mirrors. A depth “d” of the steps is set substantially one-half of a wavelength λ, and a depth d | 2010-04-01 |
20100080106 | OPTICAL PICKUP APPARATUS AND OPTICAL DISC APPARATUS - An optical pickup apparatus changes a propagation direction of luminous fluxes, out of a laser light reflected by a disc, in four luminous flux regions set about a laser optical axis so as to mutually disperse these luminous fluxes. A signal light region in which only a signal light is present appears on a detection surface of a photodetector. A plurality of sensors for a signal light are placed at positions irradiated with the signal light within the region. When an arithmetic process is performed on a detection signal outputted from each sensor, a DC component occurring in a tracking error signal is suppressed. | 2010-04-01 |
20100080107 | METHOD FOR PRODUCING SEMICONDUCTOR LASER, SEMICONDUCTOR LASER, OPTICAL PICKUP, AND OPTICAL DISK DRIVE - A method for producing a semiconductor laser having an edge window structure includes the steps of forming masks of insulating films on a nitride-based III-V compound semiconductor substrate including first regions and second regions periodically arranged in parallel therebetween; and growing a nitride-based III-V compound semiconductor layer in a region not covered by the masks. The first region between each two adjacent second regions has two or more positions, symmetrical with respect to a center line thereof, where laser stripes are to be formed. The masks are formed on one or both sides of each of the positions where the laser stripes are to be formed at least near a position where edge window structures are to be formed such that the masks are symmetrical with respect to the center line. The nitride-based III-V compound semiconductor layer includes an active layer containing at least indium and gallium. | 2010-04-01 |
20100080108 | TONE ARM ASSEMBLY - A tone arm assembly for use with a rotatable turntable. The tone arm assembly includes a tone arm body supported adjacent to the rotating turntable being horizontally pivotable about a vertically extending axis. A tone arm tube is provided having a longitudinal axis and a first end and a second end, the first end extending within and being supported by the tone arm body and the second end terminating at a shell for releaseably supporting a pick up cartridge. A counterweight is included which is translatable along a horizontal path parallel to the longitudinal axis of the tone arm tube between a first position and a second position, the first position being closest to the shell and a second position being farthest from the shell to adjust contact pressure between a stylus maintained by the pick up cartridge and a record supported by the rotatable turntable. At least a portion of the counterweight is capable of extending fore and aft of the vertically extending axis when the counterweight is positioned on its horizontal path between its first and second positions. | 2010-04-01 |
20100080109 | Variable Slippage Control For A Disc Jockey Control Surface - The disclosure pertains to a scratch effect controller for use by a disk jockey, wherein at least one electromagnet creates the slippage tension or friction effect between the user manipulated disc, which includes a vinyl-like surface thereby simulating a vinyl record, and the rotatable or fixed platter. The strength of the electromagnet is variable so as to create a variable slippage tension or friction effect. | 2010-04-01 |
20100080110 | High Capacity Digital Data Storage By Transmission of Radiant Energy Through Arrays of Small Diameter Holes - A method and apparatus for reading a storage medium is provided. The apparatus includes a plurality of emitters configured to emit a radiant energy at a predetermined optical wavelength, a plurality of detectors configured to detect the radiant energy at the predetermined optical wavelength, and a storage medium holder configured to hold the storage medium between the plurality of emitters and the plurality of detectors. A first detector is configured to detect radiant energy which is emitted by a first emitter through data holes of a first track of the storage medium, and a second detector is configured to detect radiant energy which is emitted by a second emitter through data holes of a second track of the storage medium. | 2010-04-01 |
20100080111 | METHOD AND SYSTEM FOR ETHERNET SWITCHING, CONVERSION, AND PHY OPTIMIZATION BASED ON LINK LENGTH IN AUDIO/VIDEO SYSTEMS - Aspects of a method and system for Ethernet Switching, Conversion, and PHY optimization based on link length in Audio/Video Systems are provided. In this regard, the length of a link over which a first communication device communicates with a second communication device may be determined and Ethernet PHY's residing in the communication devices may be configured based on the determination. One or both of the communication devices may comprise an Ethernet switch operable to switch packetized audio and/or video content. The packetized audio and/or video may be switched between the configured Ethernet PHY and one or more other Ethernet PHYs. Audio and/or video data may be received via the one or more corresponding Ethernet PHYs, the received audio and/or video data may be reformatted to be compatible with an audio and/or video interface, and the reformatted audio and/or video data may be transmitted via the audio and/or video interface. | 2010-04-01 |
20100080112 | Frequency Offset Estimation in Orthogonal Frequency Division Multiple Access Wireless Networks - A method of wireless transmission for estimating the carrier frequency offset in a base station of a received transmission from a user equipment (UE) accessing a radio access network. The method time de-multiplexes selected symbols of a received sub-frame, computes the frequency-domain symbols received from each antenna through an FFT, de-maps the UEs selected sub-carriers for each antenna, computes metrics associated to a carrier frequency offset hypothesis spanning a searched frequency offset window, repeats these steps on subsequent received sub-frames from the UE over an estimation interval duration, non-coherently accumulates the computed metrics and selects the carrier frequency offset hypothesis with largest accumulated metric amplitude. | 2010-04-01 |
20100080113 | TONE RESERVATION TECHNIQUES FOR REDUCING PEAK-TO-AVERAGE POWER RATIOS - Embodiments of the present disclosure describe closed loop scheduled peak-to-average power (PAPR) reduction systems and methods to facilitate desired PAPR reduction. Other embodiments describe weighted tone reservation (WTR) methods and systems for PAPR reduction. Still other embodiments may be described and claimed. | 2010-04-01 |
20100080114 | LOW COMPLEXITY BANDWIDTH EFFICIENT CARRIER FREQUENCY OFFSET ESTIMATION TECHNIQUE FOR OFDMA UPLINK TRANSMISSIONS - A system and a method for estimating low complexity bandwidth efficient carrier frequency offset for orthogonal frequency division multiple access (OFDMA) and or single carrier frequency division multiple access (SC-FDMA) uplink transmissions in a communication network systems comprising a group of subscriber stations, a base station including carrier frequency offset unit, said method steps comprising: | 2010-04-01 |
20100080115 | METHODS AND APPARATUS TO MONITOR BORDER GATEWAY PROTOCOL SESSIONS - Example methods and apparatus to monitor border gateway protocol sessions are disclosed. A disclosed example method includes detecting a failure of a first border gateway protocol (BGP) session and initiating a session-down timer in response to detecting the failure. The example method also includes generating a sustained-down alarm when a threshold time value of the session-down timer is exceeded before the first BGP session is re-established. | 2010-04-01 |
20100080116 | RE-ESTABLISHING A RADIO RESOURCE CONTROL CONNECTION WITH A NON-PREPARED BASE STATION - A method for establishing a radio resource control connection is disclosed. A wireless communication device may establish a radio resource control connection with a first base station. The wireless communication device may send a message to a second base station that requests re-establishment of the radio resource control connection. The wireless communication device may receive a message from the second base station that initiates setup of a new radio resource control connection. | 2010-04-01 |
20100080117 | Method to Manage Path Failure Threshold Consensus - A system for providing hosts with a capability to determine which threshold rule of a plurality of threshold rules to use based upon threshold consensus. For example, the system would address a configuration case of several hosts sharing an output port of a fabric via zoning and that port being connected to a single port of a storage controller. If one host is executing lower priority jobs and its threshold is much higher than another host with higher priority jobs and a lower threshold, and the storage controller recognizes that several hosts are sharing the same storage controller port, the consensus will be to ignore the threshold of the first host and to use the threshold of the second host to prevent performance degradation in the system. | 2010-04-01 |
20100080118 | Radio network system and control node switching method - A radio network system and a control node switching method which can improve a reliability of the whole network and improve a wording efficiency. The system includes at least one alternate control node which can be substituted form the control node. The alternate control node monitors an operating state in the control node and discriminates whether or not the operating state is abnormal. When the operating state is determined to be abnormal, the alternate control node sets its own address into a control node address. | 2010-04-01 |
20100080119 | Method for restoring connections in a network - The present invention relates to a method for restoring connections in a network, in particular in a telecommunication network, the network being provided with a data plane, a control plane and a number of nodes ( | 2010-04-01 |
20100080120 | PROTECTED-FAR-NODE-BASED SOLUTION FOR FAULT-RESILIENT MPLS/T-MPLS MULTICAST SERVICES - A system and method providing fault resilient multicast services using a network topology in which a source node communicates with a plurality of receiver nodes via at least two disjoint paths in which at least one receiver node is provisioned according to a 1+1 protection mechanism. | 2010-04-01 |
20100080121 | Communication Method And Radio Network Control Device In A Mobile Communication System - A mobile communication system in which a mobile station copies data and transmits that copied data to a plurality of base stations, each base station sends that copied data to a serving radio network control device (S-RNC) directly or via a drift radio network control device (D-RNC), and the S-RNC selectively combines and outputs the received copied data; wherein a congestion monitoring unit monitors the congestion state of a line between the D-RNC and S-RNC, and when that line is congested, a D-RNC selectively combines the copied data that is inputted from the plurality of base stations and sends the result to that line, and when the line is not congested, the D-RNC sends the copied data that is inputted from the plurality of base stations to the line without performing selective combination. | 2010-04-01 |
20100080122 | COMMUNICATION DEVICE AND COMPUTER USABLE MEDIUM THEREFOR - A communication device that is to be connected to a providing server for providing time information via a network is provided. The communication device includes a congestion-degree obtainer to obtain a congestion degree indicating a condition of traffic in the network, a time information obtainer to obtain the time information provided by the providing server, and an obtainment restrictor to compare the obtained congestion degree with a predetermined reference degree of congestion, and restricts the time information obtainer from obtaining the time information if the comparison indicates that the traffic in the network is busier than the reference degree of congestion. | 2010-04-01 |
20100080123 | Method and Apparatus for Signaling Proprietary Information Between Network Elements of a Core Network in a Wireless Communication Network - The invention includes a method and apparatus for signaling proprietary information between network elements of a core network (CN) of a wireless communication network. A method for signaling proprietary information within the CN includes encoding the proprietary information in an IPv4 Options field of an inner header of an IP packet, and pre-pending an outer header to the IP packet for Mobile IPv4 (MIPv4) tunneling the IP packet from a first node of the CN to a second node of the CN. The first and second nodes of the CN may include a mobility anchor node and a mobility gateway node, respectively. The first and second nodes of the CN may include a mobility gateway node and a mobility anchor node, respectively. A method for signaling proprietary information includes receiving a tunneled IP packet at a first node of the CN (where the IP packet includes an outer header, an inner header, and a payload), removing the outer header from the IP packet, stripping an IP Options field from the inner header of the IP packet where the IPv4 Options field includes the proprietary information, and propagating the proprietary information from the first node of the CN to a second node. The first node of the CN may be a mobility gateway node and the second node may be a node of a radio access network (RAN). The first node of the CN may be a mobility anchor node and the second node may be another node of the CN. | 2010-04-01 |
20100080124 | METHOD TO MANAGE THE LOAD OF PERIPHERAL ELEMENTS WITHIN A MULTICORE SYSTEM - A method to provide reliability, power management and load balancing support for multicore systems based on Networks-on-Chip (NoCs) and to efficiently implement architectural support for this method by introducing complex packet handling mechanisms is achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved with a method to manage the load of peripheral elements within a multicore system comprising several processing units accessing peripheral elements through a NoC, each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the NoC, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element. | 2010-04-01 |
20100080125 | Edge Continued Evolution, Improved Channel Request Method And System - The present invention is a method and system adapted to facilitate, between a mobile station (MS) and network, an indication of support for reduced time transmission interval (RTTI). The MS can provide a base station system (BSS) with an indication of its multislot capability within an access burst sent at the start of a contention based access. In another aspect, the MS can indicate support for a new Immediate Assignment message as the conventional Immediate Assignment message can only assign single timeslots. The present invention enables the Radio Access Network (RAN) to assign RTTI and more than one timeslot for GPRS/EDGE temporary block flows (TBFs) during an Access Grant Channel (AGCH) assignment. The method of the present invention can be implemented in a computer program product or distributed software adapted to be loaded into at least one or a plurality of memory locations and executed by at least one or a plurality of respective computer processors. | 2010-04-01 |
20100080126 | TRANSMISSION APPARATUS AND TRANSMISSION METHOD - A transmission apparatus for stably transmitting or receiving data of high priority is provided. In the transmission apparatus of the present invention, processing of the priority packet to be transmitted and processed by priority and processing of the non-priority packet are conducted separately. At transmission side, the above-mentioned priority packet is transmitted by priority by making its average transmission interval shorter than its average generation interval, and said non-priority packet is transmitted during the transmit margin period caused by the above-mentioned processing. At receive side, in the layer of processing the receive frame as a layer lower than the layer of processing the priority packet and non-priority packet, the priority packet and the non-priority packet is sorted based on the communication protocol header of the receive packet stored in the receive frame, and processing of the priority packet and that of the non-priority packet are conducted separately. | 2010-04-01 |
20100080127 | INTERCEPTION METHOD AND DEVICE THEREOF - An interception method and an interception device are provided. The interception method includes the following steps. An interception center assigns an interception task to an interception network element (NE) to request to intercept an interception target. The interception NE reports user plane data of corresponding service sessions of the interception target satisfying an interception reporting policy according to the received interception task and the configured interception reporting policy. | 2010-04-01 |
20100080128 | SYSTEM AND METHOD FOR PROVIDING LEAST-COST ROUTING OF VOICE CONNECTIONS BETWEEN HOME AND FOREIGN NETWORKS USING VOICE-OVER-IP INFRASTRUCTURE - A system and method are described for providing least-cost call routing for mobile wireless devices having access to voice-over-IP (VoIP) infrastructure, such as may be operated by an enterprise having global presence. Using a local wireless connection, such as a wireless local area network (WLAN), a software agent on the mobile wireless device registers with a common, enterprise-wide registrar, which, in turn, informs a VoIP gateway in the device's home region of the device's new location. The home region VoIP gateway will then re-route incoming calls for the device to a VoIP gateway serving the region in which the device is currently located. The local VoIP gateway will then route the call to the device via the WLAN. Seamless routing occurs even when the wireless device obtains a local phone number in a foreign network. Outgoing calls from the device can be routed via the VoIP infrastructure or the foreign network based on availability of service and/or cost. | 2010-04-01 |