| 13th week of 2010 patent applcation highlights part 12 |
| Patent application number | Title | Published |
|---|
| 20100078629 | ORGANIC EL DISPLAY DEVICE - An organic EL display device includes a pixel electrode which is disposed in each of first to third organic EL elements, a first light emission layer which includes a first dopant material having a first absorbance peak, the first light emission layer extending over the first to third organic EL elements and being disposed above the pixel electrode, a second light emission layer which includes a second dopant material having a second absorbance peak and is disposed above the first light emission layer, a third light emission layer which is disposed above the second light emission layer, a counter-electrode which is disposed above the third light emission layer, and a hole transport layer which is formed of a material having an absorbance bottom on a shorter wavelength side than the first absorbance peak and the second absorbance peak in absorbance spectrum characteristics of the hole transport layer. | 2010-04-01 |
| 20100078630 | Organic Electroluminescence Element, Method for Manufacturing the Same, Image Display Unit and Illuminating Device - In an organic electroluminescent element of the present invention, which has at least a hole transport layer having an inorganic compound and an organic luminescent layer between a first electrode and a second electrode on a substrate, a high light extraction efficiency can be obtained by reflecting light emitted from the organic luminescent layer off the hole transport layer. | 2010-04-01 |
| 20100078631 | Organic light emitting diode display device - The OLED display device includes a first stack and a second stack that are separated from each other between an anode electrode and a cathode electrode, with a charge generation layer sandwiched between the first stack and the second stack, each of the first stack and the second stack having an emission layer. The first stack includes a blue emission layer formed between the anode electrode and the CGL. The second stack includes a fluorescent green emission layer and a phosphorescent red emission layer formed between the cathode electrode and the CGL. The blue emission layer includes one of a fluorescent blue emission layer and a phosphorescent blue emission layer. | 2010-04-01 |
| 20100078632 | ELECTRONIC ELEMENT - The object is to fabricate a novel organic semiconductor element which can effectively utilize the main-chain conduction of a conjugated high molecular compound having semiconductor-like properties. Provided is an electronic element which contains, as components, a pair of electrodes which is formed on a substrate, a mesoporous film in which tubular mesopores, which are orientation controlled in one direction, are formed, the mesoporous film being formed between the electrodes so as to be in contact with the electrodes, a conjugated high molecular compound held in the tubular mesopores, and a third electrode which is electrically insulated from the conjugated high molecular compound and is in contact with the mesoporous film. | 2010-04-01 |
| 20100078633 | INSULATED GATE TYPE TRANSISTOR AND DISPLAY DEVICE - A transistor comprises an active layer of an oxide containing at least one element selected from In, Ga and Zn. The active layer is formed such that a desorption gas monitored as a water molecule by a temperature programmed desorption analysis is 1.4/nm | 2010-04-01 |
| 20100078634 | SEMICONDUCTOR DEVICE - One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more of a metal oxide including zinc-germanium, zinc-lead, cadmium-germanium, cadmium-tin, cadmium-lead. | 2010-04-01 |
| 20100078635 | SEMICONDUCTOR DEVICE - As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path. Further, an interposer for facilitating the connection with the processor LSI is connected to the input terminal of the memory LSI to be stacked thereby increasing the degree of freedom in selecting memories. | 2010-04-01 |
| 20100078636 | SEMICONDUCTOR DEVICE WITH BACKSIDE TAMPER PROTECTION - A tamper-resistant semiconductor device ( | 2010-04-01 |
| 20100078637 | PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION DEVICE, AND IMAGE SENSOR - A photoelectric conversion element includes a light receiving layer that is formed of microcrystal semiconductor, a first semiconductor layer of a first conductive type that is formed on one face side of the light receiving layer, and a first intermediate layer that is interposed between the first semiconductor layer and the light receiving layer and is formed of amorphous semiconductor. | 2010-04-01 |
| 20100078638 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor and a method of fabricating an image sensor. An image sensor may include a readout circuitry arranged over a semiconductor substrate, an interlayer dielectric film provided with metal lines arranged over a semiconductor substrate, and/or a lower electrode arranged over a interlayer dielectric film such that a lower electrode may be connected to metal lines. An image sensor may include a first-type conductive layer pattern arranged over a lower electrode, an intrinsic layer arranged over a surface of a semiconductor substrate such that an intrinsic layer may substantially cover a first-type conductive layer pattern. An image sensor may include a second-type conductive layer arranged over an intrinsic layer. A method of fabricating an image sensor may include a patterned n-type amorphous silicon layer which may be treated with N | 2010-04-01 |
| 20100078639 | THIN FILM SEMICONDUCTOR DEVICE FABRICATION METHOD AND THIN FILM SEMICONDUCTOR DEVICE - The present invention provides a method for making a thin film semiconductor device having a bottom-gate, bottom-contact-type thin film transistor structure finer in size with satisfactory characteristics, in which the interface between a gate insulating film and a thin film semiconductor layer can be maintained at satisfactory conditions without being affected by formation of source/drain electrodes. A first gate insulating film ( | 2010-04-01 |
| 20100078640 | Thin Film Transistor Backplane - A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer. | 2010-04-01 |
| 20100078641 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME - In a display substrate and a method of the display substrate, a bank pattern provided with openings formed therethrough is formed by an imprint method, and the openings are filled with a conductive material by an inkjet method to form a data line and a pixel electrode, in accordance with one or more embodiments. When the display substrate is manufactured, a patterning process by a photolithography method may be replaced with the patterning process by the imprint method and the inkjet method, which simplifies a manufacturing method of the display substrate. In case that the display substrate includes a plastic substrate, the plastic substrate may be prevented from being deformed during a photolithography process. | 2010-04-01 |
| 20100078642 | LAYERED STRUCTURE AND ELECTRON DEVICE THAT USES SUCH A LAYERED STRUCTURE, FABRICATION PROCESS THEREOF, ELECTRON DEVICE ARRAY AND DISPLAY APPARATUS - A layered structure comprises a variable wettability layer including a material that changes a critical surface tension in response to energy provided thereto, the wettability changing layer including at least a high surface energy part of large critical surface tension and a low surface energy part of low critical surface tension, a conductive layer formed on the variable wettability layer at the high surface energy tension part, and a semiconductor layer formed on the variable wettability layer at the low surface energy part. | 2010-04-01 |
| 20100078643 | DISPLAY DEVICE - In view of the problem that a reduced thickness of an EL film causes a short circuit between an anode and a cathode and malfunction of a transistor, the invention provides a display device that has a light emitting element including an electrode and an electroluminescent layer, a wire electrically connected to the electrode of the light emitting element, a transistor provided with an active layer including a source, a drain and a channel forming region, and a power supply line electrically connected to one of the source and the drain of the transistor, wherein the wire is electrically connected to the other of the source and the drain of the transistor, and the width of a part of the electrode in the vicinity of a portion where the electrode is electrically connected to the wire is smaller than that of the electrode in the other portion. | 2010-04-01 |
| 20100078644 | INSULATING FILM PATTERN, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE USING THE SAME - In an insulating film pattern, a first pattern part is formed at one surface of the insulating film pattern to form a source electrode, a drain electrode, and a semiconductor layer of the thin film transistor. The first pattern part is recessed in one surface of the insulating film pattern. The insulating film pattern is formed on a substrate through an imprint scheme, and is deposited on a base substrate having a gate electrode and a gate line through a contact print scheme. A source electrode, drain electrode, and semiconductor layer of a thin film transistor are formed through an inkjet print scheme using a first pattern part of the insulating film pattern. A gate electrode and gate line may be formed using a second pattern part of the insulating film pattern | 2010-04-01 |
| 20100078645 | SEMICONDUCTOR DEVICE COMPRISING A BURIED POLY RESISTOR - An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance. | 2010-04-01 |
| 20100078646 | DISPLAY DEVICE - A display device including an active area having a plurality of pixels comprises an array substrate including a plurality of display elements disposed at said pixels respectively; a sealing substrate disposed to be opposed to said array substrate; and a seal member disposed between said array substrate and said sealing substrate and encircling said active area; wherein said seal member is made of frit glass, and a resin layer is disposed between said array substrate and said sealing substrate in said active area. | 2010-04-01 |
| 20100078647 | THIN FILM TRANSISTOR SUBSTRATE AND ORGANIC LIGHT EMITTING DISPLAY HAVING THE SAME - In an organic light emitting display, a switching transistor includes an active pattern having a crystal structure grown at an angle of 0°±10° relative to a current flow direction, and a driving transistor includes an active pattern having a crystal structure grown at an angle of 90°±10° relative to a current flow direction. As a result, the driving transistor more precisely controls intensity of supply voltage applied to an organic light emitting layer. | 2010-04-01 |
| 20100078648 | GALLIUM NITRIDE-BASED EPITAXIAL WAFER AND METHOD OF FABRICATING EPITAXIAL WAFER - A gallium nitride-based epitaxial wafer for a nitride light-emitting device comprises a gallium nitride substrate having a primary surface, a gallium nitride-based semiconductor film provided on the primary surface of the gallium nitride substrate, and, an active layer provided on the gallium nitride-based semiconductor film, the active layer having a quantum well structure. The active layer includes a well layer of a gallium nitride-based semiconductor. The gallium nitride-based semiconductor contains indium as a Group III element. A normal line of the primary surface and a C-axis of the gallium nitride substrate form an off angle with each other. The off angle is distributed on the primary surface, and the off angle monotonically increases on the line that extends from one point to another point through a center point of the primary surface of the gallium nitride substrate. The one point and the other point are on an edge of the primary surface, and indium contents of the well layer defined at n points (n: integer) on the line monotonically decrease in a direction from the one point to the other point. The thickness values of the well layer defined at the n points monotonically increase in the direction. | 2010-04-01 |
| 20100078649 | Light emitting element and light emitting device - A light emitting element which emits light of a wavelength, includes a substrate which is transparent to the wavelength of emitted light and includes a first surface and a second surface; a semiconductor layer stacked on the first surface; a first electrode which is reflective to the wavelength of emitted light and formed on a surface of the semiconductor layer, wherein electrical resistance of the first electrode in a farthest distance is equal to or smaller than 1Ω; and a second electrode which is reflective to the wavelength of emitted light and formed on the second surface, wherein electrical resistance of the second electrode in a farthest distance is equal to or smaller than 1Ω. | 2010-04-01 |
| 20100078650 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate made of silicon carbide and having a surface, a normal vector for the surface having an off angle with respect to a <0001> direction or a <000-1> direction, a semiconductor layer of a first conductivity type formed on the semiconductor substrate, a first semiconductor region of a second conductivity type formed in a surface region of the semiconductor layer, a source region of a first conductivity type formed in a surface region of the first semiconductor region, a second semiconductor region of a second conductivity type formed in the surface region of the semiconductor layer, contacting the first semiconductor region, and having a bottom surface lower than a bottom surface of the first semiconductor region, wherein at least one end of the bottom surface of the second semiconductor region is perpendicular to an off angle direction. | 2010-04-01 |
| 20100078651 | ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE - Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials. | 2010-04-01 |
| 20100078652 | DIAMOND ELECTRONIC DEVICES INCLUDING A SURFACE AND METHODS FOR THEIR MANUFACTURE - The present invention relates to a diamond electronic device comprising a functional surface formed by a planar surface of a single crystal diamond, the planar surface of the single crystal diamond having an Rq of less than 10 nm and at least one of the following characteristics: (a) the surface has not been mechanically processed since formation by synthesis; (b) the surface is an etched surface; (c) a density of dislocations in the diamond breaking the surface is less than 400 cm″2 measured over an area greater than 0.014 cm2; (d) the surface has an Rq less than 1 nm; (e) the surface has regions with a layer of charge carriers immediately below it, such that the regions of the surface are normally termed conductive, such as a hydrogen terminated {100} diamond surface region; (f) the surface has regions with no layer of charge carriers immediately below it, such that these regions of the surface are normally termed insulating, such as an oxygen terminated {100} diamond surface; and (g) the surface has one or more regions of metallization providing electrical contact to the diamond surface beneath these regions. | 2010-04-01 |
| 20100078653 | TRANSISTOR HAVING A HIGH-K METAL GATE STACK AND A COMPRESSIVELY STRESSED CHANNEL - In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region. | 2010-04-01 |
| 20100078654 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a first transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first epitaxial crystal layers formed on both sides of the first channel region in the semiconductor substrate, the first epitaxial crystal layers comprising a first crystal; and a second transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, second epitaxial crystal layers formed on both sides of the second channel region in the semiconductor substrate, and third epitaxial crystal layers formed on the second epitaxial crystal layers, the second epitaxial crystal layers comprising a second crystal, the third epitaxial crystal layers comprising the first crystal, the second transistor having a conductivity type different from that of the first transistor. | 2010-04-01 |
| 20100078655 | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same - The present invention comprises a first substrate with a die formed on a die metal pad, a first and a second wiring circuits formed on the surfaces of the first substrate. A second substrate has a die opening window for receiving the die, a third wiring circuit is formed on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. During the formation, laser is introduced to cut the backside of the first substrate and an opening hole is formed in the first substrate to expose a part of the backside of the Au or Au/Ag metal layer of chip/die. | 2010-04-01 |
| 20100078656 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells are disposed on top of the substrate to be spaced apart from one another. Each of the light emitting cells comprises a first upper semiconductor layer, an active layer, and a second lower semiconductor layer. Reflective metal layers are positioned between the substrate and the light emitting cells. The reflective metal layers are prevented from being exposed to the outside. | 2010-04-01 |
| 20100078657 | SEMICONDUCTOR LIGHT EMITTING DEVICE, LIGHT EMITTING MODULE, LIGHTING APPARTUS, DISPLAY ELEMENT AND MANUFACTURING METHOD OF SEMICONDUCTOR LIGHT EMITTING DEVICE - An LED array chip ( | 2010-04-01 |
| 20100078658 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a light emitting device and a method of manufacturing the light emitting device. According to the present invention, the light emitting device comprises a substrate, an N-type semiconductor layer formed on the substrate, and a P-type semiconductor layer formed on the N-type semiconductor layer, wherein a side surface including the N-type or P-type semiconductor layer has a slope of 20 to 80° from a horizontal plane. Further, the present invention provides a light emitting device comprising a substrate formed with a plurality of light emitting cells each including an N-type semiconductor layer and a P-type semiconductor layer formed on the N-type semiconductor layer, and a submount substrate flip-chip bonded onto the substrate, wherein the N-type semiconductor layer of one light emitting cell and the P-type semiconductor layer of another adjacent light emitting cell are connected to each other, and a side surface including at least the P-type semiconductor layer of the light emitting cell has a slope of 20 to 80° from a horizontal plane. Further, the present invention is provides a method of manufacturing the light emitting device. Accordingly, there is an advantage in that the characteristics of a light emitting device such as luminous efficiency, external quantum efficiency and extraction efficiency are enhanced and the reliability is secured such that light with high luminous intensity and brightness can be emitted. | 2010-04-01 |
| 20100078659 | Light-emitting element - A light-emitting element includes a semiconductor laminated structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type and an active layer sandwiched by the first and second semiconductor layers, a first electrode on one surface side of the semiconductor laminated structure, a conductive reflective layer on an other surface side of the semiconductor laminated structure for reflecting light emitted from the active layer, a contact portion partially formed between the semiconductor laminated structure and the conductive reflective layer and being in ohmic contact with the semiconductor laminated structure, and a second electrode on a part of a surface of the conductive reflective layer on the semiconductor laminated structure without contacting the semiconductor laminated structure for feeding current to the contact portion. | 2010-04-01 |
| 20100078660 | Group III Nitride compound semiconductor light-emitting device and method for producing the same - An n-type layer of a light-emitting device has a structure in which a first n-type layer, a second n-type layer and a third n-type layer are sequentially laminated in this order on a sapphire substrate, and an n-electrode composed of V/Al is formed on the second n-type layer. The first n-type layer and the second n-type layer are n-GaN, and the third n-type layer is n-InGaN. The n-type impurity concentration of the second n-type layer is higher than that of the first n-type layer and the third n-type layer. | 2010-04-01 |
| 20100078661 | MACHINED SURFACE LED ASSEMBLY - A substrate for an LED assembly can have a plurality of cups formed therein. At least one cup can be formed within another cup. The cups can be co-axial with respect to one another, for example. A machined surface of the substrate can enhance reflectivity of the LED assembly. A transparent and/or non-global solder mask can enhance reflectivity of the LED assembly. A transparent ring can enhance reflectivity of the LED assembly. By enhancing reflectivity of the LED assembly, the brightness of the LED assembly can be increased. Brighter LED assemblies can be used in applications such as flashlights, displays, and general illumination. | 2010-04-01 |
| 20100078662 | NON-GLOBAL SOLDER MASK LED ASSEMBLY - A substrate for an LED assembly can have a plurality of cups formed therein. At least one cup can be formed within another cup. The cups can be co-axial with respect to one another, for example. A machined surface of the substrate can enhance reflectivity of the LED assembly. A transparent and/or non-global solder mask can enhance reflectivity of the LED assembly. A transparent ring can enhance reflectivity of the LED assembly. By enhancing reflectivity of the LED assembly, the brightness of the LED assembly can be increased. Brighter LED assemblies can be used in applications such as flashlights, displays, and general illumination. | 2010-04-01 |
| 20100078663 | TRANSPARENT SOLDER MASK LED ASSEMBLY - A substrate for an LED assembly can have a plurality of cups formed therein. At least one cup can be formed within another cup. The cups can be co-axial with respect to one another, for example. A machined surface of the substrate can enhance reflectivity of the LED assembly. A transparent and/or non-global solder mask can enhance reflectivity of the LED assembly. A transparent ring can enhance reflectivity of the LED assembly. By enhancing reflectivity of the LED assembly, the brightness of the LED assembly can be increased. Brighter LED assemblies can be used in applications such as flashlights, displays, and general illumination. | 2010-04-01 |
| 20100078664 | LED PHOSPHOR DEPOSITION - LED phosphor deposition for use with LEDs. In an aspect, a method is provided for forming an encapsulation. The method includes determining a geometric shape for the encapsulation, selecting a dam material, applying the dam material to a substrate to form a boundary defining a region having the geometric shape, and filling the region with encapsulation material to form the encapsulation. In another aspect, an LED apparatus is provided that includes at least one LED chip and an encapsulation disposed on the at least one LED chip. The encapsulation is formed by determining a geometric shape for the encapsulation, selecting a dam material, applying the dam material to a substrate to form a boundary defining a region having the geometric shape, and filling the region with encapsulation material to form the encapsulation. | 2010-04-01 |
| 20100078665 | Organic Electroluminescence Element and Method for Manufacturing Thereof - One embodiment of the present invention is an organic electroluminescence element having a substrate, a first electrode formed on the substrate, an organic luminescent medium layer which includes an organic luminescent layer and is formed on the first electrode, a second electrode formed on the organic luminescent medium layer and arranged so as to face the first electrode, a first passivation layer formed on the second electrode, an adhesive layer adhered to the substrate and formed so as to cover the first electrode, the organic luminescent medium layer, the second electrode and the first passivation layer, a sealing substrate formed on the adhesive layer and a second passivation layer formed so as to entirely cover the adhesive layer, the sealing substrate and an upper surface of an exposure part of the substrate. | 2010-04-01 |
| 20100078666 | ELECTRO-OPTICAL DEVICE, ELECTRONIC APPARATUS, AND TRANSISTOR - An electro-optical device includes a substrate, a data line, and a transistor formed on the substrate and including (i) a semiconductor film having a channel region having a channel length according to one direction, first and second source/drain regions which are formed with the channel region interposed therebetween, and first and second junction regions respectively formed between the first and second source/drain region and the channel region, and (ii) a gate electrode overlapping with the channel region, wherein at least one of the first and second junction regions is formed such that the width thereof is at least partially larger than that of the channel region. | 2010-04-01 |
| 20100078667 | LIGHT-EMITTING DIODE - The present invention relates to a light-emitting diode (LED).The LED comprises an LED die, one or more metal pads, and a fluorescent layer. The characteristics of the present invention include that the metals pads are left exposed for the convenience of subsequent wiring and packaging processes. In addition, the LED provided by the present invention is a single light-mixing chip, which can be packaged directly without the need of coating fluorescent powders on the packaging glue. Because the fluorescent layer and the packaging glue are not processed simultaneously and are of different materials, the stress problem in the packaged LED can be reduced effectively. | 2010-04-01 |
| 20100078668 | LIGHT EMITTING DEVICE - Provided is a light emitting device. The light emitting device comprises a body, a light emitting diode on the body, a resistor integrated on the body and configured to sense a temperature of the light emitting diode, and a plurality of metal layers on the body. | 2010-04-01 |
| 20100078669 | LIGHT EMITTING DEVICE AND LEAD FRAME FOR THE SAME - An LED according to the present invention includes a light-emitting chip emitting light, a chip-mounting portion on which the light-emitting chip is mounted, a light-reflecting layer formed on at least a portion of the chip-mounting portion and a gold plating layer formed on at least a portion of the light-reflecting layer, the gold plating layer having a thickness such that the gold plating layer has a different color from a color of gold. The chip-mounting portion may have various shapes and materials. For example, the chip-mounting portion may be a lead terminal, a slug, a printed circuit board, a ceramic substrate, a CNT substrate, etc. | 2010-04-01 |
| 20100078670 | Light emitting element with improved light extraction efficiency, light emitting device comprising the same, and fabricating method of the light emitting element and the light emitting device - Provided is a light emitting element, a light emitting device including the same, and fabrication methods of the light emitting element and light emitting device. The light emitting device comprises a substrate, a light emitting structure including a first conductive layer of a first conductivity type, a light emitting layer, and a second conductive layer of a second conductivity type which are sequentially stacked, a first electrode which is electrically connected with the first conductive layer; and a second electrode which is electrically connected with the second conductive layer and separated apart from the first electrode, wherein at least a part of the second electrode is connected from a top of the light emitting structure, through a sidewall of the light emitting structure, and to a sidewall of the substrate. | 2010-04-01 |
| 20100078671 | Nitride based semiconductor light emitting device - A nitride based semiconductor light emitting device is revealed. The light emitting device includes a light emitting epitaxial layer, a P-type electrode and a N-type electrode. The P-type electrode and the N-type electrode are disposed on the light emitting epitaxial layer. The light emitting device features on that the N-type electrode is arranged on the inner side of the P-type electrode. The P-type electrode extends toward the N-type electrode along the edge of the light emitting epitaxial layer and the N-type electrode extends inward along the inner side of the P-type electrode. By means of the electrode pattern with special design, the light emitting area of the light emitting device is increased. | 2010-04-01 |
| 20100078672 | Group III nitride semiconductor light-emitting device and production method therefor - Provided is a method for producing a Group III nitride semiconductor light-emitting device including a GaN substrate serving as a growth substrate, which method realizes processing of the GaN substrate to have a membrane structure at high reproducibility. In the production method, a stopper layer of AlGaN having an Al compositional proportion of 20% is formed on the top surface of a GaN substrate; an n-type layer, an active layer, a p-type layer, and a p-electrode are sequentially formed on the stopper layer; and the p-electrode is joined to a support substrate. Subsequently, a mask having a center-opening pattern is formed on the bottom surface of the GaN substrate, and the bottom surface is subjected to PEC etching. The bottom surface is irradiated with light having a wavelength corresponding to an energy higher than the band gap of GaN, but lower than the band gap of AlGaN having an Al compositional proportion of 20%. Since etching stops when it proceeds to a depth reaching the stopper layer, a membrane structure can be formed at high reproducibility. | 2010-04-01 |
| 20100078673 | ACTIVE SEMICONDUCTOR COMPONENT WITH A REDUCED SURFACE AREA - A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established. | 2010-04-01 |
| 20100078674 | INSULATED GATE BIPOLAR TRANSISTOR - A trench structure of an insulated gate bipolar transistor (IGBT) is formed as a trench net in a P region and extends into an N− layer. The trench net separates the P region into P wells and floating P layers. The P wells contact an emitter electrode while the floating P layers are not in direct contact with the emitter electrode. A gate formed of conductive material and having a surrounding insulation oxide layer is formed in the trench net. An N+ layer may be formed above each floating P layer under the gate. The floating P layers are isolated from the gate and are also not connected to the emitter electrode. | 2010-04-01 |
| 20100078675 | CIRCUIT DEVICE - Provided is a circuit device having a configuration in which thermal interference between built-in elements is suppressed and being miniaturized in total size. A hybrid integrated circuit device of the present invention includes: a circuit substrate, a sealing resin and leads. The circuit substrate in its upper surface is incorporated with a hybrid integrated circuit formed of semiconductor elements and the like respectively fixed to heat spreaders. The sealing resin coats the circuit substrate and thus seals the hybrid integrated circuit. The leads each extend to the outside while being fixed to a pad formed of a conductive pattern. In this hybrid integrated circuit device, the semiconductor elements are mounted on the respective heat spreaders at positions offset from each other, and thereby are arranged to be spaced away from each other. | 2010-04-01 |
| 20100078676 | SEMICONDUCTOR DEVICE - The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply. | 2010-04-01 |
| 20100078677 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor substrate having a first semiconductor region of a first semiconductor type, a second semiconductor region of a second conductivity type extended in the first semiconductor region, and a mesa area forming a slope along an outer circumference of the semiconductor substrate; a first electrode provided on a first principal surface of the semiconductor substrate; and a second electrode provided on a second principal surface of the semiconductor substrate that is opposed to the first principal surface; wherein the second semiconductor region comprises a main region provided in the semiconductor substrate while being brought into contact with the first electrode, the main region including an annular portion and diffused portions arranged in a spread manner in an area surrounded by the annular portion; and wherein a portion of the first semiconductor region is interposed between the diffused portions and between the diffused portions and the annular portion; and the diffused portions are composed of a small pitch region and a large pitch region having a larger pitch than that of the small pitch region. | 2010-04-01 |
| 20100078678 | SEMICONDUCTOR ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area to the upper layer area is bent at said boundary surface. | 2010-04-01 |
| 20100078679 | LIGHT-RECEIVING DEVICE AND MANUFACTURING METHOD FOR A LIGHT-RECEIVING DEVICE - Provided is a light-receiving device which has light-receiving sensitivity superior to that of a conventional Schottky diode type light-receiving device and also has sufficiently-strengthened junction of a Schottky electrode. A first contact layer formed of AlGaN and having conductivity, a light-receiving layer formed of AlGaN, and a second contact layer formed of AlN and having a thickness of 5 nm are epitaxially formed on a predetermined substrate in the stated order, and a second electrode is brought into Schottky junction with the second contact layer, to thereby form MIS junction. Further, after the Schottky junction, heat treatment is performed under a nitrogen gas atmosphere at 600° C. for 30 seconds. | 2010-04-01 |
| 20100078680 | SEMICONDUCTOR SENSOR STRUCTURES WITH REDUCED DISLOCATION DEFECT DENSITIES AND RELATED METHODS FOR THE SAME - Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique. | 2010-04-01 |
| 20100078681 | Integrated Circuit Including a Hetero-Interface and Self Adjusted Diffusion Method for Manufacturing the Same - An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region. | 2010-04-01 |
| 20100078682 | POWER MOSFET HAVING A STRAINED CHANNEL IN A SEMICONDUCTOR HETEROSTRUCTURE ON METAL SUBSTRATE - A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor. | 2010-04-01 |
| 20100078683 | SEMICONDUCTOR DEVICE - A semiconductor device include: a nitride group semiconductor functional layer including a second nitride group semiconductor region on a first nitride group semiconductor region where a two-dimensional carrier gas layer is made, the second nitride group semiconductor region functioning as a barrier layer; a first main electrode electrically connected to one end of the two-dimensional carrier gas layer; a second main electrode electrically connected to the other end of the two-dimensional carrier gas layer; and metal oxide films placed between the first and second main electrodes, electrically connected to the first main electrode, and reducing a carrier density of the two-dimensional carrier gas layer. | 2010-04-01 |
| 20100078684 | SELECTIVE HIGH-K DIELECTRIC FILM DEPOSITION FOR SEMICONDUCTOR DEVICE - Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer. | 2010-04-01 |
| 20100078685 | SEMICONDUCTOR MEMORY DEVICE - There is provided a semiconductor memory device including: a first wiring layer; a second wiring layer; a third wiring layer; a memory array region; a first gate array region being formed at a region at which the first wiring layer, the second wiring layer and the third wiring layer can be used in wiring of the plural unit cells; and a second gate array region being formed at a region at which two wiring layers that are the first wiring layer and the second wiring layer can be used in wiring of the plural memory cells, and the plural unit cells are arrayed so as to be separated at an interval needed for placement, by using the first wiring layer, of wiring that should be placed by using the third wiring layer. | 2010-04-01 |
| 20100078686 | Image Sensor and Method for Manufacturing the Same - An image sensor and manufacturing method thereof are provided. The image sensor can include a readout circuitry, an interconnection, a second interlayer dielectric, an image sensing device, a contact plug, and a sidewall dielectric. The contact plug can electrically connect the first conductive type layer to the interconnection through a via hole passing through the image sensing device. The sidewall dielectric can be disposed on a sidewall of the second conductive type layer within the via hole. | 2010-04-01 |
| 20100078687 | Method for Transistor Fabrication with Optimized Performance - A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors ( | 2010-04-01 |
| 20100078688 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device of the present invention includes: a nitride semiconductor laminated structure including an n-type first layer, a second layer that is laminated on the first layer and contains a p-type impurity, and an n-type third layer laminated on the second layer, each layer of the nitride semiconductor laminated structure being made of a Group III nitride semiconductor, and having a wall surface extending from the first, second, to third layers; a fourth layer that is formed on the wall surface in the second layer and that has a different conductive characteristic from that of the second layer; a gate insulating film formed to contact the fourth layer; and a gate electrode formed as facing the fourth layer with the gate insulating film being sandwiched between the gate electrode and the fourth layer. | 2010-04-01 |
| 20100078689 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION - A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency. | 2010-04-01 |
| 20100078690 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects. | 2010-04-01 |
| 20100078691 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY - In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability. | 2010-04-01 |
| 20100078692 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a first pixel having a first photodiode and a first readout circuit and a second pixel having a second photodiode and a second readout circuit. The second pixel is aligned at one side of the first pixel, and a light receiving area of the first photodiode is different from a light receiving area of the second photodiode. | 2010-04-01 |
| 20100078693 | Semiconductor device and method of manufacturing semiconductor device - The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized. | 2010-04-01 |
| 20100078694 | SEMICONDUCTOR COMPONENT HAVING A DRIFT ZONE AND A DRIFT CONTROL ZONE - A description is given of a normally on semiconductor component having a drift zone, a drift control zone and a drift control zone dielectric arranged between the drift zone and the drift control zone. | 2010-04-01 |
| 20100078695 | Low Leakage Capacitors Including Portions in Inter-Layer Dielectrics - An integrated circuit structure includes a semiconductor substrate including a first region and a second region; an insulation region in the second region of the semiconductor substrate; and an inter-layer dielectric (ILD) over the insulation region. A transistor is in the first region. The transistor includes a gate dielectric and a gate electrode over the gate dielectric. A first conductive line and a second conductive line are over the insulation region. The first conductive line and the second conductive line are substantially parallel to each other and extending in a first direction. A first metal line and a second metal line are in a bottom metal layer (M | 2010-04-01 |
| 20100078696 | SEMICONDUCTOR MEMORY DEVICE WITH POWER DECOUPLING CAPACITORS AND METHOD OF FABRICATION - Provided is a semiconductor memory device including a capacitor structure extending over core and peripheral areas of a substrate. Respective portions of the capacitor structure function as memory cell capacitors in the core area and as first and second capacitors in the peripheral area. A combination of the first and second capacitors functions as a first power decoupling capacitor, and a transistor disposed in the peripheral area functions as a second power decoupling capacitor. | 2010-04-01 |
| 20100078697 | Semiconductor device including capacitor and method for manufacturing the same - A semiconductor device according to the present invention uses a capacitor including a capacitive insulating film sandwiched between an upper electrode and a lower electrode. The lower electrode of the capacitor is constructed by overlappingly connecting a plurality of electrode portions together. A lower electrode portion (plug type electrode) of the adjacent electrode portions is made of columnar tungsten. The lower electrode portion further includes a conductive film (barrier film) that covers a side surface and a bottom surface of the tungsten. A top surface of the tungsten is covered with a bottom portion of an upper electrode portion (cylinder type electrode). | 2010-04-01 |
| 20100078698 | Vertical semiconductor device, dram device including the same - A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion. | 2010-04-01 |
| 20100078699 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A silicide layer is formed at least in a part on an impurity diffusing layer to avoid a region on a gate electrode on a gate oxide film. Voltage is applied between the gate electrode and the impurity diffusing layer to destroy the gate oxide film. | 2010-04-01 |
| 20100078700 | Semiconductor Memory Device - To realize a semiconductor memory device whose capacitance value per unit area in a memory cell is increased without increase in the area of the memory cell. The memory cell includes a transistor, a memory element, a first capacitor, and a second capacitor. The first capacitor includes a semiconductor film, a gate insulating film, and a gate electrode which are included in the transistor and is formed at the same time as the transistor. The second capacitor includes an electrode which is included in the memory element and an insulating film and an electrode which are formed over the electrode. Further, the second capacitor is formed over the first capacitor. In this manner, the first capacitor and the second capacitor which are connected in parallel with the memory element are formed. | 2010-04-01 |
| 20100078701 | THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING REPEATING LAYER PATTERNS OF DIFFERENT THICKNESSES - A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described. | 2010-04-01 |
| 20100078702 | Semiconductor storage device and method for manufacturing the same - A semiconductor storage device according to the present invention includes: a semiconductor substrate; an embedded insulator embedded in a trench formed in the semiconductor substrate and having an upper portion protruding above a top surface of the semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a floating gate formed on the first insulating film at a side of the embedded insulator, having a side portion arching out above the embedded insulator, and having a side surface made of a flat surface and a curved surface continuing below the flat surface; a second insulating film contacting an upper surface, the flat surface and the curved surface of the floating gate; and a control gate opposing the upper surface, the flat surface and the curved surface of the floating gate across the second insulating film. | 2010-04-01 |
| 20100078703 | SPLIT-GATE NON-VOLATILE MEMORY CELL AND METHOD - A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate. | 2010-04-01 |
| 20100078704 | SEMICONDUCTOR STORAGE ELEMENT AND MANUFACTURING METHOD THEREOF - A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film. | 2010-04-01 |
| 20100078705 | NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE - A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided. | 2010-04-01 |
| 20100078706 | Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device (and method of forming same) includes a word gate provided above a channel region of a semiconductor substrate via an insulating layer, a control gate provided at a side of the word gate, and a charge storage layer provided by an ONO film between the channel region and the control gate, and between the word gate and the control gate. The control gate includes a silicide layer including silicide containing nickel, and a non-silicide layer provided between the silicide layer and the charge storage layer. | 2010-04-01 |
| 20100078707 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region. | 2010-04-01 |
| 20100078708 | MOS TRANSISTOR HAVING AN INCREASED GATE-DRAIN CAPACITANCE - A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which s dieletrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode. | 2010-04-01 |
| 20100078709 | SEMICONDUCTOR DEVICE - In a conventional semiconductor device, protection of a to-be-protected element from a surge voltage is difficult because the to-be-protected element is turned on before a protection element due to variations in manufacturing conditions. In a semiconductor device of the present invention, a protection element and a MOS transistor have part of their structures formed under common conditions. N type diffusion layers of the protection element and the MOS transistor are formed in the same process, while the N type diffusion layer of the protection element has a larger diffusion width than the N type diffusion layer of the MOS transistor. With this structure, when a surge voltage is applied to an output terminal, the protection element is turned on before the MOS transistor, and thereby the MOS transistor is protected from an avalanche current. | 2010-04-01 |
| 20100078710 | Semiconductor component with a drift zone and a drift control zone - A semiconductor component has a drift zone and a drift control zone, a drift control zone dielectric, which is arranged in sections between the drift zone and the drift control zone, and has a first and a second connection zone, which are doped complementarily with respect to one another and which form a pn junction between the drift control zone and a section of the drift zone. | 2010-04-01 |
| 20100078711 | METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER - A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides. | 2010-04-01 |
| 20100078712 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor pillar, a first gate insulating film, a gate electrode, and a first contact. The first semiconductor pillar extends upwardly from a semiconductor substrate. The first gate insulating film covers side surfaces of the first semiconductor pillar. The gate electrode covers the first gate insulating film. The first gate insulating film insulates the gate electrode from the first semiconductor pillar. The first contact partially overlaps, in plane view, the first semiconductor pillar and the gate electrode. The first contact includes a silicon layer having a top level which is higher than a top level of the gate electrode. | 2010-04-01 |
| 20100078713 | SEMICONDUCTOR COMPONENT STRUCTURE WITH VERTICAL DIELECTRIC LAYERS - A method for producing a semiconductor structure and a semiconductor component are described. | 2010-04-01 |
| 20100078714 | TRENCH METAL OXIDE-SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF - A fabrication method of a trench metal oxide-semiconductor (MOS) transistor is provided. After the gate trenches are formed in the epitaxial layer, impurities of a first conductive type are implanted into the epitaxial layer by using a blanket implantation process. A polysilicon pattern filling the gate trenches and covering a predetermined range of epitaxial layer surrounding the gate trenches is formed on the epitaxial layer. Impurities of a second conductive type are implanted through the polysilicon pattern into the epitaxial layer to form a well. Impurities of the first conductive type are implanted to form a plurality of first doping regions. A portion of the polysilicon layer above the upper surface of the epitaxial layer is removed by etching to form a plurality of polysilicon gates. Impurities in the first doping regions are driven in to form a plurality of source regions adjacent to the gate trenches. | 2010-04-01 |
| 20100078715 | LATERAL DMOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A LDMOS transistor and a method for fabricating the same. A LDMOS transistor may include a P-type body region formed over a N-well. A LDMOS transistor may include a source region and a source contact region formed over a P-type body region. A LDMOS transistor may include a drain region spaced a distance from a P-type body region. A LOCOS may be formed over a surface of a N-well between a P-type body region and a drain region. A LDMOS transistor may include a main gate electrode formed over at least a portion of a LOCOS and a N-well. A LDMOS transistor may include a sub-gate electrode formed between a source region and a source contact region. A method for fabricating a LDMOS transistor is described herein. | 2010-04-01 |
| 20100078716 | Semiconductor component and method for producing a semiconductor component - A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench. | 2010-04-01 |
| 20100078717 | VERTICAL MOS TRANSISTOR AND METHOD THEREFOR - In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor. | 2010-04-01 |
| 20100078718 | SEMICONDUCTOR DEVICE AND METHODS FOR PRODUCING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a trench, a buried insulated source electrode arranged in a bottom portion of the trench, a first gate electrode and a second gate electrode arranged in an upper portion of the trench and spaced apart from one another. A surface gate contact extends into the upper portion of the trench and is in physical and electrical contact with the first gate electrode and second gate electrode. | 2010-04-01 |
| 20100078719 | SEMICONDUCTOR DEVICE - A semiconductor device in which a desired device is formed, comprising a semiconductor substrate having a first impurity region of a first conductivity type provided around an edge of a region in which the desired device is formed, and a second impurity region of the first conductivity type provided in a scribe region of the semiconductor substrate; wherein a channel stopper is formed between the first impurity region and the second impurity region. | 2010-04-01 |
| 20100078720 | Semiconductor device and method for manufacturing the same - There is provided a semiconductor device including a field effect transistor. The field effect transistor includes a p-type low concentration region formed over a surface of a substrate, an n-type drain-side diffusion region and an n-type source-side diffusion region formed over a surface of the p-type low concentration region, an element isolation insulating layer, and another element isolation insulating layer. A p-type high concentration region, which has an impurity concentration higher than the impurity concentration of the p-type low concentration region, is formed below the n-type source-side diffusion region in the p-type low concentration region over a range at least from one end, which is opposite to the other end facing to the channel region, of the source-side diffusion region to one end, which is facing to the channel region, of the second element isolation insulating layer, when seen in a plan view. | 2010-04-01 |
| 20100078721 | SEMICONDUCTOR DEVICE - A field-effect transistor ( | 2010-04-01 |
| 20100078722 | Method for fabricating high-speed thin-film transistors - This invention provides methods for fabricating high speed TFTs from silicon-on-insulator and bulk single crystal semiconductor substrates, such as Si(100) and Si(110) substrates. The TFTs may be designed to have a maximum frequency of oscillation of 3 GHz, or better. | 2010-04-01 |
| 20100078723 | NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME - Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate. | 2010-04-01 |
| 20100078724 | TRANSISTOR-TYPE PROTECTION DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF THE SAME - A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region. | 2010-04-01 |
| 20100078725 | Standard Cell without OD Space Effect in Y-Direction - An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region. | 2010-04-01 |
| 20100078726 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor diffusion region of a first transistor, a second semiconductor diffusion region of a second transistor, and a third semiconductor diffusion region that connects the first and second semiconductor diffusion regions to each other. | 2010-04-01 |
| 20100078727 | eFuse and Resistor Structures and Method for Forming Same in Active Region - A semiconductor fabrication process and apparatus are provided for forming passive devices, such as a fuse ( | 2010-04-01 |
| 20100078728 | RAISE S/D FOR GATE-LAST ILD0 GAP FILLING - The present disclosure provides an integrated circuit having metal gate stacks. The integrated circuit includes a semiconductor substrate; a gate stack disposed on the semiconductor substrate, wherein the gate stack includes a high k dielectric layer and a first metal layer disposed on the high k dielectric layer; and a raised source/drain region configured on a side of the gate stack and formed by an epitaxy process, wherein the semiconductor substrate includes a silicon germanium (SiGe) feature underlying the raised source/drain region. | 2010-04-01 |
