13th week of 2022 patent applcation highlights part 71 |
Patent application number | Title | Published |
20220102535 | Method of Forming Backside Power Rails - A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact. | 2022-03-31 |
20220102536 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: implanting a P-type impurity from a region where the first conductor film is formed toward an inside of the semiconductor substrate with a first acceleration energy; forming a nitride film provided with a first opening on the first conductor film; forming an insulating film with a second opening from which the first conductor film is exposed; forming a second conductor film to fill the second opening of the insulating film; removing the nitride film and a portion of the first conductor film positioned below the nitride film to expose the oxide film in a peripheral area of a formation region of the insulating film; and implanting the P-type impurity from a region from which the oxide film is exposed toward an inside of the semiconductor substrate with a second acceleration energy smaller than the first acceleration energy. | 2022-03-31 |
20220102537 | BIPOLAR JUNCTION DEVICE - The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature. | 2022-03-31 |
20220102538 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to one embodiment includes an IGBT having a p-type collector layer and an n-type field stop layer on a back surface of a silicon substrate. The n-type field stop layer is selectively provided on an upper side of the p-type collector layer such that a first end portion of the n-type field stop layer is separated from a first side surface of the silicon substrate by a predetermined distance, and an n-type drift layer is provided between the first side surface of the silicon substrate and the first end portion of the n-type field stop layer. An impurity concentration of the n-type drift layer is lower than an impurity concentration of the n-type field stop layer. | 2022-03-31 |
20220102539 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies. | 2022-03-31 |
20220102540 | GAN-HEMT DEVICE WITH SANDWICH STRUCTURE AND METHOD FOR PREPARING THE SAME - A GaN-HEMT device with a sandwich structure and a method for preparing the same are provided. The GaN-HEMT device includes an epitaxial layer and electrodes, wherein the epitaxial layer includes a GaN channel layer ( | 2022-03-31 |
20220102541 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure. | 2022-03-31 |
20220102542 | FLEXIBLE MICROWAVE POWER TRANSISTOR AND PREPARATION METHOD THEREOF - The present disclosure provides a flexible microwave power transistor and a preparation method thereof. In view of great lattice mismatch and poor performance of a device prepared with a Si substrate in an existing preparation method, the preparation method of the present disclosure grows a gallium nitride high electron mobility transistor (GaN HEMT) layer on a rigid silicon carbide (SiC) substrate to avoid lattice mismatch between a silicon (Si) substrate and gallium nitride (GaN), improving performance of the flexible microwave power transistor. Moreover, in view of problems such as low output power, power added efficiency and power gain with the existing device preparation method, the present disclosure retains part of the rigid SiC substrate and grows a flexible substrates at room temperature to prepare a high-quality device. The present disclosure has greatly improved power output capability, efficiency and gain, and basically unchanged performance of device under 0.75% of stress. | 2022-03-31 |
20220102543 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device | 2022-03-31 |
20220102544 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, POWER CIRCUIT, AND COMPUTER - A semiconductor device according to an embodiment includes a nitride semiconductor layer; an insulating layer; a first region disposed between the nitride semiconductor layer and the insulating layer and containing at least one element of hydrogen and deuterium; and a second region disposed in the nitride semiconductor layer, adjacent to the first region, and containing fluorine. | 2022-03-31 |
20220102545 | NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR PACKAGE - Provided is a nitride semiconductor device | 2022-03-31 |
20220102546 | NON-VOLATILE MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory structure includes a substrate, a tunnel dielectric layer on the substrate, and several separate gate structures on the substrate. The gate structures are disposed within an array region of the substrate. Each gate structure includes a floating gate and a control gate on the floating gate. A first dielectric layer is formed above the substrate and covers the top surface of the tunnel dielectric layer. The first dielectric layer also covers the side surfaces and the top surface of each gate structure. Gaps between portions of the first dielectric layer on the side surfaces of two adjacent gate structures are fully filled with the air to form air gaps. Several insulating blocks are formed on the first dielectric layer, and they correspond to the gate structures. A second dielectric layer is formed on the insulating blocks and covers the insulating blocks and the air gaps. | 2022-03-31 |
20220102547 | Semiconductor Die and Method of Manufacturing the Same - A semiconductor die is described. The semiconductor die includes a semiconductor body having an active region, a metallization formed on the semiconductor body, and a passivation formed on the metallization. The metallization includes at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The passivation includes a silicon oxide layer. Corresponding methods of manufacturing and using the semiconductor die are also described. | 2022-03-31 |
20220102548 | SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME - This application relates to semiconductor die including: a transistor device formed in an active area of a semiconductor body and having a channel region, a gate region, and a field electrode region, the gate region arranged laterally aside the channel region and having a gate electrode for controlling a current flow in the channel region, the gate electrode formed in a gate trench extending into the semiconductor body; and an additional device formed in an additional device area of the semiconductor body. A recess extends into the semiconductor body in the additional device area, and a semiconductor material is arranged in the recess in which the additional device is formed. | 2022-03-31 |
20220102549 | SILICON CARBIDE DEVICE WITH TRANSISTOR CELL AND CLAMP REGION - A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode. | 2022-03-31 |
20220102550 | METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A metal-oxide-semiconductor device can include: a base layer; a source region extending from an upper surface of the base layer to internal portion of the base layer and having a first doping type; a gate structure located on the upper surface of the base layer and at least exposing the source region, and a semiconductor layer located on the upper surface of the base layer and having the first doping type, where the semiconductor layer is used as a partial withstand voltage region of the device, and the source region is located at a first side of the gate structure, the semiconductor layer is located at a second side of the gate structure, and the first side and the second side of the gate structure are opposite to each other. | 2022-03-31 |
20220102551 | LDMOS transistor having vertical floating field plate and manufacture fhereof - The present application provides a LDMOS transistor having a floating vertical field plate (VFP) and a manufacturing method thereof. The floating VFP comprises a floating field plate polysilicon layer and a laminated structure. The laminated structure comprises a stack of alternate layers of insulating material and ferroelectric material, and in the laminated structure, an outermost layer and an innermost layer are the insulating material. In the present application, the polarization in the ferroelectric material is set in the floating VFP with smaller size, the polarization of the ferroelectric layer enhances the “charge sharing” effect to produce higher breakdown voltage when the transistor is off; and the polarization of the ferroelectric material layer induces more electrons in the drift zone to reduce on resistance when the transistor is on. Accordingly, the increase of breakdown voltage and the reduction of on resistance can be achieved simultaneously. | 2022-03-31 |
20220102552 | HIGH PERFORMANCE FLOATING BODY VFET WITH DIELECTRIC CORE - Aspects of the present disclosure provide a floating body vertical field effect transistor with dielectric core and a method for fabricating the same. The floating body vertical field effect transistor can include a first semiconductor device including sidewall structures of a first gate metal sandwiched by dielectric layers, a first epitaxially grown channel surrounded by the sidewall structures and can include a second semiconductor device formed on the same substrate adjacent to the first semiconductor device; a salicide layer or doped layer formed between the first and second semiconductor devices and metallization contacting each of the S/D regions and the gate regions. The floating body vertical field effect transistor may include a P+ epitaxially grown channel formed on the same substrate adjacent to an N+ epitaxially grown channel, the P+ epitaxially grown channel separated from N+ epitaxially grown channel by a diffusion break. | 2022-03-31 |
20220102553 | DAMAGE IMPLANTATION OF CAP LAYER - A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer. | 2022-03-31 |
20220102554 | GATE AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Gate and fin trim isolation for advanced integrated circuit structure fabrication is described. For example, a method of fabricating an integrated circuit structure includes forming a plurality of fins along a first direction, removing a portion of one of the plurality of fins to form a trench, forming an isolation structure in the trench, the isolation structure extending above the one of the plurality of fins, forming a gate structure over the plurality of fins, the gate structure along a second direction orthogonal to the first direction, forming a dielectric spacer along sidewalls of the gate structure and the isolation structure, and, subsequent to forming the dielectric spacer, forming epitaxial source or drain structures in or on the plurality of fins. | 2022-03-31 |
20220102555 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen. | 2022-03-31 |
20220102556 | TRIPLE-GATE MOS TRANSISTOR AND METHOD FOR MANUFACTURING SUCH A TRANSISTOR - A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor. | 2022-03-31 |
20220102557 | SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES - Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin. | 2022-03-31 |
20220102558 | SEMICONDUCTOR DEVICE - A Semiconductor device includes a semiconductor substrate, an insulating film, a first conductive film, a ferroelectric film, an insulating layer, a first plug and a second plug. The semiconductor substrate includes a source region and a drain region which are formed on a main surface thereof. The insulating film is formed on the semiconductor substrate such that the insulating film is located between the source region and the drain region in a plan view. The first conductive film is formed on the insulating film. The ferroelectric film is formed on the first conductive film. The insulating layer covers the first conductive film and the ferroelectric film. The first plug reaches the first conductive film. The second plug reaches the ferroelectric film. A material of the ferroelectric film includes hafnium and oxygen. In plan view, a size of the ferroelectric film is smaller than a size of the insulating film. | 2022-03-31 |
20220102559 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR DEVICE - Disclosed are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a substrate; an active region extending vertically on the substrate, wherein the active region includes a first source/drain layer, a channel layer and a second source/drain layer that are sequentially stacked; a gate stack formed around at least part of an outer peripheral sidewall of the channel layer. A sidewall of the gate stack close to the channel layer is aligned with the outer peripheral sidewall of the channel layer, so as to occupy substantially a same range in a vertical direction, and a part of the gate stack close to the channel layer has a shape that gradually tapers as getting close to the channel layer. | 2022-03-31 |
20220102560 | THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE - A first thin-film transistor includes a polysilicon film. A second thin-film transistor includes an oxide semiconductor film. A first insulating film is located upper than the polysilicon film and the oxide semiconductor film. The first insulating film is in contact with the oxide semiconductor film and covers at least a part of the polysilicon film and at least a part of the oxide semiconductor film. A second insulating film is located upper than the first insulating film and contains hydrogen at a concentration higher than the first insulating film. The first insulating film includes a first part and a second part. The first part includes a part covering the at least a part of the polysilicon film. The second part includes a part covering the at least a part of the oxide semiconductor film. The first part is thinner than the second part. | 2022-03-31 |
20220102561 | Photodetector - A photodetector having a sufficient ESD withstand voltage is provided. An embodiment of a photodetector includes a plurality of photodiodes including germanium or a germanium compound in a light absorption layer, and a plurality of heaters configured to apply heat to the light absorption layer of each of the plurality of photodiodes, in which the plurality of heaters are connected in series, the plurality of heaters are connected in parallel, or a plurality of sets of the plurality of heaters serially connected are connected in parallel. | 2022-03-31 |
20220102562 | Optoelectronic Sensor Arrangement and Optical Measuring Method - In an embodiment an optoelectronic sensor arrangement includes a carrier substrate, an illuminating device, a frequency-selective optical element and a photodetector, wherein the illuminating device and the photodetector form a stacked arrangement on or with the carrier substrate, wherein the frequency-selective optical element is arranged between the illuminating device and the photodetector, wherein the photodetector is arranged in a cavity of the carrier substrate which is covered by the illuminating device and/or the frequency-selective optical element, and wherein the frequency-selective optical element includes a divider mirror and an optical filter. | 2022-03-31 |
20220102563 | MICROSTRUCTURE ENHANCED ABSORPTION PHOTOSENSITIVE DEVICES - Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more. | 2022-03-31 |
20220102564 | FOUR JUNCTION METAMORPHIC MULTIJUNCTION SOLAR CELLS FOR SPACE APPLICATIONS - A method of fabricating four junction solar cell wherein the selection of the composition of the subcells and their band gaps maximizes the efficiency at high temperature (in the range of 50 to 100 degrees Centigrade) in deployment in space at a specific predetermined time after initial deployment (referred to as the beginning of life or BOL), such predetermined time being referred to as the end-of-life (EOL), and being at least five years after the BOL, such selection being designed not to maximize the efficiency at BOL but to increase the solar cell efficiency at the EOL while disregarding the soar cell efficiency achieved at the BOL, such that the solar cell efficiency designed at the BOL is less than the solar cell efficiency at the BOL that would be achieved if the selection were designed to maximize the solar cell efficiency at the BOL. | 2022-03-31 |
20220102565 | PHOTOVOLTAIC CELL, MANUFACTURING METHOD THEREOF, AND PHOTOVOLTAIC BATTERY MODULE - The purpose of the present invention is to improve the reliability of a photovoltaic cell. In the present invention, a photovoltaic cell (CL) comprises a back electrode (BE), a p-type semiconductor layer (semiconductor substrate | 2022-03-31 |
20220102566 | COLOR-CODED PATTERNS FOR EPITAXIAL LIFT-OFF (ELO) FILMS BACKGROUND - The present disclosure provides a photovoltaic device formed according to a color code scheme and methods of manufacturing thereof. In an example, the photovoltaic device may include one or more photovoltaic cells formed according to one or more applications of the photovoltaic cells. The photovoltaic device may also include a rear contact layer formed on a rear surface of the one or more photovoltaic cells, the rear contact layer including one or both of a composition or a thickness configured to produce a unique color code in the color code scheme that is visible in areas of the photovoltaic device outside of areas covered by the photovoltaic cells and corresponding to the particular product configuration of the photovoltaic device. The photovoltaic device may also include a back reflector formed on a rear surface of the rear contact layer. | 2022-03-31 |
20220102567 | METAL OXYNITRIDE BACK CONTACT LAYERS FOR PHOTOVOLTAIC DEVICES - According to the embodiments provided herein, back contacts for photovoltaic devices can include one or more metal oxynitride layers. | 2022-03-31 |
20220102568 | Solar Cell And Photovoltaic Module - A solar cell and a photovoltaic module including the solar cell. The solar cell includes: a semiconductor substrate including a first surface and a second surface opposite to each other; a first dielectric layer located on the first surface; a first N+ doped layer located on a surface of the first dielectric layer; a first passivation layer located on a surface of the first N+ doped layer; a first electrode located on a surface of the first passivation layer; a second dielectric layer located on the second surface; a first P+ doped layer located on a surface of the second dielectric layer; a second passivation layer located on a surface of the first P+ doped layer; and a second electrode located on a surface of the second passivation layer. | 2022-03-31 |
20220102569 | MONOLITHIC MULTIJUNCTION POWER CONVERTER - Resonant cavity power converters for converting radiation in the wavelength range from 1 micron to 1.55 micron are disclosed. The resonant cavity power converters can be formed from one or more lattice matched GaInNAsSb junctions and can include distributed Bragg reflectors and/or mirrored surfaces for increasing the power conversion efficiency. | 2022-03-31 |
20220102570 | P-I-N PHOTODETECTOR - A photodetector which comprises a measurement layer ( | 2022-03-31 |
20220102571 | AVALANCHE PHOTODETECTOR (VARIANTS) AND METHOD FOR MANUFACTURING THE SAME (VARIANTS) - An avalanche photodetector (APD) is proposed, wherein a photoconverter and at least one avalanche amplifier are located on the same wafer, its multiplication layer covers the entire surface of the conductive wafer, and its contact layer is formed in some region of the multiplication layer. Outside the contact layer, the multiplication layer functions as a photoconverter, thus facilitating the photocarriers getting into the avalanche amplifier. A dielectric-filled circular groove surrounding the avalanche amplifier suppresses photoelectric communication noises generated by neighboring avalanche amplifiers, thus allowing to manufacture multi-channel avalanche instruments with higher threshold sensitivity. | 2022-03-31 |
20220102572 | P-OHMIC CONTACT STRUCTURE AND PHOTODETECTOR USING THE SAME - A photodetector includes an UV transparent n-type structure, an UV transparent p-type structure, and a photon absorbing region sandwiched between the n-type structure and the p-type structure; a p-contact layer formed on the p-type structure; and a p-ohmic contact of a thickness in the range of 0.2-100 nm formed on the p-contact layer, wherein the p-ohmic contact comprises one or more layer of metal oxide. | 2022-03-31 |
20220102573 | LIGHT DETECTING DEVICE AND METHOD OF MANUFACTURING SAME - A light detecting device includes a light absorbing layer configured to absorb light in a wavelength range from visible light to short-wave infrared (SWIR); a first semiconductor layer provided on a first surface of the light absorbing layer; an anti-reflective layer provided on the first semiconductor layer and comprising a material having etch selectivity with respect to the first semiconductor layer; and a second semiconductor layer provided on a second surface of the light absorbing layer. The first semiconductor layer has a thickness less than 500 nm so as to be configured to allow light to transmit therethrough in the wavelength range from visible light to SWIR. | 2022-03-31 |
20220102574 | Photodetector - The present invention is to provide a GePD, the optical sensitivity of which is independent from a temperature, and to achieve a photodetector in which heat applied from heaters is constant even when a plurality of GePDs are provided and in which a temperature and sensitivity of each of the GePDs are the same. The photodetector includes germanium photoreceivers including a silicon substrate, a lower clad layer, a silicon core layer, a silicon waveguide layer, a germanium layer, an upper clad layer, and electrodes. In the photodetector, two or more germanium photoreceivers are arranged adjacent to each other on the silicon substrate, and the photodetector includes resistors embedded in the upper clad layer to cover or surround respective germanium layers of the two or more germanium photoreceivers arranged adjacent to each other, the resistors being made of a metal or a metal compound. | 2022-03-31 |
20220102575 | SENSOR PACKAGE ARRAY, METHOD OF MANUFACTURING THE SAME, AND SENSOR PACKAGE STRUCTURE - A sensor package array, a method of manufacturing the same, and a sensor package structure are provided. The method of manufacturing a sensor package array including: disposing a plurality of sensors on a substrate sequentially in an array; electrically connecting the plurality of sensors to the substrate; disposing a plastic shield on the substrate, so as to form a plurality of channels and a plurality of accommodating grooves among the plastic shield, the substrate, and the plurality of sensors; and filling a sealing material in the plurality of accommodating grooves, through the plurality of channels. | 2022-03-31 |
20220102576 | OPTICAL SENSOR PACKAGE AND MANUFACTURING METHOD FOR THE SAME - A manufacturing method of an optical sensor package includes: disposing a chip on a circuit board, the chip including a light emitting area and a light receiving area; disposing at least one light emitting element, which is electrically connected to the circuit board, on the light emitting area of the chip; coating a light blocking material between the light emitting area and the light receiving area; filling a light permeable material that covers the circuit board, the chip, the light blocking material, and the at least one light emitting element; removing a part of the light permeable material disposed between the light emitting area and the light receiving area, forming a first recess and expose the light blocking material; and filling an anti-light-leakage material in the first recess, to form a lateral light blocking structure through stacking the anti-light-leakage material and the light blocking material. | 2022-03-31 |
20220102577 | DISTRIBUTED BRAGG REFLECTOR STRUCTURES IN MULTIJUNCTION SOLAR CELLS - A multijunction solar cell and its method of fabrication, including an upper and a lower solar subcell each having an emitter layer and a base layer forming a photoelectric junction; a near infrared (NIR) wideband reflector layer disposed below the upper subcell and above the lower subcell for reflecting light in the spectral range of 900 to 1050 nm which represents unused and undesired solar energy and thereby reducing the overall solar energy absorptance in the solar cell and providing thermodynamic radiative cooling of the solar cell when deployed in space outside the atmosphere. | 2022-03-31 |
20220102578 | DEVICE ARCHITECTURES HAVING ENGINEERED STRESSES - The present disclosure relates to a method that includes depositing a spalling layer onto a surface that includes a substrate, depositing a device comprising a III-V material onto the spalling layer, resulting in the forming of a stack, and dividing the stack substantially at a plane positioned within the spalling layer to form a first portion that includes the substrate and a second portion that includes the PV device, where the spalling layer includes a first layer configured to provide a compressive stress and a second layer configured to provide a tensile stress, the first layer and the second layer form an interface, the dividing occurs as result of the interface, and the compressive stress and the tensile stress are strain-balanced so that a total strain within the spalling layer is approximately zero. | 2022-03-31 |
20220102579 | SEMICONDUCTOR LIGHT EMITTING ELEMENT WITH MAGNETIC LAYER, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME - A semiconductor light emitting element can include an n-type semiconductor layer, a p-type semiconductor layer in a first region on the n-type semiconductor layer, a p-type electrode on the p-type semiconductor layer, an n-type electrode in a second region different from the first region on the n-type semiconductor layer, a magnetic layer under the n-type semiconductor layer, a reflective layer between the n-type semiconductor layer and the magnetic layer, and a passivation layer surrounding the n-type semiconductor layer, the p-type semiconductor layer, the p-type electrode, the n-type electrode, and the magnetic layer. | 2022-03-31 |
20220102580 | WAFER BONDING FOR EMBEDDING ACTIVE REGIONS WITH RELAXED NANOFEATURES - A method for fabricating a device, as well as the device itself, which includes growing a bonding layer on a first wafer or substrate, wherein the bonding layer includes at least partially relaxed features; and then bonding a second wafer or substrate to the features in on the first wafer or substrate, to cap and contact the features with separately grown material. | 2022-03-31 |
20220102581 | LIGHT-EMITTING DEVICE - A light-emitting devise includes first and second type semiconductor layers, an active layer interposed therebetween, a current blocking layer disposed on the first type semiconductor layer and including a first strip portion, and a first electrode disposed on the current blocking layer and including a first electrode pad, a first electrode end portion distal from the first electrode pad, and a first electrode extension portion extending between the first electrode pad and the first electrode end portion. The first strip portion of the current blocking layer is located beneath the first electrode extension portion, and has a widened section having a width that gradually increases in a direction away from the first electrode pad. | 2022-03-31 |
20220102582 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a carrier, a bonding structure, a semiconductor stack, a supporting element and a bridge layer. The bonding structure is on the carrier and has an upper surface. The semiconductor stack is on the bonding structure. The supporting element is on the bonding structure and has a side wall. The bridge layer has a first portion directly connected to the supporting element, a second portion connected to the first portion and a third portion connected to the second portion. The second portion and the third portion of the bridge layer are suspended above the upper surface of the bonding structure. The first portion of the bridge layer directly contacts the side wall of the supporting element. | 2022-03-31 |
20220102583 | -LED, -LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2022-03-31 |
20220102584 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An embodiment provides a display device including: a substrate; a first electrode and a second electrode spaced from each other on the substrate; and a first light emitting element and a second light emitting element between the first electrode and the second electrode, wherein the first light emitting element and the second light emitting element are electrically insulated from each other, and the first light emitting element and the second light emitting element have different lengths. | 2022-03-31 |
20220102585 | DISPLAY DEVICE - A display device comprises a substrate, a first electrode on the substrate and extending in a first direction, a second electrode on the substrate and extending in the first direction, the second electrode being spaced apart from the first electrode in a second direction, a first insulating layer on the first electrode and the second electrode, light-emitting elements on the first insulating layer, the light-emitting elements being disposed on the first electrode and the second electrode, a second insulating layer disposed on the light-emitting elements, a first contact electrode disposed on the first electrode and electrically contacting the light-emitting elements, and a second contact electrode disposed on the second electrode and electrically contacting the light-emitting elements. The second insulating layer comprises patterns that cover at least part of the light-emitting elements and are spaced apart from one another in the first direction. | 2022-03-31 |
20220102586 | LIGHT-EMITTING ELEMENT - A light-emitting element includes: a semiconductor stack having a triangular shape in a top plan view, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first and seconds semiconductor layers; a first electrode located on the first semiconductor layer and including a first connecting portion and a first extension extending from the first connecting portion; and a second electrode located on the second semiconductor layer and including a second connecting portion and a second extension extending from the second connecting portion. The first extension includes a first portion extending from the first connecting portion toward the second connecting portion. The second extension includes a second portion including a portion extending along a first side, a third portion including a portion extending along a second side, and fourth and fifth portions each including a portion extending along a third side. | 2022-03-31 |
20220102587 | LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE - A light-emitting element includes: a semiconductor layered body including first and second semiconductor layers, the first semiconductor layer having a plurality of exposed portions exposed from the second semiconductor layer at locations inward of an outer periphery of the second semiconductor layer; an insulating film covering the semiconductor layered body and defining a first opening above the exposed portions and a second opening above a part of the second semiconductor layer; first and second electrodes electrically connected to the first and second semiconductor layer through the first and second openings, respectively; first bumps and second bumps disposed on the first and second electrodes, respectively. The first electrode and the second electrode have a first surface and a second surface, respectively, that are located at the same height from the second semiconductor layer. The first and second bumps are respectively connected to the first and second surfaces. | 2022-03-31 |
20220102588 | P-OHMIC CONTACT STRUCTURE AND LIGHT EMITTING DEVICE USING THE SAME - A light emitting diode includes an n-type structure, a p-type structure, and an active-region sandwiched between the n-type structure and the p-type structure; a p-contact layer formed on the p-type structure; and a p-ohmic contact of a thickness in the range of 0.2-100 nm formed on the p-contact layer, wherein the p-ohmic contact comprises one or more layer of metal oxide. | 2022-03-31 |
20220102589 | DISPLAY DEVICE - A display device includes a light emitting diode LED element having a horizontal length in an X-axis direction and a vertical length in a Y-axis direction, a driving element connected to the LED element, and a reflective functional layer positioned to overlap an upper portion or a lower portion of the LED element, wherein the reflective functional layer includes a central area overlapping the LED element, an outer area including a graduation smaller than the horizontal length or the vertical length of the LED element, and a peripheral area between the central area and the outer area. Accordingly, it is possible to reduce a contact defect of the light emitting diode and the driving element by checking a position where the light emitting diode is attached on a substrate and a degree of misalignment. | 2022-03-31 |
20220102590 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A method for manufacturing a light emitting device includes: preparing a light-shielding frame defining a through-hole, and having at least one convex portion; supplying a light reflecting resin so that the convex portion is at least partially covered; preparing a light-transmissive member having a first surface with an outer periphery smaller than an inner periphery of the first main surface, a first side surface contiguous with the first surface, a second side surface located outside of the first side surface, and a third surface contiguous with the first and second side surfaces; bringing the third surface into contact with the convex portion, or with the light reflecting resin in contact with the convex portion, so that the light reflecting resin is disposed between the first side surface and an inside surface of the light-shielding frame; curing the light reflecting resin; and joining light emitting elements and the light-transmissive member. | 2022-03-31 |
20220102591 | ELECTRONIC PACKAGE - The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated. | 2022-03-31 |
20220102592 | LIGHT EMITTING DEVICE PACKAGE HAVING LEAD ELECTRODE WITH VARYING HEIGHT - A package for mounting a light emitting element includes: a first lead electrode defining a portion of a bottom of a recess and comprising a base member and a plating disposed on the base member, and wherein the first lead electrode comprises, in a plan view: a first region, a second region surrounding a periphery of the first region, wherein, in a height direction, an upper surface of the base member in an entirety of the second region is higher than an upper surface of the base member in the first region, and a third region surrounding at least a portion of a periphery of the second region, wherein, in the height direction, an upper surface of the base member in the third region is lower than the upper surface of the base member in the entirety of the second region; a second lead electrode; and a resin molded body. | 2022-03-31 |
20220102593 | ULTRA-THIN PHOSPHOR LAYERS PARTIALLY FILLED WITH SI-BASED BINDERS - A light emitting device and method of forming a light emitting device are disclosed. The light emitting device includes a light emitting diode and a phosphor layer formed on the light emitting diode, the phosphor layer including a plurality of phosphor particles formed in a particle layer, the particle layer including interstices between the phosphor particles, and a matrix material disposed in a portion of the interstices. A plurality of cavities may be disposed in a remaining portion of the interstices. | 2022-03-31 |
20220102594 | SOLAR SPECTRAL WAVELENGTH CONVERTING MATERIAL AND SOLAR CELL COMPRISING SAME - A solar spectral wavelength converting material with improved efficiency and a solar cell including the same. According to an embodiment, a solar spectral wavelength converting material includes an aluminum hydroxide precursor and an aromatic ring compound or a derivative including the same. | 2022-03-31 |
20220102595 | PHOTORESIST PATTERNING PROCESS SUPPORTING TWO STEP PHOSPHOR-DEPOSITION TO FORM AN LED MATRIX ARRAY - A method is described for low temperature curing of silicone structures, including the steps of providing patterning photoresist structures on a substrate. The photoresist structures define at least one open region that can be at least partially filled with a condensation cure silicone system. Vapor phase catalyst deposition is used to accelerate the cure of the condensation cure silicone, and the photoresist structure is removed to leave free standing or layered silicone structures. Phosphor containing silicone structures that are coatable with a reflective metal or other material are enabled by the method. | 2022-03-31 |
20220102596 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a first light-emitting element and a second light-emitting element, each configured to be independently driven; a wall portion located between the first light-emitting element and the second light-emitting element; a first light-transmissive member separated from the second light-emitting element by the wall portion and covering at least a portion of lateral surfaces of the first light-emitting element, wherein the first light-transmissive member contains a first wavelength converting member; and a second light-transmissive member covering the first light-emitting element, the second light-emitting element, and the first light-transmissive member in a plan view, wherein the second light-transmissive member contains a second wavelength converting member. A peak emission wavelength of the first wavelength converting member is longer than a peak emission wavelength of the second wavelength converting member. | 2022-03-31 |
20220102597 | LIGHT EMITTING DEVICES HAVING PROFILED SIDE SURFACES - A light emitting diode package, including a substrate having a side surface, wherein the substrate is adapted for mounting one or more light emitting diode light sources thereon; one or more light emitting diode light sources mounted to the substrate; a light conversion component that converts incident light emitted from the one or more light emitting diode light sources; a light reflective encapsulation component having an outermost side surface; and wherein the outermost side surface of the light reflective encapsulation component forms a step with the side surface of the substrate, and wherein both surfaces are non-coplanar. | 2022-03-31 |
20220102598 | OPTOELECTRONIC DEVICE WITH MICROMETRIC OR NANOMETRIC LIGHT-EMITTING DIODE ON WHICH AN OPTICAL LENS IS MOUNTED - An optoelectronic device includes at least one light-emitting diode having a three-dimensional shape having a height along a longitudinal axis and having a first longitudinal dimension measured along the longitudinal axis and at least a second transverse dimension corresponding to a dimension of the three-dimensional shape measured perpendicular to the longitudinal axis. The first longitudinal dimension and the second transverse dimension are each less than or equal to substantially 20 μm. The optoelectronic device has at least one optical lens capable of transforming the light rays emitted by the light-emitting diode which pass through the optical lens. | 2022-03-31 |
20220102599 | DEEP MOLDED REFLECTOR CUP USED AS COMPLETE LED PACKAGE - A light emitting device is disclosed. The light emitting device comprises a metal lead frame including a first lead and a second lead. The light emitting device comprises a first bonding pad on the first lead. The light emitting device comprises a second bonding pad on the second lead. The light emitting device comprises a structure molded on the first lead and the second lead. The structure includes walls extending from a first area of the structure proximate to the metal lead frame. The light emitting device comprises a light emitting diode (LED) die disposed on the first area of the structure. The LED die includes a first electrode electrically coupled to the first bonding pad and a second electrode electrically coupled to the second bonding pad. The light emitting device comprises an encapsulant partially filling the structure. | 2022-03-31 |
20220102600 | LEAD FRAME AND HOUSING SUB-ASSEMBLY FOR USE IN A LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A lead frame and housing sub-assembly for use in a light emitting diode package, including: a lead frame, wherein the lead frame includes a substrate metal alloy having a top surface and a bottom surface, and wherein the top surface and the bottom surface of the substrate have been pre-plated with a layer of nickel; and a housing, wherein the housing includes a top surface and a bottom surface, and wherein at least a portion of the bottom surface of the housing contacts the top surface of the lead frame that has been pre-plated with the layer of nickel. | 2022-03-31 |
20220102601 | ADDITIVE MANUFACTURING OF ELECTRICAL CIRCUITS - A method of manufacturing an electronics assembly includes forming a base layer using an additive manufacturing process, forming a first thermally and electrically conductive intermediate layer onto the base layer using an additive manufacturing process, placing an electronics component onto the first thermally and electrically conductive intermediate layer, the electronics component comprising a plurality of vias, forming a second thermally and electrically conductive intermediate layer over the first thermally and electrically conductive intermediate layer and over at least a portion of the electronics component using an additive manufacturing process, wherein a material of the second thermally and electrically conductive intermediate layer extends through the vias to contact the first thermally and electrically conductive intermediate layer and the vias, thereby forming a bond therebetween, and forming a protective layer over at least a portion of the second thermally and electrically conductive intermediate layer using an additive manufacturing process. | 2022-03-31 |
20220102602 | MICRO LIGHT EMITTING DEVICE, DISPLAY APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE MICRO LIGHT EMITTING DEVICE - A micro light emitting device, a display apparatus including the same, and a method of manufacturing the micro light emitting device are disclosed. The micro light emitting device includes a first type semiconductor layer; a light emitting layer provided on the first type semiconductor layer; a second type semiconductor layer provided on the light emitting layer; one or more first type electrodes provided on the second type semiconductor layer; one or more second type electrodes provided on the second type semiconductor layer and spaced apart from the one or more first type electrodes; and a bonding spread prevention portion provided between the one or more first type electrodes and the one or more second type electrodes. | 2022-03-31 |
20220102603 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - Provided is a method of fabricating a semiconductor package. The method of fabricating the semiconductor package include preparing a lower element including a lower substrate, a lower electrode, an UBM layer, and a reducing agent layer, providing an upper element including an upper substrate, an upper electrode, and a solder bump layer, providing a pressing member on the upper substrate to press the upper substrate to the lower substrate, and providing a laser beam passing through the pressing member to bond the upper element to the lower element. | 2022-03-31 |
20220102604 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - A display device includes a first electrode disposed on a substrate, a second electrode disposed on the substrate, and spaced apart from and facing the first electrode, at least one light emitting element disposed between the first electrode and the second electrode, a first conductive contact pattern disposed on the first electrode and electrically contacting the first electrode and an end of the at least one light emitting element, and a second conductive contact pattern disposed on the second electrode and electrically contacting the second electrode and another end of the at least one light emitting element. | 2022-03-31 |
20220102605 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a display panel and a method for manufacturing the same. The method includes the following. A first adhesive layer and a second adhesive layer are disposed sequentially on a surface of a driving substrate, and the first adhesive layer includes conductive particles. Multiple light emitting units arranged in an array are adhered to one side of the second adhesive layer away from the driving substrate. The second adhesive layer is semi-cured. The first adhesive layer and the second adhesive layer are cured, and the multiple light emitting units are electrically connected with the driving substrate through the conductive particles. | 2022-03-31 |
20220102606 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a light-emitting element having an upper surface, and including a plurality of semiconductor light-emitting structures; and a substrate supporting the light-emitting element. The semiconductor light-emitting structures include a first semiconductor light-emitting structure and a second semiconductor light-emitting structure. The substrate includes: an interconnection layer including: a first interconnection portion comprising a first land, a second interconnection portion comprising a second land and a third land, and a third interconnection portion comprising a fourth land, and a first reflective member covering a portion of the interconnection layer and having an opening. The light-emitting element is located inside the opening of the first reflective member as viewed from above. A portion of the first land, a portion of the second land, a portion of the third land, and a portion of the fourth land are exposed in the opening of the first reflective member. | 2022-03-31 |
20220102607 | THERMOELECTRIC MATERIAL AND PREPARATION METHOD THEREFOR - The present invention relates to a thermoelectric material and, specifically, to a thermoelectric material capable of improving the figure of merit and a preparation method therefor. In the present invention, the thermoelectric material may comprise: a matrix compound having a composition of chemical formula 1 or 2; and particles having a composition of chemical formula 3 dispersed in the matrix compound. (AB | 2022-03-31 |
20220102608 | FAST-RATE THERMOELECTRIC DEVICE - A fast-rate thermoelectric device control system includes a fast-rate thermoelectric device, a sensor, and a controller. The fast-rate thermoelectric device includes a thermoelectric actuator array disposed on a wafer, and the thermoelectric actuator array includes a thin-film thermoelectric (TFTE) actuator that generates a heating and/or a cooling effect in response to an electrical current. The sensor is configured to measure a temperature associated with the heating or cooling effect and output a feedback signal indicative of the measured temperature. The controller is in communication with the fast-rate thermoelectric device and the sensor, and is configured to control the electrical current based on the feedback signal. | 2022-03-31 |
20220102609 | THERMO-ELECTRIC CONTROLLED SWITCHING CIRCUIT - A system on an integrated circuit (IC) chip includes an input terminal and a return terminal, a heater, a thermopile, and a switch device. The heater is coupled between the input terminal and the return terminal. The thermopile is spaced apart from the heater by a galvanic isolation region. The switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip. | 2022-03-31 |
20220102610 | METHOD FOR MANUFACTURING A THERMOELECTRIC DEVICE BY ADDITIVE MANUFACTURING OF COMBS TO BE SET IN CONTACT WITH ONE ANOTHER - A method for manufacturing a thermoelectric device where a first part formed in a first doped material and a second part formed in a second doped material each shaped like a comb are manufactured, before being assembled together and electrically connected. Then, the first base of the first part is sectioned into at least one first area and the second base of the second part is sectioned into at least one second area. Each first branch of the first part and each second branch of the second part separated respectively constitute a first element and a second element of a thermoelectric junction, electrically connected via portion of the second base that links them. In addition, each first branch and each second branch separated by a second area constitute a first element and a second element of a thermoelectric junction, electrically connected via the portion of the first base. | 2022-03-31 |
20220102611 | MAGNETIC JOSEPHSON JUNCTION SYSTEM - One example includes a magnetic Josephson junction (MJJ) system. The system includes a first superconducting material layer and a second superconducting material layer each configured respectively as a galvanic contacts. The system also includes a ferrimagnetic material layer arranged between the first and second superconducting material layers and that is configured to exhibit a fixed net magnetic moment at a predetermined operating temperature of the MJJ system. The system also includes a ferromagnetic material layer arranged between the first and second superconducting material layers and that is configured to exhibit a variable magnetic orientation in response to an applied magnetic field. The MJJ system can be configured to store a binary logical value based on a direction of the variable magnetic orientation of the ferromagnetic material layer. The system further includes a spacer layer arranged between the ferromagnetic and the ferrimagnetic material layers. | 2022-03-31 |
20220102612 | VACUUM ENCAPSULATED JOSEPHSON JUNCTION - Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity. | 2022-03-31 |
20220102613 | SUPERCONDUCTING CIRCUIT PROVIDED ON AN ENCAPSULATED VACUUM CAVITY - Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity. | 2022-03-31 |
20220102614 | Silicide passivation of niobium - A superconducting device which includes a substrate, multiple niobium leads formed on the substrate, a niobium silicide (NbSi | 2022-03-31 |
20220102615 | Piezoelectric Actuator and Inspection Method for Piezoelectric Actuator - There is provided a piezoelectric actuator including a vibration plate; first and second piezoelectric layers; individual electrodes; a first common electrode arranged between the vibration plate and the first piezoelectric layer; a second common electrode arranged between the first piezoelectric layer and the second piezoelectric layer; a first surface electrode which is arranged on the second piezoelectric layer and which is in conduction with the first common electrode; and a second surface electrode which is arranged on the second piezoelectric layer and which is in conduction with the second common electrode. The piezoelectric actuator further comprises an inspection electrode which is arranged on the second piezoelectric layer at an end portion of the second piezoelectric layer, which is overlapped with the one of the first and second common electrodes, and which is not in conduction with any of the individual electrodes, and the first and second common electrodes. | 2022-03-31 |
20220102616 | PIEZOELECTRIC COMPONENT, PIEZOELECTRIC APPARATUS AND METHOD FOR MANUFACTURING THE SAME - This application provides a piezoelectric component, a piezoelectric apparatus and a method for manufacturing the same, and relates to the field of piezoelectric technologies. In order to solve a problem of a relatively large misalignment between a piezoelectric component and a target transfer position on a glass substrate occurred after the piezoelectric component is transferred in the related transfer methods, and to improve the transfer accuracy of the piezoelectric component. The piezoelectric component includes: a component body and at least one electrode structure arranged on a side of the component body. The at least one electrode structure includes a plurality of strip-shaped electrode pins, and the plurality of electrode pins is arranged at intervals. | 2022-03-31 |
20220102617 | Piezoelectric Actuator - There is provided piezoelectric actuator including: vibration plate; first and second piezoelectric layers; a plurality of individual electrodes arranged on actuator surface, of the second piezoelectric layer, on first side in first direction of the second piezoelectric layer; first and second common electrodes; first surface electrode arranged on the actuator surface at an end portion in second direction orthogonal to the first direction; second surface electrode arranged on the actuator surface; and non-conductive electrodes arranged at end portions in the second direction of at least two of the actuator surface, and the first and second boundary surfaces, and which are not in conduction with any of the individual electrodes, and the first and second common electrodes. The non-conductive electrodes are arranged at least in an area of an end portion in the second direction of a stack of the vibration plate, and the first and second piezoelectric layers. | 2022-03-31 |
20220102618 | THIN-FILM PIEZOELECTRIC MICROELECTROMECHANICAL STRUCTURE HAVING IMPROVED ELECTRICAL CHARACTERISTICS AND CORRESPONDING MANUFACTURING PROCESS - A piezoelectric microelectromechanical structure is provided with a piezoelectric stack having a main extension in a horizontal plane and a variable section in a plane transverse to the horizontal plane. The stack is formed by a bottom-electrode region, a piezoelectric material region arranged on the bottom-electrode region, and a top-electrode region arranged on the piezoelectric material region. The piezoelectric material region has, as a result of the variable section, a first thickness along a vertical axis transverse to the horizontal plane at a first area, and a second thickness along the same vertical axis at a second area. The second thickness is smaller than the first thickness. The structure at the first and second areas can form piezoelectric detector and a piezoelectric actuator, respectively. | 2022-03-31 |
20220102619 | POLYMER-BASED PIEZOELECTRIC COMPOSITE MATERIAL, PIEZOELECTRIC FILM, PIEZOELECTRIC SPEAKER, AND FLEXIBLE DISPLAY - The present invention provides a polymer-based piezoelectric composite material from which a piezoelectric film capable of outputting a higher sound pressure and exhibiting excellent flexibility even in a low-temperature environment is obtained in a case of using a piezoelectric speaker, a piezoelectric film formed of the polymer-based piezoelectric composite material, and a piezoelectric speaker and a flexible display which are formed of the piezoelectric film. The polymer-based piezoelectric composite material of the present invention is a polymer-based piezoelectric composite material including a polymer matrix which contains a polymer containing a group represented by Formula (1), and piezoelectric particles. | 2022-03-31 |
20220102620 | METHOD, ELECTRONIC APPARATUS, AND SYSTEM FOR DEFECT DETECTION - Aspects of the disclosure provide a method including determining a measurement configuration for one or more piezoelectric devices in an electronic apparatus. The electronic apparatus includes an electronic device mounted on a substrate block using a bonding layer. The one or more piezoelectric devices including a first subset and a second subset are attached to one of the electronic device and the bonding layer. The method includes performing, based on the measurement configuration, a defect measurement on the electronic apparatus by causing the first subset to transmit and the second subset to receive one or more acoustic signals. The method includes determining whether at least one mechanical defect is located in at least one of (i) the bonding layer, (ii) the electronic device, (iii) the substrate block, (iv) interfaces of the electronic device, the bonding layer, and the substrate block based on the received one or more acoustic signals. | 2022-03-31 |
20220102621 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ. | 2022-03-31 |
20220102622 | MAGNETIC RANDOM-ACCESS MEMORY - The present disclosure provides a magnetic random-access memory, comprising: an antiferromagnetic layer; a magnetic tunnel junction disposed on the antiferromagnetic layer and comprising a ferromagnetic layer disposed corresponding to the antiferromagnetic layer; wherein the ferromagnetic layer of the magnetic tunnel junction has in-plane magnetic anisotropy, and an exchange bias field is formed between the antiferromagnetic layer and the ferromagnetic layer by an annealing process. A direction of the exchange bias field is changed by a spin orbit torque, thereby changing a direction of a magnetic moment of the ferromagnetic layer and realizing data writing. The present disclosure can improve a thermal stability of the i-MTJ and reduce a lateral dimension of the i-MTJ, thereby improving a storage density of the magnetic memory. | 2022-03-31 |
20220102623 | MAGNETIC MEMORY STRUCTURE - A magnetic memory structure includes a heavy-metal layer, a plurality of magnetic tunneling junction (MTJ) layer, a conductive layer and an insulation layer. In an example, the pinned-layer of the MTJ layers are arranged in a string form and disposed over the barrier-layer. In an example also disclosed, the pinned-layer, the free-layer of the MTJ layers are arranged in a string form. Whereas the pinned-layers are disposed over the barrier-layer and the free-layers are disposed over the heavy-metal layer. The conductive layer is formed under the heavy-metal layer and includes a first conductive portion and a second conductive portion separated from each other and connected with two end of the heavy-metal layer respectively. The insulation layer fills up an interval between the first conductive portion and the second conductive portion. The conductive layer has an electric conductivity higher than that of the heavy-metal layer. | 2022-03-31 |
20220102624 | ION BEAM ETCHING WITH GAS TREATMENT AND PULSING - One or more layers of a magnetic random access memory (MRAM) stack on a substrate are etched by ion beam etching. An ion beam of an inert gas is generated in an ion beam source chamber and applied to a substrate in a continuous or pulsed manner. Without passing through the ion beam source chamber, a reactive gas is flowed directly into a processing chamber in which the substrate is located, where the reactive gas is pulsed or continuously provided into the processing chamber. The reactive gas may include a carbon-containing gas having a hydroxyl group that is flowed towards the substrate to limit re-deposition of sputtered atoms on exposed surfaces of the substrate from ion beam etching. | 2022-03-31 |
20220102625 | METAL OXIDE LINER FOR CROSS-POINT PHASE CHANGE MEMORY CELL - Phase change memory material stacks having a metal oxide liner for memory integrated circuits, related systems, and methods of fabrication are disclosed. Such phase change memory material stacks include a phase change material and a switching device and the sidewalls of the phase change memory material stacks are lined with a metal oxide to protect the material stacks during manufacture and use and to provide isolation between the material stacks. | 2022-03-31 |
20220102626 | PHASE-CHANGE MEMORY (PCM) INCLUDING LINER REDUCING RESISTANCE DRIFT - A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer. | 2022-03-31 |
20220102627 | PHASE CHANGE MEMORY USING MULTIPLE PHASE CHANGE LAYERS AND MULTIPLE HEAT CONDUCTORS - A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure. | 2022-03-31 |
20220102628 | VARIABLE RESISTANCE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - There are provided a variable resistance memory device and a manufacturing method of the same. The variable resistance memory device includes: a first electrode; a second electrode arranged in a vertical direction from the first electrode; and an oxide layer having an oxygen deficient region extending in the vertical direction between the second electrode and the first electrode. | 2022-03-31 |
20220102629 | Semiconductor structure and manufacturing method thereof - The invention provides a semiconductor structure, the semiconductor structure includes a resistance random access memory (RRAM), a first spacer located at two sides of the RRAM, a second spacer located outside the first spacer, wherein the second spacer contains metal material or metal oxide material, and a third spacer located outside the second spacer. | 2022-03-31 |
20220102630 | RESISTIVE MEMORY CELL - Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions. | 2022-03-31 |
20220102631 | SEMICONDUCTOR FABRICATION METHOD AND SEMICONDUCTOR DEVICE INCLUDING AMORPHOUS SILICON-CONTAINING LINER ON PILLAR SIDEWALLS THEREOF - A semiconductor fabrication method, a semiconductor device and a semiconductor module. The method comprises: providing a stack on a substrate, the stack including a plurality of device layers comprising electrically conductive layers; patterning the stack using an etch to form trenches extending therethrough and pillars between the trenches; providing an a-Si-containing liner on sidewalls of the pillars; filling spaces between the pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form the semiconductor device. The a-Si-containing liner may include a liner made substantially of amorphous silicon, or a liner including a non-uniform distribution of a-Si and silicon nitride. | 2022-03-31 |
20220102632 | ORGANIC ELECTROLUMINESCENCE DEVICE - [Object] An object of the present invention is to provide, as a material for an organic EL device having high efficiency and a high durability, a material for an organic EL device having excellent injection/transport performance of holes, excellent electron blocking capability, excellent stability in a thin-film state, and an excellent durability, and to further provide an organic EL device having high efficiency, a low drive voltage, and a long lifetime by combining the material and various materials for an organic EL device having excellent injection/transport performance of holes and electrons, excellent electron blocking capability, excellent stability in a thin-film state, and an excellent durability so that the properties of the respective materials can be effectively exhibited. | 2022-03-31 |
20220102633 | ORGANIC ELECTROLUMINESCENT DEVICE - The present disclosure relates to an organic electroluminescent device. The organic electroluminescent device of the present disclosure shows high luminous efficiency and good lifespan by comprising a specific combination of the plural kinds of host compounds and a specific hole transport compound. | 2022-03-31 |
20220102634 | METHOD OF PREPARING LIGHT-EMITTING MATERIAL, LIGHT-EMITTING MATERIAL PREPARED BY METHOD, AND LIGHT-EMITTING DEVICE INCLUDING LIGHT-EMITTING MATERIAL - A method of preparing a light-emitting material, the method including mixing a first precursor solution including a first precursor and a first solvent with a second precursor solution including a second precursor and a second solvent to form a precipitate, and separating the precipitate to obtain a light-emitting material, wherein a solubility of the first precursor in the first solvent may be greater than a solubility of the first precursor in the second solvent, and a solubility of the second precursor in the second solvent may be greater than a solubility of the second precursor in the first solvent. A light-emitting material prepared by the method, and a light-emitting device including the light-emitting material is also described. | 2022-03-31 |