13th week of 2022 patent applcation highlights part 69 |
Patent application number | Title | Published |
20220102335 | MEMORY DEVICE - A memory device includes first and second chips. The first chip includes a memory cell array disposed on a first substrate, and first metal pads on a first uppermost metal layer of the first chip. The second chip includes peripheral circuits disposed on a second substrate, and second metal pads on a second uppermost metal layer of the second chip, the peripheral circuits operating the memory cell array. A first metal pad and a second metal pad are connected in a first area, the first metal pads being connected to the memory cell array and the second metal pad being connected to the peripheral circuits. A further first metal pad and a further second metal pad are connected in a second area, the further first metal pad being not connected to the memory cell array and the further second metal pad being connected to the peripheral circuits. | 2022-03-31 |
20220102336 | INTEGRATED CIRCUIT INCLUDING ASYMMETRIC DECOUPLING CELL AND METHOD OF DESIGNING THE SAME - An integrated circuit includes at least one decoupling cell, wherein the at least one decoupling cell includes at least one P-type decoupling MOSFET and at least one N-type decoupling MOSFET, and a number of the at least one P-type decoupling MOSFET is different from a number of the at least one N-type decoupling MOSFET. | 2022-03-31 |
20220102337 | TRANSISTOR DRAIN DESIGN FOR ESD PROTECTION AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided. The semiconductor device comprises a substrate of a first type, a first doped region embedded within the substrate and having a first portion and a second portion, and a first gate electrode disposed above the substrate. The semiconductor device further comprises a well region of a second type and embedded within the substrate. The well region is in contact with the second portion of the first doped region. | 2022-03-31 |
20220102338 | ELECTROSTATIC PROTECTION ELEMENT AND SEMICONDUCTOR DEVICE - A high-density source region is formed along a surface of a semiconductor substrate and is connected to either one of a power source line and ground line. A low-density source region has an exposed surface at a surface of the semiconductor substrate and is in contact with the high-density source region. A high-density drain region is formed along the surface of the semiconductor substrate and is connected to the other one of the power source line and the ground line. A low-density drain region has an exposed surface at the surface of the semiconductor substrate, is in contact with the high-density drain region, and extends to a deeper region from the surface of the semiconductor substrate than does the low-density source region. A gate electrode is connected to either one of the power source line and the ground line. | 2022-03-31 |
20220102339 | GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY - Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer. | 2022-03-31 |
20220102340 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING SEMICONDUCTOR DEVICE - A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electronic device, and the like are provided. The semiconductor device includes a capacitor, a first amplifier circuit including a first output terminal electrically connected to a first electrode of the capacitor, and a second amplifier circuit including an input terminal, a second output terminal, a first transistor, and a second transistor; a second electrode of the capacitor is electrically connected to the input terminal; the input terminal is electrically connected to a gate of the first transistor and one of a source and a drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to the second output terminal; the second transistor has a function of supplying a potential to the input terminal and holding the potential; and a channel formation region of the second transistor includes a metal oxide containing at least one of indium and gallium. | 2022-03-31 |
20220102341 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present disclosure is an RC-IGBT in which an IGBT region | 2022-03-31 |
20220102342 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first electrically conductive portion, a first semiconductor chip of a reverse-conducting insulated gate bipolar transistor, a second electrically conductive portion, a third electrically conductive portion, a second semiconductor chip of an insulated gate bipolar transistor, and a fourth electrically conductive portion. The first semiconductor chip includes a first electrode and a second electrode. The first electrode is electrically connected to the first electrically conductive portion. The second electrically conductive portion is electrically connected to the second electrode. The third electrically conductive portion is electrically connected to the first electrically conductive portion. The second semiconductor chip includes a third electrode and a fourth electrode. The third electrode is electrically connected to the third electrically conductive portion. The fourth electrically conductive portion is electrically connected to the fourth electrode and the second electrically conductive portion. | 2022-03-31 |
20220102343 | MULTI-LAYER ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Multi-layer etch stop layers are described. In an example, an integrated circuit structure includes a conductive line in a first interlayer dielectric material above a substrate. A first dielectric etch stop layer, a second dielectric layer and a third dielectric layer are on the conductive line and the first interlayer dielectric material. A second interlayer dielectric material is on the third dielectric etch stop layer. An opening is in the second interlayer dielectric material, in the third dielectric etch stop layer, and in the second dielectric etch stop layer, in the first dielectric etch stop layer. A conductive structure is in the opening, the conductive structure in direct contact with the conductive line. | 2022-03-31 |
20220102344 | GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY - Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer. | 2022-03-31 |
20220102345 | PLURALITY OF 3D VERTICAL CMOS DEVICES FOR HIGH PERFORMANCE LOGIC - Techniques herein include methods for fabricating vertical stacks of vertical-channel transistors. Vertical channels can be made from an initial epitaxial structure, and electrically isolated at locations to divide the structure into multiple, independent vertical channels. Techniques enable modulating PMOS and NMOS channel composition and channel geometry to match drive currents thereby providing advanced circuit tuning. Advantageously, one process step can be performed per type of epitaxial material to dope epitaxial materials in respective source/drain regions. | 2022-03-31 |
20220102346 | FORKSHEET TRANSISTOR ARCHITECTURES - Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone. | 2022-03-31 |
20220102347 | CROWN CAPACITOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer. | 2022-03-31 |
20220102348 | Integrated Circuitry, Memory Circuitry, Method Used In Forming Integrated Circuitry, And Method Used In Forming Memory Circuitry - A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed. | 2022-03-31 |
20220102349 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure manufacturing method includes: providing a substrate and etching the substrate to form first trenches; filling each of the first trenches with an oxide layer having a top surface not lower than that of the substrate; etching regions, adjacent to side walls of the first trench, in the oxide layer downwards to form second trenches, wherein a depth of the second trench is less than a depth of the first trench and a width of the second trench is less than half of a width of the first trench; and forming supplementary layers in the second trenches. | 2022-03-31 |
20220102350 | SEMICONDUCTOR DEVICE AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE - A method for preparing a semiconductor device, including providing a substrate, where a word line structure is formed in the substrate; a bit line supporting layer includes a first oxide layer and a first nitride layer. A bit line structure is formed in the first nitride layer, and the first oxide layer is formed on both sides of the bit line structure and located in the first nitride layer; patterning the supporting structure to form a first via corresponding to the bit line structure; and etching the bit line supporting layer to a preset height along the first via, adjusting an etching parameter and a selective etching ratio of etching gas for an oxide layer to a nitride layer, and continuing to etch the bit line supporting layer until the bit line structure is exposed, to form a polymer layer above the bit line structure. | 2022-03-31 |
20220102351 | APPARATUSES INCLUDING ELONGATE PILLARS OF ACCESS DEVICES - A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described. | 2022-03-31 |
20220102352 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern. | 2022-03-31 |
20220102353 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a trench, a direct contact in the trench, the direct contact having a width smaller than a width of the trench, a bit line structure on the direct contact, the bit line structure having a width smaller than the width of the trench, a first spacer including a first portion and a second portion, the first portion extending along an entire side surface of the direct contact, and the second portion extending along the trench, a second spacer on the first spacer, the second spacer filling the trench, a third spacer on the second spacer, and an air spacer on the third spacer, the air spacer being spaced apart from the second spacer by the third spacer, wherein the first spacer includes silicon oxide. | 2022-03-31 |
20220102354 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device, including the steps of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a spacer on a sidewall of the opening; performing a wet etching process to form a hole in the conductive portion; removing the spacer; and depositing a conductive pattern over the sidewall of the opening and a surface of the hole. | 2022-03-31 |
20220102355 | METHOD FOR PREPARING SEMICONDUCTOR MEMORY DEVICE WITH AIR GAPS FOR REDUCING CAPACITIVE COUPLING - The present disclosure provides a method for preparing a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature. The method includes forming an isolation member defining an active region in a substrate and a doped area in the active region; forming a gate structure in the substrate, wherein the gate structure divides the doped are into a first doped region and a second doped region; forming a bit line structure on the first doped region; forming an air gap adjacent to the bit line structure; forming a capacitor plug on the second doped region and a barrier layer on a sidewall of the capacitor plug; and forming a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer over the protruding portion and a second silicide layer on a sidewall of the barrier layer. | 2022-03-31 |
20220102356 | EPITAXIAL SINGLE CRYSTALLINE SILICON GROWTH FOR A HORIZONTAL ACCESS DEVICE - Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings. | 2022-03-31 |
20220102357 | BITLINE STRUCTURE FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME - The invention involves a method of manufacturing a bonded semiconductor structure, comprising providing a support substrate which carries a transistor, and providing an interconnect region earned by the support substrate. The interconnect region includes a first multiple bypass bitline having an upper bypass interconnect and upper bypass via. The method includes providing a first conductive bonding layer carried by the interconnect region, wherein the first conductive bonding layer is connected to the upper bypass interconnect through the upper bypass via, and providing a vertical transistor carried by the first conductive bonding layer, the vertical transistor being in communication with the transistor through the interconnect region. The first multiple bypass bitline reduces the impedance experienced by the vertical transistor. | 2022-03-31 |
20220102358 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in the first direction, at least one gate electrode on the horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction, and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, wherein a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction. | 2022-03-31 |
20220102359 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer. | 2022-03-31 |
20220102360 | STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELL CIRCUITS WITH A MINIMUM DISTANCE BETWEEN A STORAGE CIRCUIT ACTIVE REGION AND A READ PORT CIRCUIT ACTIVE REGION TO REDUCE AREA AND SRAM BIT CELL ARRAY CIRCUITS - SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area. | 2022-03-31 |
20220102361 | METHOD AND DEVICE FOR FINFET SRAM - A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer. | 2022-03-31 |
20220102362 | CFET SRAM BIT CELL WITH TWO STACKED DEVICE DECKS - A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the at least six transistors being lateral transistors with channels formed from nano-sheets grown by epitaxy. The at least six transistors positioned in two decks in which a second deck is positioned vertically above a first deck relative to a working surface of the substrate, wherein at least one NMOS transistor and at least one PMOS transistor share a common vertical gate. A first inverter formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in either the first deck or the second deck. | 2022-03-31 |
20220102363 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein. | 2022-03-31 |
20220102364 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor. | 2022-03-31 |
20220102365 | ASYMMETRIC JUNCTIONS OF HIGH VOLTAGE TRANSISTOR IN NAND FLASH MEMORY - The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors. | 2022-03-31 |
20220102366 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A memory device includes a substrate, an active region, a first gate structure, a second gate structure, a first word line, and a second word line. The active region protrudes from a top surface of the substrate. The active region has at least one ring structure, in which when viewed from above, the ring structure has a first linear portion, a second linear portion, a first curved portion, and a second curved portion, the first curved portion connects first sides of the first and second linear portions, and the second curved portion connects second sides of the first and second linear portions. The first gate structure and the second gate structure are over the substrate and cross the active region. The first word line and the second word line are electrically connected to the first gate structure and the second gate structure, respectively. | 2022-03-31 |
20220102367 | SMALL-AREA AND LOW-VOLTAGE ANTI-FUSE ELEMENT AND ARRAY - A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array. | 2022-03-31 |
20220102368 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A memory device includes a substrate, a first gate structure and a second gate structure, first, second, third source/drain structures, gate spacers, a first via and a second via, and a semiconductor layer. The first gate structure and the second gate structure are over the substrate. The first, second, third source/drain structures are over the substrate, in which the first and second source/drain structures are on opposite sides of the first gate structure, the second and third source/drain structures are on opposite sides of the second gate structure. The gate spacers are on opposite sidewalls of the first and second gate structures. The first via and the second via are over the first gate structure and the second gate structure, respectively, in which the first via is in contact with the first gate structure. The semiconductor layer is between the second via and the second gate structure. | 2022-03-31 |
20220102369 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction. | 2022-03-31 |
20220102370 | MEMORY DEVICE - A memory device includes a cell stacked structure on a substrate, the cell stacked structure including insulation layers and gate patterns alternately stacked, a channel structure passing through the cell stacked structure, the channel structure extending in a vertical direction, a dummy structure on the substrate, the dummy structure being spaced apart from the cell stacked structure, and the dummy structure including insulation layers and metal patterns alternately stacked, a first through via contact passing through the dummy structure, the first through via contact extending in the vertical direction, and a first capping insulation pattern between a sidewall of the first through via contact and each of the metal patterns in the dummy structure, the first capping insulation pattern insulating the first through via contact from each of the metal patterns. | 2022-03-31 |
20220102371 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer. | 2022-03-31 |
20220102372 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including: a stack including first conductive layers and insulating layers that are alternately stacked; and second conductive layers disposed on the stack; a separation insulating structure disposed on the stack and configured to insulate the second conductive layers from each other; first channel layers passing through the stack; memory layers enclosing sidewalls of the first channel layers; second channel layers disposed on the stack and passing through the second conductive layers, and each having a width less than a width of the first channel layers; gate insulating layers enclosing sidewalls of the second channel layers; and third channel layers configured to respectively couple the first channel layers with the second channel layers and extending into the second channel layers. | 2022-03-31 |
20220102373 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided herein may be a method of manufacturing a semiconductor device. The method may include forming a stacked structure including alternately stacked first material layers and second material layers; forming a first opening including a through hole passing through the stacked structure and a notch coupled to the through hole and located in at least one of the interfaces of the first material layers and second material layers; forming a sacrificial layer including a first part located in the through hole and a second part located in the notch; and oxidizing the first part of the sacrificial layer and thereby forming a first sacrificial pattern located in the through hole and a plugging pattern located in the notch. | 2022-03-31 |
20220102374 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers. | 2022-03-31 |
20220102375 | THREE-DIMENSIONAL MEMORY DEVICE WITH DIELECTRIC OR SEMICONDUCTOR WALL SUPPORT STRUCTURES AND METHOD OF FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through each layer of the alternating stack; memory opening fill structures located in the memory openings, and a perforated wall structure including lateral openings at levels of the insulating layers. | 2022-03-31 |
20220102376 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions. | 2022-03-31 |
20220102377 | THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME - Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. First, a slit structure and a support structure are formed in a stack structure having interleaved a plurality of sacrificial material layers and a plurality of insulating material layers, the initial support structure between adjacent slit openings of the slit structure. A source structure is formed to include a source portion in each of the slit openings. A pair of first portions of a connection layer is formed in contact with and conductively connected to the source portion. A second portion of the connection layer is formed in contact with and conductively to the pair of first portions of the connection layer. | 2022-03-31 |
20220102378 | MICROELECTRONIC AND SEMICONDUCTOR DEVICES WITH A TUNNELING STRUCTURE FREE OF HIGH- k MATERIAL BY A SELECT GATE STRUCTURE, AND RELATED METHODS - A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier. | 2022-03-31 |
20220102379 | NAND FERROELECTRIC MEMORY CELL WITH THREE-DIMENSIONAL STRUCTURE AND PREPARATION METHOD THEREOF - A NAND ferroelectric memory cell with a three-dimensional structure and a preparation method thereof are provided, the ferroelectric memory cell comprises: an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer, and/or a gate buffer layer, and a gate arranged successively from the inside to the outside. In the memory cell of the present disclosure, the buffer layer has the following effects: 1. It can induce the crystallization of ferroelectric film to form ferroelectric phase; 2. It can reduce adverse effects caused by different crystalline characteristics of the channel layer and the ferroelectric layer, improve the quality and uniformity of the deposited film; 3. It can enhance the interface property of the channel layer, reduce leakage current, and enhance endurance of the device. Therefore, the buffer layer can improve the overall storage property and homogeneity of memory cells with a three-dimensional structure. | 2022-03-31 |
20220102380 | CONNECTIONS FROM BURIED INTERCONNECTS TO DEVICE TERMINALS IN MULTIPLE STACKED DEVICES STRUCTURES - In vertically stacked device structures, a buried interconnect and bottom contacts can be formed, thereby allowing connections to be made to device terminals from both below and above the stacked device structures. Techniques herein include a structure that enables electrical access to each independent device terminal of multiple devices, stacked on top of each other, without interfering with other devices and the local connections that are needed. | 2022-03-31 |
20220102381 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a semiconductor body, bit lines and word lines. The semiconductor body includes a substrate and an isolation structure positioned above the substrate and configured to isolate a plurality of active regions, part of each of the active regions being formed from the substrate. The bit lines are positioned in the substrate and are connected to the active regions. The word lines intersect with the active regions and surround the active regions. The substrate is Silicon On Insulator (SOI) substrate. | 2022-03-31 |
20220102382 | PIXEL STRUCTURE, ARRAY SUBSTRATE AND DISPLAY PANEL - The present disclosure discloses a pixel structure, an array substrate and a display panel. The pixel structure includes a first data line; a first gate line and a second gate line; a first pixel unit and a second pixel unit. The first pixel units and second pixel units arranged along a second direction; a first pixel electrode relative to the second pixel electrode is close to the first data line, a first thin film transistor and second thin film transistors are arranged close to the first data line; first connecting trace is set between the first drain electrode and the first pixel electrode, a second connecting trace is set between the second drain electrode and the second pixel electrode to make a capacitance of the first pixel unit matching with a capacitance of the second pixel unit. | 2022-03-31 |
20220102383 | GOA CIRCUIT, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises: a GOA area, and the GOA area comprises a plurality of GOA unit circuits cascaded with each other; a lead area, wherein at least one STV signal line and at least one non-STV signal line are arranged in the lead area, each STV signal line and each non-STV signal line is connected to at least one GOA unit circuit, and the non-STV signal line comprises at least one of a Vdd signal line, a Clk signal line, a VGH signal line and a VGL signal line; a projection of the at least one STV signal line on the lead area does not overlap a projection of the at least one non-STV signal line on the lead area. | 2022-03-31 |
20220102384 | EPITAXIAL SINGLE CRYSTALLINE SILICON GROWTH FOR MEMORY ARRAYS - Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for memory arrays. One example method includes forming logic circuitry on a silicon substrate in a first working surface and depositing an isolation material on the first working surface to encapsulate the logic circuitry and to form a second working surface above the first working surface. Further, the example method includes etching the isolation material to form a vertical opening through the isolation material and epitaxially growing single crystalline silicon from the silicon substrate and horizontally on the second working surface in a first, a second, and a third direction to cover the second working surface. The example method further includes removing a portion of the epitaxially grown single crystalline silicon to partition distinct and separate third working surface areas in which to form memory cell components and forming storage nodes above the memory cell components. | 2022-03-31 |
20220102385 | SUBSTRATE-FREE INTEGRATED CIRCUIT STRUCTURES - Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures. | 2022-03-31 |
20220102386 | PIXEL STRUCTURE OF REFLECTIVE DISPLAY AND MANUFACTURING METHOD THEREOF - The present disclosure discloses a pixel structure of a reflective display comprising a substrate, a shielding layer, a low reflective layer, and a reflective layer. The shielding layer is disposed on the substrate. The low reflective layer is disposed on the shielding layer. The reflective layer is disposed on the low reflective layer, wherein the reflective layer comprises a plurality of reflection regions, the plurality of reflection regions are arranged at intervals. A part of the low reflective layer is exposed between the plurality of reflection regions. In the present disclosure, the reflection of light in the gap between the pixels is avoided by the low reflective layer, such that the notice of liquid crystal disturbance by human eyes is reduced, and a reflective display with good display function and low power consumption is implemented. | 2022-03-31 |
20220102387 | DISPLAY DEVICE - A display device includes a display medium layer, an active component array layer, a support layer, and a first adhesive layer. The display medium layer has a light-emitting surface. The active component array layer is disposed on a side of the display medium layer away from the light-emitting surface. The support layer is disposed on a side of the active component array layer away from the display medium layer. The first adhesive layer is connected between the active component array layer and the support layer, in which the active component array layer is directly connected to the first adhesive layer. The first adhesive layer has a Young's modulus greater than 10 GPa. | 2022-03-31 |
20220102388 | DISPLAY DEVICE - A display device includes a substrate, a driving circuit disposed on the substrate and for driving display units, sensing units disposed on the substrate and including a first semiconductor layer, a sensing circuit configured for driving the sensing units and including a second semiconductor layer, and a first passivation layer disposed on the sensing circuit. A thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer. At least a part of one of the sensing units is disposed in a recess penetrating through the first passivation layer. | 2022-03-31 |
20220102389 | DISPLAY SUBSTRATE AND DISPLAY APPARATUS - A display substrate includes: a base, a plurality of pixel units arranged in columns in a first direction and in rows in a second direction, a plurality of data lines and first gate lines extending in the first direction, a plurality of second gate lines extending in the second direction, and at least one gate driver circuit connected to the first gate lines and located at a side of the display substrate parallel to the second direction. One pixel unit includes a TFT. The TFT is connected to one data line. In a column of pixel units, TFTs of any two adjacent pixel units are respectively located at first and second sides of a respective data line. Each second gate line is connected to a row of pixel units and at least one of the first gate lines. First gate lines connecting different second gate lines are different. | 2022-03-31 |
20220102390 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a base layer; a first pattern disposed on the base layer; an insulating layer disposed on the first pattern and including layers; and a second pattern disposed on the insulating layer. At least two of the layers of the insulating layer include a same material. | 2022-03-31 |
20220102391 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor. | 2022-03-31 |
20220102392 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor. | 2022-03-31 |
20220102393 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor. | 2022-03-31 |
20220102394 | SINGLE CRYSTAL HORIZONTAL ACCESS DEVICE FOR VERTICAL THREE-DIMENSIONAL (3D) MEMORY - Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have epitaxially grow single crystal silicon to fill the first horizontal opening and house a first source/drain in electrical contact with a conductive material and to form part of an integral, horizontally oriented, conductive digit line. The memory cells also have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain region. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric. | 2022-03-31 |
20220102395 | IMAGE SENSING DEVICE - An image sensing device is provided to include a pixel array having a plurality of pixels arranged in a matrix shape. Each of the pixels includes: a control node configured to generate a hole current in a substrate; a detection node configured to capture photocharge migrated by the hole current, formed in a shape whose at least part is partially open, and disposed to surround the control node, and a low resistance region including a dielectric layer formed in the substrate, and disposed in the opening on of the detection node. The low resistance region includes an inner low resistance region disposed between the control node and the center of the pixel. | 2022-03-31 |
20220102396 | Image Sensor Device and Method - A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range. | 2022-03-31 |
20220102397 | BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR - The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer. | 2022-03-31 |
20220102398 | IMAGE SENSOR - An image sensor includes a substrate, and a pixel separation pattern disposed in the substrate and interposed between a plurality of unit pixels. The plurality of unit pixels include a first unit pixel region and a second unit pixel region adjacent to the first unit pixel region in a first direction. The first unit pixel region and the second unit pixel region respectively include a first transfer gate and a second transfer gate. The pixel separation pattern includes a first pixel separation part interposed between the first unit pixel region and the second unit pixel region, and a second pixel separation part spaced apart from the first pixel separation part in the first direction. A top surface of the first pixel separation part is lower than a top surface of the second pixel separation part. | 2022-03-31 |
20220102399 | METHOD OF MANUFACTURING RADIOGRAPHIC IMAGING APPARATUS, AND TRANSPORT JIG - A method of manufacturing a radiographic imaging apparatus, including: providing a flexible base material on a support body and forming a substrate in which pixels are provided in a pixel region of a first surface of the base material; providing a terminal portion for connecting a cable on the first surface; connecting a circuit board for reading the electric charges from the pixels or driving the pixels to the terminal portion via the cable; peeling the substrate from the support body; and using a transport jig including a suction unit having suction members and a holding part having a holding member, to suction and support the first surface or a second surface opposite to the first surface with the suction members, and transporting the substrate peeled from the support body in a state where the circuit board is held by the holding member. | 2022-03-31 |
20220102400 | SOLID-STATE IMAGE-CAPTURING DEVICE AND PRODUCTION METHOD THEREOF, AND ELECTRONIC APPLIANCE - A high degree of phase difference detection accuracy can be obtained using a phase difference pixel with a simpler configuration. A solid-state image-capturing device includes a pixel array unit in which a plurality of pixels including a phase difference pixel which is a pixel for focal point detection and an image-capturing pixel which is a pixel for image generation are arranged in a two-dimensional array. In this case, a predetermined layer between a light shielding layer and a micro lens formed in the image-capturing pixel has a higher refraction index than a refraction index of the predetermined layer formed in the phase difference pixel. The technique of the present disclosure can be applied to, for example, a back-illuminated-type solid-state image-capturing device and the like. | 2022-03-31 |
20220102401 | IMAGE SENSING DEVICE - An image sensing device includes a first subpixel block, a second subpixel block, a first conversion gain transistor, and a second conversion gain transistor. The first subpixel block includes a first floating diffusion region and a plurality of unit pixels sharing the first floating diffusion region. The second subpixel block includes a second floating diffusion region coupled to the first floating diffusion region and a plurality of unit pixels sharing the second floating diffusion region. The first conversion gain transistor includes a first impurity region coupled to the first and second floating diffusion regions and a second impurity region coupled to a first conversion gain capacitor. The second conversion gain transistor includes a third impurity region coupled to the second impurity region of the first conversion gain transistor and a fourth impurity region coupled to a second conversion gain capacitor. | 2022-03-31 |
20220102402 | IMAGE SENSING DEVICE - An image sensing device includes a first unit pixel block, a second unit pixel block, and an isolation transistor. The first unit pixel block includes a first common floating diffusion node, a plurality of first photoelectric conversion elements, a plurality of first transfer transistors configured to transmit the photocharges generated by the first photoelectric conversion elements to the first common floating diffusion node, and a first conversion gain transistor configured to change capacitance of the first common floating diffusion node. The second unit pixel block adjacent to the first unit pixel block in a first direction includes a second common floating diffusion node, a plurality of second photoelectric conversion elements, a plurality of second transfer transistors configured to transmit the photocharges generated by the second photoelectric conversion elements to the second common floating diffusion node, and a second conversion gain transistor configured to change capacitance of the second common floating diffusion node. The isolation transistor located in a boundary region between the first unit pixel block and the second unit pixel block isolates the first conversion gain transistor and the second conversion gain transistor from each other. | 2022-03-31 |
20220102403 | SCALABLE-PIXEL-SIZE IMAGE SENSOR - Photodetection elements within an integrated-circuit pixel array are dynamically configurable to any of at least three uniform-aspect-ratio, size-scaled pixel footprints through read-out-time control of in-pixel transfer gates associated with respective photodetection elements and binning transistors coupled between the transfer gates for respective clusters of the photodetection elements and a shared reset node. | 2022-03-31 |
20220102404 | Transistor Integration with Stacked Single-Photon Avalanche Diode (SPAD) Pixel Arrays - Disclosed herein are photodetectors using arrays of pixels with single-photon avalanche diodes (SPADs). The pixel arrays may have configurations that include one or more control transistors for each SPAD collocated on the same chip or wafer as the pixels and located on a surface of the wafer opposite to the light gathering surface of the pixel arrays. The control transistors may be positioned or configured for interconnection with a logic chip that is bonded to the wafer of the pixel array. The pixels may be formed in a substrate having doping gradient. The control transistors may be positioned on or within the SPADs, or adjacent to, but isolated from, the SPADs. Isolation between the individual SPADs and the respective control transistors may make use of shallow trench isolation regions or deep trench isolation regions. | 2022-03-31 |
20220102405 | IMAGE SENSOR - An image sensor is provided and may include a semiconductor substrate having a surface and including trench, the trench extending from the surface into the semiconductor substrate, an insulating pattern provided in the trench and a doped region in the semiconductor substrate and on the insulating patterns. The doped region includes a side portion on a side surface of the insulating pattern, and a bottom portion on a bottom surface of the insulating pattern. A thickness of the side portion of the doped region is from 85% to 115% of a thickness of the bottom portion of the doped region, and a number of dopants per unit area in the side portion of the doped region is from 85% to 115% of a number of dopants per unit area in the bottom portion. | 2022-03-31 |
20220102406 | PACKAGE STRUCTURE, PACKAGING METHOD, CAMERA MODULE, AND ELECTRONIC EQUIPMENT - The present disclosure provides chip package structure, packaging method, camera module and electronic equipment. The package structure includes chip package module, which includes light-transmitting substrate, wiring layer located on side of light-transmitting substrate and including first metal wire, conductor located on side of wiring layer facing away from light-transmitting substrate, photosensitive chip located on side of wiring layer facing away from the light-transmitting substrate, active chip located on side of wiring layer facing away from light-transmitting substrate, and plastic encapsulation layer encapsulating photosensitive chip and active chip. The conductor includes first end electrically connected to first metal wire, and second end. The photosensitive chip includes pin electrically connected to first metal wire and has photosensitive surface facing towards light-transmitting substrate. The photosensitive surface includes photosensitive region that is not overlapping first metal wire. The active chip includes pin electrically connected to first metal wire. | 2022-03-31 |
20220102407 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - To provide a solid-state imaging device that can achieve a higher image quality. | 2022-03-31 |
20220102408 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND CAMERA WITH ALTERNATIVELY ARRANGED PIXEL COMBINATIONS - A solid-state imaging device includes a semiconductor substrate; and a pixel unit having a plurality of pixels on the semiconductor substrate, wherein the pixel unit includes first pixel groups having two or more pixels and second pixel groups being different from the first pixel groups, wherein a portion of the pixels in the first pixel groups and a portion of the pixels in the second pixel groups share a floating diffusion element. | 2022-03-31 |
20220102409 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a substrate having a plurality of first photoelectric conversion elements and a plurality of second photoelectric conversion elements. The semiconductor device also includes a light-adjusting structure disposed on the substrate. The light-adjusting structure includes a patterned multi-film having a plurality of trenches that correspond to the first photoelectric conversion elements. The first photoelectric conversion elements are used for sensing near infrared light, and the second photoelectric conversion elements are used for sensing visible light. | 2022-03-31 |
20220102410 | IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION - Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer. | 2022-03-31 |
20220102411 | IMAGING DEVICE AND IMAGING SYSTEM - An imaging device includes: a semiconductor substrate having a first surface and a second surface opposed to each other, and provided with a plurality of pixels; a wiring layer which is provided on side of the second surface of the semiconductor substrate and to which a signal is to be transmitted for each of the plurality of pixels; a light-blocking film opposed to the wiring layer with the semiconductor substrate interposed therebetween and having an opening satisfying Expression (1) below for each of the pixels; and a waveguide provided on side of the first surface of the semiconductor substrate for each of the plurality of pixels and extending to the opening of the light-blocking film. | 2022-03-31 |
20220102412 | SOLID-STATE IMAGE SENSOR - A solid-state image sensor is provided. The solid-state image sensor includes a plurality of photoelectric conversion elements. The solid-state image sensor also includes a modulation layer disposed above the photoelectric conversion elements, and the modulation layer has a plurality of modulation segments. The modulation layer includes a plurality of first sub-layers and a plurality of second sub-layers having different refractive indexes. From the top view of the modulation layer, the modulation segments form a first group and a second group, and the second group is adjacent to the first group. The arrangement of the first sub-layers and the second sub-layers in the first group is different from the arrangement of the first sub-layers and the second sub-layers in the second group. | 2022-03-31 |
20220102413 | IMAGE SENSING DEVICE - An image sensing device includes a pixel array including a plurality of image detection pixels structured to convert light incident onto the image detection pixels into pixel signals representing an image of an object, a plurality of phase-difference detection pixels in the pixel array structured to detect light from the object to generate a phase signal for measuring a distance between the image sensing device and the object, and a first lens positioned to direct light to the plurality of phase-difference detection pixels and including a plurality of portions each corresponding to at least one of the phase-difference detection pixels. A center of the first lens is located over a center of the plurality of phase-difference detection pixels, and each portion of the first lens extends from the center along a row or column direction between adjacent phase-difference detection pixels or along diagonal directions between the row and column directions. | 2022-03-31 |
20220102414 | IMAGE SENSING DEVICE - An image sensing device includes a plurality of pixel groups, each pixel group including first to fourth unit pixels that are configured to respond to incident light and generate electrical signals, and wherein each of the first to fourth unit pixels of a pixel group includes optical filters operable to transmit incident light corresponding to a same color, wherein the first unit pixel and the second unit pixel that are included in the pixel group are located adjacent to each other and include portions of a first microlens, and wherein a light reception area of the third unit pixel of the pixel group has a size smaller than a size of a light reception area of the fourth unit pixel of the pixel group. | 2022-03-31 |
20220102415 | ELECTRONIC DEVICES - An electronic device is provided. The electronic device includes an optical sensing module that includes an optical sensor array. The optical sensor array includes at least one optical sensor, at least one transparent layer disposed on the optical sensor array, and a microlens array. The microlens array includes at least one microlens and is disposed on the transparent layer. | 2022-03-31 |
20220102416 | DETECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an aspect, a detection device includes: a substrate; a plurality of photodiodes arranged on a first principal surface of the substrate; a protective film that covers the photodiodes; a plurality of lenses provided for each of the photodiodes so as to face the photodiode with the protective film interposed between the lenses and the photodiodes; and a projection provided between the lenses. A top of the projection is located at a position higher than a top of each of the lenses when viewed from the first principal surface. | 2022-03-31 |
20220102417 | SUBSTRATE FOR IMAGE SENSOR - An image sensor substrate according to an embodiment includes: an insulating layer; and a conductive pattern part disposed on the insulating layer, wherein the insulating layer includes: a first insulating part: and a second insulating part disposed surrounding a periphery of the first insulating part and spaced apart from the first insulating part with a first open region interposed therebetween, and the conductive pattern part includes: a first conductive pattern part disposed on the first insulating part; a second conductive pattern part disposed on the second insulating part; and an extension pattern part disposed on the first open region and interconnecting the first and second conductive pattern parts, wherein the extension pattern part includes a bent portion disposed on a corner region of the first open region. | 2022-03-31 |
20220102418 | IMAGE TRANSDUCER AND 3D IMAGE CAPTURING SYSTEM HAVING THE SAME - An image transducer and a 3D image capturing system having the image transducer are provided. The image transducer includes a microlens, first function layer, first photosensitive layer, second function layer, second photosensitive layer, first read circuit and second read circuit; thus, the image transducer includes two photosensitive layers and is vertically structured. The two photosensitive layers greatly increase sensing waveband. The 3D image capturing system uses the image transducer to enhance pixel screen fineness of a 3D screen. | 2022-03-31 |
20220102419 | IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - An imaging device suitable for detecting infrared light is provided. The imaging device includes a first layer, a second layer, a third layer, and a fourth layer, which are stacked in this order. The first layer includes an infrared-light-transmitting filter. The second layer includes single crystal silicon. The third layer includes a device-formation layer. The fourth layer includes a support substrate. The second layer includes a photoelectric-conversion device whose light-absorption layer is the single crystal silicon. The third layer includes a transistor which includes a metal oxide in its channel formation region. The photoelectric-conversion device and the transistor are electrically connected. The photoelectric-conversion device receives light which has passed through the infrared-light-transmitting filter. | 2022-03-31 |
20220102420 | MANUFACTURING METHOD FOR SEMICONDUCTOR FILM, PHOTOELECTRIC CONVERSION ELEMENT, IMAGE SENSOR, AND SEMICONDUCTOR FILM - A semiconductor film contains aggregates of semiconductor quantum dots containing a metal atom and a ligand that is coordinated to the semiconductor quantum dot, where the ligand contains a first ligand that is an inorganic halide and a second ligand that is represented by any one of Formulae (A) to (C). X | 2022-03-31 |
20220102421 | DISPLAY PANEL AND DISPLAY DEVICE - Display panels and display devices are provided. The display panel may include a first display area, a second display area and a third display area with a light transmittance of the first display area being greater than a light transmittance of the third display area; first pixel circuits; second pixel circuits; third pixel circuits; first light-emitting units, second light-emitting units; third light-emitting units; and first signal lines extending along a first direction and spaced apart along a second direction intersecting the first direction. Each first signal line is connected with one or more first pixel circuits, one or more second pixel circuits and one or more third pixel circuit, and the one or more first pixel circuit and the one or more third pixel circuit electrically connected to each of at least one portion of first signal lines are misaligned along the first direction. | 2022-03-31 |
20220102422 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device according to one embodiment of the present disclosure includes: a base layer including a display area; a circuit layer including a conductive pattern in a pixel area of the display area; a first insulating film on the circuit layer, the first insulating film being opened in a contact portion on the conductive pattern; a reflective film on the first insulating film and including a first opening that corresponds to the contact portion; a second insulating film on the reflective film and including a second opening overlapping the first opening; and a display layer on the second insulating film, connected to the conductive pattern through the contact portion, and including a first electrode, a second electrode, and a light-emitting element overlapping the reflective film, wherein, in the contact portion, the reflective film has a wider opening than the second insulating film. | 2022-03-31 |
20220102423 | DISPLAY DEVICE - A display device includes subpixels, each of the subpixels including a first electrode extending in a first direction, a second electrode extending in the first direction and spaced apart from the first electrode in a second direction, and light emitting elements disposed on the first electrode and the second electrode and extending in a direction, wherein the subpixels includes a first subpixel including first light emitting elements having a first length in the direction and a second subpixel including second light emitting elements having a second length greater than the first length in the direction. | 2022-03-31 |
20220102424 | DISPLAY DEVICE - A display device including a base layer, a pixel circuit layer disposed on the base layer and including a pixel circuit and a plurality of insulation layers, a first electrode electrically connected to the pixel circuit, a second electrode spaced apart from the first electrode, a light emitting element electrically connected to the first electrode and the second electrode, a first refraction layer disposed on the pixel circuit layer and having a first refractive index, and a second refraction layer disposed on the light emitting element and having a second refractive index larger than the first refractive index. | 2022-03-31 |
20220102425 | FABRICATION METHODS - Various fabrication methods are disclosed. In one such method, at least one structure is formed on a substrate which protrudes outwardly from a plane of the substrate. A beam is used to form a layer of material, at least part of which is in direct contact with a semiconductor structure on the substrate, the semiconductor structure comprising at least one nanowire. The beam has a non-zero angle of incidence relative to the normal of the plane of the substrate such that the beam is incident on one side of the protruding structure, thereby preventing a portion of the nanowire in a shadow region adjacent the other side of the protruding structure in the plane of the substrate from being covered with the material. | 2022-03-31 |
20220102426 | MAGNETIC MEMORY DEVICES - A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material. | 2022-03-31 |
20220102427 | VARIABLE RESISTANCE MEMORY DEVICE - A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines. | 2022-03-31 |
20220102428 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer. | 2022-03-31 |
20220102429 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell. | 2022-03-31 |
20220102430 | DISPLAY DEVICE AND ELECTRONIC DEVICE - A display device having a non-contact input function without contact is provided. A first light-emitting device that performs display, a second light-emitting device that emits light for detection, and a light-receiving device are included, and the light-receiving device has a function of detecting light that has been emitted by the second light-emitting device and reflected by an object. Near-infrared light, which has substantially no visibility, is used as the light emitted by the second light-emitting device. Therefore, the light emitted from a display portion even at high luminance does not affect visual recognition of the display. In addition, when the light is emitted at high luminance, an object that is positioned away from the display device can be detected with high sensitivity. | 2022-03-31 |
20220102431 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel is provided with a plurality of sub-pixel areas and includes: a base substrate, a light emitting structure including a plurality of light emitting devices corresponding to the sub-pixel areas, an encapsulating layer, and a pixel defining layer. The pixel defining layer includes: a plurality of openings; at least two sub-pixel defining layers, and a quantum dot color film layer. Each of the sub-pixel defining layers is provided with a pixel separator. The pixel separators fence each of the plurality of openings, and define the plurality of sub-pixel areas. In the at least two sub-pixel defining layers, the sectional shape of the pixel separator in the sub-pixel defining layer which is farthest away from the encapsulating layer includes a regular trapezoid. The quantum dot color film layer includes a plurality of quantum dot color films arranged in the corresponding openings. | 2022-03-31 |
20220102432 | DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - Provided is a display substrate, including: a base substrate and a color filter layer disposed on a side of the base substrate, wherein a target surface of the color filter layer is provided with a scattering structure, and the target surface comprises at least one of a first surface and a second surface opposite to each other. | 2022-03-31 |
20220102433 | DISPLAY DEVICE - A display device may include a substrate, a first color conversion layer on the substrate, a low refractive layer on the first color conversion layer and including low refractive structures, a planarization layer on the low refractive layer, and a first color filter on the planarization layer. The planarization layer may also be between the low refractive structures. | 2022-03-31 |
20220102434 | Display Panel and Preparation Method therefor, and Display Apparatus - A display panel and a preparation method therefor, and a display apparatus. The display panel comprises: a display region and a bezel region surrounding the display region; a barrier structure, located in the bezel region and arranged on one side of the base substrate, surrounding the display region; a touch-control electrode lead, comprising a first metal lead and a metal connection bridge which are electrically connected; said first metal lead is arranged on the upper side of said barrier structure; the first metal lead extends from the display region to the bezel region and is located on the side of the barrier structure facing the display region; said metal connection bridge is located in the bezel region; the metal connection bridge is arranged between the base substrate and the surface of the barrier structure on the side away from the base substrate. | 2022-03-31 |