13th week of 2011 patent applcation highlights part 10 |
Patent application number | Title | Published |
20110073818 | PULLING TORPEDO HAVING A MATING FEATURE THEREON THAT MATES WITH A MATING FEATURE FORMED ON A CABLE BOOT - A torpedo is provided for use in pulling an optical communications device through ducts, vents, pipes, and the like. The torpedo has at least one mating feature formed thereon that mates with at least one mating feature formed on a boot of an optical fiber cable when the torpedo is attached to the boot. The mating feature formed on the torpedo is typically a key and the mating feature formed on the boot is typically a keyway having a shape that is complementary to the shape of the key. The mating of the key and keyway eliminate the need to use a clamping force to ensure that the grip between the torpedo and the cable will not be lost or compromised when the torpedo is being pulled. The boot of the optical fiber cable may be a standard boot of a standard optical fiber cable, and therefore does not need to be a specialized boot designed specifically for the purpose of attaching to a torpedo. The boot of the optical fiber cable is attached in the normal manner to the strain relief device of the optical fiber cable. Consequently, pulling forces that are exerted by the torpedo on the boot are translated through the boot into the strain relief device of the cable, thereby preventing forces from being exerted on the cable that could possibly damage it. | 2011-03-31 |
20110073819 | ADJUSTABLE CARRIAGE ASSEMBLY - An adjustable carriage assembly is provided that includes a shaft assembly, a carriage section and a vertical movement section. The carriage section has a centerline and first and second lift pad assemblies operably connected to the shaft assembly. The shaft assembly is configured to translate rotational movement to synchronous movement of the lift pad assemblies. The vertical movement section is connected to the carriage section and is configured to attach to a lift system for raising and lowering the carriage section. | 2011-03-31 |
20110073820 | SAFETY BRAKE DEVICE FOR THEATRE HOIST - A safety brake device for a theatre hoist to prevent the uncontrolled release of a load that is suspended above or below people includes an overrunning clutch and a torque disc. The torque disc only rotates with the overrunning clutch when the load is lowered, but must overcome friction forces applied to the surface of the torque disc to do so. The friction forces are constantly applied to the torque disc by maintaining friction material in contact with the torque disc. The friction material is a non-asbestos, non-metallic composite saturated with a lubricant. | 2011-03-31 |
20110073821 | Trailer Jack With Safety Features - A jack assembly including a jack body sub-assembly and a swivel plate. The jack assembly preferably includes the following indicators: (i) at least one jack extension indicator for indication the extension position of the jack; and/or (ii) a disengagement indicator for indicating disengagement of rotational constraints as between the jack body sub-assembly and the load to which the jack is secured (for example, the swivel plate on the tongue of a trailer). In a preferred embodiment, the fixed-engagement indicator takes the form of a marking on a pin that: (i) engages with a swivel plate to rotationally constrain the jack body with respect to the swivel plate; and (ii) disengages with the swivel plate to allow relative rotation of the jack body relative to the swivel plate. | 2011-03-31 |
20110073822 | HYDRAULIC JACK CAPABLE OF DISPLAYING LOAD AND OVERLOAD WARNING - A hydraulic jack capable of displaying load and overload warning, belonging to the technical field of hydraulic lifting equipment. It comprises: a base, a lifting arm, a pump body, a handle, and a tray, wherein, a signal collection assembly designed to sense the load on the tray is arranged at the end of the lifting arm, and the signal collection assembly is electrically connected to a weighing controller arranged on either the base or the pump body, and the tray is arranged on the signal collection assembly. Since a signal collection assembly designed to sense the load on the tray is arranged at the end of the lifting arm and electrically connected to the weighing controller, the load sensing method by the aid of communication with the oil circuit in the prior art is abandoned and the leakage of hydraulic oil can be avoided; since the signal collection assembly is arranged at the end of the lifting arm, the entire assembly can be easily processed, installed, and maintained. | 2011-03-31 |
20110073823 | PANEL AND KIT FOR CONSTRUCTING FENCE - A kit and a connector are provided for constructing a fence or barrier. The kit can include upper and lower rails formed with bar-connecting holes distributed along their lengths. First and second bar sections together with the rails can be used to form a fence panel. The first bar sections are mounted between and connect the upper and lower rails and extend between aligned pairs of holes in the upper and lower rails. The second bar sections are connectable to the tops of the first bar sections and each is mountable on the upper rail so as to extend upwardly from one of the holes in this rail. Upper connecting mechanisms join the first bar sections to the second bar sections. Lower connecting mechanisms join the first bar sections to the lower rail at the holes formed therein. | 2011-03-31 |
20110073824 | RAILING SYSTEM AND COUPLING ELEMENT AND METHODS OF ASSEMBLY - A connector for attaching a hollow baluster to a hollow rail in an extruded railing system includes two sections. A plug portion is adapted to be received in an end of the hollow baluster. A projection is adapted to be received in an aperture formed through a wall of the hollow rail. The projection may include a resilient tab configured to engage an interior surface of the hollow rail when received therein. In one embodiment, the plug portion and projection have axes that are not collinear and form an included angle. An outer taper of the plug portion allows for installation in stairway railing systems having ramp angles that deviate from the nominal. | 2011-03-31 |
20110073825 | MEMORY DEVICE AND STORAGE APPARATUS - A memory device | 2011-03-31 |
20110073826 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. | 2011-03-31 |
20110073827 | NANODEVICE ARRAYS FOR ELECTRICAL ENERGY STORAGE, CAPTURE AND MANAGEMENT AND METHOD FOR THEIR FORMATION - An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material. Both the first material and the second material are exposed at the first distal end of the column. | 2011-03-31 |
20110073828 | MEMRISTOR AMORPHOUS METAL ALLOY ELECTRODES - A nanoscale switching device comprises at least two electrodes, each of a nanoscale width; and an active region disposed between and in electrical contact with the electrodes, the active region containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical field, wherein at least one of the electrodes comprises an amorphous conductive material. | 2011-03-31 |
20110073829 | PHASE CHANGE MEMORY DEVICE HAVING A HEATER WITH A TEMPERATURE DEPENDENT RESISTIVITY, METHOD OF MANUFACTURING THE SAME, AND CIRCUIT OF THE SAME - A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity. | 2011-03-31 |
20110073830 | PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change random access memory includes a semiconductor substrate, a switching device pattern formed on the semiconductor substrate, a bottom electrode contact pattern formed on the switching device pattern, a phase change layer pattern formed on the bottom electrode contact pattern, and an insulating layer disposed at a portion of an contact surface between the bottom electrode contact pattern and the phase change layer pattern. | 2011-03-31 |
20110073831 | FERROELECTRIC POLYMER MEMORY DEVICE INCLUDING POLYMER ELECTRODES AND METHOD OF FABRICATING SAME - A method of fabricating a ferroelectric memory module with conducting polymer electrodes, and a ferroelectric memory module fabricated according to the method. The ferroelectric polymer memory module includes a first set of layers including: an ILD layer defining trenches therein; a first electrode layer disposed in the trenches; a first conductive polymer layer disposed on the first electrode layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer. The module further includes a second set of layers including: an ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the ILD layer of the second set of layers; and a second electrode layer disposed on the second conductive polymer layer. The first conductive polymer layer and the second conductive polymer layer cover the electrode layers to provide a reaction and/or diffusion barrier between the electrode layers and the ferroelectric polymer layer. | 2011-03-31 |
20110073832 | PHASE-CHANGE MEMORY DEVICE - A phase-change memory device, including a lower electrode, a phase-change material pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the phase-change material pattern. The lower electrode may include a first structure including a metal semiconductor compound, a second structure on the first structure, the second structure including a metal nitride material, and including a lower part having a greater width than an upper part, and a third structure including a metal nitride material containing an element X, the third structure being on the second structure, the element X including at least one selected from the group of silicon, boron, aluminum, oxygen, and carbon. | 2011-03-31 |
20110073833 | RESISTANCE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes. | 2011-03-31 |
20110073834 | ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION - A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a silicon oxide layer disposed between the silicon carbide layer and a bottommost of the one or more graphene layers, thereby electrically activating the bottommost graphene layer. | 2011-03-31 |
20110073835 | SEMICONDUCTOR NANOCRYSTAL FILM - A film comprised of semiconductor nanocrystals having an aspect ratio less than 3:1 and a diameter greater than 10 nanometers, wherein the film has less than 5% by volume of organic material. | 2011-03-31 |
20110073836 | High Power Density Photo-electronic and Photo-voltaic Materials and Methods of Making - A high power density photo-electronic and photo-voltaic material comprising a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein encapsulated inside a multi-wall carbon nanotube or nanotube array. The array can be on an electrode. The photosynthetic reaction center protein can be immobilized on the electrode surface and the protein molecules can have the same orientation. A method of making a high power density photo-electronic and photo-voltaic material comprising the steps of immobilizing a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein inside a carbon nanotube, wherein the immobilizing is by passive diffusion, wherein the immobilizing can include using an organic linker. | 2011-03-31 |
20110073837 | HIGH-PERFORMANCE SINGLE-CRYSTALLINE N-TYPE DOPANT-DOPED METAL OXIDE NANOWIRES FOR TRANSPARENT THIN FILM TRANSISTORS AND ACTIVE MATRIX ORGANIC LIGHT-EMITTING DIODE DISPLAYS - Methods, materials, apparatus and systems are described for implementing high-performance arsenic (As)-doped indium oxide (In | 2011-03-31 |
20110073838 | ULTRAVIOLET LIGHT EMITTING DIODE WITH AC VOLTAGE OPERATION - Ultraviolet light emitting illuminator, and method for fabricating same, comprises an array of ultraviolet light emitting diodes and a first and a second terminal. When an alternating current is applied across the first and second terminals and thus to each of the diodes, the illuminator emits ultraviolet light at a frequency corresponding to that of the alternating current. The illuminator includes a template with ultraviolet light emitting quantum wells, a first buffer layer with a first type of conductivity and a second buffer layer with a second type of conductivity, all deposited preferably over a strain-relieving layer. A first and second metal contact are applied to the semiconductor layers having the first and second type of conductivity, respectively, to complete the LED. The emission spectrum ranges from 190 nm to 369 nm. The illuminator may be configured in various materials, geometries, sizes and designs. | 2011-03-31 |
20110073839 | II-VI SEMICONDUCTOR NANOWIRES - A high quality II-VI semiconductor nanowire is disclosed. A plurality of II-VI semiconductor nanowires is provided, with each being fixed to a support. Each nanowire terminates in a free end and a metal alloy nanoparticle is fixed to each nanowire at its free end. | 2011-03-31 |
20110073840 | RADIAL CONTACT FOR NANOWIRES - An embodiment is a method and apparatus of radial contact using nanowires. An inner contact has a center. An outer contact surrounds the inner contact around the center and is spaced from the inner contact by a channel length. A nanowire connects the center of the inner contact and the outer contact in a rotationally invariant geometry. | 2011-03-31 |
20110073841 | NANO LINE STRUCTURES IN MICROELECTRONIC DEVICES - A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed. | 2011-03-31 |
20110073842 | NANO-WIRE FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE TRANSISTOR, AND INTEGRATED CIRCUIT INCLUDING THE TRANSISTOR - Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor. | 2011-03-31 |
20110073843 | Organic Light Emitting Display and Process for its Manufacturing - An organic electro-luminescent display is provided, including a thin layer ( | 2011-03-31 |
20110073844 | White Organic Light Emitting Device - A white organic light emitting device having a stack structure of blue fluorescence and red/green phosphorescence is disclosed, in which efficiency of the blue fluorescence is improved to increase lifespan of the white organic light emitting device, color quality is improved, and power consumption is reduced. | 2011-03-31 |
20110073845 | Organic Electroluminescence Device - An organic electroluminescence device includes an organic layer disposed between at least one pair of electrodes, wherein the organic layer includes at least one fluorescent compound selected from compounds represented by the following general formulae (1) and (2): | 2011-03-31 |
20110073846 | ORGANIC ELECTROLUMINESCENT ELEMENT, METHOD FOR MANUFACTURING THE ORGANIC ELECTROLUMINESCENT ELEMENT, AND LIGHT EMITTING DISPLAY DEVICE - Disclosed is an organic electroluminescent element having an element structure that can reduce damage to an organic layer during electrode formation and can facilitate the injection of charges from the electrode into the organic layer. The organic electroluminescent element includes an anode, a cathode, and an organic layer held between the anode and the cathode. The organic layer contains a luminescent material. The organic electroluminescent element further includes a transparent protective layer provided between the anode or the cathode and the organic layer. The transparent protective layer contains a bipolar charge transport organic compound and an electron-accepting compound. The transparent protective layer is formed in a period between after the formation of the organic layer and before the formation of the anode or the cathode on the organic layer. | 2011-03-31 |
20110073847 | LAMINATE, PREPARATORY SUPPORT, METHOD FOR PRODUCING LAMINATE, AND METHOD FOR PRODUCING DEVICE - There are provided a laminate, a preparatory support, a laminate production method and a device production method which make it possible to successfully produce a thin device on a flexible substrate which is likely to bend or break. A laminate | 2011-03-31 |
20110073848 | ORGANIC ELECTROLUMINESCENCE DEVICE - A material for a light emitting device containing a compound represented by the following formula (1): | 2011-03-31 |
20110073849 | METAL COMPLEXES OF CYCLOMETALLATED IMIDAZO[1,2-f ]PHENANTHRIDINE AND DIIMIDAZO[1,2-a:1',2'-c ]QUNIAZOLINE LIGANDS AND ISOELECTRONIC AND BENZANNULATED ANALOGS THEREOF - Compounds comprising phosphorescent metal complexes comprising cyclometallated imidazo[1,2-f]phenanthridine and diimidazo[1,2-a:1′,2′-c]quinazoline ligands, or isoelectronic or benzannulated analogs thereof, are described. Organic light emitting diode devices comprising these compounds are also described. | 2011-03-31 |
20110073850 | ORGANIC ELECTROLUMINESCENT ELEMENT, ILLUMINATOR AND DISPLAY - An organic electroluminescent element containing an anode and a cathode having therebetween a light emitting layer, wherein the light emitting layer contains a guest compound having a substructure represented by the following Formula (A): | 2011-03-31 |
20110073851 | ORGANIC ELECTROLUMINESCENT ELEMENT, ILLUMINATOR AND DISPLAY - An organic electroluminescent element containing an anode and a cathode having therebetween a light emitting layer, wherein the light emitting layer contains a guest compound having a substructure represented by the following Formula (A): | 2011-03-31 |
20110073852 | ORGANIC ELECTROLUMINESCENT DEVICE - A problem of the invention is to provide an organic EL device having a high efficiency, a low driving voltage and a long life, by combining various materials for organic EL device, which are excellent in an injection or transportation performance of holes or electrons, and in stability and durability in a thin film, so as to enable the respective materials to effectively reveal their characteristics. The invention relates to an organic electroluminescent device including at least an anode electrode, a hole-injecting layer, a hole-transporting layer, an emitting layer, an electron-transporting layer and a cathode electrode in this order, in which the hole-injecting layer contains an arylamine compound having, in its molecule, a structure in which three or more triphenylamine structures are connected through a single bond or a hetero atom-free divalent group; and the hole-transporting layer contains an arylamine compound having two triphenylamine structures in its molecule. | 2011-03-31 |
20110073853 | ORGANIC LIGHT-EMITTING DIODE LUMINAIRES - There is provided n organic light-emitting diode luminaire. The luminaire includes a first electrode, a second electrode, and a light-emitting layer therebetween. The light-emitting layer includes a small molecule host material having dispersed therein a first dopant having a first emitted color and a second dopant having a second emitted color. The overall emission color is white. | 2011-03-31 |
20110073854 | POLYMER COMPOUND AND ORGANIC TRANSISTOR USING THE SAME - A polymer compound comprising a repeating unit represented by the formula (I): | 2011-03-31 |
20110073855 | LIQUID CRYSTAL DISPLAY PANEL AND FABRICATION METHOD THEREOF - A method for manufacturing a LCD panel includes providing a substrate defining a TFT region and a pixel region; forming a transparent conductive layer and a first metal layer on the substrate in that order; forming a gate line in the TFT region, and a pixel electrode within the pixel region via a first photo-etching process; forming an insulating layer and a semiconductor layer on the substrate in that order; removing the insulating layer and the semiconductor layer from the pixel region; removing the first metal layer from the pixel region; forming a second metal layer on the substrate; forming a source electrode and a drain electrode in the TFT region via a second photo-etching process, and forming a protecting layer above the substrate. | 2011-03-31 |
20110073856 | THIN FILM TRANSISTOR - To achieve, in an oxide semiconductor thin layer transistor, both the stability of threshold voltage against electric stress and suppression of variation in the threshold voltage in a transfer characteristic. A thin film transistor includes an oxide semiconductor layer and a gate insulating layer disposed so as to be in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer contains hydrogen atoms and includes at least two regions that function as active layers of the oxide semiconductor and have different average hydrogen concentrations in the layer thickness direction; and when the regions functioning as the active layers of the oxide semiconductor are sequentially defined as, from the side of the gate insulating layer, a first region and a second region, the average hydrogen concentration of the first region is lower than the average hydrogen concentration of the second region. | 2011-03-31 |
20110073857 | SEMICONDUCTOR DEVICE, ITS MANUFACTURE METHOD AND TEMPLATE SUBSTRATE - A semiconductor device includes a ZnO-containing substrate containing Li, a zinc silicate layer formed above the ZnO-containing substrate, and a semiconductor layer epitaxially grown relative to the ZnO-containing substrate via the zinc silicate layer. | 2011-03-31 |
20110073858 | Test Structure for Determination of TSV Depth - A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel. | 2011-03-31 |
20110073859 | Reduced Stiction MEMS Device with Exposed Silicon Carbide - A MEMS device has a first member that is movable relative to a second member. At least one of the first member and the second member has exposed silicon carbide with a water contact angle of greater than about 70 degrees. | 2011-03-31 |
20110073860 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A thin film transistor comprising an insulating film, a gate electrode embedded in a superficial portion of the insulating film, a gate insulating film on the gate electrode and the insulating film, a semiconductor film on the gate insulating film, a channel protection film on a portion of the semiconductor film with end surfaces which have a forward tapered slope, a first electrode on the semiconductor film which mounts onto one tapered side of the channel protection film, and a second electrode on the semiconductor film which mounts onto the other tapered side of the channel protection film, where an edge of the gate electrode closest to the first electrode is offset towards the second electrode from the point where the first electrode abuts the semiconductor film. | 2011-03-31 |
20110073861 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE - An object of the present invention is to provide a structure of a thin film circuit portion and a method for manufacturing a thin film circuit portion by which an electrode for connecting to an external portion can be easily formed under a thin film circuit. A stacked body including a first insulating film, a thin film circuit formed over one surface of the first insulating film, a second insulating film formed over the thin film circuit, an electrode formed over the second insulating film, and a resin film formed over the electrode, is formed. A conductive film is formed adjacent to the other surface of the first insulating film of the stacked body to be overlapped with the electrode. The conductive film is irradiated with a laser. | 2011-03-31 |
20110073862 | ARRAY STRUCTURE AND FABRICATING METHOD THEREOF - An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer. | 2011-03-31 |
20110073863 | Organic light emitting diode display - An organic light emitting diode display includes a thin film transistor on a substrate ( | 2011-03-31 |
20110073864 | ARRAY SUBSTRATE AND MANUFACTURING METHOD - A method of manufacturing an array substrate comprising: forming a data line and a gate line which are crossed with each other and a gate electrode on a base substrate, and the data line is discontinuously disposed so as to be separated from the gate line or the gate line is discontinuously disposed so as to be separated from the data line; forming an active layer and a gate insulating layer including bridge via holes and a source electrode via hole on the base substrate, and the bridge via holes are located at positions respectively corresponding to adjacent discontinuous sections of the data line or adjacent discontinuous sections of the gate line, and the source electrode via hole is located at a position corresponding to the data line; and forming a pixel electrode, a source electrode, a drain electrode and a bridge line on the base substrate, and the pixel electrode and the drain electrode are formed integrally, and the source electrode is connected to the data line through the source electrode via hole, and the bridge line connects the adjacent discontinuous sections of the data line or the adjacent discontinuous sections of the gate line through the bridge via holes. | 2011-03-31 |
20110073865 | Display Device and Manufacturing Method Thereof - Conventionally, photolithography and anisotropic etching are performed to form a plug between an electrode and a wiring, etc., thereby increasing the number of steps, getting the throughput worse, and producing unnecessary materials. To solve the problems, the present invention provides a method for manufacturing a display device, including the formation steps of a conductive layer or wirings, and a contact plug that can treat a larger substrate. In the case of forming a plug for electrically connecting conductive patterns comprising plural layers, a pillar made of a conductor is formed over a base conductive layer pattern, and then, after an insulating film is formed over the entire surface, the insulating film is etched back to expose the conductor pillar, and a conductive pattern in an upper layer is formed by ink jetting. In this case, when the conductor pillar is processed, a resist to be a mask can be formed in itself by ink jetting. | 2011-03-31 |
20110073866 | VERTICAL-TYPE SEMICONDUCTOR DEVICE - In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern. | 2011-03-31 |
20110073867 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An array substrate comprises a substrate provided with a circuit pattern and covering layers that cover the upper surfaces and side surfaces of respective portions of the circuit pattern. | 2011-03-31 |
20110073868 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device comprises: a first data line extending in a first direction; a second data line extending in the first direction and arranged so as to be at least partially overlapped with the first data line; a first scanning line and a second scanning line extending in a second direction intersecting the first direction; a first transistor electrically connected to the first data line and electrically connected to the first scanning line; a first pixel electrode electrically connected to the first transistor; a second transistor electrically connected to the second data line and electrically connected to the second scanning line; and a second pixel electrode electrically connected to the second transistor. | 2011-03-31 |
20110073869 | METHOD TO REDUCE DISLOCATION DENSITY IN SILICON USING STRESS - A crystalline material structure with reduced dislocation density and method of producing same is provided. The crystalline material structure is annealed at temperatures above the brittle-to-ductile transition temperature of the crystalline material structure. One or more stress elements are formed on the crystalline material structure so as to annihilate dislocations or to move them into less harmful locations. | 2011-03-31 |
20110073870 | III-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - The present III-nitride semiconductor light-emitting device comprises: a first III-nitride semiconductor layer having a first conductivity type; a second III-nitride semiconductor layer having a second conductivity type different from the first conductivity type; an active layer disposed between the first III-nitride semiconductor layer and the second III-nitride semiconductor layer and generating light by recombination of electrons and holes; and a depletion barrier layer brought into contact with the active layer and having a first conductivity type. | 2011-03-31 |
20110073871 | GALLIUM NITRIDE SUBSTRATE - A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m | 2011-03-31 |
20110073872 | HIGH BRIGHTNESS LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A high brightness light emitting diode includes a carrier substrate and an epitaxial multi-layer formed thereon. The carrier substrate includes a metal material and a medium, and a coefficient of thermal expansion (CTE) of the medium is less than a CTE of the metal material. | 2011-03-31 |
20110073873 | COMPOUND SEMICONDUCTOR DEVICE USING SIC SUBSTRATE AND ITS MANUFACTURE - A compound semiconductor device includes: a conductive SiC substrate; an AlN buffer layer formed on said conductive SiC substrate and containing Cl; a compound semiconductor buffer layer formed on said AlN layer which contains Cl, said compound semiconductor buffer layer not containing Cl; and a device constituent layer or layers formed above said compound semiconductor buffer layer not containing Cl. | 2011-03-31 |
20110073874 | METHOD OF REDUCING MEMORY EFFECTS IN SEMICONDUCTOR EPITAXY - A method of reducing memory effects during an epitaxial growth process is provided in which a gas mixture comprising hydrogen gas and a halogen-containing gas is used to flush the CVD reaction chamber between growth steps. | 2011-03-31 |
20110073875 | OPTICAL SIGNAL TRANSFER IN A SEMICONDUCTOR DEVICE BY USING MONOLITHIC OPTO-ELECTRONIC COMPONENTS - In a semiconductor device, optical signal transfer capabilities are implemented on the basis of silicon-based monolithic opto-electronic components in combination with an appropriate waveguide. Thus, in complex circuitries, such as microprocessors and the like, superior performance may be obtained in terms of signal propagation delay, while at the same time thermal requirements may be less critical. | 2011-03-31 |
20110073876 | LIGHT-EMITTING DEVICE AND DISPLAY - A light-emitting device allowed to obtain polarized light without increasing the number of components or the thickness thereof, and a display including the light-emitting device are provided. The light-emitting device includes: a light-emitting element including, on a substrate, a first electrode, a light-emitting layer and a second electrode in order from the substrate. The substrate has, on a surface facing the first electrode, a first concavo-convex structure including a plurality of strip-shaped protrusion sections with a width equal to or smaller than an upper wavelength limit of visible light, and the first electrode, the light-emitting layer and the second electrode each have, on a surface opposite to a surface facing the substrate, a second concavo-convex structure imitating the protrusion sections of the first concavo-convex structure. | 2011-03-31 |
20110073877 | HIGH-CURRENT/LOW COST READ-IN INTEGRATED CIRCUIT - A Read-In Integrated Circuit scene generator incorporates an array of unit cells, with each cell having a switching control circuit. An array of emitting elements is associated with the unit cells and each element is connected with a lead to the switching control circuit of the associated cell. A first electrically conducting overlayer is deposited substantially covering the array of unit cells and connected for current supply. Each emitting element is connected to the first conducting overlayer and the first conducting overlayer includes vias through which each connecting lead from the emitting element to the switching control circuit extends. A second electrically conducting overlayer is deposited substantially covering the array of unit cells and connected for current return. Each switching control circuit is connected to the second conducting overlayer. The second conducting overlayer also has vias through which each lead from the emitting element extends to the switching circuit. | 2011-03-31 |
20110073878 | LED ARRAY PACKAGE COVERED WITH A HIGHLY THERMAL CONDUCTIVE PLATE - A light source includes a substrate, a light emitting diode on the substrate, and a phosphor layer over the light emitting diode. A plate is on the phosphor layer. An attachment member is coupled to the plate and is configured to conduct heat away from the plate. | 2011-03-31 |
20110073879 | LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS - A light-emitting device operating on a high drive voltage and a small drive current. LEDs ( | 2011-03-31 |
20110073880 | GLASS PLATE WITH GLASS FRIT STRUCTURE - A light emitting device includes: a first substrate; a second substrate; a light emitting unit interposed between the first substrate and the second substrate; and a sealing material bonding the first substrate to the second substrate and sealing the light emitting unit. The sealing material comprises V | 2011-03-31 |
20110073881 | LEDs USING SINGLE CRYSTALLLINE PHOSPHOR AND METHODS OF FABRICATING SAME - Methods for fabricating LED chips from a wafer and devices fabricated using the methods with one method comprising depositing LED epitaxial layers on an LED growth wafer to form a plurality of LEDs on the growth wafer. A single crystalline phosphor is bonded over at least some the plurality of LEDs so that at least some light from the covered LEDs passes through the single crystalline phosphor and is converted. The LED chips can then be singulated from the wafer to provide LED chips each having a portion of said single crystalline phosphor to convert LED light. | 2011-03-31 |
20110073882 | System for Wafer-Level Phosphor Deposition - System for wafer-level phosphor deposition. In an aspect, a semiconductor wafer is provided that includes a plurality of LED dies wherein at least one die includes an electrical contact, a photo-resist post covering the electrical contact, and a phosphor deposition layer covering the semiconductor wafer and surrounding the photo-resist post. In another aspect, a semiconductor wafer is provided that comprises a plurality of LED dies wherein at least one die comprises an electrical contact, a phosphor deposition layer covering the semiconductor wafer, and a cavity in the phosphor deposition layer exposing the at least one electrical contact. | 2011-03-31 |
20110073883 | LED LAMP - An LED lamp A | 2011-03-31 |
20110073884 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display is disclosed. The organic light emitting diode display includes a plurality of subpixels that emit light of at least three colors, the plurality of subpixels each including a first electrode, an organic light emitting layer, and a second electrode. Each of the organic light emitting layers of at least two of the plurality of subpixels includes at least two electron transport layers. The organic light emitting layer of at least one of the plurality of subpixels includes at least one electron transport layer. | 2011-03-31 |
20110073885 | ORGANIC ELECTROLUMINESCENT DEVICE - An electroluminescent device includes: first to third pixel regions; a first electrode in each of the first to third pixel regions, wherein the first electrode of the third pixel region has a first thickness, the first electrode of the first pixel region has a second thickness less than the first thickness, and the first electrode of the second pixel region has a third thickness less than the second thickness; a second electrode in each of the first to third pixel regions; at least two electroluminescent units in each of the first and third pixel regions and disposed between the first electrode and second electrode, wherein one of the at least two electroluminescent units includes a blue light emitting layer and the other of the at least two electroluminescent units include a red/green light emitting layer; and a charge generation layer disposed between the at least two electroluminescent units. | 2011-03-31 |
20110073886 | LED multi-side light source bracket - The present invention relates to a LED multi-side light source bracket, in particular to the bracket design that extends in the rectangular shape directly above the conducting pin for distribution and fixing of a plurality of chips before, after and above the rectangular block, wherein the chips are bridged to another conducting pin on the side through a plurality of conducting wires to be integrated with the resin or silicon lamp housing, the rectangular block support can be bent into the | 2011-03-31 |
20110073887 | OPTOELECTRONIC DEVICES HAVING A DIRECT-BAND-GAP BASE AND AN INDIRECT-BAND-GAP EMITTER - Optoelectronic devices, junctions and methods of fabricating a device or junction where the emitter layer is of an indirect-band-gap material and the base layer is of a direct-band-gap material. The device or junction may have, among other structures and layers, a base layer of a first semiconductor material having a first conductivity type and further having a direct band gap and an emitter layer forming a junction with the base layer. In this embodiment, the emitter layer may be of a second semiconductor material having a second conductivity type and further having an indirect band gap. The optoelectronic device may have the semiconductor material of the emitter layer substantially lattice mismatched with the semiconductor material of the base layer in bulk form. Alternatively, the emitter layer may be substantially lattice matched with the base layer. | 2011-03-31 |
20110073888 | GROUP III NITRIDE SEMICONDUCTOR OPTICAL DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF MAKING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A group III nitride semiconductor optical device includes: a substrate comprising a group III nitride semiconductor; a first group-III nitride semiconductor region on a primary surface of the substrate; a second group-III nitride semiconductor region on the primary surface of the substrate; and an active layer between the first group-III nitride semiconductor region and the second group-III nitride semiconductor region. The primary surface of the substrate tilts at a tilt angle in the range of 63 degrees to smaller than 80 degrees toward the m-axis of the group III nitride semiconductor from a plane perpendicular to a reference axis extending along the c-axis of the group III nitride semiconductor. The first group-III nitride semiconductor region, the active layer, and the second group-III nitride semiconductor region are arranged in the direction of the normal axis to the primary surface of the substrate. The active layer is configured to produce light having a wavelength in the range of 580 nm to 800 nm. The active layer includes an epitaxial semiconductor layer comprising a gallium nitride based semiconductor containing indium as a group III element. The epitaxial semiconductor layer has an indium content ranging from 0.35 to 0.65. The c-axis of the gallium nitride based semiconductor tilts from the normal axis. The reference axis is oriented in the direction of either the axis [0001] or [000−1] of the group III nitride semiconductor. | 2011-03-31 |
20110073889 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light-emitting device of the invention includes: a semiconductor layer including a light-emitting layer and having a first major surface and a second major surface opposite to the first major surface; a phosphor layer facing to the first major surface; an interconnect layer provided on the second major surface side and including a conductor and an insulator; and a light-blocking member provided on a side surface of the semiconductor layer and being opaque to light emitted from the light-emitting layer. | 2011-03-31 |
20110073890 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING DEVICE - A method for manufacturing a semiconductor light-emitting device of the invention includes: forming a semiconductor layer including a light-emitting layer and a first interconnect layer on a major surface of a temporary substrate; dividing the semiconductor layer and the first interconnect layer into a plurality of chips by a trench; collectively bonding each divided portion of the first interconnect layer of a plurality of chips to be bonded not adjacent to each other out of the plurality of chips on the temporary substrate to a second interconnect layer while opposing the major surface of the temporary substrate and the major surface of a supporting substrate forming the second interconnect layer, and collectively transferring a plurality of the bonded chips from the temporary substrate to the supporting substrate after irradiating interfaces between the bonded chips and the temporary substrate and separating the chips and the temporary substrate from each other. | 2011-03-31 |
20110073891 | AC DRIVEN LIGHT EMITTING DIODE LIGHT APPARATUS, AND ITS AC DRIVEN LIGHT EMITTING DIODE PACKAGE ELEMENT THEREIN - An AC driven light emitting diode light apparatus, and its AC driven light emitting diode package element therein are provided. The AC driven light emitting diode package element includes a heat sinking substrate, a chip set, a pair of electrodes, and a package body. The heat sinking substrate has a fixing flange extended from a rim of the heat sinking substrate for fixing the heat sinking substrate on a support. The chip set is on the heat sinking substrate. The conductive electrodes are respectively set at two opposite sides of the heat sinking substrate. The package body envelops the heat sinking substrate, the chip set and a part of the conductive electrodes to be one. | 2011-03-31 |
20110073892 | LIGHT EMITTING DEVICE - A light emitting device having a relatively simple configuration is provided that emits stable light having a plurality of wavelengths. The light emitting device | 2011-03-31 |
20110073893 | LED STRUCTURE TO INCREASE BRIGHTNESS - A light emitting semiconductor device comprising an LED having an emission aperture located on a surface of the LED and the emission aperture has a size that is smaller than a surface area of the LED where the emission aperture is formed. The device further includes a reflector surrounding both side walls, a bottom surface, and portions of a surface of the LED where the emission aperture is formed or surrounding the bottom surface and portions of the surface of the LED where the emission aperture is formed so that an area on the surface uncovered by the reflector is the emission aperture and is smaller than the area of the LED. Alternatively, in the light emitting semiconductor, the surface of the LED substantially aligned with the emission aperture may be roughened and the surface of the LED beyond the emission aperture may be smooth. The surface of the LED beyond the emission aperture may also be covered by a low loss reflector. | 2011-03-31 |
20110073894 | LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - In one aspect of the invention, an LED includes a substrate, an n-type semiconductor layer, a light emitting layer, a p-type semiconductor layer and a transparent conductive layer sequentially stacked on the substrate, and p-type and n-type electrodes. The p-type semiconductor layer has a rough surface region and at least one flat surface region. The transparent conductive layer has a rough surface region and a flat surface region corresponding to the rough surface region and the at least one flat surface region of the p-type semiconductor layer, respectively. The p-type electrode is disposed on the flat surface region of the transparent conductive layer. The n-type electrode is electrically couple to the n-type semiconductor layer. | 2011-03-31 |
20110073895 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a semiconductor light emitting element, a lead electrically connected to the semiconductor light emitting element, and a resin package covering the semiconductor light emitting element and part of the lead. The resin package includes a lens facing the semiconductor light emitting element. The lead includes an exposed portion that is not covered by the resin package. The exposed portion includes a first portion and a second portion, where the first portion has a first mount surface oriented backward along the optical axis of the lens, and the second portion has a second mount surface oriented perpendicularly to the optical axis of the lens. | 2011-03-31 |
20110073896 | System for Wafer-Level Phosphor Deposition - System for wafer-level phosphor deposition. A method for phosphor deposition on a semiconductor wafer that has a plurality of LED dies includes the operations of covering the semiconductor wafer with a selected thickness of photo resist material, removing portions of the photo resist material to expose portions of the semiconductor wafer so that electrical contacts associated with the plurality of LED dies remain unexposed, and depositing phosphor on the exposed portions of the semiconductor wafer. | 2011-03-31 |
20110073897 | ORGANIC LED AND MANUFACTURING METHOD THEREOF - The present invention provides an organic light emitting diode comprising a substrate, a first electrode provided on the substrate, one or more organic material layers provided on the first electrode, a second electrode provided on the organic material layer, and a light extraction layer provided on the top portion of the second electrode, and a method for manufacturing the same. The organic light emitting diode according to the present invention minimizes total internal reflection of the light emitted from a device to improve the light emitting efficiency. | 2011-03-31 |
20110073898 | LED MODULE - The present invention relates to a LED module which converts pump light from a LED chip ( | 2011-03-31 |
20110073899 | WHITE LIGHT SOURCE, BACKLIGHT, LIQUID CRYSTAL DISPLAY APPARATUS, AND ILLUMINATING APPARATUS - A white light source includes: an insulating substrate; a light-emitting diode chip provided on the insulating substrate and that emits ultraviolet light with a wavelength of 330 nm to 410 nm; and a phosphor layer formed to cover the light-emitting diode chip, including a red emitting phosphor, a green emitting phosphor, and a blue emitting phosphor as a phosphor, and the phosphors are dispersed in a cured transparent resin, wherein when it is assumed that the shortest distance between a surface of the phosphor layer and a peripheral portion of the light-emitting diode chip is t(mm) and the mean free path defined by the following expression (1) is L(mm), the t and L satisfy 3.2≦t/L. | 2011-03-31 |
20110073900 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a semiconductor structure unit; an interconnect layer provided on the major surface side of the semiconductor structure unit; an electrode pad provided on a surface of the interconnect layer on a side opposite to a surface on which the semiconductor structure unit is provided, and the electrode pad electrically connected to the interconnect layer; a plurality of metal pillars joined to the electrode pad separately from each other; and an external terminal provided commonly at tips of the plurality of metal pillars, the metal pillars having an area in a plan view smaller than an area in a plan view of the external terminal. | 2011-03-31 |
20110073901 | ADHESIVE ENCAPSULATING COMPOSITION AND ELECTRONIC DEVICES MADE THEREWITH - Adhesive encapsulating compositions for use in electronic devices such as organic electroluminescent devices, touch screens, photovoltaic devices, and thin film transistors are disclosed herein. The adhesive encapsulating compositions include pressure sensitive adhesives comprising one or more cyclic olefin copolymers, in combination with multifunctional (meth)acrylate monomers and tackifiers. | 2011-03-31 |
20110073902 | Semiconductor Body and Method of Producing a Semiconductor Body - A semiconductor body includes an n-conductive semiconductor layer and a p-conductive semiconductor layer. The p-conductive semiconductor layer contains a p-dopant and the n-conductive semiconductor layer an n-dopant and a further dopant. | 2011-03-31 |
20110073903 | SEMICONDUCTOR DEVICE - A reverse blocking IGBT according to the invention can include a reverse breakdown withstanding region, p-type outer field limiting rings formed in a reverse breakdown withstanding region and an outer field plate connected to the outer field limiting rings, the outer field plate including a first outer field plate in contact with outer filed limiting rings nearest to the active region and second outer field plates in contact with other outer field limiting rings. The first outer field plate having an active region side edge portion projecting toward the active region and second outer field plate having an edge area side edge portion projecting toward the edge area. The reverse blocking IGBT according to the invention can facilitate improving the withstand voltages thereof and reducing the area thereof. | 2011-03-31 |
20110073904 | Semiconductor device having SOI substrate and method for manufacturing the same - A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element. | 2011-03-31 |
20110073905 | SEMICONDUCTOR DEVICE AND POWER CONVERTER USING IT - A semiconductor device and a power converter using it wherein a switching power device and a flywheel diode are connected in series, the flywheel diode includes a region having a Schottky junction to operate as a Schottky diode and a region having a pn junction to operate as a pn diode and control operation is performed such that when current flows forwardly through the flywheel diode, the pn diode operates and when the flywheel diode recovers backwardly, the Schottky diode operates mainly. | 2011-03-31 |
20110073906 | High voltage MOSFET diode reverse recovery by minimizing P-body charges - This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions; and f) etching contact trenches into the source, body contact, and body regions. | 2011-03-31 |
20110073907 | INTEGRATED CIRCUIT STRUCTURES CONTAINING A STRAIN-COMPENSATED COMPOUND SEMICONDUCTOR LAYER AND METHODS AND SYSTEMS RELATED THERETO - A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein. | 2011-03-31 |
20110073908 | III-V Semiconductor Device Structures - The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. | 2011-03-31 |
20110073909 | REPLACEMENT SPACER FOR TUNNEL FETS - A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess. | 2011-03-31 |
20110073910 | NITRIDE SEMICONDUCTOR MATERIAL, SEMICONDUCTOR ELEMENT, AND MANUFACTURING METHOD THEREOF - The nitride semiconductor material according to the present invention includes a group III nitride semiconductor and a group IV nitride formed on the group III nitride semiconductor, where an interface between the group III nitride semiconductor and the group IV nitride has a regular atomic arrangement. Moreover, an arrangement of nitrogen atoms of the group IV nitride in the interface and an arrangement of group III atoms of the group III nitride semiconductor in the interface may be substantially identical. | 2011-03-31 |
20110073911 | SEMICONDUCTOR DEVICE - A semiconductor device including: a substrate, which has a composition represented by the formula: Al | 2011-03-31 |
20110073912 | AlGaN/GaN hemt with normally-off threshold minimized and method of manufacturing the same - In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained. | 2011-03-31 |
20110073913 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES ON A GROUP IV SUBSTRATE WITH CONTROLLED INTERFACE PROPERTIES AND DIFFUSION TAILS - Electronic and opto-electronic devices having epitaxially-deposited III/V compounds on vicinal group IV substrates and method for making same. The devices include an AlAs nucleating layer on a Ge substrate. The group IV substrate contains a p-n junction whose change of characteristics during epitaxial growth of As-containing layers is minimized by the AlAs nucleating layer. The AlAs nucleating layer provides improved morphology of the devices and a means to control the position of a p-n junction near the surface of the group IV substrate through diffusion of As and/or P and near the bottom of the III/V structure through minimized diffusion of the group IV element. | 2011-03-31 |
20110073914 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD. | 2011-03-31 |
20110073915 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to the present invention includes an I/O cell, a first PAD connected to the I/O cell, first and second PADs, a package wire which is connected to the first PAD and allows connection between the first PAD and an outside of the semiconductor integrated circuit, and a second package wire which is connected to the second PAD and allows connection between the second PAD and an outside of the semiconductor integrated circuit. A connection point between the first PAD and the fist package wire is located in an area where the I/O cell is placed. A connection point between the second PAD and the second package wire is located outside an area where the I/O cell is placed. | 2011-03-31 |
20110073916 | GATE ARRAY - A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased. | 2011-03-31 |
20110073917 | Method of high density memory fabrication - The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level. | 2011-03-31 |