13th week of 2012 patent applcation highlights part 16 |
Patent application number | Title | Published |
20120074528 | TECHNIQUE TO MODIFY THE MICROSTRUCTURE OF SEMICONDUCTING MATERIALS - A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material. | 2012-03-29 |
20120074529 | SEMICONDUCTOR PACKAGE WITH THROUGH ELECTRODES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips. | 2012-03-29 |
20120074530 | INTERPOSER INCLUDING AIR GAP STRUCTURE, METHODS OF FORMING THE SAME, SEMICONDUCTOR DEVICE INCLUDING THE INTERPOSER, AND MULTI-CHIP PACKAGE INCLUDING THE INTERPOSER - Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element. | 2012-03-29 |
20120074531 | EPITAXY SUBSTRATE - An epitaxy substrate for growing a plurality of semiconductor epitaxial layers thereon, includes a plurality of growth areas and a plurality of protected areas. The growth areas are provided for growing the semiconductor epitaxial layers thereon. The growth areas and the protected areas are alternating. A thickness of the growth areas is less than ⅓ of a thickness H of the protected areas. | 2012-03-29 |
20120074532 | SEMICONDUCTOR PACKAGE WITH INTEGRATED METAL PILLARS AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a substrate and a semiconductor device. The semiconductor device includes a body having a center, a layer disposed adjacent to the body, and a plurality of conductive pillars configured to electrically connect the semiconductor device to the substrate. The layer defines a plurality of openings. Each of the plurality of conductive pillars extends at least partially through a corresponding one of the plurality of openings. An offset between a first central axis of the each of the plurality of conductive pillars and a second central axis of the corresponding one of the plurality of openings varies with distance between the first central axis and the center of the body. The second central axis of the corresponding one of the plurality of openings is disposed between the first central axis of the each of the plurality of conductive pillars and the center of the body. | 2012-03-29 |
20120074533 | Structures And Techniques For Atomic Layer Deposition - In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C. | 2012-03-29 |
20120074534 | Semiconductor Device and Method of Forming Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. | 2012-03-29 |
20120074535 | LOW DIELECTRIC CONSTANT MATERIAL - The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH | 2012-03-29 |
20120074536 | Methods of Manufacturing Semiconductor Devices and Structures Thereof - Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern. | 2012-03-29 |
20120074537 | DIELECTRIC STACK - A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness T | 2012-03-29 |
20120074538 | PACKAGE STRUCTURE WITH ESD AND EMI PREVENTING FUNCTIONS - A package structure with ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a carrier having first and second ground structures electrically insulated from one another; a semiconductor component disposed on one surface of the carrier and electrically connected to the first ground structure; and a lid member disposed to cover the carrier and the semiconductor component and electrically connected to the second ground structure. The semiconductor component and the lid member are electrically connected with the first ground structure and the second ground structure, respectively, such that electrostatic charges and electromagnetic waves can be conducted away individually without damaging the semiconductor component, thereby improving yield and reducing the risk of short circuits. | 2012-03-29 |
20120074539 | DEVICE AND METHODS FOR ELECTROSTATIC DISCHARGE PROTECTION - An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss. | 2012-03-29 |
20120074540 | SEMICONDUCTOR CHIP PACKAGE - A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads. | 2012-03-29 |
20120074541 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique is provided which allows a chip mounted by wire bonding and a chip mounted by bump electrodes to share a manufacturing process. Both in a case where a chip is electrically coupled to an external circuit by bump electrodes and a case where the chip is electrically coupled to the external circuit by bonding wires, a bump coupling part and a bonding pad are both provided in a single uppermost wiring layer. When the bump electrodes are used, an opening is provided in an insulating film on the bump coupling part and a surface of the bonding pad is covered with the insulating film. On the other hand, when the bonding wires are used, an opening is provided in an insulating film on the bonding pad and a surface of the bump coupling part is covered with the insulating film. | 2012-03-29 |
20120074542 | SEMICONDUCTOR DEVICE - A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath case, includes a metal step support, a shield plate and a metal ring. The support includes a base portion implanted in the sheath case, a connection portion which extends from an end of the base portion, and a step portion formed at a boundary between the base portion and the connection portion. The shield plate is disposed over the step portion such that the connection portion of the support pierces the shield plate. An end of the metal ring protrudes from an end of the connection portion over the shield plate. The semiconductor device is adapted such that the control circuit board is mounted over the protruded end of the metal ring and is fixed onto the connection portion by an engagement member. | 2012-03-29 |
20120074543 | PACKAGE APPARATUS OF POWER SEMICONDUCTOR DEVICE - A package apparatus is for packaging a power semiconductor device that includes a substrate formed, a mold part molded on the substrate, and electrode terminals extended from the mold part to a side opposite from the substrate by a predetermined length; includes: a holding unit that has insertion slots and is to holding the power semiconductor device, the insertion slots each being an opening into which the power semiconductor device is insertable in a direction perpendicular to extending direction of the electrode, edges of the opening being formed to make contact with the mold part and the substrate; and a container box that contains the holding unit. The insertion slots are provided to the holding unit so that an interval between the insertion slots in an extending direction of the electrode terminals of the power semiconductor device inserted is greater than the extending length of the electrode terminals. | 2012-03-29 |
20120074544 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the die pad of the lead frame, and bonding wires for electrically interconnecting the lead of the lead frame and the semiconductor element. The lead frame, the semiconductor element, and the bonding wires are sealed with a sealing resin section. The sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region. Thickness of the central region is greater than that of the marginal region. | 2012-03-29 |
20120074545 | THIN FLIP CHIP PACKAGE STRUCTURE - A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess. | 2012-03-29 |
20120074546 | Multi-chip Semiconductor Packages and Assembly Thereof - Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die. | 2012-03-29 |
20120074547 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole. | 2012-03-29 |
20120074548 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a lead overhang protruding from a lead non-horizontal side and a lead ridge protruding from the lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming an encapsulation over the integrated circuit, the lead, and the package paddle, the encapsulation under the lead overhang. | 2012-03-29 |
20120074549 | SEMICONDUCTOR DEVICE WITH EXPOSED PAD - A semiconductor device has a die attached to a die pad and electrically connected to lead fingers. The die, a top surface of the die pad, and a first portion of the lead fingers are covered with a mold compound. A second portion of the lead fingers project from the mold compound and allow for external electrical connection to the die. The mold compound around the die and lead fingers is extended such that a cavity is formed below the die pad. The die pad is exposed via the cavity. A heat sink may be inserted into the cavity and attached to the bottom surface of the die pad. | 2012-03-29 |
20120074550 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame includes a die stage; an inner lead provided near the die stage; and a bus bar provided between the die stage and the inner lead and supported by a hanging lead, wherein the hanging lead is inclined with respect to the inner lead, and a wire connection face of the bus bar is displaced with respect to a wire connection face of the inner lead in a direction of a frame thickness. | 2012-03-29 |
20120074551 | SEMICONDUCTOR DEVICE - An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating resin. Lead frames are provided in both sides of the lead frame. A portion of the lead frame is encapsulated with the encapsulating resin to function as an inner lead. The encapsulating resin is composed of a resin composition that contains substantially no halogen. Further, an exposed portion of the Al pad provided in the semiconductor chip is electrically connected to the inner lead via the AuPd wire. | 2012-03-29 |
20120074552 | CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a hybrid integrated circuit device, a circuit board on which an island portion of a lead is fixedly attached and a control board on which a control element and the like are mounted are disposed in an overlapping manner. The circuit board and the control board are integrally encapsulated with an encapsulating resin. A transistor disposed on an upper surface of the circuit board and a control element mounted on an upper surface of the control board are also covered by the encapsulating resin. Thus, a module in which an inverter circuit and a control circuit are integrally encapsulated with resin is provided. | 2012-03-29 |
20120074553 | METHOD AND SYSTEM FOR IMPROVING RELIABILITY OF A SEMICONDUCTOR DEVICE - A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a semiconductor chip, a metallization layer comprising a metallic material disposed over a surface of the semiconductor chip, and an alloy layer comprising the metallic material disposed over the metallization layer. | 2012-03-29 |
20120074554 | BOND RING FOR A FIRST AND SECOND SUBSTRATE - The present disclosure provides a device having a plurality of bonded substrates. The substrates are bonded by a first bond ring and a second bond ring. In an embodiment, the first bond ring is a eutectic bond and the second bond ring is at least one of an organic material and a eutectic bond. The second bond ring encircles the first bond ring. The first bond ring provides a hermetic region of the device. In a further embodiment, a plurality of wafers are bonded which include a third bond ring disposed at the periphery of the wafers. | 2012-03-29 |
20120074555 | SEMICONDUCTOR PACKAGE INCLUDING CAP - A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns. | 2012-03-29 |
20120074556 | SEMICONDUCTOR POWER MODULE AND METHOD OF MANUFACTURING THE SAME - A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block. | 2012-03-29 |
20120074557 | Integrated Circuit Package Lid Configured For Package Coplanarity - An integrated circuit package apparatus comprises a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided. | 2012-03-29 |
20120074558 | Circuit Board Packaged with Die through Surface Mount Technology - A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications. | 2012-03-29 |
20120074559 | INTEGRATED CIRCUIT PACKAGE USING THROUGH SUBSTRATE VIAS TO GROUND LID - An integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias. The stack of two or more integrated circuit chips is disposed within the metal lid and electrically mounted to the package substrate. An inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias. The TSVs provide electromagnetic interference shielding. A conductive thermal interface material may also be used. An alternative embodiment includes a single integrated circuit chip using TSVs to ground the metal lid. | 2012-03-29 |
20120074560 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier. | 2012-03-29 |
20120074561 | BACKMETAL REPLACEMENT FOR USE IN THE PACKAGING OF INTEGRATED CIRCUITS - One aspect of the invention pertains to an arrangement for forming exposed die packages. The arrangement includes a semiconductor wafer having multiple integrated circuit dice whose back surfaces cooperate to form the back surface of the wafer. A thermally conductive adhesive layer is deposited on the back surface of the wafer. The metal foil is attached to the wafer with the adhesive layer. Methods of forming exposed die packages using the above arrangement are also described. | 2012-03-29 |
20120074562 | Three-Dimensional Integrated Circuit Structure with Low-K Materials - A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the substrate; and a low-k dielectric layer over the substrate. | 2012-03-29 |
20120074563 | Semiconductor apparatus and the method of manufacturing the same - A semiconductor apparatus includes a semiconductor chip, a post electrode positioned on the front surface electrode, and a metal particle layer having metal particles bonded actively to each other. The front surface electrode and the post electrode are bonded with each other through the metal particle layer. A method of manufacturing a semiconductor apparatus includes the steps of coating metal particles protected with organic coating films to at least one of the front surface electrode of a semiconductor chip or the post electrode; pressing and heating the metal particles between the front surface electrode of the semiconductor chip and post electrode for breaking the organic coating films and for exposing the metal particles; and actively bonding the exposed metal particles to each other for bonding the front surface electrode and post electrode. | 2012-03-29 |
20120074564 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device comprises a semiconductor substrate having a connection pad, an external connection electrode provided on the semiconductor substrate to be connected to the connection pad, and a sealing film provided to cover the external connection electrode, wherein an opening is provided in the sealing film to expose a center of the upper surface of the external connection electrode, and the sealing film is provided to cover an outer peripheral part of the upper surface of the external connection electrode. | 2012-03-29 |
20120074565 | SEMICONDUCTOR DEVICE PROVIDED WITH REAR PROTECTIVE FILM ON OTHER SIDE OF SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - An opening is formed in a part of a rear protective film corresponding to the center of a dicing street by laser processing which applies a laser beam. The rear protective film is formed on the lower surface of a semiconductor wafer, and made of a resin. By using a resin cutting blade, parts of a sealing film and the upper side of the semiconductor wafer corresponding to the dicing street and both its sides are then cut to form a trench. By using a silicon cutting blade, parts of the semiconductor wafer and the rear protective film corresponding to the dicing street are then cut. In this case, cutting of the rear protective film with the silicon cutting blade is reduced by the opening. | 2012-03-29 |
20120074566 | Package For Semiconductor Device Including Guide Rings And Manufacturing Method Of The Same - An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate. | 2012-03-29 |
20120074567 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers - A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die. | 2012-03-29 |
20120074568 | METHOD AND SYSTEM FOR MINIMIZING CARRIER STRESS OF A SEMICONDUCTOR DEVICE - A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier. | 2012-03-29 |
20120074569 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate. | 2012-03-29 |
20120074570 | Method for Forming a Through Via in a Semiconductor Element and Semiconductor Element Comprising the Same - A method for forming a through via in a semiconductor element includes providing a semiconductor element having electronic circuitry integrated on the main side thereof. The semiconductor element further includes an etch stop layer and a conductive region, wherein the conductive region is arranged between the etch stop layer and the main side of the semiconductor element. The method also includes selectively etching a through via from a backside of the semiconductor element, opposite to the main side of the semiconductor element, to the etch stop layer and removing at least partly the etch stop layer, so that the conductive region is exposed to the backside and filling at least partly the through via with a conductive material, wherein the conductive material is electrically isolated from the semiconductor element. | 2012-03-29 |
20120074571 | METHODS AND ARCHITECTURES FOR BOTTOMLESS INTERCONNECT VIAS - An apparatus includes an interconnect in a recess. The interconnect includes a liner structure and the liner structure in the recess. The liner structure is breached at the recess bottom feature and a bottom interconnect makes a single-interface contact with a subsequent interconnect through the breach. | 2012-03-29 |
20120074572 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer. | 2012-03-29 |
20120074573 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure. | 2012-03-29 |
20120074574 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer. | 2012-03-29 |
20120074575 | COPPER LINE HAVING SELF-ASSEMBLED MONOLAYER FOR ULSI SEMICONDUCTOR DEVICES, AND A METHOD OF FORMING SAME - A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region. | 2012-03-29 |
20120074576 | INTERCONNECT FOR AN OPTOELECTRONIC DEVICE - Interconnects for optoelectronic devices are described. An interconnect may include a stress relief feature. An interconnect may include an L-shaped feature. | 2012-03-29 |
20120074577 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE, AND SWITCHING CIRCUIT - It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a plurality of signal side electrodes arranged on a semiconductor substrate in an alternating manner; a plurality of control electrodes arranged respectively between each pair of a ground side electrode and a signal side electrode; a ground side electrode connecting section that connects the ground side electrodes to each other; a signal side electrode connecting section that connects the signal side electrodes to each other; and ground side lead wiring and signal side lead wiring that extend respectively from a region near one end and a region near another end of an arranged electrode section, in which the ground side electrodes and the signal side electrodes are arranged in an arrangement direction, away from the arranged electrode group in the arrangement direction. | 2012-03-29 |
20120074578 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT MOUNTED BOARD, AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor element includes connection terminals. The connection terminals are each shaped in such a manner that the transverse cross-sectional area in a portion near the leading end thereof decreases toward the leading end. Specifically, the shape of each of the connection terminals is columnar except for the portion near the leading end, and the side surface in the portion near the leading end of the connection terminal is shaped in a tapered form. Furthermore, a metal layer for improving a solder wettability may be formed at least on the side surface shaped in the tapered form, of the connection terminal. | 2012-03-29 |
20120074579 | SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS - A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side. | 2012-03-29 |
20120074580 | METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C | 2012-03-29 |
20120074581 | DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate. | 2012-03-29 |
20120074582 | DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME - A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. | 2012-03-29 |
20120074583 | SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING - A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width. | 2012-03-29 |
20120074584 | MULTI-LAYER TSV INSULATION AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate. The stacked insulation layer can include at least one first insulation layer and at least one second insulation layer whose dielectric constant is different than that of the first insulation layer. One insulation layer may be a polymer and one insulation layer may be a silicon based insulation layer. The insulation layers may be uniform in thickness or may vary as a distance from the substrate changes. | 2012-03-29 |
20120074585 | Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer - A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die. | 2012-03-29 |
20120074586 | METHODS OF FABRICATING PACKAGE STACK STRUCTURE AND METHOD OF MOUNTING PACKAGE STACK STRUCTURE ON SYSTEM BOARD - A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate. | 2012-03-29 |
20120074587 | Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level - A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die. | 2012-03-29 |
20120074588 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier. | 2012-03-29 |
20120074589 | CORNER STRUCTURE FOR IC DIE - One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip. | 2012-03-29 |
20120074590 | MULTIPLE BONDING IN WAFER LEVEL PACKAGING - The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided. | 2012-03-29 |
20120074591 | THIN WAFER SUPPORT ASSEMBLY - A semiconductor wafer assembly formed by bonding a support wafer to a thin wafer using a double-sided bonding release tape. The support wafer provides support for the thin target wafer such that existing handling tools can accommodate transporting and processing the assembly without compromising the profile of the thin target wafer. | 2012-03-29 |
20120074592 | WAFER-LEVEL PACKAGING METHOD USING COMPOSITE MATERIAL AS A BASE - An electronic package that includes a composite material base. In one embodiment the electronic package is an expanded wafer-level package. The composite material base is composed of woven strands and polymer material. In one embodiment the composite material base is composed of woven fiberglass strands and an epoxy material. In various embodiments the package includes an electronic circuitry layer on one or another face of the composite material base. In other embodiments conductive vias connect the circuitry layers, including a redistribution layer. In yet another embodiment an electronic package is mounted on the composite material base and electrically couples to the circuit of the expanded wafer-level package. The package having the composite material base is mechanically stronger and can be made thinner than a package that relies on an encapsulant material for structure, and resists cracking. | 2012-03-29 |
20120074593 | CHIP STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME - A chip stacked structure and method of fabricating the same are provided. The chip stacked structure includes a first chip and a second chip stacked on the first chip. The first chip has a plurality of metal pads disposed on an upper surface thereof and grooves disposed on a side surface thereof. The metal pads are correspondingly connected to upper openings of the grooves. The second chip has a plurality of grooves on a side surface of the second chip, locations of which are corresponding to that of the grooves on the side surface of the first chip. Conductive films are formed on the grooves of the first chip and the second chip and the metal pads to electronically connect the first chip and second chip. The chip stacked structure may simplify the process and improve the process yield rate. | 2012-03-29 |
20120074594 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprising a support plate, a semiconductor element mounted on the support plate and including a circuit element surface having a plurality of first electrodes, a first insulation layer covering the circuit element surface of the semiconductor element, and including a plurality of first apertures exposing the plurality of first electrodes, a second insulation layer covering an upper part of the support plate and side parts of the semiconductor element, and wirings formed on an upper part of the first insulation layer and on an upper part of the second insulation layer, and electrically connected to the corresponding first electrodes. | 2012-03-29 |
20120074595 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate on which a first semiconductor chip is mounted, a second substrate spaced apart from the first substrate and on which a second semiconductor chip is mounted, first pads disposed on the first substrate, second pads disposed on the second substrate to be opposite to the first pads, and connection patterns electrically connecting the opposite first and second pads to each other, respectively. The first pads are disposed asymmetrically with respect to the central axis of the first substrate. | 2012-03-29 |
20120074596 | SET OF RESIN COMPOSITIONS FOR PREPARING SYSTEM-IN-PACKAGE TYPE SEMICONDUCTOR DEVICE - Set of compositions for preparing system-in-package type semiconductor device. The composition set consists of underfill composition for preparing underfill part and encapsulation resin composition for preparing resin encapsulation part. 1) A cured product of the underfill composition has a glass transition temperature, Tg, ≧100° C. and is the same with or differs from a Tg of a cured product of the encapsulation resin composition by ≦20° C. 2) Total linear expansion coefficient of the cured product of the underfill composition at a temperature not higher than (Tg−30)° C. and a linear expansion coefficient of the cured product of the encapsulation resin composition at a temperature not higher than (Tg−30)° C. is ≦42 ppm/° C. 3) A ratio of the linear expansion coefficient of the cured product of the encapsulation resin composition to the linear expansion coefficient of the cured product of the underfill composition ranges from 0.3 to 1.0. | 2012-03-29 |
20120074597 | FLEXIBLE UNDERFILL COMPOSITIONS FOR ENHANCED RELIABILITY - Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed. | 2012-03-29 |
20120074598 | CHIP, METHOD FOR PRODUCING A CHIP AND DEVICE FOR LASER ABLATION - In various embodiments, a chip may include a substrate; a coating, the coating covering the substrate at least partially and the coating being designed for being stripped at least partially by means of laser ablation; wherein between the substrate and the coating, a laser detector layer is arranged at least partially, the laser detector layer being designed for generating a detector signal for ending the laser ablation. | 2012-03-29 |
20120074599 | METHOD OF FORMING WAFER LEVEL MOLD USING GLASS FIBER AND WAFER STRUCTURE FORMED BY THE SAME - According to example embodiments, a wafer level mold may be formed by a method including attaching a substrate to a lower side of a wafer on which a semiconductor chip is arranged, applying molding liquid to an upper and at least one lateral side of the semiconductor chip and an upper side of the wafer where the semiconductor chip is not arranged, loading a fiber onto the applied liquid, forming a mold layer by compression-molding and curing the liquid loaded with the fiber, and separating the substrate from the wafer. | 2012-03-29 |
20120074600 | ELECTRICALLY ACTIVATED CARBURETTOR - In order to create an electrically activated carburettor for petrol engines with an air funnel for sucking in fuel from a fuel line leading into the air funnel which is connected to a fuel chamber and between fuel chamber and orifice in the air funnel a fuel jet for adjusting a fuel quantity that can be sucked in from the fuel chamber because of vacuum in the air funnel that can be flexibly adapted as carburettor more preferably for power implements, which overcomes the abovementioned disadvantages of the prior art and has a simple, sturdy construction which allows constant long-term behaviour, it is proposed that in series connection with the fuel jet at least two Tesla diodes are provided, between which a pumping chamber with a pumping unit is located. | 2012-03-29 |
20120074601 | HUMIDIFICATION CHAMBERS - A humidification chamber ( | 2012-03-29 |
20120074602 | Lens Blocking Method and Related Device - A method for blocking an optical lens ( | 2012-03-29 |
20120074603 | Delivery of Herbicidal Actives From Highly Charged Microcapsules - This invention relates to a method for forming hollow silica-based particles suitable for containing one or more herbicidal active ingredients. In the method for forming the herbicidal composition, an emulsion is prepared wherein the emulsion includes a continuous phase that is polar or non-polar, and a dispersed phase comprising droplets including (i) a polar herbicidal active ingredient when the continuous phase is non-polar or (ii) a non-polar herbicidal active ingredient when the continuous phase is polar. A silica precursor is added to the emulsion such that the silica precursor can be emulsion templated on the droplets to form hollow silica-based particles that encapsulate the herbicidal active ingredient, | 2012-03-29 |
20120074604 | Formliner Bridge - A form liner system comprises a first form liner, a second form liner and a bridge member. Each form liner comprises a plurality of raised portions defining a plurality of cells and at least one partial cell. The form liners are arranged such that the partial cells form a collective cell. The bridge member can be oriented in said collective cell, wherein a first portion of the bridge member is oriented in the first liner partial cell and a second portion of the bridge member is oriented in the second liner partial cell. | 2012-03-29 |
20120074605 | FINE PROCESSING METHOD, FINE PROCESSING APPARATUS, AND RECORDING MEDIUM WITH FINE PROCESSING PROGRAM RECORDED THEREON - According to one embodiment, a fine processing method includes determining a resist amount required for each first region of a pattern formation surface and a total amount of resist. The method include dividing the total amount of resist by a volume of one resist drop to determine the resist drops total number. The method include determining a provisional position for the resist drop of the total number. The method include assigning the each first region to nearest one resist drop, and partitioning again the pattern formation surface into second regions assigned to the each resist drop. The method include determining a divided value by dividing the volume of the one resist drop by the required total amount of resist determined. The method include finalizing a final position of the each resist drop, if a distribution of the divided value in the pattern formation surface falls within a target range. | 2012-03-29 |
20120074606 | INJECTION MOULDING METHOD FOR OPTIONAL MANUFACTURING OF MOULDED PARTS WITH OR WITHOUT A BREAKTHROUGH - An injection-moulding method for selectively manufacturing moulded parts with and without a breakthrough is disclosed. A moulded part with a breakthrough is manufactured by positioning a mould core in a mould cavity, whereas a moulded part without breakthrough is manufactured by removing the mould core at least partly from the mould cavity. The mould cavity delimited by a nozzle-side mould platen and an ejector-side mould platen. The mould core is movable relative to at least one of the mould platens, in particularly the nozzle-side mould platen, in an advance direction, where the mould core is closer to the nozzle-side mould platen and an opposite withdrawal direction. | 2012-03-29 |
20120074607 | IN AN INJECTION UNIT HAVING A FILTER, A METHOD OF CONTROLLING MELT PRESSURE IN ACCORDANCE WITH A TARGET PRESSURE RANGE - There is provided a method ( | 2012-03-29 |
20120074608 | CONTROL MODULE MANUFACTURING METHOD - In one embodiment, a control module manufacturing method includes disposing a board, on which electronic components are mounted, in a case includes a top opening, injecting a filler into the case, pressing the filler from the surface side thereof by means of a jig, which comprises an upwardly convex hollow portion corresponding to taller ones of the electronic components with respect to the board and covers the opening and curing the filler. | 2012-03-29 |
20120074609 | Fabric for Non-Woven Web Forming Process and Method of Using Same - A method of manufacturing a non-woven web includes the step of collecting stretched filaments that form the non-woven web on a fabric in an apparatus for the formation of non-woven webs. The fabric comprises machine direction (MD) yarns and cross-machine direction (CMD) yarns, wherein the MD and CMD yarns are interwoven in a repeating pattern in which at least some of the CMD yarns are interwoven with the MD yarns in pairs that follow the same weaving sequence. Such a fabric can provide potential advantages such as reduced air leakage, reduced air disturbances, and improved web hold-down effect. | 2012-03-29 |
20120074610 | ANODE MATERIAL OF LITHIUM-ION SECONDARY BATTERY AND PREPARATION METHOD THEREOF - In an anode material of a lithium-ion secondary battery and its preparation method, a natural graphite, an artificial graphite or both are mixed to form a graphite powder, and the graphite powder is mixed with a resin of a high hard carbon content and processed by a mist spray drying process, and finally added or coated with a special resin material after a carburizing heat treatment takes place to prepare a graphite composite of the anode material of the lithium-ion secondary battery and achieve a smaller surface area of an anode graphite composite of the battery and extended cycle life and capacity. | 2012-03-29 |
20120074611 | Process of Forming Nano-Composites and Nano-Porous Non-Wovens - A process for forming a nano-composite including mixing a first and second thermoplastic polymer in a molten state forming a molten polymer blend. The second polymer is soluble in a first solvent and the first polymer is insoluble in the first solvent. The first polymer forms discontinuous regions in the second polymer. Next, the polymer blend is subjected to extensional flow, shear stress, and heat forming nanofibers where less than about 30% by volume of the nanofibers are bonded to other nanofibers. | 2012-03-29 |
20120074612 | Process of Forming a Nanofiber Non-Woven Containing Particles - A process for forming a nanofiber non-woven includes mixing a first and second thermoplastic polymer and a plurality of particles, then subjecting the mixture to elongational forces when the first and second polymers are in a softened condition forming nanofibers of the first polymer. Next, the mixture is brought to a condition where the temperature is below the softening temperature of the first polymer forming a first intermediate. The first intermediate is consolidated forming the second intermediate where at least 70% of the nanofibers are fused to other nanofibers. Next, at least a portion of the second polymer is removed and at least 50% of the particles are positioned adjacent a surface of the nanofibers. | 2012-03-29 |
20120074613 | INTRINSIC INJECTION MOLDING GATE AND METHOD OF OVERMOLDING CORDAGE - The present invention relates generally to intrinsic injection molding gates and a method of overmolding cordage. More specifically, this disclosure relates to a mold configuration wherein the viscous material is first injected into a distributor collar and then into a plurality of intrinsic injection molding gates with are formed between the injection mold and the cordage to be overmolded. | 2012-03-29 |
20120074614 | SYSTEMS, METHODS AND APPARATUSES FOR MANUFACTURING DOSAGE FORMS - Systems, methods and apparatuses for manufacturing dosage forms, and to dosage forms made using such systems, methods and apparatuses are provided. Novel compression, thermal cycle molding, and thermal setting molding modules are disclosed. One or more of such modules may be linked, preferably via novel transfer device, into an overall system for making dosage forms. | 2012-03-29 |
20120074615 | IMPRINT DEVICE AND MICROSTRUCTURE TRANSFER METHOD - There is provided an imprint device for transferring a fine pattern to a material to form a patterned material. The device comprises a stamper having the fine pattern thereon, and a pressure distribution mechanism. The stamper is pressed against the material, and the pressure distribution mechanism provides a nonuniform pressure distribution in a patterned region of the patterned material, while the stamper is in contact with the material. There are provided an imprint device and a microstructure transfer method, by which it is possible to sufficiently spread a resin or other material for forming a pattern layer between a stamper and a patterned material with a lower pressure so as not to damage the stamper or the patterned material, and to form a pattern formation layer having the uniform thickness on the patterned material. | 2012-03-29 |
20120074616 | MOLDING APPARATUS - Described herein is a mold. The mold includes a first mold half and a second mold half. A molding cavity is definable between the first mold half and the second mold half within which a molded article is moldable. The mold also includes a core configured to form a seal on the molded article. The first mold half and the second mold half are configured to remain in a mold closed configuration with molding and stripping of the molded article. | 2012-03-29 |
20120074617 | FLAME-RETARDANT IMPACT-MODIFIED BATTERY BOXES BASED ON POLYCARBONATE I - Battery box comprising compositions containing A) 70.0 to 90.0 parts by weight of linear and/or branched aromatic polycarbonate and/or aromatic polyester carbonate, B) 6.0 to 15.0 parts by weight of at least one graft polymer, C) 2.0 to 15.0 parts by weight of one or more phosphorus compounds, D) 0 to 3.0 parts by weight of antidripping agents, E) 0 to 3.0 parts by weight of thermoplastic vinyl (co)polymer (E.1) and/or polyalkylene terephthalate (E.2), and F) 0 to 20.0 parts by weight of further additives, wherein the compositions are optionally free from rubber-free polyalkyl(alkyl)acrylate. | 2012-03-29 |
20120074618 | PROCESS FOR MOLDING A PLASTIC PART WITH A METAL INSERT HELD IN PLACE BY MAGNETIZATION, MOLDING DEVICE AND USE OF A METHOD FOR FASTENING SAID INSERT - A process for molding a beading in particular on the periphery of a window or for molding a plastic window, in which a constituent plastic of said beading or of said plastic window respectively is introduced into a molding cavity in which at least one ferromagnetic insert, such as a trim, has been placed beforehand, wherein said insert is held in position in said molding cavity during the introduction of said plastic by at least one magnet which can move between two positions, an active position in which it exerts an attractive force on said insert across the internal surface of the molding cavity and an inactive position I in which it exerts no attractive force on said insert. | 2012-03-29 |
20120074619 | BLOW NEEDLE FOR EXTRUSION BLOW MOLDING PET - The present invention relates to a hollow blow needle for introducing a pressurized fluid into an extruded parison enclosed by two mold halves, the needle comprising: a body portion having an inner first diameter; a neck portion having an inner second diameter, wherein the inner second diameter is less than the inner first diameter; and a tip portion comprising a first angled portion, a second angled portion that is a different angle relative to the first angled portion, and an orifice. | 2012-03-29 |
20120074620 | FURNACE TAP HOLE FLOW CONTROL AND TAPPER SYSTEM AND METHOD OF USING THE SAME - A molten metal flow controller ( | 2012-03-29 |
20120074621 | Press quenching machine for steel plates - A press quenching machine for steel plates includes a press bed structure, a hydraulic cylinder, a drive roller for advancing and stopping the steel plates, a fixed upper pressure head part, a bottom pressure head part movable up and down within the press bed structure, a plurality of upper pressed ribs provided on the upper pressure head part, and a plurality of bottom pressed ribs provided on the bottom pressure head part. The upper pressed ribs are crosswise arranged with the bottom pressed ribs, the upper and bottom pressed ribs have a density distribution according to a position of a special-shape plate for ensuring the flatness of the steel plates after quenching. In the press quenching machine, the transfer time and heat dissipation of the steel plates can be reduced, and no blind areas or soft spots exist. Therefore, the press quenching machine has a high yield and production efficiency. | 2012-03-29 |
20120074622 | Movable device for injecting oxygen and other materials into electric arc furnace - A movable device for injecting oxygen and other technical materials into an electric arc furnace comprising a housing ( | 2012-03-29 |
20120074623 | INJECTING GAS INTO A VESSEL - An apparatus for injecting gas into a vessel is disclosed. The apparatus comprises a gas flow duct from which to discharge gas from the duct, an elongate central structure extending within the gas flow duct, and a plurality of flow directing vanes disposed about the central structure adjacent the forward end of the duct to impart swirl to a gas flow through the forward end of the duct. The apparatus also comprises cooling water flow passages in the vanes that have inlets at the forward ends of the vanes and outlets at the rear ends of the vanes. | 2012-03-29 |
20120074624 | FURNACE FURNITURE - Furnace furniture ( | 2012-03-29 |
20120074625 | AIR SPRING TYPE SUSPENSION - An air spring type suspension includes: a cylinder including an air chamber; an outer tube surrounding the cylinder and constituting a buffer chamber outside the cylinder, the buffer chamber connected to the air chamber; a damper capable of being inputted into and outputted from the air chamber; a piston rod in the air chamber and inserted into the damper; and an accumulator module constituting a control chamber connected to the buffer chamber, wherein a single closed space is constituted by the air chamber, the buffer chamber and the control chamber, and wherein a pressure change of the air chamber is induced by a pressure change of the control chamber. | 2012-03-29 |
20120074626 | BODY AMPLITUDE SENSITIVE AIR SPRING - Provided is an air spring for sensing a behavior of a vehicle and varying a spring constant by changing a chamber volume of the air spring, improving the ride comfort and the steering stability according to situations. | 2012-03-29 |
20120074627 | ACTUATOR ARRANGEMENT FOR ACTIVE VIBRATION ISOLATION COMPRISING AN INERTIAL REFERENCE MASS - Actuator arrangement with an actuator ( | 2012-03-29 |