13th week of 2013 patent applcation highlights part 65 |
Patent application number | Title | Published |
20130080649 | SECURE RESOURCE NAME RESOLUTION - Techniques for securing name resolution technologies and for ensuring that name resolution technologies can function in modern networks that have a plurality of overlay networks accessible via a single network interface. In accordance with some of the principles described herein, a set of resolution parameters may be implemented by a user, such as an end user or an administrator, to be used during a name resolution process for securing the process and/or for conducting the process in an overlay network. In some implementations, the set of resolution parameters may be maintained as a table of rules, and used to govern name resolution processes. For example, resolution parameters may be created that govern a DNSSEC session, or that govern how to communicate with networks implemented with Microsoft's Direct Access overlay technologies, or that govern communications using any other networking technology. | 2013-03-28 |
20130080650 | SYSTEMS AND METHOD FOR REDUCED POWER WIRELESS COMMUNICATION - In a particular embodiment, a method includes intercepting, at a first device, a message to be processed by a first protocol layer of the first device. The method also includes processing the message to a second protocol layer of the first device. The method further includes generating, at the first device, a packet based on an operand associated with the message. The method also includes transmitting the generated packet via a media access control (MAC) layer from the first device to a second device to enable the second device to host a protocol stack corresponding to the first protocol layer. | 2013-03-28 |
20130080651 | MESSAGE ACCELERATION - A data processing system comprising: a host computing device supporting an operating system and a network protocol stack, the network protocol stack being operable to support one or more transport streams by performing transport stream protocol processing of data packets received over the streams; a network interface device arranged to couple the host computing device to a network and operable to receive data packets over a transport stream supported by the network protocol stack; and a message engine configured to perform upper layer protocol processing; wherein the network interface device is configured to, on receiving a data packet over one of a predetermined set of transport streams, pass the payload data of the data packet to the message engine and the message engine is configured to, in response to receiving the payload data, identify and process any upper layer messages in the payload data in accordance with the upper layer protocol. | 2013-03-28 |
20130080652 | DYNAMIC RUNTIME CHOOSING OF PROCESSING COMMUNICATION METHODS - Techniques are described for assigning and changing communication protocols for a pair of processing elements. The communication protocol determines how the pair of processing elements transmits data in a stream application. The pair may be assigned a communication protocol (e.g., TCP/IP or a protocol that uses a relational database, shared file system, or shared memory) before the operator graph begins to stream data. This assignment may be based on a priority of the processing elements and/or a priority of the communication protocols. After the operator graph begins to stream data, the pair of processing elements may switch to a different communication protocol. The decision to switch the communication protocol may be based on whether the pair of processing elements or assigned communication protocol is meeting established performance standards for the stream application. | 2013-03-28 |
20130080653 | USING PREDICTIVE DETERMINISM WITHIN A STREAMING ENVIRONMENT - Techniques are described for transmitting predicted output data on a processing element in a stream computing application instead of processing currently received input data. The stream computing application monitors the output of a processing element and determines whether its output is predictable, for example, if the previously transmitted output values are within a predefined range or if one or more input values correlate with the same one or more output values. The application may then generate a predicted output value to transmit from the processing element instead of transmitting a processed output value based on current input values. The predicted output value may be, for example, an average of the previously transmitted output values or a previously transmitted output value that was transmitted in response to a previously received input value that is similar to a currently received input value. | 2013-03-28 |
20130080654 | OVERLOADING PROCESSING UNITS IN A DISTRIBUTED ENVIRONMENT - Techniques are disclosed for overloading, at one or more nodes, an output of data streams containing data tuples. A first plurality of tuples is received via a first data stream and a second plurality of tuples is received via a second data stream. A first value associated with the first data stream and a second value associated with the second data stream are established based on a specified metric. A third plurality of tuples is output based on the first value and the second value, wherein the third plurality of tuples is a subset of the first plurality of tuples and the second plurality of tuples. | 2013-03-28 |
20130080655 | ESTIMATING LOAD SHED DATA IN STREAMING DATABASE APPLICATIONS - Techniques are disclosed for processing data streams containing data tuples, where some of the data tuples are load shed. Load shedding refers to a process of selectively discarding some data tuples, e.g., when the amount of received data becomes too overwhelming to manage. When operations are invoked that depend on the values (or count) of the load shed tuples, the value (or counts) of the load shed tuples may be used to perform such operations. For example, and aggregation operation may return the sum, average, mean and/or variance associated with a plurality of tuples processed by a node of the stream application. | 2013-03-28 |
20130080656 | SYSTEM AND METHOD FOR PROVIDING FLEXIBILITY IN CONFIGURING HTTP LOAD BALANCING IN A TRAFFIC DIRECTOR ENVIRONMENT - Described herein are systems and methods for use with a load balancer or traffic director, and administration thereof, wherein the traffic director is provided as a software-based load balancer that can be used to deliver a fast, reliable, scalable, and secure platform for load-balancing Internet and other traffic to back-end origin servers, such as web servers, application servers, or other resource servers. In accordance with an embodiment, the system comprises a high-speed network infrastructure which provides communication protocols or sockets for use by the origin servers in receiving requests; one or more protocol terminator/emulators for use with the communication protocols or sockets; and an inbound socket configuration and an outbound socket configuration which together indicate which terminator/emulator the traffic director should use in communicating requests to particular ones of the origin servers. | 2013-03-28 |
20130080657 | DATA TRANSMISSION DEVICE AND DATA TRANSMISSION METHOD - A data transmission device ( | 2013-03-28 |
20130080658 | DIGITAL ASSET HOSTING AND DISTRIBUTION - A first collection of content that includes digital assets is maintained on a host computer. Based on a determination that a portable media device becomes connected to a client computer that is separate from the host computer and that interacts with the host computer, initiation of a synchronization of the first collection of content resident on the host computer with a second collection of content on the portable media device is automatically triggered. The synchronization of the first collection with the second collection includes a transfer of at least one of the digital assets from the host computer to the client computer to the portable media device and is triggered and conditioned upon the determination that the portable media device has become connected to the client computer. | 2013-03-28 |
20130080659 | DEVICE AND METHOD FOR CONTROLLING USB TERMINAL - Provided are a device and method for controlling a Universal Serial Bus (USB) terminal. A control module senses that a terminal is connected through USB, provides a terminal control module for controlling the terminal through USB, and then provides a control command to the terminal control module through USB. The terminal control module executes the control command, and then captures and provides a display image of the execution result to the control module. Then, the control device displays the display image. Accordingly, it is possible to readily and rapidly control a mobile terminal by simply connecting the mobile terminal to the control device through USB. | 2013-03-28 |
20130080660 | COMMAND QUEUE FOR PERIPHERAL COMPONENT - In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands. | 2013-03-28 |
20130080661 | Configuring Buffers with Timing Information - Configuring a buffer with timing information. Initially, a buffer for transferring data from a first device to a second device may be configured, e.g., in response to user input. For example, configuring the buffer may include specifying a size of the buffer, specifying timing for delivery of data of the buffer, and/or specifying transfer of the data from a first device to a second device. In response to the configuration of the buffer, code may be automatically generated which implements the transfer of the data from the first device to the second device according to the specified timing for delivery of the data of the buffer. Accordingly, the automatically generated code may be executable to transfer the data according to the specified timing from the first device to the second device. | 2013-03-28 |
20130080662 | In-Band Peripheral Authentication - This document describes techniques ( | 2013-03-28 |
20130080663 | MULTIMEDIA INTERFACE WITH CONTENT PROTECTION IN A WIRELESS COMMUNICATION DEVICE - In general, this disclosure relates to techniques for management of a multimedia connection between a wireless communication device (WCD) and one or more output devices. The connection may be a multimedia interface connection with content protection, e.g., High Definition Multimedia Interface (HDMI). In some cases, the multimedia interface connection with content protection may be inactive because the output device is no longer connected or the multimedia application is stopped or paused. The techniques include detecting a use mode of the multimedia interface connection with content protection between the WCD and one or more output devices. When the use mode of the multimedia interface connection with content protection is inactive, the WCD may reduce at least one of content processing or content protection processing. In this way, the techniques may reduce battery power consumption from multimedia processing by the WCD. | 2013-03-28 |
20130080664 | SYSTEMS AND METHODS FOR CREATING BIDIRECTIONAL COMMUNICATION CHANNELS USING BLOCK DEVICES - A system includes an initiator device including an initiator interface. A target device includes a target interface that communicates with the initiator interface via a protocol. The protocol supports commands being sent from the initiator device to the target device. The protocol does not support commands being sent from the target device to the initiator device. The target interface is configured to send a command to the initiator device via the protocol. The initiator interface is configured to execute the command. | 2013-03-28 |
20130080665 | SYSTEM AND METHOD FOR TRANSMITTING USB DATA OVER A DISPLAYPORT TRANSMISSION LINK - A data transmission system is provided. The data transmission system includes a source device having a source device controller and a register and a sink device having a sink device controller. The data transmission system also includes a transmission link coupling the source device and the sink device. The transmission link includes a unidirectional main line having a plurality of main link channels, a bidirectional auxiliary line configured to transmit data between the source device and the sink device at a first data rate, and a unidirectional interrupt line. The transmission link is configured to transmit data from the source device to the sink device over one of the main link lines at a second data rate and to transmit data from the sink device to the source device over the auxiliary line at the second data rate. The transmission link may comply with the DisplayPort standard, and the data may be transmitted in accordance with the USB standard. | 2013-03-28 |
20130080666 | HARD DISK DRIVE INTEGRATED CIRCUIT WITH INTEGRATED GIGABIT ETHERNET INTERFACE MODULE - An integrated circuit of a hard disk drive includes an Ethernet network interface module configured to transmit and receive data packets via an Ethernet connection. The data packets respectively include packet headers and at least one of small computer system interface (SCSI) commands and SCSI data requests. A processor is configured to process the data packets transmitted and received by the Ethernet network interface module. A hard disk control module is configured to control, based on the at least one of the SCSI commands and the SCSI data requests, writing of data to a hard disk and reading of the data from the hard disk. Each of the hard disk control module, the processor, and the network interface module is located in the integrated circuit. | 2013-03-28 |
20130080667 | Handling Atomic Operations For A Non-Coherent Device - In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed. | 2013-03-28 |
20130080668 | INTEGRATED CIRCUT WITH SERIAL INTERFACE, RECEIVING TRANSMITTAL INFORMATION CONFORMING TO TWO COMMUNICATION PROTOCOLS - A processing system including a control integrated circuit (IC), a serial transmission interface, a transformation unit and an application unit is disclosed. The control IC provides transmittal information, which conforms to a first communication protocol or a second communication protocol. The serial transmission interface is coupled to the control IC and receives the transmittal information. The transformation unit is coupled to the serial transmission interface. The transformation unit transforms the transmittal information received by the serial transmission interface to generate processed information when the transmittal information conforms to the first communication protocol. The transformation unit transforms the transmittal information received by the serial transmission interface to generate the processed information when the transmittal information conforms to the second communication protocol. The application unit is coupled to the transformation unit and executes a corresponding operation according to the processed information. | 2013-03-28 |
20130080669 | Dynamically Determining A Primary Or Slave Assignment Based On An Order Of Cable Connection Between Two Devices - Methods, apparatuses, and computer program products for dynamically determining a primary or slave assignment based on an order of cable connection between two devices are provided. Embodiments include detecting, by a first device, insertion of one end of a cable into a port of the first device; determining, by the first device, whether a power signal is received from the cable at the port of the first device; if the power signal is received, performing, by the first device, a data transfer operation over the cable as a slave device to a second device that is coupled to the other end of the cable; and if the power signal is not received, performing, by the first device, a data transfer operation over the cable as a primary device to the second device that is coupled to the other end of the cable. | 2013-03-28 |
20130080670 | MODULAR SYSTEM HAVING CROSS PLATFORM MASTER DEVICE - A modular system of devices, in which a (master) device can be combined with one or more of the other (slave) devices in the system to form a functional electronic device (e.g., handheld cellular phone, tablet computing device), having different functionalities and features in different form factors across various platforms. The master device provides control and/or stored data to operate the slave devices, to reduce redundancy between devices of various form factors and/or platforms, in a manner that provides additional or different functions and features in an optimized and/or enhanced manner as the form factor and/or platform changes from one to another. The master device is not functional independent without attachment to a slave device. The master device requires at least a peripheral component (e.g., a display module) provided by the slave device to become an overall functional unit. | 2013-03-28 |
20130080671 | BUS CONTROLLER AND CONTROL UNIT THAT OUTPUTS INSTRUCTION TO THE BUS CONTROLLER - A bus controller is arranged on a plurality of network communication buses that connect together a plurality of bus masters, each sending out a packet, and at least one node, to which the packet is sent from each said bus master, in order to control the transmission route of a packet that is flowing through the plurality of communication buses. The bus controller includes: a route diagram manager configured to manage a plurality of transmission routes and their respective transmission statuses; a parameter generator configured to generate either a parameter that conforms to a predetermined probability distribution or a parameter that follows a predefined rule; a processor configured to select one of the plurality of transmission routes based on the respective transmission statuses of the transmission routes and the parameter; and a relay configured to perform relay processing on the packet that is flowing through the communication bus. | 2013-03-28 |
20130080672 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ACCESS CONTROL - An access control system for controlling access to a resources group including multiple computer accessible resources, the system including: a lock, configured to selectively deny a request of a process to access the resource when the resource is locked; and a global lock, configured to grant to the process exclusive access to add a pending-task entry into a resource-associated data structure associated with the resource; wherein the global lock has to be acquired by any process whose request to access any resource of the resources group for performing of any task was denied, in order for access thereto for performing the respective task to be granted; wherein the lock is further configured to selectively grant, following the adding of the pending task-entry into the resource-associated data structure, exclusive access to the resource for performing a task associated with the pending task entry upon a releasing of the resource associated lock. | 2013-03-28 |
20130080673 | VALIDATING MESSAGE-SIGNALED INTERRUPTS - The disclosed embodiments provide a system that validates message-signaled interrupts. During operation, the system receives a message-signaled interrupt from a requesting device. This message-signaled interrupt includes an interrupt vector that identifies an interrupt, and is accompanied by an identification tag that identifies the source of the interrupt. The system uses the interrupt vector to access a stored tag from a tracking mechanism that associates source devices with their assigned interrupt vector(s). The system then compares the identification tag and the stored tag to validate the message-signaled interrupt. | 2013-03-28 |
20130080674 | Source Core Interrupt Steering - An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein. | 2013-03-28 |
20130080675 | Dual PCI-X/PCI-E Card - A dual bus interface PCB includes a main chipset component, a first type bus interface connector, and a second type bus interface connector. The PCB can be configured at fabrication time to enable a variety of configurations for operation. Optionally, the PCB can also be provided at least one memory chip and a NIC (Network Interface Card) chip. By virtue of having a dual interface, the PCB can be used with either the first type or the second type bus. Furthermore, the dual interface PCB eliminates the need by chipset manufacturers to carry multiple PCB variations of the same product in order to support various bus interfaces. In one embodiment, the PCB is a dual PCI-X/PCI-E interface PCB. | 2013-03-28 |
20130080676 | Wireless Data Input System - A data input system includes a wireless keyboard and docking station, which can be connected to a computer system. When the keyboard and docking station are mechanically connected, the docking station is configured automatically to generate a new pairing code or key that is different to a previously-generated one. This new code/key is then transmitted back to the keyboard over a wireless control link and the keyboard and docking station then set up a paired data channel over which data from the keyboard is transmitted wirelessly to the docking station, and so the computer system. When a new mechanical connection is made, e.g. using the same or a different keyboard, the process repeats so that a new pairing code or key is generated, thus avoiding interference with other keyboard(s) that were previously paired with the same docking station. | 2013-03-28 |
20130080677 | Virtual General Purpose Input/Output for a Microcontroller - A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set. | 2013-03-28 |
20130080678 | CABLE REDUNDANCY AND FAILOVER FOR MULTI-LANE PCI EXPRESS IO INTERCONNECTIONS - Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device. | 2013-03-28 |
20130080679 | SYSTEM AND METHOD FOR OPTIMIZING THERMAL MANAGEMENT FOR A STORAGE CONTROLLER CACHE - The present invention is directed to a method for optimizing thermal management for a storage controller cache of a data storage system. The method allows for pending writes of a storage controller to be selectively provided to solid-state device (SSD) module(s) of the controller in a manner which allows operating temperatures of the SSD module(s) to be maintained within a thermal envelope. | 2013-03-28 |
20130080680 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER, AND TEMPERATURE MANAGEMENT METHOD - A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and a memory controller used for controlling the rewritable non-volatile memory module are provided. The temperature management method includes detecting and determining whether the hot-spot temperature of the memory storage device is higher than a predetermined temperature; and when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the memory storage device. Accordingly, the problem of heat buildup of the (rewritable non-volatile) memory storage device can be mitigated, as well as the problems of data loss and device aging of the (rewritable non-volatile) memory storage device. | 2013-03-28 |
20130080681 | EFFICIENT TWO WRITE WOM CODES, CODING METHODS AND DEVICES - The invention provides a family of 2-write WOM-codes, preferred embodiments of which provide improved WOM-rates. Embodiments of the invention provide constructs for linear codes C having a 2-write WOM-code. Embodiments of the invention provide 2-write WOM-codes that improve the best known WOM-rates known to the present inventors at the time of filing with two writes. Preferred WOM-codes are proved to be capacity achieving when the parity check matrix of the linear code C is chosen uniformly at random. Preferred embodiments of the invention provide an electronic device utilizing an efficient coding scheme of WOM-codes with two write capability. The coding) method is based on linear binary codes and allows the electronic device to write information to the memory twice before erasing it This method can be applied for any kind of memory systems, and in particular for flash memories. The method is shown to outperform all well-known codes. | 2013-03-28 |
20130080682 | RECLAIMING SPACE OCCUPIED BY AN EXPIRED VARIABLE RECORD IN A NON-VOLATILE RECORD STORAGE - In a method for reclaiming space occupied by an expired variable record in a non-volatile record storage, a reclaim state data that includes a state of a reclaim operation is maintained. In addition, the state of the reclaim operation is marked to indicate a progress of the reclaim operation at a plurality of stages of the reclaim operation. The reclaim operation is implemented by sliding, one section at a time, the data in a first direction along the plurality of sections and by sliding, one section at a time, the variable records, excluding the expired variable record, in a second direction along the plurality of sections, to thereby remove the expired variable record. | 2013-03-28 |
20130080683 | MEMORY SYSTEM PROVIDED WITH NAND FLASH MEMORY AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory system includes first, and second districts, and control section. Each of the first and second districts includes a memory cell array. The control section receives a write command to simultaneously write first data to the first, and second districts, and addresses, and simultaneously writes the first data to the first and second districts. | 2013-03-28 |
20130080684 | ADAPTER HAVING HIGH SPEED STORAGE DEVICE - An adapter, providing a selective connection between a host and mass storage device, includes a high-speed storage device, a host interface and a device interface. The high-speed storage device is provided on a front surface of a printed circuit board (PCB), and includes multiple nonvolatile memory devices and a controller configured to control operations of the nonvolatile memory devices. The host interface is on a back surface of the PCB, and is configured to interface between the high-speed storage device and the host. The device interface is on the back surface of the PCB, and is configured to interface between the high-speed storage device and the mass storage device. | 2013-03-28 |
20130080685 | STORAGE DEVICES AND METHODS OF DRIVING STORAGE DEVICES - A storage device includes a data storage having first and second storage areas corresponding to different physical addresses. First data are stored in the first storage area. The storage device further includes a first memory that stores a reference count associated with the first data, and a controller that rearranges the first data from the first storage area to the second storage area in response to a change in the reference count of the first data. | 2013-03-28 |
20130080686 | DATA MANAGEMENT METHOD FOR NONVOLATILE MEMORY - A method of managing data in a system comprising a nonvolatile memory comprises storing a root object of application data, and at least one sub object referenced by the root object in the nonvolatile memory, and mapping virtual addresses of the root object and sub object to physical addresses of the nonvolatile memory respectively, in a page unit. The root object stored in the nonvolatile memory comprises a pointer that references the sub object stored in the nonvolatile memory. | 2013-03-28 |
20130080687 | SOLID STATE DISK EMPLOYING FLASH AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A central processing unit (CPU) subsystem is disclosed to include a MRAM used among other things for storing tables used for flash block management. In one embodiment all flash management tables are in MRAM and in an alternate embodiment tables are maintained in DRAM and are near periodically saved in flash and the parts of the tables that are updated since last save are additionally maintained in MRAM. | 2013-03-28 |
20130080688 | DATA STORAGE DEVICE AND METHOD OF WRITING DATA IN THE SAME - A method is provided for writing data in a storage device, including a nonvolatile memory. The method includes receiving a pre-write command including a logical address and size information of write data, performing a pre-operation for optimization of a write operation based on the pre-write command, and writing the write data in the nonvolatile memory after the pre-operation is completed. | 2013-03-28 |
20130080689 | DATA STORAGE DEVICE AND RELATED DATA MANAGEMENT METHOD - A storage device performs data management for a nonvolatile memory device by detecting an allocation order of a first memory block, assigning page data of the first memory block to a second memory block or a third memory block having different erase counts based on the allocation order. | 2013-03-28 |
20130080690 | METHOD TO EMULATE EEPROM USING FLASH MEMORY - Methods of using FLASH memory to emulate EEROM are disclosed. The present method uses two pages of FLASH memory, where each page is one or more separately erasable blocks. One page is referred to as the current page, while the other is the next page. Tokens, which are data structures containing a data element, are written in successive locations in the current page. When the current page is nearly completely filled, the write operation starts writing the new tokens to the next page. In some embodiments, to equalize the execution time of the write routine, the write routine also copies one token from the current page to the next page after a new token is written to the next page. Once all tokens have been copied to the next page, the current page can be erased. At this point, the next page becomes the current page. | 2013-03-28 |
20130080691 | FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for converting a measured physical level of a cell into a logical value, in an array of memory cells storing physical levels which diminish over time, the method may include: determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in the array; and reading the individual cell including reading a physical level in said cell and converting said physical level into a logical value using at least some of said thresholds, wherein said determining extent of deterioration comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and determining extent of deterioration by computing deterioration of said predefined physical levels. | 2013-03-28 |
20130080692 | CONTENT-AWARE DIGITAL MEDIA STORAGE DEVICE AND METHODS OF USING THE SAME - A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module and configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated. | 2013-03-28 |
20130080693 | HYBRID MEMORY DEVICE, COMPUTER SYSTEM INCLUDING THE SAME, AND METHOD OF READING AND WRITING DATA IN THE HYBRID MEMORY DEVICE - A hybrid memory device includes a DRAM and a non-volatile memory. When a program is executed for the first time by a central processing unit (CPU), and data is copied to the DRAM from an external memory device, the data is also copied to the non-volatile memory. The non-volatile memory is configured to directly output data stored therein to an exterior without passing through the DRAM. | 2013-03-28 |
20130080694 | Methods And Apparatus For Refreshing Digital Memory Circuits - Dynamic memory systems require each memory cell to be continually refreshed. During a memory refresh operation, the refreshed memory cells cannot be accessed by a memory read or write operation. In multi-bank dynamic memory systems, concurrent refresh systems allow memory refresh circuitry to refresh memory banks that are not currently involved in memory access operations. To efficiently refresh memory banks and advanced round robin refresh system refreshes memory banks in a nominal round robin manner but skips memory banks blocked by memory access operations. Skipped memory banks are prioritized and then refreshed when they are no longer blocked. | 2013-03-28 |
20130080695 | RESTORE IN CASCADED COPY ENVIRONMENT - In one aspect of the present description, handling multiple backup processes comprises detecting that a defined storage volume is present in a first cascade of storage volumes; detecting that the defined storage volume is present in a second cascade of storage volumes; receiving a data write for a last storage volume in the first cascade of storage volumes; and performing a cleaning data write on the defined storage volume in the second cascade of storage volumes, wherein the cleaning data write corresponds to the received data write. Other aspects may be utilized, depending upon the particular application. | 2013-03-28 |
20130080696 | STORAGE CACHING/TIERING ACCELERATION THROUGH STAGGERED ASYMMETRIC CACHING - A multi-tiered system of data storage includes a plurality of data storage solutions. The data storage solutions are organized such that the each progressively faster, more expensive solution serves as a cache for the previous solution, and each solution includes a dedicated data block to store individual data sets, newly written in a plurality of write operations, for later migration to slower data storage solutions in a single write operation. | 2013-03-28 |
20130080697 | DRIVE MAPPING USING A PLURALITY OF CONNECTED ENCLOSURE MANAGEMENT CONTROLLERS - According to one aspect, a computing system having a plurality of enclosure management controllers (EMCs) is disclosed. In one embodiment, the EMCs are communicatively coupled to each other and each EMC is operatively connected to a corresponding plurality of drive slots and at least one of a plurality of drive slot status indicators. Each EMC is operative to receive enclosure management data, detect an operational status of the drive slots, and generate drive slot status data. One of the EMCs is configured to function at least partly as a master EMC to receive drive slot status data and, based on received enclosure management data and received drive slot status data, generate mapped data for each one of the EMCs for selectively activating at least one of the drive slot status indicators to indicate corresponding operational status. | 2013-03-28 |
20130080698 | GLOBAL DISTRIBUTED MEMORY RESHAPE OPERATIONS ON RANGE-PARTITIONED ARRAYS - Embodiments are directed to reshaping a partitioned data array. In an embodiment, a computer system identifies a block length parameter that describes the number of data blocks in the range-partitioned flattened representation of the array that appear consecutively in each locale. The computer system then identifies a stride parameter that describes the amount of separation between data blocks in the range-partitioned flattened representation of the array that appear consecutively in a plurality of locales. Based on the identified block length parameter and the stride parameter, the computer system determines which of the data blocks on the plurality of locales are to be sent to other locales to produce a local version of the reshaped array. The computer system then receives data blocks from the different locales in the distributed system and reconstructs the array based on the received blocks to create a local version of the reshaped array. | 2013-03-28 |
20130080699 | INFORMATION PROCESSING APPARATUS CONTROL METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND INFORMATION PROCESSING APPARATUS - A control method includes allocating a plurality of virtual disks to a virtual storage allocated to a physical storage, associating data with one of the plurality of virtual disks which has been instructed to store the data and storing the data in the physical storage, and selecting, by a processor, one of the plurality of virtual disks as a data movement target virtual disk from which data is to be moved in accordance with a network bandwidth of the physical storage corresponding to the virtual storage when free space in the virtual storage exceeds a threshold value. | 2013-03-28 |
20130080700 | RAID GROUP CONTROL DEVICE - A RAID group control device for performing access control over one or more RAID groups each having redundancy. The RAID group control device includes an acquiring unit to acquire access frequency information with respect to a RAID group among the one or more RAID groups; a scheduling unit to find a time period exhibiting a lower access frequency than access frequencies of anterior and posterior time periods in a specified time range on the basis of the access frequency information, and to determine start timing of a process of rewriting firmware of drives belonging to the RAID group on the basis of the found time period; and a firmware rewrite processing unit to start the process of rewriting the firmware of the drives at the determined start timing. | 2013-03-28 |
20130080701 | Decentralized Caching System - In a satellite communication system comprising at least a hub and a plurality of terminals, at least one terminal may include a cache for storing data objects. The cache may be based on a detachable memory device that may be inserted to or removed from the terminal at any given time, including after the terminal is deployed. Aspects are directed to preventing a prefetching of objects already stored in a cache of a remote terminal. In some embodiments, an efficient multicasting of content to terminals over an adaptive link may occur in a manner which may benefit terminals comprising a cache while not affecting or minimally affecting the performance of terminals that may not include a cache. | 2013-03-28 |
20130080702 | Micro-SD Device Loaded with a Smart Card - A Micro-Secure Digital (“SD”) device loaded with a smart card that can be issued in bulk and in card form is provided. The device includes: a SD interface electrically connected to a host terminal; at least one memory module; a SD controller connected to the SD interface to provide communication between a host terminal and the memory module; at least one smart card IC for data communication with the SD controller; and a smart card interface for issuing smart cards. Since the Micro-SD device is provided with a smart card function and a card form satisfying the ISO | 2013-03-28 |
20130080703 | METHOD FOR CALCULATING TIER RELOCATION COST AND STORAGE SYSTEM USING THE SAME - Conventionally, the fees for using services of a storage system was calculated based on the status of use or access performance of storage areas and not based on migration of data. The present invention provides a storage system in which multiple tiers composed of storage areas of various memory devices are assigned in page units and the assigned tiers are changed based on access frequency, wherein stored costs are calculated based on status of use of the storage areas constituting the tiers, and migration costs are calculated and charged based on the amount of migration of data among tiers and the I/O access counts after migration, according to which appropriate charging of cost for using the storage system is enabled. | 2013-03-28 |
20130080704 | MANAGEMENT OF POINT-IN-TIME COPY RELATIONSHIP FOR EXTENT SPACE EFFICIENT VOLUMES - A storage controller receives a request to establish a point-in-time copy operation by placing a space efficient source volume in a point-in-time copy relationship with a space efficient target volume, wherein subsequent to being established the point-in-time copy operation is configurable to consistently copy the space efficient source volume to the space efficient target volume at a point in time. A determination is made as to whether any track of an extent is staging into a cache from the space efficient target volume or destaging from the cache to the space efficient target volume. In response to a determination that at least one track of the extent is staging into the cache from the space efficient target volume or destaging from the cache to the space efficient target volume, release of the extent from the space efficient target volume is avoided. | 2013-03-28 |
20130080705 | MANAGING IN-LINE STORE THROUGHPUT REDUCTION - Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred. | 2013-03-28 |
20130080706 | PREVENTION OF CLASSLOADER MEMORY LEAKS IN MULTITIER ENTERPRISE APPLICATIONS - A classloader cache class definition is obtained by a processor. The classloader cache class definition includes code that creates a classloader object cache that is referenced by a strong internal reference by a classloader object in response to instantiation of the classloader cache class definition. A classloader object cache is instantiated using the obtained classloader cache class definition. The strong internal reference is created at instantiation of the classloader object cache. A public interface to the classloader object cache is provided. The public interface to the classloader object cache operates as a weak reference to the classloader object cache and provides external access to the classloader object cache. | 2013-03-28 |
20130080707 | PREVENTION OF CLASSLOADER MEMORY LEAKS IN MULTITIER ENTERPRISE APPLICATIONS - A classloader cache class definition is obtained by a processor. The classloader cache class definition includes code that creates a classloader object cache that is referenced by a strong internal reference by a classloader object in response to instantiation of the classloader cache class definition. A classloader object cache is instantiated using the obtained classloader cache class definition. The strong internal reference is created at instantiation of the classloader object cache. A public interface to the classloader object cache is provided. The public interface to the classloader object cache operates as a weak reference to the classloader object cache and provides external access to the classloader object cache. | 2013-03-28 |
20130080708 | DYNAMIC MODE TRANSITIONS FOR CACHE INSTRUCTIONS - A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter, selecting one of the plurality of requests as a selected request, the selected request having been provided by a first state machine, determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache, determining that the location in the cache is unavailable, and replacing the mode with a modified mode that only includes the second step. | 2013-03-28 |
20130080709 | System and Method for Performing Memory Operations In A Computing System - A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line are not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded. | 2013-03-28 |
20130080710 | HARDWARE METHOD FOR DETECTING TIMEOUT CONDITIONS IN A LARGE NUMBER OF DATA CONNECTIONS - Tracking several open data connections is difficult with a large number of connections. Checking for timeouts in software uses valuable processor resources. Employing a co-processor dedicated to checking timeouts uses valuable logic resources and consumes extra space. In one embodiment, a finite state machine implemented in hardware increases the speed connections can be checked for timeouts. The finite state machine stores a last accessed time stamp for each connection in a memory, and loops through the memory to compare each last accessed time stamp with a current time stamp of the system minus a global timeout value. In this manner, the finite state machine can efficiently find and react to timed out connections. | 2013-03-28 |
20130080711 | DYNAMIC POWER SCALING OF AN INTERMEDIATE SYMBOL BUFFER ASSOCIATED WITH COVARIANCE COMPUTATIONS - An intermediate symbol buffer (ISB) configuration and method is provided such that the ISB memory comprises 15 portions, one for each HSDPA spreading code. Symbols associated with a spreading code are written to the memory portion associated with the same spreading code. When a covariance calculation is performed to obtain a more accurate channel estimate, only the symbols associated with spreading codes determined to be needed for the covariance calculation are written to the ISB by a buffer block and red from the ISB by a correlation core. The symbols associated with spreading codes that are not necessary for a covariance calculation may be masked from being written or read from the ISB. In some embodiments each memory portion is an individual memory block. In other embodiments a plurality of memory blocks may contain a plurality of memory portions, one memory partition designated, at least temporarily, for each spreading code. | 2013-03-28 |
20130080712 | Non-Uniform Memory Access (NUMA) Enhancements for Shared Logical Partitions - In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition. | 2013-03-28 |
20130080713 | STORAGE CARTRIDGE AND CARTRIDGE DRIVE - A docking station for receiving a cartridge includes a housing having a receiving space configured to receive the cartridge. A movable carriage is disposed in the receiving space and configured to transport the cartridge into the receiving space. A movable mouth piece is configured to at least partially surround a multipoint connector of a non-tape storage medium of the cartridge through a horizontal access side opening of the cartridge so as to fix the multipoint connector. A fixing slider is configured to move the mouth piece through the horizontal access side opening so as to fix the multipoint connector within the receiving space. A connector slider is configured to move a connector within the docking station through a vertical access bottom opening of the cartridge against the electrical multipoint connector. | 2013-03-28 |
20130080714 | I/O MEMORY TRANSLATION UNIT WITH SUPPORT FOR LEGACY DEVICES - An apparatus, method, and medium are disclosed for managing memory access from I/O devices. The apparatus comprises a memory management unit configured to receive, from an I/O device, a request to perform a memory access operation to a system memory location. The memory management unit is configured to detect that the request omits a memory access parameter, determine a value for the omitted parameter, and cause the memory access to be performed using the determined value. | 2013-03-28 |
20130080715 | COMPUTING DEVICE SYSTEM AND INFORMATION MANAGING METHOD - The present invention provides a technique of suitably configuring a decision criterion for determining a transfer destination layer in rearrangement processing according to a task type and operation status and preventing performance degradation caused by arranging task data requiring a high response to a lower layer. At least one computing device (or management computing device or each host computing device) of a plurality of computing devices configures rearrangement reference information showing whether an access characteristic related to a task executed on a plurality of host computing devices is considered as a decision criterion for transfer destination determination in rearrangement processing of transferring data between actual storage areas of physical storage devices of different response performance. Also, a storage subsystem refers to the rearrangement reference information and, based on an access characteristic of the plurality of computing devices with respect to the actual storage areas assigned to the plurality of computing devices, executes rearrangement processing of transferring data stored in the actual storage areas to different actual storage areas in the physical storage devices of different response performance (see FIG. | 2013-03-28 |
20130080716 | CONTROLLER, MEMORY SYSTEM, AND INSPECTION METHOD - According to embodiments, a controller includes a read inspection unit, an inspection block setting unit, and a timing determining unit. The read inspection unit performs a read inspection for determining whether to perform rewriting of valid data to a block in which the valid data is stored among a plurality of blocks included in a nonvolatile memory. The inspection block setting unit generates an inspection block by writing inspection pattern data having a threshold as high as possible in at least one of the blocks included in the nonvolatile memory. The timing determining unit determines a timing of performing the read inspection by the read inspection unit based on the number of inverted bits that occurs in inspection pattern data written in the inspection block. | 2013-03-28 |
20130080717 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD - According to one embodiment, an apparatus includes a volatile memory, a nonvolatile semiconductor disk drive, a hibernation control module, a resume control module, and a release module. The drive includes SLC and MLC areas. The hibernation control module saves system context data in a first storage area in the SLC area in response to a hibernate request. The system context data includes contents of the volatile memory. The resume control module reads the system context data from the first storage area to restore the contents of the volatile memory, in response to a resume request. The release module releases the first storage area so as to allow the first storage area to be used to store other data, in response to completion of the read of the system context data. | 2013-03-28 |
20130080718 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory string including memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory string coupled between a bit line and a source line, a control circuit configured to control an erase operation of the memory cells, a first erase verify operation of the memory cells coupled to even word lines, and a second erase verify operation of the memory cells coupled to odd word lines, and an operation circuit, performing the erase operation of the memory cells, applying a first voltage to the odd and even word lines to form a channel in the vertical semiconductor layer between the odd and even word lines when the first and second erase verify operations are performed, respectively. | 2013-03-28 |
20130080719 | Shopping Cart - A shopping cart is disclosed. The shopping cart comprises a frame, a receptacle for holding items and a scanning apparatus for scanning items to be placed within the receptacle. The shopping cart further comprising weighing means for monitoring the weight of the receptacle. | 2013-03-28 |
20130080720 | INFORMATION PROCESSING APPARATUS AND METHOD - A processor stores first information when first data is stored in a storage. The first information includes pointers pointing to primary blocks of the storage. Each of the primary blocks stores a divided part of the first data. The processor stores second information when data update for updating the first data to second data is performed. The second information includes pointers pointing to secondary blocks of the storage. Each of the secondary blocks stores a divided part of the second data. The second information does not include a first pointer included in the first information. The first pointer points to a first block storing a to-be-deleted portion. The second information includes a second pointer. The second pointer points to a second block storing an added portion. The second information includes a third pointer included in the first information. The third pointer points to a third block storing an unchanged portion. | 2013-03-28 |
20130080721 | JUDGMENT APPARATUS, JUDGMENT METHOD, AND RECORDING MEDIUM OF JUDGMENT PROGRAM - A judgment apparatus includes a processor that executes a procedure, the procedure including obtaining a plurality of pieces of data having a certain relationship with a specific number or more of pieces of data included in a first data group, in the case that a piece of data included in a second data group different from the first data group does not have the certain relationship with the specific number or more of pieces of data included in the second data group, judging whether the piece of data has the certain relationship with the specific number or more of pieces of data included in the obtained plurality of pieces of data, and storing the piece of data in a storage device in the case that the piece of data is judged to have the given relationship with the specific number or more pieces of data. | 2013-03-28 |
20130080722 | STORAGE SYSTEM AND VOLUME PAIR SYNCHRONIZATION METHOD - To inhibit the occurrence of communication failures in the system in which a secondary storage control apparatus acquires journal data from a primary storage control apparatus and writes the data to a secondary volume. | 2013-03-28 |
20130080723 | MANAGEMENT SERVER AND DATA MIGRATION METHOD - A management server and a data migration method enabling a storage apparatus to be replaced while retaining data consistency and without halting access by a host apparatus are proposed. | 2013-03-28 |
20130080724 | STORAGE APPARATUS, CONTROL METHOD FOR STORAGE APPARATUS, AND STORAGE SYSTEM - A storage apparatus includes a memory that stores data groups, a rearranging unit that rearranges a transmission group order of the data groups based on each of storage positions in a storage device provided in a copy destination storage apparatus in which the each of data groups is to be stored, and a transmitting unit that transmits the data groups rearranged by the rearranging unit to the copy destination storage apparatus. | 2013-03-28 |
20130080725 | CONTROL APPARATUS, CONTROL METHOD, AND STORAGE APPARATUS - A control apparatus includes an identifying unit for detecting, upon receiving a request for creating a second bitmap during copying of data from a first storage area to a second storage area, a bit group in which bit values “1” and “0” are present among bit groups of a first bitmap that correspond to respective bits of the second bitmap and identifying a bit having the bit value “1” in the detected bit group, a copy processing unit for copying data managed by the identified bit to the second storage area and changing the bit value of the identified bit from “1” to “0”, and a setting unit for setting the bit value of the bit of the second bitmap that corresponds to the bit group of the first bitmap when the bit value of the identified bit is changed to “0”. | 2013-03-28 |
20130080726 | INPUT/OUTPUT MEMORY MANAGEMENT UNIT WITH PROTECTION MODE FOR PREVENTING MEMORY ACCESS BY I/O DEVICES - A memory management unit is configured to receive requests for memory access from a plurality of I/O devices. The memory management unit implements a protection mode wherein the unit prevents memory accesses by the plurality of I/O devices by mapping memory access requests (from the I/O devices) to the same set of memory address translation data. When the memory management unit is not in the protected mode, the unit maps memory access requests from the plurality of I/O devices to different respective sets of memory address translation data. Thus, the memory management unit may protect memory from access by I/O devices using fewer address translation tables than are typically required (e.g., none). | 2013-03-28 |
20130080727 | COMPUTER SYSTEM AND STORAGE MANAGEMENT METHOD - A storage tiered that satisfies desired performance is configured by recognizing the type and capacity of storage media of a storage apparatus, which are held by a user, and using the storage media. | 2013-03-28 |
20130080728 | AUTOMATED SELECTION OF FUNCTIONS TO REDUCE STORAGE CAPACITY BASED ON PERFORMANCE REQUIREMENTS - A plurality of functions to configure a unit of a storage volume is maintained, wherein each of the plurality of functions, in response to being applied to the unit of the storage volume, configures the unit of the storage volume differently. Statistics are computed on growth rate of data and access characteristics of the data stored in the unit of the storage volume. A determination is made as to which of the plurality of functions to apply to the unit of the storage volume, based on the computed statistics. | 2013-03-28 |
20130080729 | PILOT PLACEMENT FOR NON-VOLATILE MEMORY - A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison. | 2013-03-28 |
20130080730 | FLASH MEMORY SYSTEM - A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row. | 2013-03-28 |
20130080731 | METHOD AND APPARATUS FOR PERFORMING MEMORY MANAGEMENT - A method for performing display control is provided, where the method is applied to an electronic device. The method includes: managing a plurality of physical blocks of at least one non-volatile (NV) memory according to a block address translation rule, the block address translation rule of both of one-to-multiple block address translation and multiple-to-one block address translation; and when it is detected that erasing a specific logical block represented by a specific block logical address is required, determining a set of block physical addresses corresponding to the specific block logical address according to the block address translation rule and erasing a set of physical blocks represented by the set of block physical addresses within the plurality of physical blocks. An associated apparatus is also provided. | 2013-03-28 |
20130080732 | APPARATUS, SYSTEM, AND METHOD FOR AN ADDRESS TRANSLATION LAYER - An apparatus, system, and method are disclosed for storage address translation. The method includes storing, in volatile memory, a plurality of logical-to-physical mapping entries for a non-volatile recording device. The method includes persisting a logical-to-physical mapping entry from the volatile memory to recording media of the non-volatile recording device. The logical-to-physical mapping entry may be selected for persisting based on a mapping policy indicated by a client. The method includes loading the logical-to-physical mapping entry from the recording media of the non-volatile recording device into the volatile memory in response to a storage request associated with the logical-to-physical mapping entry. | 2013-03-28 |
20130080733 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor connected to a storage device including a buffer area where an address translation pair is stored includes: an LRU register that holds a number of a plurality of real address registers, the real address register being the oldest in a use history; a reading unit that reads the number of the real address register held in the LRU register when a real address included in an access request to the storage device does not fall within a range of a real address space from a lower limit real address held in a lower limit real address register to an upper limit real address held in an upper limit real address register; and a setting unit that invalidates the real address register corresponding to the read number and sets a real address space corresponding to the real address included in the access request to the invalided real address register. | 2013-03-28 |
20130080734 | ADDRESS TRANSLATION UNIT, METHOD OF CONTROLLING ADDRESS TRANSLATION UNIT AND PROCESSOR - Disclosed herein is a micro TLB which includes a CAM section having a plurality of CAM circuits, each stores address information which represents correlation between a virtual address and a physical address; and a write control section which directs writing of the address information into each CAM circuit pointed by a write pointer, when a new address information is requested to be stored, wherein the micro TLB being configured to increment the write pointer, if the address information stored in each CAM circuit pointed by the write pointer has been used for address translation, so as to hold a recently-used address information while preventing the CAM circuit, having indication of use of the address information, from being overwritten with the new address information. | 2013-03-28 |
20130080735 | ADDRESS TRANSLATION DEVICE, PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE - An address translation buffer (TLB) which holds pairs of virtual addresses and physical addresses by respective page sizes and performs an address translation, a storage unit which holds a pair of a virtual address removed from the TLB and page size corresponding thereto when a pair of a new virtual address and physical address read from a page table is registered to the TLB, base registers which hold a base address by each page size are held. The TLB is searched based on a translation object virtual address included in a memory access request, and when a TLB miss occurs, a main storage is searched based on a pointer address generated from information held by the storage unit and the base register, and the translation object virtual address is translated into the physical address. | 2013-03-28 |
20130080736 | SYSTEMS AND METHODS FOR UNIQUELY DEFINING FORTRAN RUN TIME TYPE DESCRIPTORS FOR POLYMORPHIC ENTITIES - Systems and methods disclosed herein uniquely define each type of Fortran type descriptor within an executable file or shared library to allow for a rapid determination of how the dynamic type of one object (e.g., a first polymorphic entity) relates to that of another object (e.g., a second polymorphic entity) while allowing for the lazy loading of shared libraries. In one aspect, type descriptor definitions are instantiated (e.g., during compile-time) in each object file in which polymorphic entities are defined, each type descriptor definition is marked with a singleton attribute, and each group of common type descriptor definitions is associated with a COMDAT group to ensure that only a single copy of each type descriptor is defined in a corresponding executable file at a particular address in memory to which polymorphic entities can reference. Type descriptor addresses can be compared to determine dynamic type relations between polymorphic entities. | 2013-03-28 |
20130080737 | Interleaving data accesses issued in response to vector access instructions - A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by the elements to the data store, and configured in response to receipt of at least two decoded vector data access instructions, and one of the instructions being a write instruction. Data accesses are performed in the instructed order to determine an element indicating the next data access for each of said vector data access instructions. One of the next data accesses is selected to be issued to the data store in dependence upon an order in which the at least two vector data instructions were received. The position of the elements indicates the next data accesses relative to each other within their respective plurality of elements. A numerical position of the element indicating the next data access within the plurality of elements of an earlier instruction is less than a predetermined value. | 2013-03-28 |
20130080738 | PROCESSOR CONFIGURED TO PERFORM TRANSACTIONAL MEMORY OPERATIONS - In a particular embodiment, a very long instruction word (VLIW) processor is operable to execute VLIW instructions. At least one of the VLIW instructions includes a first load or store instruction and a second load or store instruction. The first instruction and the second instruction are executed as a single atomic unit. At least one of the first and second instructions is a store-conditional instruction. | 2013-03-28 |
20130080739 | SIMD PROCESSOR AND CONTROL PROCESSOR, AND PROCESSOR ELEMENT - To improve processing efficiency of a SIMD processor that divides two-dimensional data into blocks, each having a width of PE number N, to store the data in a local memory of each of PEs by a lateral direction priority method. | 2013-03-28 |
20130080740 | FAST CONDITION CODE GENERATION FOR ARITHMETIC LOGIC UNIT - In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify an arithmetic operation specified in the instruction, and execution logic configured to receive operands specified by the instruction. The execution logic includes a primary logic path configured to perform the arithmetic operation on such operands and a secondary parallel logic path configured to output metadata associated with the result of the arithmetic operation. | 2013-03-28 |
20130080741 | HARDWARE CONTROL OF INSTRUCTION OPERANDS IN A PROCESSOR - An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may have a counter and may be configured to adjust at least one control signal in response to a current value of the counter. The first circuit may be implemented only in hardware. The counter generally counts a number of loops in which a plurality of instructions are executed. The second circuit may be configured to set the counter to an initial value. The third circuit may be configured to execute the instructions using a plurality of data items as a plurality of operands such that at least two of the instructions use different ones of the operands. The data items may be routed to the third circuit in response to the control signal. The apparatus generally forms a processor. | 2013-03-28 |
20130080742 | METHOD, APPARATUS AND INSTRUCTIONS FOR PARALLEL DATA CONVERSIONS - Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register. | 2013-03-28 |
20130080743 | ROUND ROBIN PRIORITY SELECTOR - Method and structures for performing round robin priority selection receive an input vector into an input port. The methods and structures group the bits of the input vector into groups of bits and supply the groups of bits to round robin priority selectors. Then, the methods and structures simultaneously identify an individual group priority bit within each group of bits based on the starting bit location, using the round robin priority selectors. The methods and structures also choose, using the group selector, a round robin priority selector based on the starting bit location. The methods and structures then output, from the group selector to a multiplexor, the individual group priority bit of the selected round robin priority selector. Following this the method outputs, from the multiplexor, an output vector having a first value (e.g., 1) only in the individual group priority bit output by the group selector. | 2013-03-28 |
20130080744 | ABSTRACTING COMPUTATIONAL INSTRUCTIONS TO IMPROVE PERFORMANCE - Methods and systems for executing a code stream of non-native binary code on a computing system are disclosed. One method includes parsing the code stream to detect a plurality of elements including one or more branch destinations, and traversing the code stream to detect a plurality of non-native operators. The method also includes executing a pattern matching algorithm against the plurality of non-native operators to find combinations of two or more non-native operators that do not span across a detected branch destination and that correspond to one or more target operators executable by the computing system. The method further includes generating a second code stream executable on the computing system including the one or more target operators. | 2013-03-28 |
20130080745 | FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY - Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.). | 2013-03-28 |
20130080746 | Providing A Dedicated Communication Path Separate From A Second Path To Enable Communication Between Complaint Sequencers Of A Processor Using An Assertion Signal - In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed. | 2013-03-28 |
20130080747 | PROCESSOR AND INSTRUCTION PROCESSING METHOD IN PROCESSOR - The present invention relates to a processor including: an instruction cache configured to store at least some of first instructions stored in an external memory and second instructions each including a plurality of micro instructions; a micro cache configured to store third instructions corresponding to the plurality of micro instructions included in the second instructions; and a core configured to read out the first and second instructions from the instruction cache and perform calculation, in which the core performs calculation by the first instructions from the instruction cache under a normal mode, and when the process enters a micro instruction mode, the core performs calculation by the third instructions corresponding to the plurality of micro instructions provided from the micro cache. | 2013-03-28 |
20130080748 | MULTI-PROCESSOR DATA PROCESSING SYSTEM HAVING SYNCHRONIZED EXIT FROM DEBUG MODE AND METHOD THEREFOR - A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic. | 2013-03-28 |