13th week of 2013 patent applcation highlights part 46 |
Patent application number | Title | Published |
20130078742 | ENHANCEMENT OF PROPERTIES OF THIN FILM FERROELECTRIC MATERIALS - Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level. | 2013-03-28 |
20130078743 | Method and Apparatus For Depositing A Layer On A Semiconductor Wafer by Vapor Deposition In A Process Chamber - A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value. | 2013-03-28 |
20130078744 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS OF THIN FILM - A semiconductor wafer, on the surface of which a silicon dioxide base material and an amorphous silicon thin film are formed in this order, is carried into a chamber. An insulated gate bipolar transistor (IGBT) is connected with a power supply circuit to a flash lamp, and the IGBT makes an energization period to the flash lamp to be 0.01 millisecond or more and 1 millisecond or less, consequently making a flash light irradiation time to be 0.01 millisecond or more and 1 millisecond or less. Since a flash heat treatment is performed with a remarkably short flash light irradiation time, the excessive heating of the thin film of amorphous silicon is suppressed and harmful influence such as the exfoliation of the film is prevented. | 2013-03-28 |
20130078745 | Production Flow and Reusable Testing Method - An embodiment is a method. The method comprises providing a substrate comprising a die area. The die area comprises sections of pad patterns, and first sections of the sections each comprise a first uniform pad pattern. The method further comprises probing a first one of the first sections with a first probe card; stepping the first probe card to a second one of the first sections; and probing the second one of the first sections with the first probe card. | 2013-03-28 |
20130078746 | RETICLE DEFECT CORRECTION BY SECOND EXPOSURE - Correction of reticle defects, such as EUV reticle defects, is accomplished with a second exposure. Embodiments include obtaining a reticle with a first pattern corresponding to a design for a wafer pattern, detecting dark defects and/or design/OPC weak spots in the first pattern, exposing a resist covered wafer using the reticle, and exposing the wafer using a second reticle with a second pattern or a second image field with openings corresponding to the dark defects, with a repair pattern on the reticle or on another reticle, or with a programmed e-beam or laser writer. | 2013-03-28 |
20130078747 | SUBSTRATE ETCHING METHOD AND SUBSTRATE ETCHING APPARATUS - A method for selectively etching a substrate includes providing a template having opening portions formed on an upper surface in a predetermined pattern and flow channels penetrating through the template from the opening portions to a lower surface of the template, filling an etching solution into the flow channels, coupling the upper surface of the template to a substrate such that the opening portions correspond to the predetermined pattern of through holes to be formed through the substrate, and supplying the etching solution onto the substrate through the opening portions of the template such that the through holes are etched through the substrate. | 2013-03-28 |
20130078748 | METHOD OF FABRICATING ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display and a fabrication method thereof, the display including a substrate; a thin film transistor on the substrate; and an organic light emitting diode on the substrate, the organic light emitting diode including a pixel electrode, an organic emission layer, and a common electrode, wherein the organic emission layer includes a red (R) pixel, a green (G) pixel, and a blue (B) pixel, the pixel electrode includes a first pixel electrode, a second pixel electrode, and a third pixel electrode that respectively correspond to the red pixel, the green pixel, and the blue pixel, the first pixel electrode, the second pixel electrode, and the third pixel electrode each have different thicknesses, and the first pixel electrode, the second pixel electrode, and the third pixel electrode each include a first hydrophobic layer. | 2013-03-28 |
20130078749 | ORGANIC LIGHT EMITTING DEVICE - The organic light emitting device of the present invention has a plurality of emission layers between an anode and a cathode, and the emission layers are separated from each other by an equipotential surface forming layer or a charge generating layer. The feature of the present invention resides in that the organic light emitting device has, at least either inside or outside the device, a light scattering means for scattering light emitted from the emission layers. The organic light emitting device can reduce the angle dependency of the emission brightness and the emission color by outputting the light emitted from the emission layers in a condition where the light is scattered by the light scattering means. | 2013-03-28 |
20130078750 | FABRICATING METHOD OF NANO STRUCTURE FOR ANTIREFLECTION AND FABRICATING METHOD OF PHOTO DEVICE INTEGRATED WITH ANTIREFLECTION NANO STRUCTURE - A method of fabricating nanostructure for antireflection and a method of fabricating a photo device integrated with the nanostructure for antireflection are provided. The fabrication of the nanostructure for antireflection includes coating a solution containing a combination of metal ions with organic or inorganic ions on a substrate, sintering the coated solution using an annealing process to grow nanoscale metal particles, and chemically etching the substrate using the metal particles as mask or accelerator to form a subwavelength nanostructure on the surface of the substrate, thereby manufacturing the nanostructure for antireflection without an apparatus requiring a vacuum state using a simple method for a short amount of time to minimize reflection of light at an interface between a semiconductor material and the air, and producing a photo device having good luminous efficiency and performance at low cost in large quantities by applying it to the photo device. | 2013-03-28 |
20130078751 | DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data interconnection pattern formed on the semiconductor layer pattern, a protection layer formed on the substrate and the data interconnection pattern, contact holes formed on the substrate to expose at least a portion of an upper surface of the semiconductor pattern and at least a portion of an upper surface of the data interconnection pattern, and contact electrodes formed in the contact holes to be in contact with the exposed upper surfaces of the data interconnection pattern and the semiconductor layer pattern. | 2013-03-28 |
20130078752 | METHOD FOR MANUFACTURING DISPLAY DEVICE - According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate. | 2013-03-28 |
20130078753 | CAPPED DEVICE INTERCONNECT IN A SEMICONDUCTOR PACKAGE - A method for fabricating a thin package that encapsulates a capped MEMS device electrically coupled with one or more encapsulated semiconductor devices is provided. A wafer-level packaging methodology is used in which the capped MEMS device is electrically coupled to a package interconnect, which then allows for electrical coupling to the one or more encapsulated semiconductor devices, as well as external connections. | 2013-03-28 |
20130078754 | Light Induced Plating of Metals on Silicon Photovoltaic Cells - A method and composition for plating metal contacts on photovoltaic solar cells is described. The cell is immersed in an aqueous bath containing platable metal ions and a solubilizing agent for aluminum or aluminum alloy ions from the back side of the solar cell. The cell is then exposed to light, causing the two sides of the cell to become oppositely charged. The metal ions are plated without requiring an external electrical contact. | 2013-03-28 |
20130078755 | METHOD OF MANUFACTURING THIN FILM SOLAR CELLS - A method for manufacturing thin film solar cells, includes forming a light permeable first electrode layer in the back light surface of a glass substrate, and formed in the first electrode layer a plurality of first openings for exposing a part of the back light surface therefrom; forming a photoelectric conversion layer on the first electrode layer and the exposed back light surface, and forming a plurality of second openings in the photoelectric conversion layer for exposing a part of the first electrode layer therefrom; and forming a glistening second electrode layer having a plurality of third openings formed therein, wherein the second electrode layer comprises a conductive colloid comprised of non-diffractive fillings and polymeric base material. | 2013-03-28 |
20130078756 | AQUEOUS ALKALINE ETCHING AND CLEANING COMPOSITION AND METHOD FOR TREATING THE SURFACE OF SILICON SUBSTRATES - An aqueous alkaline etching and cleaning composition for treating the surface of silicon substrates, the said composition comprising: (A) a quaternary ammonium hydroxide; and (B) a component selected from the group consisting of water-soluble acids and their water-soluble salts of the general formulas (I) to (V): (R | 2013-03-28 |
20130078757 | METHODS OF MAKING PHOTOVOLTAIC DEVICES - One aspect of the present invention includes a method of making a photovoltaic device. The method includes disposing an absorber layer on a window layer. The method further includes treating at least a portion of the absorber layer with a first solution including a first metal salt to form a first component, wherein the first metal salt comprises a first metal selected from the group consisting of manganese, cobalt, chromium, zinc, indium, tungsten, molybdenum, and combinations thereof. The method further includes treating at least a portion of the first component with cadmium chloride to form a second component. The method further includes treating at least a portion of the second component with a second solution including a second metal salt to form an interfacial layer on the second component, wherein the second metal salt comprises a second metal selected from the group consisting of manganese, cobalt, nickel, zinc, and combinations thereof. | 2013-03-28 |
20130078758 | METHOD OF FABRICATING A SOLAR CELL WITH A TUNNEL DIELECTRIC LAYER - Methods of fabricating solar cells with tunnel dielectric layers are described. Solar cells with tunnel dielectric layers are also described. | 2013-03-28 |
20130078759 | COMPOSITION FOR FORMING N-TYPE DIFFUSION LAYER, METHOD OF FORMING N-TYPE DIFFUSION LAYER, AND METHOD OF PRODUCING PHOTOVOLTAIC CELL - The composition for forming an n-type diffusion layer in accordance with the present invention contains a glass powder and a dispersion medium, in which the glass powder includes an donor element and a total amount of the life time killer element in the glass powder is 1000 ppm or less. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment. | 2013-03-28 |
20130078760 | THIN FILM TRANSISTOR FABRICATING METHOD - A thin film transistor fabricating method is disclosed. The thin film transistor fabricating method comprises providing a substrate; forming an oxide semiconductor layer on an upper surface of the substrate; forming a gate insulating layer on an upper surface of the oxide semiconductor layer; masking a portion of the oxide semiconductor layer with the gate insulating layer; irradiating the oxide semiconductor layer with irradiating light having photon energy less than a band gap of the oxide semiconductor layer; forming a drain region and a source region at lateral portions of the oxide semiconductor layer exposed to the irradiating light, and forming a channel region in the portion of the oxide semiconductor layer masked by the gate insulating layer; and forming a gate electrode on an upper surface of the gate insulating layer. | 2013-03-28 |
20130078761 | METHOD FOR MANUFACTURING A FLEXIBLE TRANSPARENT 1T1R STORAGE UNIT BASED ON A COMPLETELY LOW-TEMPERATURE PROCESS - The present invention belongs to the technical field of low temperature atomic layer deposition technology, and specifically relates to a method for manufacturing a flexible transparent 1T1R storage unit. In the present invention, a fully transparent 1T1R storage unit is developed on a flexible substrate through a completely low-temperature process, including an oxide layer dielectric, a transparent electrode and a transparent substrate which are deposited together through a low-temperature process, thus realizing a fully transparent device capable of achieving the functions of nontransparent devices. The present invention can be applied to the manufacturing of flexible low-temperature storage units in the future, as well as changing the packaging and existing modes of devices, which will make foldable and bendable portable storage units possible. | 2013-03-28 |
20130078762 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized. | 2013-03-28 |
20130078763 | MULTI-CHIP SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed. | 2013-03-28 |
20130078764 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter. The computing processor device is connected to the second external electrode, and a bump is formed on the third external electrode. | 2013-03-28 |
20130078765 | On-Chip Heat Spreader - A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader. | 2013-03-28 |
20130078766 | METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices. | 2013-03-28 |
20130078767 | METHODS FOR FABRICATING INTEGRATED CIRCUIT SYSTEMS INCLUDING HIGH RELIABILITY DIE UNDER-FILL - A method is provided for fabricating an integrated circuit system that includes fabricating a plurality of integrated circuits in and on a semiconductor substrate. Spaced apart solder bumps are attached to the plurality of integrated circuits, the solder bumps in electrical contact to components of the integrated circuits. A dicing tape having a layer of under-fill material thereon is provided and the semiconductor substrate is laminated to the dicing tape with the layer of under-fill material filling spaces between the solder bumps. The semiconductor substrate and layer of under-fill material are diced to singulate individual ones of the plurality of integrated circuits, and one of the individual ones of the plurality of integrated circuits is attached to a second substrate such as another integrated circuit chip or printed circuit board. | 2013-03-28 |
20130078768 | NEST MECHANISM WITH RECESSED WALL SEGMENTS - A nest mechanism includes a 2-dimensional grid of support positions for supporting singulated electronic units. The support positions each include an inner opening and an outer horizontal base around the inner opening having a support surface that supports units thereon. A segmented wall arrangement is on the outer horizontal base located beyond an area of the unit for preventing movement of the unit while on the support surface. The segmented wall arrangement includes (i) a plurality of raised wall segments that extend to a first height above the support surface, and (ii) at least one recessed segment between the plurality of raised wall segments that has a height less than the first height. The recessed segment(s) help liquid-based washing processes to remove residue material generated by a sawing process that can become stuck under the units while in the nest mechanism awaiting transfer. | 2013-03-28 |
20130078769 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device for improving production efficiency and the flexibility of production design thereof is provided. The method includes preparing semiconductor chips having a first main surface on which an electroconductive member is formed, preparing a supporting structure in which over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order, arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to the first main surfaces of the semiconductor chips, laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips, and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer and the first thermosetting resin layer from each other. | 2013-03-28 |
20130078770 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer. | 2013-03-28 |
20130078771 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate. | 2013-03-28 |
20130078772 | Tilt Implantation for Forming FinFETs - In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin. | 2013-03-28 |
20130078773 | Method for manufacturing CMOS FET - A method for manufacturing a CMOS FET comprises forming a first interfacial SiO | 2013-03-28 |
20130078774 | METHOD FOR FORMING DOPE REGIONS WITH RAPID THERMAL PROCESS - The invention provides a method for forming a semiconductor device, including providing a substrate, forming a gate dielectric layer, forming a gate electrode on the gate dielectric layer, forming a spacer on sidewalls of the gate dielectric layer and the gate electrode, and using a rapid thermal process (RTP) apparatus comprising a plurality of lamps and a bias applying system to dope the substrate to form a source/drain region, wherein in the RTP apparatus, gaseous dopant species are illuminated by the lamps to be excited for transference gaseous dopant species to dopant ions and the dopant ions are moved by a bias from the bias applying system to be doped into the substrate. | 2013-03-28 |
20130078775 | METHOD OF FABRICATING MEMORY - A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings. | 2013-03-28 |
20130078776 | Methods of Manufacturing a Three-Dimensional Semiconductor Device - The inventive concept provides methods of manufacturing three-dimensional semiconductor devices. In some embodiments, the methods include forming a stack structure including sacrificial layers and insulation layers, forming a trench penetrating the stack structure, forming a hydrophobic passivation element on the surfaces of the insulation layers that were exposed by the trench and selectively removing the sacrificial layers. | 2013-03-28 |
20130078777 | METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR - A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type. | 2013-03-28 |
20130078778 | SEMICONDUCTOR PROCESS - A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed. | 2013-03-28 |
20130078779 | METAL GATE DEVICE WITH LOW TEMPERATURE OXYGEN SCAVENGING - A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate, source and drain features on the semiconductor substrate, and a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes an interfacial layer (IL) layer, a high-k (HK) dielectric layer formed over the semiconductor substrate, an oxygen scavenging metal formed on top of the HK dielectric layer, a scaling equivalent oxide thickness (EOT) formed by using a low temperature oxygen scavenging technique, and a stack of metals gate layers deposited over the oxygen scavenging metal layer. | 2013-03-28 |
20130078780 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer. | 2013-03-28 |
20130078781 | SEMICONDUCTOR FABRICATION - Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics. | 2013-03-28 |
20130078782 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed. | 2013-03-28 |
20130078783 | FORMING A PROTECTIVE FILM ON A BACK SIDE OF A SILICON WAFER IN A III-V FAMILY FABRICATION PROCESS - Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer. | 2013-03-28 |
20130078784 | CMP SLURRY AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, the CMP slurry includes abrasive particles made of colloidal silica in an amount of 0.5 to 3% by mass of a total mass of the CMP slurry, and a polycarboxylic acid having a weight average molecular weight of from 500 to 10,000, in an amount of 0.1 to 1% by mass of the total mass of the CMP slurry. 50 to 90% by mass of the abrasive particles each has a primary particle diameter of 3 to 10 nm. The CMP slurry has a pH within a range of 2.5 to 4.5. | 2013-03-28 |
20130078785 | METHOD FOR TRIMMING A STRUCTURE OBTAINED BY THE ASSEMBLY OF TWO PLATES - A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer. | 2013-03-28 |
20130078786 | HEAT TREATMENT METHOD FOR PROMOTING CRYSTALLIZATION OF HIGH DIELECTRIC CONSTANT FILM - A film of silicon dioxide is formed on the silicon-germanium layer, and a high dielectric constant film is further formed on the film of silicon dioxide. First irradiation from a flash lamp is performed on the semiconductor wafer to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 3 milliseconds to 1 second. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 3 milliseconds to 1 second. This promotes the crystallization of the high dielectric constant film while suppressing the alleviation of distortion in the silicon-germanium layer. | 2013-03-28 |
20130078787 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device, including the steps of: forming a first semiconductor film ( | 2013-03-28 |
20130078788 | PRODUCING METHOD OF SEMICONDUCTOR DEVICE AND PRODUCTION DEVICE USED THEREFOR - According to one embodiment, a producing method for a semiconductor device comprises: heating a semiconductor substrate to thereby maintain a substrate temperature of the semiconductor substrate at a desired temperature and simultaneously dope the semiconductor substrate with conductive impurities; and performing an activation treatment for activating the conductive impurities for doping. | 2013-03-28 |
20130078789 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium - A substrate processing apparatus includes a process chamber accommodating a substrate including a thin film formed at a film-forming temperature; a gas supply unit for supplying a process gas including oxygen and/or nitrogen onto the substrate; an excitation unit for exciting the process gas supplied into the process chamber; a heating unit for heating the substrate; an exhaust unit for exhausting an inside of the process chamber; and a control unit for controlling the gas supply unit, the excitation unit, the heating unit and the exhaust unit such that a temperature of the substrate is equal to or lower than the film-forming temperature when the substrate is processed by heating the substrate by the heating unit, exciting the process gas supplied from the gas supply unit by the excitation unit, and supplying the process gas excited by the excitation unit onto a surface of the substrate. | 2013-03-28 |
20130078790 | CARBON MATERIALS FOR CARBON IMPLANTATION - A method of implanting carbon ions into a target substrate, including: ionizing a carbon containing dopant material to produce a plasma having ions; optionally co-flowing an additional gas or series of gases with the carbon-containing dopant material; and implanting the ions into the target substrate. The carbon-containing dopant material is of the formula C | 2013-03-28 |
20130078791 | SEMICONDUCTOR DEVICE FABRICATION METHODS WITH ENHANCED CONTROL IN RECESSING PROCESSES - Semiconductor device fabrication methods having enhanced control in recessing processes are provided. In a method for fabricating a semiconductor device or plurality of them, a structure is formed. The method includes preparing a limited amount of the structure having a depth of less than ten atomic layers for removal. Further, the method includes performing a removal process to remove the limited amount of the structure. The method repeats preparation of successive limited amounts of the structure for removal, and performance of the removal process to form a recess at an upper portion of the structure. | 2013-03-28 |
20130078792 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess. | 2013-03-28 |
20130078793 | METHOD FOR DEPOSITING A GATE OXIDE AND A GATE ELECTRODE SELECTIVELY - The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for depositing a gate oxide and a gate electrode selectively. The present invention makes use of Octadecyltriethoxysilane's (ODTS') easy attachment to the Si—OH interface and difficult attachment to the Si—H interface, and selectively deposits the gate oxide and gate electrode materials, which avoids the unnecessary waste of materials and saves cost. Meanwhile, the present invention will transfer the etching of the gate oxide and gate electrode into the etching of SiO | 2013-03-28 |
20130078794 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer. | 2013-03-28 |
20130078795 | ETCH STOP LAYER FOR MEMORY CELL RELIABILITY IMPROVEMENT - A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device. | 2013-03-28 |
20130078796 | PROCESS FOR MAKING A PATTERNED METAL OXIDE STRUCTURE - There is provided a process for making a patterned metal oxide structure comprising the step of heating an imprint structure comprising a polymerized organometallic compound to remove organic material and thereby form the patterned metal oxide structure, wherein the imprint structure is formed by polymerizing a resist mixture comprising at least one olefinic polymerizable compound and a polymerizable organometallic compound having, e.g., at least one carboxylate of Formula 1: | 2013-03-28 |
20130078797 | METHOD FOR MANUFACTURING A COPPER-DIFFUSION BARRIER LAYER USED IN NANO INTEGRATED CIRCUIT - The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for manufacturing a copper-diffusion barrier layer. In the present invention, a proper reaction precursor has been selected and the atomic layer deposition (ALD) technology has been adopted to develop Co or Ru on a TaN layer to obtain a diffusion barrier layer used in the interconnection for process nodes no more than 32 nm, which overcomes the insufficiency of the PVD deposition Ta/TaN double-layer structure as the copper-diffusion barrier layer in step coverage and conformity, and also effectively solves various serious problems in the Cu/low-k dual damascene process, such as the generation of voids in grooves and through-holes, and electromigration stability. | 2013-03-28 |
20130078798 | METHOD FOR IMPROVING THE ELECTROMIGRATION RESISTANCE IN THE COPPER INTERCONNECTION PROCESS - The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi | 2013-03-28 |
20130078799 | METHOD OF FORMING METAL CARBIDE BARRIER LAYERS FOR FLUOROCARBON FILMS - A method of forming metal carbide barrier layers for fluorocarbon films in semiconductor devices is described. The method includes depositing a fluorocarbon film on a substrate and depositing a metal-containing layer on the fluorocarbon film at a first temperature, where the metal-containing layer reacts with the fluorocarbon film to form a metal fluoride layer at an interface between the metal-containing layer and the fluorocarbon film. The method further includes heat-treating the metal-containing layer at a second temperature that is greater than the first temperature, wherein the heat-treating the metal-containing layer removes fluorine from the metal fluoride layer by diffusion through the metal-containing layer and forms a metal carbide barrier layer at the interface between the metal-containing layer and the fluorocarbon film, and wherein the metal-containing layer survives the heat-treating at the second temperature without blistering or pealing. | 2013-03-28 |
20130078800 | METHOD FOR FABRICATING MOS TRANSISTOR - A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process. | 2013-03-28 |
20130078801 | MANUFACTURE METHODS OF DOUBLE LAYER GATE ELECTRODE AND RELEVANT THIN FILM TRANSISTOR - Disclosed is a manufacture method of a double layer gate electrode by patterning the photoresist layer with a half tone mask to make thicknesses of two sides of the photoresist layer are smaller than a thickness of middle of the photoresist layer and twice wet etchings thereafter to realize the manufacture of the double layer gate electrode. The present invention also relates to a manufacture method of a thin film transistor. The manufacture methods of a double layer gate electrode and a relevant thin film transistor according to the present invention employs half tone mask and twice wet etchings thereafter for manufacturing the gate electrode to solve technical problems of high manufacture cost and great manufacture difficulty of double layer gate electrodes according to prior arts. | 2013-03-28 |
20130078802 | HEAT TREATMENT METHOD FOR GROWING SILICIDE - Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer. | 2013-03-28 |
20130078803 | SEMICONDUCTOR DEVICE INCLUDING A CIRCUIT AREA AND A MONITOR AREA HAVING A PLURALITY OF MONITOR LAYERS AND METHOD FOR MANUFACTURING THE SAME - In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate, and, at the same time, five isolation insulating films extending in one specific direction are formed within a monitor area at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate, and, at the same time, five gate insulation films and five gate electrodes extending in the same direction as the isolation insulating films are formed within the monitor area at the same spacing as that of the isolation insulating films. | 2013-03-28 |
20130078804 | METHOD FOR FABRICATING INTEGRATED DEVICES WITH REDUCTED PLASMA DAMAGE - A method for fabricating an integrated device with reduced plasma damage is disclosed, including providing a substrate, forming a structural layer on the substrate, forming a photoresist layer on the structural layer, and performing an etching process to the structural layer, wherein the photoresist layer is conductive to reduce plasma damage during the etching process. | 2013-03-28 |
20130078805 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The present invention provides a semiconductor device manufacturing method. This method comprises: etching a first dielectric layer to form a recess; depositing a second dielectric layer over said first dielectric layer and said recess, such that said recess is enclosed by said first dielectric layer and said second dielectric layer to form an air gap; and performing etching, such that a first trench is formed in said first dielectric layer and said second dielectric layer, adjacent to said air gap. The first trench can be filled with a conductive material to form wiring. | 2013-03-28 |
20130078806 | Method for Fabricating Copper Interconnections in an Ultra Low Dielectric Constant Film - The invention relates to a method for fabricating copper interconnections in an ultra low dielectric constant film, comprising the following steps of: depositing an etching stop layer on a silicon wafer, depositing an ultra-low-k film on the etching stop layer, and depositing a SiO | 2013-03-28 |
20130078807 | WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME - A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads. | 2013-03-28 |
20130078808 | ELECTROLESS DEPOSITION SOLUTIONS AND PROCESS CONTROL - One embodiment of the present invention is a method of electroless deposition of cap layers for fabricating an integrated circuit. The method includes controlling the composition of an electroless deposition bath so as to substantially maintain the electroless deposition properties of the bath. Other embodiments of the present invention include electroless deposition solutions. Still another embodiment of the present invention is a composition used to recondition an electroless deposition bath. | 2013-03-28 |
20130078809 | SILICON NITRIDE ETCHING IN A SINGLE WAFER APPARATUS - A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture. | 2013-03-28 |
20130078810 | METHOD AND APPARATUS FOR PERFORMING A POLISHING PROCESS IN SEMICONDUCTOR FABRICATION - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a polishing head that is operable to perform a polishing process to a wafer. The apparatus includes a retaining ring that is rotatably coupled to the polishing head. The retaining ring is operable to secure the wafer to be polished. The apparatus includes a soft material component located within the retaining ring. The soft material component is softer than silicon. The soft material component is operable to grind a bevel region of the wafer during the polishing process. The apparatus includes a spray nozzle that is rotatably coupled to the polishing head. The spray nozzle is operable to dispense a cleaning solution to the bevel region of the wafer during the polishing process. | 2013-03-28 |
20130078811 | SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF - A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad. | 2013-03-28 |
20130078812 | Wafer Carrier with Flexible Pressure Plate - A wafer carrier with a wafer mounting plate disposed under a plenum which can be pressurized and depressurized to alter the shape of the wafer mounting plate and a plenum, formed with the wafer mounting plate and the wafer itself, to which vacuum can be applied to hold the wafer to the wafer mounting plate during polishing | 2013-03-28 |
20130078813 | PATTERN FORMING METHOD - The invention provides a pattern-formation process comprising a step of providing a substrate material having on a major surface a difficult-to-access recess formed by the presence of a 1 | 2013-03-28 |
20130078814 | RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON HAVING ANION GROUP - There is provided a method of making a semiconductor device utilizing a resist underlayer film forming composition comprising a silane compound containing an anion group, wherein the silane compound containing an anion group is a hydrolyzable organosilane in which an organic group containing an anion group is bonded to a silicon atom and the anion group forms a salt structure, a hydrolysis product thereof, or a hydrolysis-condensation product thereof. The anion group may be a carboxylic acid anion, a phenolate anion, a sulfonic acid anion, or a phosphonic acid anion. The hydrolyzable organosilane may be a compound of Formula (1): R | 2013-03-28 |
20130078815 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH REDUCED LINE EDGE ROUGHNESS - A method for forming a semiconductor structure with reduced line edge roughness is provided, including: providing a device layer with a patterned photoresist layer formed thereon; and performing a plasma etching process to pattern the device layer with the patterned photoresist layer formed thereon, forming a patterned device layer, wherein the plasma etching process is operated under a continuous on-stage voltage provided with a relative higher frequency and an on-off stage voltage with pulsing modulation provided with a relative lower frequency. | 2013-03-28 |
20130078816 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium - A substrate processing apparatus includes: a process chamber accommodating a substrate including a polysilicon film having an oxygen-containing layer formed thereon; a heating unit in the process chamber to heat the substrate; a gas supply unit to supply a process gas containing nitrogen and hydrogen to the substrate in the process chamber; an excitation unit to excite the process gas supplied into the process chamber; an exhaust unit to exhaust an inside of the process chamber; and a control unit to control at least the heating unit, the gas supply unit, the excitation unit and the exhaust unit for modifying the oxygen-containing layer into an oxynitride or nitride layer by heating the substrate to a predetermined temperature using the heating unit, exciting the process gas supplied by the gas supply unit using the excitation unit, and supplying the process gas excited by the excitation unit to the substrate. | 2013-03-28 |
20130078817 | METHOD OF FORMING FILM, METHOD OF FORMING PATTERN, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an embodiment, a method of forming a film is provided. In the method of forming a film, a reversed pattern which is the reverse of a desired layout pattern is formed on a first substrate. Subsequently, a pattern material of the desired layout pattern is supplied to a second substrate as a reversal material. Thereafter, the reversed pattern is brought into contact with the reversal material such that the reversed pattern faces the reversal material, so that the reversed pattern is filled with the reversal material by a capillary phenomenon. | 2013-03-28 |
20130078818 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure. | 2013-03-28 |
20130078819 | METHOD FOR CLEANING & PASSIVATING GALLIUM ARSENIDE SURFACE AUTOLOGOUS OXIDE AND DEPOSITING AL2O3 DIELECTRIC - The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning & passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al | 2013-03-28 |
20130078820 | IMPRINT METHOD, IMPRINT APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In an imprint method of an embodiment, in the imprinting of an imprint shot including an outermost peripheral region of a substrate where resist is not desired to be entered at the time of imprinting, light curing the resist is applied to a light irradiation region with a predetermined width including a boundary between the outermost peripheral region and a pattern formation region more inside than the outermost peripheral region, whereby the resist which is to enter inside the outermost peripheral region is cured. Then, light curing the resist filled in a template pattern is applied onto a template. | 2013-03-28 |
20130078821 | IMPRINT METHOD, IMPRINT APPARATUS, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In an imprint method according to embodiments, light that hardens a resist is irradiated to a light irradiation region near an alignment mark in order to prevent the resist from being filled in the alignment mark of a template, when the alignment process between the template and a substrate is performed. After the alignment process is completed, the resist is filled in the template pattern and the alignment mark, and then, light that hardens the resist is irradiated onto the template. | 2013-03-28 |
20130078822 | HEAT TREATMENT METHOD FOR HEATING SUBSTRATE BY IRRADIATING SUBSTRATE WITH FLASH OF LIGHT - First flash irradiation from flash lamps is performed on an upper surface of a semiconductor wafer supported on a temperature equalizing ring of a holder to cause the semiconductor wafer to jump up from the temperature equalizing ring into midair. While the semiconductor wafer is in midair above the temperature equalizing ring, second flash irradiation from the flash lamps is performed on the upper surface of the semiconductor wafer to increase the temperature of the upper surface of the semiconductor wafer to a treatment temperature. Cracking in the semiconductor wafer is prevented because the second flash irradiation is performed while the semiconductor wafer is in midair and subject to no restraints. | 2013-03-28 |
20130078823 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device including: mounting a substrate on a substrate mounting member that is disposed in a reaction container; heating the substrate at a predetermined processing temperature and supplying a first gas and a second gas to the substrate to process the substrate; stopping supply of the first gas and the second gas, and supplying an inert gas into the reaction container; and unloading the substrate to outside the reaction container. | 2013-03-28 |
20130078824 | CONNECTOR FOR CONNECTING A COAXIAL CABLE AND A CIRCUIT BOARD AND RELATED TRANSMISSION INTERFACE AS WELL AS ASSEMBLY METHOD THEREWITH - A connector for connecting a coaxial cable and a circuit board is disclosed. The connector includes a main body, a first holding portion, a second holding portion and a fixing structure. The first holding portion extends from a first end portion of the main body for holding a first insulation layer of the coaxial cable. The second holding portion extends from the main body in a position located between a second end portion opposite to the first end portion and the first holding portion for holding a braid layer of the coaxial cable. The fixing structure extends from the second end portion of the main body in a direction away from the second holding portion for disposing through at least one hole on the circuit board, so as to fix the coaxial cable on the circuit board. | 2013-03-28 |
20130078825 | METHOD FOR CONNECTING PRINTED CIRCUIT BOARDS - There is provided a first, connecting printed circuit board (PCB) and a second, receiving PCB and a method for connecting the first and second PCBs. The first PCB has three projections or prongs extending from the main body of the PCB. The second PCB has three holes into which the prongs of the first PCB can be inserted to provide a secure mechanical connection whilst the PCBs are soldered together. | 2013-03-28 |
20130078826 | TORSIONALLY-INDUCED CONTACT-FORCE CONDUCTORS FOR ELECTRICAL CONNECTOR SYSTEMS - An electrical connector comprising a pair of elongated bodies, each having a facing ramp, the ramp having an notch, each having a rotatable torsion bar conductor with a tip located in the notch, the end of a tip spaced above the ramp such that when the two bodies are mated, the tips engage the ramp of the other connector and rotate against a torsional restoring force, and when fully mated, the two ramps abut each other, notches aligned, with the respective tips of the torsion bars engaging the torsion bar of the other body in the aligned notches. | 2013-03-28 |
20130078827 | ELECTRICAL CONNECTOR HAVING HOLDER FOR CARRYING AN IC PACKAGE - An electrical connector for electrically connecting an IC package to a circuit board includes an insulating housing having a number of contacts received therein, a load plate covering the insulating housing and rotating between an open position and a closed position and a holder assembled on the load plate for retaining the IC package. The holder is sandwiched between the insulating housing and the load plate and capable of loading the IC package to the insulating housing when the load plate is rotated to a close position. | 2013-03-28 |
20130078828 | Connection Assembly On Circuit Boards - A connection arrangement with a plug element and a circuit board with plated-through holes. The plug element has a plurality of pluggable contact elements. The plated-through holes are arranged in an arrangement corresponding to the arrangement of the contact elements of the plug element. The plated-through holes and the contact elements that can be plugged into them, are matched to one another such that the plug element is manually connectable to the circuit board by inserting the contact elements into the plated-through holes and the plug element is manually removable. The contact elements are simultaneously pluggable into their associated plated-through holes. The contact elements include two legs having a space between them, with both legs of each contact element pluggable into a respective plated-through hole. | 2013-03-28 |
20130078829 | SOCKET CONNECTOR HAVING CONTACT WITH MULTIPLE BEAMS JOINTLY GRASPING BALL OF IC PACKAGE - A socket connector is provided to receive an IC package having an array of conductive balls thereunder. The socket connector includes an insulative housing defining a plurality of receiving holes and a plurality of contacts received in the receiving holes respectively. Each contact includes a bottom plate and at least two contacting beams extending upwardly from the bottom plate and jointly defining a receiving space for the ball of the IC package. At least one contacting beam has a sharp blade facing toward the receiving space so as to engage the ball when the IC package is mounted on the housing. | 2013-03-28 |
20130078830 | ELECTRICAL CONNECTOR HAVING CIRCUIT DEFINING A NUMBER OF DIFFERENTIAL CHANNELS - An electrical connector has a circuit comprising a first side; a second side; a first differential channel located between the first side and the second side and comprising a first positive differential trace and a first negative differential trace for transmitting first differential signal; a second differential channel located between the first side and the second side comprising a second positive differential trace and a second negative differential trace for transmitting second differential signal; and a plurality of mating contacts connected to the second side and comprising a first contact connected to the first positive differential trace, a second contact connected to the first negative differential trace, a third contact connected to the second positive differential trace and a sixth contact connected to the second negative differential trace, the first contact, the second contact, the third second and the sixth contact are arranged one by one. | 2013-03-28 |
20130078831 | VERTICAL CONNECTOR AND ASSEMBLY THEREOF - The instant disclosure relates to a vertical mount connector, which includes an insulating body, a metal casing, and a terminal assembly. The insulating body has a base and at least one tongue portion extended therefrom. A plurality of terminal grooves is formed and spaced on the insulating body, where each terminal groove concavely extends from the tongue portion to the base. The base defines a plurality of first openings in communication with the terminal grooves. The metal casing is engaged to the insulating body and defines in insertion opening. The terminal assembly includes a plurality of terminals disposed in the terminal grooves. Each terminal has a mounting portion and a connecting portion bendingly extends therefrom. The connecting portions protrude from the base of the insulating body via the first openings. | 2013-03-28 |
20130078832 | Compact All-In-One Power Adapter - A compact power adapter comprises an electric circuit, a casing and two electrically conductive AC prongs. A first portion of the casing contains the electric circuit. A second portion of the casing extends from a side of the first portion and has a generally cylindrical shape and size receivable in a car cigarette lighter. The second portion has two recesses and electrical contacts that receive electrical energy when the second portion is received in the car cigarette lighter. The AC prongs are receivable in an AC power outlet, and are rotatably coupled to the casing to rotate between a first position where the AC prongs extend from the casing approximately perpendicular to a longitudinal axis of the generally cylindrical shape of the second portion and a second position where each of the AC prongs is received in a respective one of the recesses of the second portion. | 2013-03-28 |
20130078833 | DISCONNECT PULLOUT HANDLE - Apparatus, systems, and methods associated with a disconnect pullout handle for selectively conducting power between jaw connectors are provided. In one embodiment, the disconnect pullout handle includes a molded handle base and a conductive blade configured for frictional engagement with the jaw connectors to provide a current path therebetween. The conductive blade is molded integrally into the blade retaining finger. | 2013-03-28 |
20130078834 | ROTATABLE PLUG ASSEMBLY AND HOUSING FOR A VOLATILE MATERIAL DISPENSER - A rotatable electrical plug assembly for a volatile material dispenser includes a support block including a base having a base member and a wall extending from the base member and forming a cavity with the base member. The plug assembly further includes a cover disposed within the cavity and electrical plug pins extending through apertures in the base and including contacts that extend at an angle of about 90 degrees with respect to the plug pins, wherein the contacts are disposed between the base member and the cover. A ratio of an overall plug assembly thickness over a plug pin thickness is less than about 1.5. | 2013-03-28 |
20130078835 | Electrical Connector System - The present invention relates to an electrical connector system. The electrical connector system includes a first connector to be mated to a corresponding counter connector and it is further adapted to be connected to a signal circuit for activating an electrical power source upon switching. As a safety feature, the connector system further includes a connector position assurance (CPA) member assigned to the first connector, which is movable, whereby an end position is not reachable if the first connector is incorrectly mated to the counter connector. The CPA member is adapted to interact with the signal circuit if placed in said end position so that it activates of the electrical power source. | 2013-03-28 |
20130078836 | High Voltage Direct Current Cable Termination Apparatus - A direct current cable termination apparatus for terminating a high voltage direct current cable. The apparatus includes a current-carrying device including a terminal portion of the direct current cable, the cable including an electrical conductor, an electrically insulating layer located outside of the electrical conductor, and a conductive shield located outside of the insulating layer and the electrical conductor; and a housing including a tubular outer shell with an inner periphery and formed by an electrically insulating and polymer-containing material. The current-carrying device is adapted to extend in the axial direction of the outer shell. Along at least a part of the axial extension of the current-carrying device the outer shell extends axially with a space between its inner periphery and the current-carrying device. | 2013-03-28 |
20130078837 | POWER SUPPLY APPARATUS - A power supply includes first connecting board, a second connecting board and a conductive module. Three adapters are located on the first connecting board. The three adapters connect with power supply via three anodes and three cathodes. A connector is located on the second connecting board and configured to output power. The conductive module includes a first bus bar and a second bus bar. The first bus bar includes three input terminals and an output terminal. The second bus bard includes three input terminals and an output terminal The three input terminals of the first bus bar are electrically connected to the three anodes of the three adapters. The three input terminals of the second bus bar are electrically connected to the three cathodes of the three adapters. The output terminals of the first bus bar and the second bus bar are electrically connected to the second connecting board. | 2013-03-28 |
20130078838 | FIXING FRAME AND FIXING APPARATUS FOR STORAGE DEVICE - An apparatus for fixing a storage device includes a metal bracket, and a fixing frame slidably received in the bracket. The bracket includes two side plates, and one of the side plates forms a resilient tab. The fixing frame includes two opposite fixing arms each defining a latching hole, two resilient members, and two metal fasteners. Each resilient member includes a pad clinging to an inner surface of a corresponding one of the fixing arms, and a projection engaging in the latching hole of the corresponding fixing arm. Each fastener includes a head, and a pin. The heads are received in the corresponding latching holes and abut against outer sides of the corresponding projections. The pins extend through the corresponding through holes for engaging with the storage device. A protrusion extends outwards from one of the heads to contact the resilient tab and connect the storage device to ground. | 2013-03-28 |
20130078839 | Funnel Shaped Charge Inlet - A vehicle charge inlet integrated into a port assembly surface is provided. The charge inlet includes an inlet housing with a perimeter that is curvilinear, non-cylindrical and shaped so that only a single orientation of a complementary sized and shaped electrical connector may be inserted into the inlet. A plurality of electrical contacts, a latching mechanism and a divider are also integrated into the charge inlet housing, the divider extending from the bottom surface of the inlet housing and configured to fit within a complementary slot of the charge connector, the divider providing further electrical isolation between the electrical contacts. A funneling surface connects the open end of the inlet housing to the port assembly surface. | 2013-03-28 |
20130078840 | POWER PLUG LOCKING DEVICE - A power plug locking device arranged in a vehicle includes a lock member moved between a lock position, in which the lock member prohibits removal of a power plug from a vehicle inlet, and an unlock position, in which the lock member permits removal of the power plug from the vehicle inlet. A drive source is activated to move the lock member from the lock position to the unlock position. An unlock switch is manually operated to move the lock member to the unlock position. An unlock circuit activates the drive source to move the lock member to the unlock position when the operation of the unlock switch and an unlock state of a vehicle door are both detected. | 2013-03-28 |
20130078841 | Electromechanical Pawl for Controlling Vehicle Charge Inlet Access - A charge connector latching mechanism integrated into a vehicle's charge inlet is provided, where the latching mechanism includes a retractable latching pawl. The retractable pawl is configured to be positioned in at least a first, default position where the pawl extends through an inlet surface of the charge inlet, and a second position where the pawl is retracted and does not extend through the inlet surface. In the first position the retractable pawl prevents insertion of a charge connector into the charge inlet if the charge connector is uncoupled from the inlet, and prevents removal of the charge connector if the charge connector is coupled to the inlet. In the second position the retractable pawl allows insertion/withdrawal of the charge connector into/from the charge inlet. The front surface of the retractable pawl may include a nub configured to fit within a recess within the front face of the charge connector. | 2013-03-28 |