13th week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130075839 | STRUCTURE AND METHOD FOR A MRAM DEVICE WITH AN OXYGEN ABSORBING CAP LAYER - The present disclosure provides a MTJ stack for an MRAM device. The MTJ stack includes a pinned ferromagnetic layer over a pinning layer; a tunneling barrier layer over the pinned ferromagnetic layer; a free ferromagnetic layer over the tunneling barrier layer; a conductive oxide layer over the free ferromagnetic layer; and a oxygen-based cap layer over the conductive oxide layer. | 2013-03-28 |
20130075840 | METHOD FOR FABRICATION OF A MAGNETIC RANDOM ACCESS MEMORY (MRAM) USING A HIGH SELECTIVITY HARD MASK - A self-aligned via of a MRAM cell that connects a memory element including a top electrode, a memory element stack having a plurality of layers, and a bottom electrode to a bit line running over array of the memory elements. The self-aligned via also serves as a hard mask for memory element etching. The hard mask material has high selectivity in the etching ambient to maintain enough remaining thickness. It is also selectively removed during dual damascene process to form a self-aligned via hole. In one embodiment, Aluminum oxide or Magnesium oxide is adapted as the hard mask. | 2013-03-28 |
20130075841 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device. | 2013-03-28 |
20130075842 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming an MTJ element and an electrode layer pattern over a substrate; forming a protective layer to protect the MTJ element and the electrode layer pattern; forming at least one insulation layer over the protective layer; forming a first hole by selectively removing the at least one insulation layer; forming an overhang pattern protruding from the sidewall of the first hole; forming a second hole exposing the electrode layer pattern by selectively removing the at least one insulation layer exposed at the bottom of the first hole by using the overhang pattern as a mask; and forming a conductive layer pattern to be electrically coupled to the electrode layer pattern exposed through the second hole. | 2013-03-28 |
20130075843 | SPIN TRANSISTOR AND MEMORY - A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film. | 2013-03-28 |
20130075844 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to the present embodiment comprises a lower electrode provided above a semiconductor substrate and made of metal, an upper electrode provided above the lower electrode and made of metal, and a crystal layer provided between the lower electrode and the upper electrode. A thickness of each of the lower electrode and the upper electrode is smaller than a thickness of a skin layer deriving from a skin effect corresponding to a frequency of a microwave used to crystallize the crystal layer. | 2013-03-28 |
20130075845 | THERMALLY TOLERANT PERPENDICULAR MAGNETIC ANISOTROPY COUPLED ELEMENTS FOR SPIN-TRANSFER TORQUE SWITCHING DEVICE - Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier, A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells. | 2013-03-28 |
20130075846 | MAGNETIC MEMORY - A memory includes an underlying layer of a ferromagnetic body, a first nonmagnetic layer on the underlying layer, a data memorizing layer laid on the first nonmagnetic layer and made of a ferromagnetic body having perpendicular magnetic anisotropy, a reference layer coupled through a second nonmagnetic layer with the data memorizing layer, and first and second magnetization fixed layers laid underneath the underlying layer to come into contact with the underlying layer. The data memorizing layer includes a magnetization liberalized region having reversible magnetization, and overlapping with the reference layer, a first magnetization fixed region coupled with an end of the magnetization liberalized region, and having a magnetization direction fixed to +z direction by the first magnetization fixed layer, and a second magnetization fixed region coupled with a different end of the magnetization liberalized region, and having a magnetization direction fixed to −z direction by the second magnetization fixed layer. | 2013-03-28 |
20130075847 | MAGNETIC MEMORY - A magnetic memory has: a pinning layer being a perpendicular magnetic film whose magnetization direction is fixed; an underlayer formed on the pinning layer; and a data storage layer being a perpendicular magnetic film formed on the underlayer. The data storage layer has: a magnetization free region whose magnetization direction is reversible; and a magnetization fixed region magnetically coupled with the pinning layer through the underlayer. A magnetization direction of the magnetization fixed region is fixed by the magnetic coupling. The underlayer has a magnetic underlayer made of a magnetic material. | 2013-03-28 |
20130075848 | THREE-DIMENSIONAL BORON PARTICLE LOADED THERMAL NEUTRON DETECTOR - Three-dimensional boron particle loaded thermal neutron detectors utilize neutron sensitive conversion materials in the form of nano-powders and micro-sized particles, as opposed to thin films, suspensions, paraffin, etc. More specifically, methods to infiltrate, intersperse and embed the neutron nano-powders to form two-dimensional and/or three-dimensional charge sensitive platforms are specified. The use of nano-powders enables conformal contact with the entire charge-collecting structure regardless of its shape or configuration. | 2013-03-28 |
20130075849 | SOLID STATE IMAGING DEVICE, SOLID STATE IMAGING ELEMENT, PORTABLE INFORMATION TERMINAL DEVICE AND METHOD FOR MANUFACTURING THE SOLID STATE IMAGING ELEMENT - According to one embodiment, a solid state imaging device includes a sensor substrate curved such that an upper face having a plurality of pixels formed is recessed and an imaging lens provided on the upper face side. | 2013-03-28 |
20130075850 | FLIP-CHIP BONDED IMAGER DIE - An image sensor includes an imager die, a circuit board, and an optical layer. The circuit board is flip-chip bonded to the imager die. The optical layer is adhered to the circuit board and includes a first portion configured to refract light differently than a second portion. Both the first portion and the second portion are integrally formed with the optical layer. | 2013-03-28 |
20130075851 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a plurality of pixels arranged in a matrix pattern on a substrate. Each of the pixels includes a photoelectric conversion portion configured to convert incident light to an electric signal, an optical waveguide formed over the photoelectric conversion portion, an interlayer insulating film formed around the optical waveguide, and a color filter formed over the optical waveguide. The optical waveguide is configured so that light intensity distribution of light that has transmitted through the color filter has a single peak in a center of an upper surface of the photoelectric conversion portion. The plurality of pixels include at least two kinds of pixels that include the color filters configured to transmit light of different wavelength bands from each other therethrough. | 2013-03-28 |
20130075852 | Highly-Depleted Laser Doped Semiconductor Volume - A device with increased photo-sensitivity using laser treated semiconductor as detection material is disclosed. In some embodiments, the laser treated semiconductor may be placed between and an n-type and a p-type contact or two Schottky metals. The field within the p-n junction or the Schottky metal junction may aid in depleting the laser treated semiconductor section and may be capable of separating electron hole pairs. Multiple device configurations are presented, including lateral and vertical configurations. | 2013-03-28 |
20130075853 | Stacked Die Package for MEMS Resonator System - A stacked die package for an electromechanical resonator system includes an electromechanical resonator die bonded or fixed to a control IC die for the electromechanical resonator by, for example, a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system (NEMS) resonator. Certain packaging configurations that may include the chip that contains the electromechanical resonator and the control chip include chip-on-lead (COL), chip-on-paddle (COP), and chip-on-tape (COT) packages. The stacked die package may provide small package footprint and/or low package thickness, and low thermal resistance and a robust conductive path between the dice. | 2013-03-28 |
20130075854 | High Voltage ESD Protection Apparatus - An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus. | 2013-03-28 |
20130075855 | Manufacturing methods for accurately aligned and self-balanced superjunction devices - A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers. | 2013-03-28 |
20130075856 | Integrated Circuit Structure and Method of Forming the Same - An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path. | 2013-03-28 |
20130075857 | ISOLATION STRUCTURE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD FOR FABRICATING THE ISOLATION STRUCTURE - An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer. | 2013-03-28 |
20130075858 | SEMICONDUCTOR DEVICE - A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof. | 2013-03-28 |
20130075859 | Semiconductor structure including guard ring - One or more embodiments related to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature. | 2013-03-28 |
20130075860 | METHOD FOR FABRICATING A THREE-DIMENSIONAL INDUCTOR CARRIER WITH METAL CORE AND STRUCTURE THEREOF - A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures. | 2013-03-28 |
20130075861 | Semiconductor structure including guard ring - One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature. | 2013-03-28 |
20130075862 | EMBEDDED CAPACITOR AND METHOD OF FABRICATING THE SAME - Methods are provided for forming a capacitor. In one embodiment, a method comprises providing an insulator material layer over a substrate, etching at least one via in the insulator material layer and depositing a contact material fill in the at least one via to form a first set of contacts. The method further comprises etching the insulator material layer adjacent at least one contact of the first set of contacts to form at least one void, depositing a dielectric material layer over the at least one void and over the first set of contacts and depositing a contact material fill in the at least void to form a second set of contacts. | 2013-03-28 |
20130075863 | ESD Protection Apparatus - An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region. | 2013-03-28 |
20130075864 | SEMICONDUCTOR DEVICE - An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current. | 2013-03-28 |
20130075865 | SEMICONDUCTOR DEVICE - An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current. | 2013-03-28 |
20130075866 | SEMICONDUCTOR DEVICE - A PN junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N− type epitaxial layer and be connected to an anode electrode. An N+ type diffusion layer and a P+ type diffusion layer connected to and surrounding the N+ type diffusion layer are formed in the N− type epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and the P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as the emitter, the N− type epitaxial layer as the base, and the P+ type drawing layer etc as the collector. | 2013-03-28 |
20130075867 | METHOD OF PROCESSING A SURFACE OF GROUP III NITRIDE CRYSTAL AND GROUP III NITRIDE CRYSTAL SUBSTRATE - There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains. | 2013-03-28 |
20130075868 | METHODS OF TRANSFERRING LAYERS OF MATERIAL IN 3D INTEGRATION PROCESSES AND RELATED STRUCTURES AND DEVICES - Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods. | 2013-03-28 |
20130075869 | Chip Comprising a Fill Structure - A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge. | 2013-03-28 |
20130075870 | METHOD FOR PROTECTION OF A LAYER OF A VERTICAL STACK AND CORRESPONDING DEVICE - A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed. | 2013-03-28 |
20130075871 | MULTI-LAYER CHIP OVERLAY TARGET AND MEASUREMENT - A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of target rectangle disposable within the target region. | 2013-03-28 |
20130075872 | Metal Pad Structures in Dies - A die includes a substrate, a metal pad over the substrate, and a passivation layer that has a portion over the metal pad. A dummy pattern is disposed adjacent to the metal pad. The dummy pattern is level with, and is formed of a same material as, the metal pad. The dummy pattern forms at least a partial ring surrounding at least a third of the metal pad. | 2013-03-28 |
20130075873 | GLASS COMPOSITION FOR PROTECTING SEMICONDUCTOR JUNCTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a glass composition for protecting a semiconductor junction which contains at least SiO | 2013-03-28 |
20130075874 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure. | 2013-03-28 |
20130075875 | SILICON NITRIDE FILM OF SEMICONDUCTOR ELEMENT, AND METHOD AND APPARATUS FOR PRODUCING SILICON NITRIDE FILM - Disclosed are: a silicon nitride film of a semiconductor element, which is formed by applying a bias power and appropriately controls hydrogen leaving from the silicon nitride film; and a method and apparatus for producing a silicon nitride film. Specifically disclosed is a silicon nitride film which is formed on a substrate ( | 2013-03-28 |
20130075876 | SEALED POROUS MATERIALS, METHODS FOR MAKING THEM, AND SEMICONDUCTOR DEVICES COMPRISING THEM - A method for at least partially sealing a porous material is provided, comprising forming a sealing layer onto the porous material by applying a sealing compound comprising oligomers wherein the oligomers are formed by ageing a precursor solution comprising cyclic carbon bridged organosilica and/or bridged organosilanes. The method is especially designed for low k dielectric porous materials to be incorporated into semiconductor devices. | 2013-03-28 |
20130075877 | SEMICONDUCTOR DEVICE HAVING LATERAL ELEMENT - A semiconductor device with a lateral element includes a semiconductor substrate, first and second electrodes on the substrate, and a resistive field plate extending from the first electrode to the second electrode. The lateral element passes a current between the first and second electrodes. A voltage applied to the second electrode is less than a voltage applied to the first electrode. The resistive field plate has a first end portion and a second end portion opposite to the first end portion. The second end portion is located closer to the second electrode than the first end portion. An impurity concentration in the second end portion is equal to or greater than 1×10 | 2013-03-28 |
20130075878 | COAXIAL POWER MODULE - A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure. | 2013-03-28 |
20130075879 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MAKING SAME - A semiconductor chip package includes a substrate unit, a chip, metal members, a molding compound and a shielding layer. The chip is assembled on and electrically connected with the substrate unit. The substrate unit includes conductive seat portions surrounding the chip, and defines through holes respectively coated by conducting films to ground the corresponding seat portions. The metal members are assembled on the seat portions, surround the chip, and are grounded through the conducting films. The molding compound encapsulates the chip and the metal members, with part of each metal member exposed out of the molding compound. The shielding layer covers the molding compound and the parts of each metal member exposed out of the molding compound to shield the chip from electromagnetic radiation. | 2013-03-28 |
20130075880 | PACKAGING STRUCTURE - A packaging structure comprises a first leadframe, a second leadframe, two grounding pins, two first pins, a plurality of first wires, a plurality of second wires, and a package body. The second leadframe is coupled to the drains of a first power transistor and a second power transistor. The two grounding pins are adjacent together and coupled to the first leadframe. The two first pins are coupled to the source of the second power transistor. The two first pins are connected together through a conductive region for increasing capability of loading current. The plurality of first wires is coupled between the source of the second power transistor and the first pin to decrease the internal resistance of the second power transistor. The plurality of second wires is coupled between the first leadframe and the source of the first power transistor to decrease the internal resistance of the first power transistor. | 2013-03-28 |
20130075881 | MEMORY CARD PACKAGE WITH A SMALL SUBSTRATE - Disclosed is a memory card package with a small substrate by using a metal die pad having an opening to substitute the chip-carrying function of a conventional substrate so that substrate dimension can be reduced. A substrate is attached under the metal die pad. A first chip is disposed on the substrate located inside the opening. A second chip is disposed on the metal die pad without covering the opening. A card-like encapsulant encapsulates the metal die pad, the top surface of the substrate, the first chip, and the second chip. The dimension of the substrate is smaller than the dimension of the encapsulant. The substrate has a lumpy sidewall encapsulated by the encapsulant so that the bottom surface of the substrate is coplanar with a bottom side of the encapsulant to increase the adhesion between the substrate and the encapsulant. | 2013-03-28 |
20130075882 | PACKAGE STRUCTURE - A package structure including a first leadframe, a second leadframe, a power pin, a ground pin, a first pin, several first wires, several second wires, and a package body is disclosed. The first leadframe is used for electrically coupling to the drains of a first power transistor and the second power transistor. The ground pin is electrically coupled to the first leadframe. The first pin is connected with the first leadframe through a conductive region used for increasing the amount of current which can be loaded by the first pin. The first wires are used for electrically coupling between the first leadframe and the source of the second power transistor, for reducing the internal resistance of the second power transistor. The second wires are used for electrically coupling between the ground pin and the source of the first power transistor, for reducing the internal resistance of the first power transistor. | 2013-03-28 |
20130075883 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral contact layer surrounding the peripheral lead with a non-horizontal side exposed from the peripheral contact layer; forming an inner lead and a paddle non-planar with the peripheral lead; mounting an integrated circuit to the paddle; and forming an encapsulation covering the integrated circuit and exposing the inner lead, the paddle, and the non-horizontal side. | 2013-03-28 |
20130075884 | SEMICONDUCTOR PACKAGE WITH HIGH-SIDE AND LOW-SIDE MOSFETS AND MANUFACTURING METHOD - A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction. | 2013-03-28 |
20130075885 | LEAD FRAME AND PACKAGING METHOD - There is provided a lead frame and a packaging method. The lead frame comprises a first plurality of die pads, a second plurality of leads extending from the first plurality of die pads, and a third plurality of tie elements, each of which connects one of the first plurality of die pads to another. | 2013-03-28 |
20130075886 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with: a semiconductor element; and a connecting conductor that electrically connects at least one of an input terminal and an output terminal of the semiconductor element to a connection terminal of an electronic device. In this semiconductor device, the connecting conductor is a block structure. | 2013-03-28 |
20130075887 | STACKED SEMICONDUCTOR DEVICE - Provided is a stacked semiconductor device ( | 2013-03-28 |
20130075888 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, which includes: a micro electro mechanical system (MEMS) chip; a cap provided on the MEMS chip; an electronic element provided on the cap including a plurality of first conductive pads and second conductive pads; a plurality of first conductive elements electrically connected to the first conductive pads and the MEMS chip; a plurality of second conductive elements formed on the second conductive pads, respectively; and an encapsulant formed on the MEMS chip covering the cap, the electronic element, the first conductive elements and the second conductive elements, with the second conductive elements being exposed from the encapsulant. Thus, the size of the semiconductor package is reduced. A method of fabricating the semiconductor package is also disclosed. | 2013-03-28 |
20130075889 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a device mounting structure over a bottom substrate; mounting a heat spreader having an opening formed by a single integral structure with a dam and a flange, the dam having a dam height greater than a flange height of the flange; and forming a package encapsulation over the device mounting structure and the bottom substrate with the device mounting structure exposed within the opening. | 2013-03-28 |
20130075890 | INTEGRATED CIRCUIT AND METHOD OF MAKING - Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via. | 2013-03-28 |
20130075891 | FLIP CHIP TYPE FULL WAVE RECTIFICATION SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - This invention reveals a flip-chip type full-wave rectification semiconductor device which includes at least a PNNP type and/or NPPN type flip-chip, and a sheet stuff or substrate including a plurality pins, and which is characterized in that: all the soldering points (bumps) of the PNNP type and/or the NPPN type flip-chip are on an identical surface, this can make easy connecting of the pins with the bumps of the flip-chips by soldering in pursuance of circuit arrangement of the full-wave rectification device, and complete manufacturing product after the steps of shaping/packing and cutting; such product has a function of making full-wave rectifying, and can simplify the manufacturing process, reduce the manufacturing cost, and get an effect of reducing the size of the product with better heat dissipation, being different from traditional full wave rectification semiconductor devices composed of two/four grains. | 2013-03-28 |
20130075892 | Method for Three Dimensional Integrated Circuit Fabrication - A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages. | 2013-03-28 |
20130075893 | Synchronous Buck Converter Having Coplanar Array of Contact Bumps of Equal Volume - A packaged power supply module ( | 2013-03-28 |
20130075894 | INTEGRATED CIRCUIT AND METHOD OF MAKING - Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends from the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. A conductive adhesive connects the conductive stud to the first side of the conductive layer. | 2013-03-28 |
20130075895 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In one embodiment, a semiconductor device includes a chip stacked body disposed on an interposer substrate and an interface chip mounted on the chip stacked body. The chip stacked body has plural semiconductor chips, and is electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor chips and bump electrodes. The interface chip is electrically connected to the interposer substrate via a rewiring layer formed on a surface of an uppermost semiconductor chip in the stacking order or through electrodes provided in the interface chip. | 2013-03-28 |
20130075896 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core. | 2013-03-28 |
20130075897 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor integrated circuit device for driving an LCD, COG chip packaging is performed. To achieve this, an elongate and relatively thick gold bump electrode is formed over an aluminum-based pad having a relatively small area. In a wafer probe test performed after formation of the gold bump electrode, a cantilever type probe needle having gold as a main component and having an almost perpendicularly bent tip portion is used. The diameter of this probe needle in the vicinity of its tip is usually almost the same as the width of the gold bump electrode. This makes it difficult to perform the wafer probe test stably. To counteract this, a plurality of bump electrode rows for outputting a display device drive signal are formed such that the width of inner bump electrodes is made greater than the width of outer bump electrodes. | 2013-03-28 |
20130075898 | SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die. | 2013-03-28 |
20130075899 | Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant - A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts. | 2013-03-28 |
20130075900 | Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding - A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate. | 2013-03-28 |
20130075901 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad | 2013-03-28 |
20130075902 | Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant - A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts. | 2013-03-28 |
20130075903 | Semiconductor Device and Method of Forming Different Height Conductive Pillars to Electrically Interconnect Stacked Laterally Offset Semiconductor Die - A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures. | 2013-03-28 |
20130075904 | COPLANER WAVEGUIDE TRANSITION - A coplanar waveguide transition includes a substrate, a first coplanar waveguide on a first side of the substrate, and a second coplanar waveguide on a second side of the substrate. The coplanar waveguide transition includes a first, a second, and a third via through the substrate electrically coupling the first coplanar waveguide to the second coplanar waveguide. The coplanar waveguide transition includes voids through the substrate between the first, second, and third vias and edges of the first coplanar waveguide and edges of the second coplanar waveguide. | 2013-03-28 |
20130075905 | Semiconductor Chips and Semiconductor Packages and Methods of Fabricating the Same - A semiconductor device includes a substrate and a through via penetrating the substrate. The through via has a protruding portion at a first end thereof extending out from a first surface of the substrate and a second end of the via contacting an interconnection line proximate a second, opposite, end of the substrate. A wetting layer is positioned between the via and the substrate and extends over the protruding portion of the via. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer. | 2013-03-28 |
20130075906 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region. | 2013-03-28 |
20130075907 | Interconnection Between Integrated Circuit and Package - In order to achieve finer bump interconnect pitch for integrated circuit packaging, while relieving pressure-induced delamination of upper layer dielectric films, the under bump metallurgy of the present invention provides a pressure distribution pedestal upon which a narrower copper pillar is disposed. A solder mini-bump is disposed on the upper exposed portion of the copper pillar, wherein the solder is softer than the copper pillar. The radius of the copper pillars is selected such that lateral deformation of the solder mini-bumps during final assembly does not form undesired conductive bridges between adjacent pillars. | 2013-03-28 |
20130075908 | SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY - An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed. | 2013-03-28 |
20130075909 | SEMICONDUCTOR DEVICE INCLUDING METAL-CONTAINING CONDUCTIVE LINE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction. | 2013-03-28 |
20130075910 | MODULATED DEPOSITION PROCESS FOR STRESS CONTROL IN THICK TiN FILMS - A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N | 2013-03-28 |
20130075911 | Semiconductor Device Having Electrode/Film Opening Edge Spacing Smaller Than Bonding Pad/Electrode Edge Spacing - A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the bonding pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the bonding pad. | 2013-03-28 |
20130075912 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor device includes: forming a silicon oxide film on a semiconductor substrate; forming a via in the silicon oxide film; forming a contact layer inside the via; forming a silicon layer on the contact layer; and forming a tungsten film embedded in the via by making a tungsten-containing gas react with the silicon layer. | 2013-03-28 |
20130075913 | STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION - A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers. | 2013-03-28 |
20130075914 | SEMICONDUCTOR ELEMENT - There is provided a semiconductor element including a semiconductor layer, a translucent electrode which is formed on the semiconductor layer, and a pad electrode which is formed on the translucent electrode, wherein the translucent electrode includes a recessed part on which the pad electrode is mounted, and wherein a thickness of a bottom surface of the recessed part of the translucent electrode is more than 0% of and equal to or less than 70% of a thickness of a part of the translucent electrode other than the recessed part. | 2013-03-28 |
20130075915 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate. | 2013-03-28 |
20130075916 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL WIRE CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation. | 2013-03-28 |
20130075917 | Multi-Chip and Multi-Substrate Reconstitution Based Packaging - Embodiments for multi-chip and multi-substrate reconstitution based packaging are provided. Example packages are formed using substrates from a reconstitution. substrate panel or strip. The reconstitution substrate panel or strip may include known good substrates of same or different material types and/or same of different layer counts and sizes. As such, different combinations of reconstitution substrates and chips can be used within the same package, thereby allowing substrate customization according to semiconductor chip block(s) and types contained in the package. | 2013-03-28 |
20130075918 | SHIFT REGISTER MEMORY - In one embodiment, a shift register memory includes a substrate, and a channel layer provided on the substrate, and having a helical shape rotating around an axis which is perpendicular to a surface of the substrate. The memory further includes at least three control electrodes provided on the substrate, extending in a direction parallel to the axis, and to be used to transfer charges in the channel layer. | 2013-03-28 |
20130075919 | Semiconductor Device and Method of Forming FO-WLCSP Having Conductive Layers and Conductive Vias Separated by Polymer Layers - A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure. | 2013-03-28 |
20130075920 | Multilayer Connection Structure and Making Method - An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers. | 2013-03-28 |
20130075921 | Forming Packages Having Polymer-Based Substrates - A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via. | 2013-03-28 |
20130075922 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SUBSTRATE EMBEDDED DUMMY-DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle. | 2013-03-28 |
20130075923 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation. | 2013-03-28 |
20130075924 | Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP - A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant. | 2013-03-28 |
20130075925 | SEMICONDUCTOR DEVICE - A semiconductor device is free from degradation of characteristics attributable to a manufacturing process thereof and its characteristics are hardly affected by changes in electric potentials of bonding pads. The semiconductor device | 2013-03-28 |
20130075926 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector. | 2013-03-28 |
20130075927 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed. | 2013-03-28 |
20130075928 | INTEGRATED CIRCUIT AND METHOD OF MAKING - Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via. | 2013-03-28 |
20130075929 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film. | 2013-03-28 |
20130075930 | SEMICONDUCTOR SUBSTRATE, ELETRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor substrate includes a vertical conductor and an insulating layer. The vertical conductor includes a metal/alloy component of a nanocomposite crystal structure and is filled in a vertical hole formed in the semiconductor substrate along its thickness direction. The insulating layer is formed around the vertical conductor in a ring shape and includes nm-sized silica particles and a nanocrystal or nanoamorphous silica filling up a space between the silica particles to provide a nanocomposite structure along with the silica particles. | 2013-03-28 |
20130075931 | BOND PAD STRUCTURE - A bond pad structure for an integrated circuit chip package is disclosed. The bond pad structure includes a top metal layer, a patterned metal layer and an interconnection structure. The patterned metal layer is formed below the top metal layer and includes an annular metal layer and a plurality of metal blocks evenly arranged at a central area of the annular metal layer; the patterned metal layer is connected to the top metal layer through both the annular metal layer and the metal blocks. The interconnection structure is formed below the patterned metal layer and is connected to patterned metal layer only through the annular metal layer. By using the above structure, active or passive devices can be disposed under the bond pad structure and will not be damaged by package stress. An integrated circuit employing the above bond pad structure is also disclosed. | 2013-03-28 |
20130075932 | Power Semiconductor Module with Integrated Thick-Film Printed Circuit Board - A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 μm. | 2013-03-28 |
20130075933 | PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant. | 2013-03-28 |
20130075934 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a first wiring provided in a first wiring layer along a first direction, a second wiring provided in a second wiring layer along a second direction orthogonal to the first direction, the second wiring intersecting with the first wiring at a first intersect portion, and a third wiring provided close to and along the second wiring in the second wiring layer, the third wiring intersecting with the first wiring at a second intersect portion, wherein a distance between the second wiring in the first intersection portion and the third wiring in the second intersection portion is narrower than a distance between the second wiring another than the first intersection portion and the third wiring another than the second intersection portion. | 2013-03-28 |
20130075935 | COMPOSITE LAYERED CHIP PACKAGE - A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other. | 2013-03-28 |
20130075936 | Semiconductor Device and Method of Forming Interconnect Substration for FO-WLCSP - A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement. | 2013-03-28 |
20130075937 | Apparatus and Methods for Molding Die on Wafer Interposers - Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits. | 2013-03-28 |
20130075938 | PHOTOLITHOGRAPHY ALIGNMENT MARK, MASK AND SEMICONDUCTOR WAFER CONTAINING THE SAME MARK - A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer. | 2013-03-28 |