13th week of 2014 patent applcation highlights part 22 |
Patent application number | Title | Published |
20140084907 | ELECTROMAGNETIC INDUCTION POSITION DETECTION SENSOR - An electromagnetic induction position detection sensor includes a plurality of loop coils, each being an N-turn loop coil formed by winding a conductor N times (N is an integer equal to or greater than 2), and each coil turn having long side portions that are separated by a predetermined width and that are parallel to each other. The loop coils are arranged at predetermined intervals in a predetermined direction intersecting the long side portions of the loop coils. The width of at least one of the N turns of the Mth loop coil from the edge portion of the sensor in the predetermined direction (M is an integer equal to or greater than 2) is larger than the predetermined width, with the long side portion of this turn of the Mth loop coil arranged more outward than the long side portions of the other turns of the Mth loop coil. | 2014-03-27 |
20140084908 | POSITION ENCODER AND ASSOCIATED PEDAL UNIT - A position encoder includes a sensor unit and an encoder unit configured to follow a motion of a lever by means of a pusher so as to enable the sensor unit to capture said motion. The encoder unit and the sensor unit include separate housings connected to each other. The connection between the housings of the encoder unit and the sensor unit is implemented by means of a hollow riveted connection with at least one fastening element configured to be guided into the hollow space thereof. | 2014-03-27 |
20140084909 | BLOCK MADE OF A BUILDING MATERIAL - A building structure includes a block of building material and a magnetic circuit buried in the block of building material. The structure also includes a plurality of sensing devices buried in the block of building material. Each sensing device may include a contactless power supplying circuit magnetically coupled with the magnetic circuit to generate a supply voltage when the magnetic circuit is subject to a variable magnetic field. | 2014-03-27 |
20140084910 | SURFACE PROPERTY INSPECTION DEVICE AND SURFACE PROPERTY INSPECTION METHOD - To provide a surface property inspection device and surface property inspection method with which the surface treatment condition of treated material such as steel subjected to such surface treatments as shot-peening treatment or heat treatment, nitriding, and the like can be non-destructively and precisely inspected, and which offers a high degree of general purpose application. A surface property inspection device | 2014-03-27 |
20140084911 | HALL SENSORS AND SENSING METHODS - Embodiments relate to multi-terminal sensor devices and operating methods thereof that can reduce or eliminate offset error. In embodiments, sensor devices can comprise three or fewer terminals, and multiple such sensor devices can be combined. The sensor devices can comprise Hall sensor devices, such as vertical Hall devices, or other sensor devices in embodiments. Operating modes can be implemented for the multi-terminal sensor devices which offer improvements over conventional spinning current techniques, including reduced residual offset. | 2014-03-27 |
20140084912 | HALL SENSOR EXCITATION SYSTEM - A Hall plate excitation system provides reduced offset and temperature dependence. The Hall plate excitation system includes a current source, a switching network, and a controller. The current source is configured to provide an excitation current to a Hall plate. The switching network is configured to switchably connect the current source to each of a plurality of terminals of the Hall plate. The controller is configured to adjust the excitation current no more than once during each spinning cycle; and to sequentially switch the excitation current to each of the plurality of terminals of the Hall plate during each spinning cycle. | 2014-03-27 |
20140084913 | LOW-NOISE MAGNETIC SENSORS - Magnetic sensors are disclosed, as well as methods for fabricating and using the same. In some embodiments, an EMR effect sensor includes a semiconductor layer. In some embodiments, the EMR effect sensor may include a conductive layer substantially coupled to the semiconductor layer. In some embodiments, the EMR effect sensor may include a voltage lead coupled to the conductive layer. In some embodiments, the voltage lead may be configured to provide a voltage for measurement by a voltage measurement circuit. In some embodiments, the EMR effect sensor may include a second voltage lead coupled to the semiconductor layer. In some embodiments, the second voltage lead may be configured to provide a voltage for measurement by a voltage measurement circuit. Embodiments of a Hall effect sensor having the same or similar structure are also disclosed. | 2014-03-27 |
20140084914 | CURRENT DETECTION DEVICE - In a current detection device for detecting current in a busbar, a reduction in device size may be realized by employing a small magnetic core. The prevention or reduction of excessive heat generation by the busbar, the facilitation of the attachment task, and a reduction in the amount of space required for the attachment task may also be realized. The folded-back busbar is U-shaped with a bar-shaped penetration portion that passes through a hole portion of a magnetic core, two bar-shaped extension portions, and two flat plate-shaped penetration portions. The width of each terminal portion is larger than the widths of the penetration portion and the extension portions. An insulating casing supports the magnetic core, a Hall element, and the folded-back busbar in a fixed positional relationship, with the two terminal portions being exposed to the outside. | 2014-03-27 |
20140084915 | NMR LOGGING APPARATUS - Technologies including NMR logging apparatus and methods are disclosed. Example NMR logging apparatus may include surface instrumentation and one or more downhole probes configured to fit within an earth borehole. The surface instrumentation may comprise a power amplifier, which may be coupled to the downhole probes via one or more transmission lines, and a controller configured to cause the power amplifier to generate a NMR activating pulse or sequence of pulses. Impedance matching means may be configured to match an output impedance of the power amplifier through a transmission line to a load impedance of a downhole probe. Methods may include deploying the various elements of disclosed NMR logging apparatus and using the apparatus to perform NMR measurements. | 2014-03-27 |
20140084916 | MAGNETIC RESONANCE PHASE CONTRAST ANGIOGRAPHY WITH ROTATING CODING GRADIENTS - In a method and magnetic resonance (MR) system to generate an MR phase contrast angiography image of an examination subject, velocity-dependent phase information is impressed on moving spins in the examination subject by switching additional bipolar coding gradients that are in addition to the basic phase coding and readout gradients. For the creation of the MR phase contrast angiography images, the MR signals of the examination subject are read out in raw data space with a non-Cartesian acquisition pattern during a readout gradient. The additional bipolar coding gradients switched such that they proceed along a coordinate system that corresponds to the non-Cartesian acquisition pattern, and such that a coordinate axis of this coordinate system proceed along the readout gradient. | 2014-03-27 |
20140084917 | MRI Scanner - A magnetic resonance imaging (MRI) scanner includes a control device, a gradient coil for generating a gradient field, a gradient coil connector for connecting the gradient coil to the control device, and a temperature sensor. The temperature sensor is configured and disposed to detect a temperature of the gradient coil connector. | 2014-03-27 |
20140084918 | MAGNETIC RESONANCE IMAGING APPARATUS AND FLIP ANGLE DETERMINATION METHOD - In order to maximize the SNR of an image in consideration of signal correction in a multi-echo sequence, flip angles of a plurality of refocus high frequency magnetic field pulses are determined in a multi-echo imaging sequence. Using an index that reflects the SNR of an image after signal correction of a plurality of acquired echo signals, a flip angle at which the SNR of the image becomes a maximum is determined by repeatedly calculating the index by changing information specifying the flip angle of each refocus RF pulse according to an optimization method set in advance. | 2014-03-27 |
20140084919 | METHOD FOR MAGNETIC RESONANCE IMAGING USING RADIAL CONES K-SPACE TRAJECTORIES - A method for magnetic resonance imaging (MRI) using a radial cone k-space trajectory is provided. The radial cone k-space trajectory is defined by the application of a radial magnetic field gradient and one or more oscillating magnetic field gradients. The amplitude of the radial magnetic field gradient increases with time before decreasing with time. While the amplitude of the radial magnetic field gradient is decreasing, the one or more oscillating magnetic field gradients are applied. As a result, the radial cone k-space trajectory is one that is oriented along an axis and that extends outward from an origin along a substantially radial trajectory before extending outward from the origin while circumscribing a conical volume having a radius that increases nonlinearly with distance from the origin. | 2014-03-27 |
20140084920 | IMAGING THE TEETH BY MEANS OF MAGNETIC RESONANCE TECHNOLOGY WITH NON-UNIQUE GRADIENTS - A gradient system according to the invention generates three superimposed gradient fields of which at least one of the three gradient fields is not unique in space (i.e. not bijective) and at least one of the three gradient has areas of the same field strength, which extend in parallel or orthogonally to a approximately U-shaped center plane of the teeth of one jaw of a patient. | 2014-03-27 |
20140084921 | MAGNETIC RESONANCE IMAGING METHOD AND APPARATUS - In a method and apparatus for automatic magnetic resonance imaging of a patient, an MR overall image is composed from several MR partial images. An MR overview image is received by a process that determines several scanning ranges based on the MR overview image. The MR scanning ranges are characterized by a length along a first direction. For all MR scanning ranges: the length along the first direction is set equal to the length of the longest MR scanning range in the first direction. | 2014-03-27 |
20140084922 | METHOD AND APPARATUS FOR MAGNETIC RESONANCE IMAGING - In a method and apparatus for magnetic resonance imaging, a flip angle and/or inversion time of a spectrum suppression pulse is calculated according to a steady state condition of a longitudinal magnetization component of a spectrum composition suppressed by the spectrum suppression pulse and a zero crossing point condition of the longitudinal magnetization component. Raw magnetic resonance image data are acquired by applying a magnetic resonance imaging sequence that includes the spectrum suppression pulse provided with the flip angle and/or the inversion time. | 2014-03-27 |
20140084923 | MAGNETIC RESONANCE METHOD, APPARATUS AND RADIOFREQUENCY COIL FOR ACQUIRING MAGNETIC RESONANCE DATA OF AT LEAST ONE TOOTH - In a magnetic resonance method and apparatus for the acquisition of measurement data of at least one tooth of an examination subject, a pulse sequence is employed that has an echo time TE of less than 0.5 milliseconds, and spatial coding of the acquired measurement data takes place in only two spatial directions. Projection image data are reconstructed from the acquired measurement data. A coil for a magnetic resonance tomography system, which coil is dedicated to dental imaging, has at least one coil element, and each coil element of the coil has an individual acquisition volume that encompasses at least one tooth. | 2014-03-27 |
20140084924 | MAGNETIC RESONANCE METHOD AND APPARATUS FOR CORRECTION OF MAGNETIC RESONANCE DATA - In a method and apparatus to acquire correction data in connection with pulse sequences to acquire measurement data whose echo times—the duration between excitation and measurement data acquisition of the pulse sequences—are less than 500 microseconds, the pulse sequences acquire measurement data by repetition of a pulse sequence scheme, wherein different gradients for spatial coding are switched in each repetition, and correction data are acquired every n repetitions in a time window in which no gradients are switched, wherein n is a predetermined natural number. The method and apparatus enable correction of measurement data with which solid substances can be depicted without the hardware being used needing to be adapted and without external sensors being necessary. | 2014-03-27 |
20140084925 | System and method for prepolarizing magnetic resonance- or relaxation-based measurements - The invention relates to a prepolarizing magnetic resonance- or relaxation-based measurement system, comprising a prepolarizing coil for producing a prepolarizing field at the target zone, means for pulsing the prepolarizing field according to a first pulsing scheme, and means for measuring magnetization of a target placed in the target zone. According to the invention, the system further comprises a shielding coil for producing a shielding field and means for pulsing the shielding field according to a second pulsing scheme, whereby the shielding coil and the second pulsing scheme are arranged to reduce the formation of unwanted transient fields caused by the coupling of the prepolarizing coil to conducting or magnetic structures in the surroundings of the system. The invention also relates to a corresponding method of measurement and a process of designing the pulsing schemes for the system or process. By means of the invention, the formation of unwanted eddy currents, for example, in the surroundings of the measurement system, can be reduced. | 2014-03-27 |
20140084926 | CORRECTING THE STATIC MAGNETIC FIELD OF AN MRI RADIOTHERAPY APPARATUS - A method of correcting a magnetic field of an MRI radiotherapy apparatus ( | 2014-03-27 |
20140084927 | SURFACE-BASED NMR MEASUREMENT - Technologies applicable to surface-based NMR measurement are disclosed. A surface probe is positionable at or above a surface of the Earth and adapted to make NMR measurements of shallow or very shallow subsurface volumes. NMR spectrometer components connected to the surface probe are configured to control electromagnetic pulses produced by the surface probe and to record resulting detected NMR signals from the subsurface volume. | 2014-03-27 |
20140084928 | NMR measuring configuration with temperature control device for a sample vial - An NMR measuring configuration has a temperature control device for a sample vial ( | 2014-03-27 |
20140084929 | MAGNETIC RESONANCE IMAGING (MRI) APPARATUS AND MANUFACTURING METHOD THEREOF - A magnetic resonance imaging (MRI) method and apparatus in which conductors are installed in the space between a static coil unit and a gradient coil unit to eliminate asymmetry of eddy current induced in the static coil unit. The structure permits a symmetrical distribution of eddy current when the concentric arrangement of the static coil unit and gradient coil unit has deviated. The MRI apparatus includes: a static coil unit configured to form a static field in a subject; a gradient coil unit configured to form a gradient field in the static field; and one or more conductors installed in the space between the static coil unit and the gradient coil unit, and configured to symmetrically distribute eddy current induced in the static coil unit. | 2014-03-27 |
20140084930 | MONITORING THE DIPOLE MOMENT VECTOR OF AN AIRBORNE ELECTROMAGNETIC SURVEY SYSTEM - An airborne electromagnetic survey system that monitors the dipole moment. A TDEM system includes a flexible transmitter loop and a receiver having three sensors with mutually perpendicular sensitive axes. In flight, mechanical and aerodynamic forces cause the transmitter loop to tilt and flex, which affects the direction and magnitude of the primary field dipole moment. The processing system measures the sign and amplitude of the primary field sensed by the receiver in each of its sensitive axes and calculates a vector which represents the orientation of the primary field in the receiver frame of reference at the receiver location. Using this vector, the processing system determines the orientation of the primary field dipole moment. | 2014-03-27 |
20140084931 | DETECTION APPARATUS FOR LIGHT-EMITTING DIODE CHIPS - A detection apparatus for light-emitting diode chips comprises a transparent chuck with the light-concentration capability, a probing device and a light-sensing device. The transparent chuck comprises a light-incident plane and a light-emitting plane. The light-incident plane is used to bear a plurality of light-emitting diode chips under detection. The probing device comprises two probe pins and a power supply. The two ends of each probe pin is electrically connected to one of the light-emitting diode chips and the power supply, respectively, to make the light-emitting diode chip emit a plurality of light beams. The light beams penetrate through the transparent chuck by emitting into the incident plane of the transparent chuck. The light-sensing device is disposed on one side of the light-emitting plane of the transparent chuck to receive the light beams which penetrate through the transparent chuck. | 2014-03-27 |
20140084932 | SYSTEM AND METHODS FOR EXTRACTION OF THRESHOLD AND MOBILITY PARAMETERS IN AMOLED DISPLAYS - A system reads a desired circuit parameter from a pixel circuit that includes a light emitting device, a drive device to provide a programmable drive current to the light emitting device, a programming input, and a storage device to store a programming signal. One embodiment of the extraction system turns off the drive device and supplies a predetermined voltage from an external source to the light emitting device, discharges the light emitting device until the light emitting device turns off, and then reads the voltage on the light emitting device while that device is turned off. The voltages on the light emitting devices in a plurality of pixel circuits may be read via the same external line, at different times. | 2014-03-27 |
20140084933 | ISOLATION RESISTANCE MEASURING APPARATUS HAVING FAULT SELF-DIAGNOSING FUNCTION AND SELF-DIAGNOSING METHOD USING THE SAME - Disclosed is an isolation resistance measuring apparatus having a fault self-diagnosing function. The isolation resistance measuring apparatus having a fault self-diagnosing function forms a diagnosis circuit by means of a first isolation resistance measuring unit and a second isolation resistance measuring unit respectively connected to a cathode terminal and an anode terminal of a battery, and includes a control unit for determining whether a fault arises at the isolation resistance measuring apparatus by using a circuit equation derived from the diagnosis circuit and first and second diagnosis voltages. Therefore, the isolation resistance measuring apparatus may diagnose whether a fault arises at a device which measures isolation resistance of a battery. | 2014-03-27 |
20140084934 | SYSTEM AND METHOD FOR DETERMINING AN ISOLATION RESISTANCE OF A BATTERY PACK DISPOSED ON A VEHICLE CHASSIS - A system for determining an isolation resistance is provided. The system includes a voltage source that applies an output voltage level between first and second electrical terminals of a battery pack. The system further includes a voltage meter that measures a first voltage level between the first electrical terminal and a vehicle chassis, and measures a second voltage level between the first electrical terminal and the vehicle chassis when a resistor is coupled between the first electrical terminal and the vehicle chassis. The voltage meter measures a third voltage level between the second electrical terminal and the vehicle chassis. The system further includes a microprocessor that determines a first isolation resistance value based on the first, second, third voltage levels and the predetermined resistance level. | 2014-03-27 |
20140084935 | DEVICE FOR DETECTING A DEFECT IN INSULATION - An electrical power supply includes DC source outputting Vm and a device that detects insulation defects in the DC source. The device includes input terminals connected to the source's terminals, impedances Z1 and Z2 connected in series between the input terminals, where Z1=Z2=Z and Vm/Imax2014-03-27 | |
20140084936 | Charge Pump Based Over-Sampling ADC for Current Detection - Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory. | 2014-03-27 |
20140084937 | On-Line Monitoring of Stator Insulation in Motors and Generators - Systems and methods are disclosed for on-line monitoring of the condition of the stator insulation of an AC motor or an electric generator. In certain embodiments, the system includes a transformer surrounding each pair of input and output cables associated with a given phase of power provided to the AC motor or generated by the electric generator. In another embodiment, a transformer surrounds the three input cables (for an AC motor) or the three output cables (for an electric generator) that correspond to phases of the AC motor or electric generator. In both embodiments, the transformers generate voltages that may be used to monitor leakage currents associated with the cables. A microcontroller monitors the voltages generated by the transformers and determines the condition of the stator insulation of the AC motor or the electric generator based on the voltages. | 2014-03-27 |
20140084938 | SENSING ELEMENT AND SIGNAL SENSING DEVICE WITH THE SAME - A sensing element suitable for sensing an interference signal radiated by an object under test is provided, including a substrate, a ground plane and a sensing antenna. The ground plane is disposed on a first surface of the substrate. The sensing antenna is disposed on the first surface of the substrate and is located on a first side of the ground plane. The sensing antenna and the ground plane are separated by a preset distance. Besides, the sensing antenna is electrically connected to the ground plane through a coaxial wire and receives the interference signal through the ground plane. | 2014-03-27 |
20140084939 | Condition estimation device and method of generating open circuit voltage characteristic - A condition estimation device includes a voltage measurement circuit, memory, and a controller. The voltage measurement circuit measures an open circuit voltage (OCV) of an electric storage device. The memory is configured to store first information on a correlation between a positive electrode potential and an electric storage capacity and second information on a correlation between a negative electrode potential and an electric storage capacity. The controller is configured to: measure an OCV under charge or discharge; calculate an electric storage capacity of the electric storage device having the OCV equal to a reference voltage; correct at least one of the first information and the second information such that a potential difference at the calculated capacity is equal to the reference voltage; and generate an OCV characteristic based on the first and the second information after the at least one of the first and the second information is corrected. | 2014-03-27 |
20140084940 | APPARATUS AND A METHOD FOR DETECTING FAULTS IN THE DELIVERY OF ELECTRICAL POWER TO ELECTRICAL LOADS - A method of and apparatus for fault detection utilizing a diagnostic procedure by a diagnostic device to detect a short circuit between at least two of a plurality of load electrical connections, the diagnostic procedure comprising applying a test electrical signal to each of the load electrical connections in turn and whilst applying the test electrical signal to a first one of the load electrical connections, detecting whether an electrical output is present, in response, on any other of the load electrical connections, wherein the detecting by the diagnostic device includes applying the test electrical signal to the first one of the load electrical connections in an operational mode of the apparatus when an electrically controlled switch connected to the first one of the load electrical connections is in an off state. | 2014-03-27 |
20140084941 | Display Device and Method for Detecting Line Defects of the Display Device - A display device, which can prevent defects in a drive power transmission line and damage which is caused to a common electrode by such defects, and a method for detecting line defects of the display device are provided. The display device includes a plurality of drive power transmission lines for transmitting drive power to pixels, at least one defect detection line that crosses at least one drive power transmission line, and a defect detector for outputting a defect detection signal to the at least one defect detection line, collecting a feedback signal generated from the defect detection line according to the defect detection signal, and determining whether or not there is a defect in the at least one drive power transmission line based on comparison between the defect detection signal and the feedback signal. | 2014-03-27 |
20140084942 | System and Method for an Arc Fault Detector - Embodiments of the present disclosure include a method of operating an arc fault detection system, an arc fault detection system, and a system. An embodiment is a method of operating an arc fault detection system coupled to a power line, the method including determining one or more arc fault detection windows in power line signals on the power line, the power line signals comprising a communication signal and an alternating current (AC) power signal. The method further includes receiving the power line signals from the power line during the one or more arc fault detection windows, and performing arc fault detection processing on the received power line signals. | 2014-03-27 |
20140084943 | STRAIN MONITORING SYSTEM AND APPARATUS - This application relates to an apparatus and system for sensing strain on a portion of an implant positioned in a living being. In one aspect, the apparatus has at least one sensor assembly that can be mountable thereon a portion of the implant and that has a passive electrical resonant circuit that can be configured to be selectively electromagnetically coupled to an ex-vivo source of RF energy. Each sensor assembly, in response to the electromagnetic coupling, can be configured to generate an output signal characterized by a frequency that is dependent upon urged movement of a portion of the passive electrical resonant circuit and is indicative of strain applied thereon a portion of the respective sensor assembly. | 2014-03-27 |
20140084944 | Coaxial probe comprising terminating resistor - A coaxial probe is for a TDR fill-level measuring instrument, in which probe the inner conductor is connected to the outer conductor via a terminating resistor. The terminating resistor is mounted in a cylindrical recess in the inner conductor and sealed with respect to the measuring environment. In this way, the measurement of the fill level in the region of the probe end can be improved. | 2014-03-27 |
20140084945 | INTERFACE DETECTION - The invention relates to a method for determining a level of a material interface in a tank, by means of a radar level gauge system comprising a transceiver; a probe for guiding a transmitted electromagnetic signal towards the material interface. The probe comprises a first plurality of reference impedance transitions located above the interface at known physical distances from a reference position, and a second plurality of reference impedance transitions located below the interface at known physical distances from the reference position. The method comprising determining electrical distances to the first and second plurality of reference impedance transitions based on a signal reflected by the reference impedance transition, determining, a first and a second approximation function relating the first and second sets of electrical distance values to the physical distances; and determining the level of the material interface based on the first approximation function and the second approximation function. | 2014-03-27 |
20140084946 | System And Method For Wireless Power And Data Transmission In A Rotary Steerable System - Various embodiments for wireless power and data communications transmissions between a cartridge in a rotary steering system and components within a drill collar are disclosed. In a certain embodiment, magnetic fields are used to transfer power and data between the cartridge of a rotary steering system and electronics and/or sensors mounted in the drill collar. A first coil is attached to the pressure housing of the cartridge by a shaft containing wires. The turbine in the pressure housing provides an alternating current to the first coil, which is attached to the shaft. Consequently, the first coil generates an alternating magnetic field that passes through the ferrite surrounding a second coil that is attached by wires to an annular pressure housing that is attached to the drill collar. The alternating magnetic field generates an emf in the second coil, which provides power for electronics and sensors mounted in the drill collar. | 2014-03-27 |
20140084947 | System and Method for Measuring Product Quantity in a Container - A system for measuring product quantity including a container that defines an internal volume, a plurality of products positioned in the internal volume, a first conductor positioned proximate the container, a second conductor positioned proximate the container, the second conductor being spaced a distance from the first conductor, and a capacitance meter electrically coupled to the first and second conductors. | 2014-03-27 |
20140084948 | TEST VEHICLES FOR EVALUATING RESISTANCE OF THIN LAYERS - Provided are test vehicles for evaluating various semiconductor materials. These materials may be used for various integrated circuit components, such as embedded resistors of resistive random access memory cells. Also provided are methods of fabricating and operating these test vehicles. A test vehicle may include two stacks protruding through an insulating body. Bottom ends of these stacks may include n-doped poly-silicon and may be interconnected by a connector. Each stack may include a titanium nitride layer provided over the poly-silicon end, followed by a titanium layer over the titanium nitride layer and a noble metal layer over the titanium layer. The noble metal layer extends to the top surface of the insulating body and forms a contact surface. The titanium layer may be formed in-situ with the noble metal layer to minimize oxidation of the titanium layer, which is used as an adhesion and oxygen getter. | 2014-03-27 |
20140084949 | SURFACE IMPEDANCE SYSTEMS AND METHODS - A surface impedance sensor and method are provided. The surface impedance sensor generally includes first and second electrodes, a driver circuit to drive the electrodes at a plurality of driving frequencies, and a detection circuit to measure the impedance across the first and second electrodes for comparison against a plurality of reference profiles. The method generally includes measuring the localized surface impedance for each of a plurality of driving frequencies to generate a measured profile, and correlating the measured profile with a reference profile. The system and method can verify contact with a particular surface and can be used with a variety of host devices, including for example ultrasound delivery devices. | 2014-03-27 |
20140084950 | CANCELLATION OF SECONDARY REVERSE REFLECTIONS IN A VERY-FAST TRANSMISSION LINE PULSE SYSTEM - An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider. | 2014-03-27 |
20140084951 | METHOD FOR DETECTING A DEVICE THAT GENERATES SPURIOUS SIGNALS IN AN ELECTRICAL NETWORK, AN ELECTRICAL SYSTEM AND AN AIRCRAFT - A method for detecting a device that generates spurious signals in an electrical network, to which several devices and at least one fault detection device are connected, includes the steps of monitoring the electrical network for electrical spurious signals, sequentially deactivating each device for a predetermined time T when an electrical spurious signal has been detected, and checking the electrical network for the disappearance of the respective spurious signal, and signaling as soon as the respective spurious signal has disappeared upon deactivating a respective device. This makes it possible to especially reliably detect a device in an electrical network that couples an undesired spurious signal into the network. | 2014-03-27 |
20140084952 | SYSTEM AND METHOD FOR ANALYZING ELECTRONIC DEVICES HAVING OPPOSING THERMAL COMPONENTS - A system for analyzing electronic devices includes an input station, a transport apparatus, an electric machine interface station, an electric machine interface, a support structure and first and second thermal components. The input station receives a plurality of electronic devices and the transport apparatus transports each of the electronic devices from the input station to the electric machine interface station. The electric machine interface engages the electronic device when the electronic device is at the electric machine interface station, and is disengageable from the electronic device for the electronic device to be transportable by the transport apparatus away from the electric machine interface station. The first and second thermal components are located on opposing sides of the electronic device when the electronic device is at the electric machine interface station to simultaneously transfer heat to or from the electronic device. | 2014-03-27 |
20140084953 | COMPLIANT THERMAL CONTACT DEVICE AND METHOD - Examples of thermal contact devices and methods are shown. Compliant thermal contact devices are shown that include interleaved conducting structures to provide a high thermal conduction contact area. Selected examples include a thermal interface material located at the interleaved interface between the conducting structures. Selected examples also include designs for alternate chip orientations. | 2014-03-27 |
20140084954 | TESTING DEVICE FOR VALIDATING STACKED SEMICONDUCTOR DEVICES - Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. | 2014-03-27 |
20140084955 | FINE PITCH INTERPOSER STRUCTURE - A fine pitch interposer structure includes a Multi-core base substrate and a plurality of buildup laminates. A surface of each Multi-core base substrate has a first circuit layer, and a second circuit layer which is electrically connected to the first circuit layer. The buildup laminates are stacked on the surface of the Multi-core base substrate. Each buildup laminate includes a photosensitive dielectric layer, and a plurality of blind vias with a pre-determined interval therebetween which are correspondingly arranged on each of the plurality of vias formed on the photosensitive dielectric layer. The blind vias are electrically connected to the first circuit layer. At least one blind via of one buildup laminate is superimposed on another blind via of another buildup laminate. | 2014-03-27 |
20140084956 | PROBE HEAD TEST FIXTURE AND METHOD OF USING THE SAME - Various probe testing load board structures and methods of using the same are disclosed. In one aspect, a method of testing a load board of a probe testing system is provided. The method includes electrically engaging a shorting substrate with conductor structures of the load board. The shorting substrate is operable to establish one or more electrical pathways between the tester and at least one electronic component of the load board. An electrical test is performed on the at least one electronic component using the one or more electrical pathways. | 2014-03-27 |
20140084957 | WIRING CHECK DEVICE AND WIRING CHECK SYSTEM - An objective of the present invention is to provide a wiring check device with which it is possible, with respect to finding a risk of deterioration of electromagnetic noise characteristics, to take into account the presence of a plane conductor other than a plane conductor located closest to the wiring. A wiring check device according to the present invention includes: a wiring information acquisition unit which acquires wiring information on a wiring which is included in a printed substrate having a multi-layered structure; a plane conductor detection unit which detects a plurality of plane conductors on multiple layers among the multi-layered structure which include a layer located closest to the wiring; a plane conductor overlap configuration detection unit which detects a plane conductor overlap configuration of a configuration in which the plurality of plane conductors overlap; and a bridge point detection unit which detects a point where the wiring steps over a plane conductor excluded region in the plane conductor overlap configuration on the basis of a wiring-plane conductor overlap configuration of a configuration in which the wiring and the plane conductor overlap configuration are overlapped. | 2014-03-27 |
20140084958 | LOW-VOLTAGE, HIGH-SPEED, CURRENT-MODE LATCH WITH INDUCTOR TAIL AND COMMON-MODE FEEDBACK FOR AMPLITUDE AND CURRENT CONTROL - Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively. | 2014-03-27 |
20140084959 | Analog Majority Vote Circuit - An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter. | 2014-03-27 |
20140084960 | DYNAMIC COMPARATOR WITH EQUALIZATION FUNCTION - The present disclosure provides a dynamic comparator with equalization function including a preamplifier, switched latch and dynamic transconductance circuit. The preamplifier amplifies input signals of the dynamic comparator. The dynamic transconductance circuit is inserted between the preamplifier and the switched latch for operating in a reset mode or a comparison mode. When operating in the reset mode, the dynamic transconductance circuit in conjunction with the switched latch performs voltage equalization of output signals of the switched latch, or when operating in the comparison mode, the dynamic transconductance circuit in conjunction with the switched latch receives the output signals generated by the preamplifier and carries out signal transconductance. The switched latch generates output signals as a comparison result of the dynamic comparator based on the transconductance signals generated by the dynamic transconductance circuit. The present disclosure provides a dynamic comparator that reduces the power consumption and increasing the operating speed. | 2014-03-27 |
20140084961 | Method and Apparatus for Analog Pulse Pile-Up Rejection - A method and apparatus for pulse pile-up rejection are disclosed. The apparatus comprises a delay value application constituent configured to receive a threshold-crossing time value, and provide an adjustable value according to a delay value and the threshold-crossing time value; and a comparison constituent configured to receive a peak-occurrence time value and the adjustable value, compare the peak-occurrence time value with the adjustable value, indicate pulse acceptance if the peak-occurrence time value is less than or equal to the adjustable value, and indicate pulse rejection if the peak-occurrence time value is greater than the adjustable value. | 2014-03-27 |
20140084962 | OUTPUT DRIVER USING LOW VOLTAGE TRANSISTORS - Aspects of the subject technology allow an output driver to be implemented using one or more transistors having an oxide-breakdown voltage below the output voltage swing of the output driver. The output driver can include one or more source followers, where a source follower provides voltage-level shifting of a voltage before the voltage is supplied to a gate of a transistor to prevent a source-to-gate voltage or a gate-to-source voltage of the transistor from exceeding the oxide-breakdown voltage of the transistor. | 2014-03-27 |
20140084963 | PASSIVE CAPTURE ADAPTER CIRCUIT FOR SENSING SIGNALS OF A HIGH-SPEED CIRCUIT - A multi-stage passive capture adapter (PCA) circuit is configured to sense and recover digital signals present on a high-speed serial bus for capture and analysis in external test equipment. A first stage of the PCA circuit includes a differentiator that functions as a high impedance probe that contacts the serial bus to capture an original input signal waveform of the high-speed digital signals. The signal waveform is fed to a dual-slope comparator/driver that includes a plurality of high-speed comparators and drivers. The second stage includes a differential receiver/shaper that converts logic levels of differential receiver outputs to input signals that set and reset a signal restorer whose output signals are fed to a driver of a driver/shaper. The output of the driver is then fed to a shaper network configured to substantially match an output signal of driver/shaper to the input signal waveform sensed from the high-speed serial bus. | 2014-03-27 |
20140084964 | LOAD DRIVER WITH CONSTANT CURRENT VARIABLE STRUCTURE - A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state. | 2014-03-27 |
20140084965 | CLOCK CONTROL DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND CLOCK CONTROL METHOD - A clock control device and method are provided. The clock control device includes a stable time controller which receives an operational condition and generates an expiration counting value based on the operational condition; a stable time counter which receives the expiration counting value and activates a clock gating enable signal after a count value of the stable time counter is equal to the expiration counting value; a clock gating cell which transmits a clock signal after receiving the clock gating enable signal; and an oscillator which generates an oscillator clock signal and transmits the oscillator clock signal to the clock gating cell and the stable time counter. | 2014-03-27 |
20140084966 | DRIVER CIRCUIT OF SCHOTTKY TRANSISTOR - A driver circuit includes an output terminal connected to a gate of a Schottky transistor, a reference transistor formed in the same manner as the Schottky transistor, a resistor connected between a first power source line and a gate of the reference transistor, a voltage generator configured to supply a second node with a voltage equal to or lower than a voltage at a first node between the resistor and the reference transistor, and a switching element configured to transmit the voltage at the second node to the output terminal in response to a signal inputted to an input terminal. | 2014-03-27 |
20140084967 | DRIVE CIRCUIT FOR SWITCHING ELEMENT - A drive circuit is provided for a target switching element and opens/closes a current path by controlling an absolute value of a potential difference between one end of the current path and an opening/closing control terminal. The drive circuit includes an integrated circuit connected to the control terminal. The integrated circuit includes an absolute value control circuit controlling the absolute value of the potential difference when the switching element is in an off-state, a stabilization circuit stabilizing the potential difference at a value for maintaining the switching element in an off-state when the switching element is in an off-state, a selection circuit selecting one of control of the absolute value of the potential difference by the control circuit and stabilization of the potential difference by the stabilization circuit, and an on-state terminal connected to the control circuit and the control terminal. The on-state terminal is connected to the stabilization circuit. | 2014-03-27 |
20140084968 | FREQUENCY SPECIFIC CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS - Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit. | 2014-03-27 |
20140084969 | METHOD FOR SETTING TRANSISTOR OPERATING POINT AND CIRCUIT THEREFOR, METHOD FOR CHANGING SIGNAL COMPONENT VALUE AND ACTIVE-MATRIX LIQUID CRYSTAL DISPLAY DEVICE - A data signal voltage on a signal line is held in a voltage holding capacitor through an n-type MOS transistor switched on by a gate scan voltage, and supplied to an analog amplifier circuit. The analog amplifier circuit is formed of an MOS transistor having a double gate structure, and the operating point thereof is set at an operating range in which dependence of Ids on Vds is substantially nullified. Even when Vds is varied due to a response of liquid crystal, Ids is substantially fixed. Accordingly, the pixel voltage which is substantially proportional to the data signal voltage can be applied to the liquid crystal. | 2014-03-27 |
20140084970 | LOW-POWER ETHERNET TRANSMITTER - An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active. | 2014-03-27 |
20140084971 | FREQUENCY MULTIPLIER APPARATUS AND OPERATING METHOD THEREOF - The present invention provides a frequency multiplier apparatus. The frequency multiplier apparatus includes an injection-locked frequency multiplier and a frequency-to-control signal converter. The injection-locked frequency multiplier outputs an output signal having a first frequency in response to an input signal having a first basic frequency. The frequency-to-control signal converter provides a first control signal to the injection-locked frequency multiplier in response to the input signal. The injection-locked frequency multiplier adjusts the first frequency to a second frequency in response to a change of the first control signal when the first basic frequency is changed to a second basic frequency. | 2014-03-27 |
20140084972 | SEMICONDUCTOR DEVICE - To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits. | 2014-03-27 |
20140084973 | SEMICONDUCTOR DEVICE - A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section. | 2014-03-27 |
20140084974 | PHASE LOCKED LOOP WITH BURN-IN MODE - A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode. | 2014-03-27 |
20140084975 | VOLTAGE TRANSLATION CIRCUIT - A voltage translation circuit ( | 2014-03-27 |
20140084976 | Delay-Locked Loop with Dynamically Biased Charge Pump - A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output. | 2014-03-27 |
20140084977 | Wide Frequency Range Delay Locked Loop - A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power. | 2014-03-27 |
20140084978 | Digitally Controlled Oscillator with Thermometer Sigma Delta Encoded Frequency Control Word - Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal. | 2014-03-27 |
20140084979 | SELF-ADJUSTING DUTY CYCLE TUNER - A duty cycle tuner measures high and low periods of a signal, calculates an actual duty cycle, generates duty control signals based on the actual duty cycle and a desired duty cycle, and adjusts the duty cycle responsive to the duty control signals. The high and low periods are measured using high-speed counters to provide a high count for the high period and a low count for the low period. The actual duty cycle value is then computed from the high and low counts, and compared to the desired duty cycle value to generate increment and decrement signals which may be positive or zero, to increase, decrease or maintain the actual duty cycle. In this manner, even if the high and low counts are subject to variations due to process, temperature or power supply voltage, their ratio is independent of such variations, so the tuner is immune to those effects. | 2014-03-27 |
20140084980 | MEMORY ARRAY PULSE WIDTH CONTROL - A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line. | 2014-03-27 |
20140084981 | CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE - Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps. | 2014-03-27 |
20140084982 | Circuits for Improving Linearity of Metal Oxide Semiconductor (MOS) Transistors - Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate. | 2014-03-27 |
20140084983 | SEMICONDUCTOR DEVICE - The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current. | 2014-03-27 |
20140084984 | LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL FROM OUTPUT POWER DOMAIN AND A METHOD OF CONVERTING A DATA SIGNAL BETWEEN POWER DOMAINS - Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source. | 2014-03-27 |
20140084985 | LEVEL-UP SHIFTER CIRCUIT - A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity. | 2014-03-27 |
20140084986 | DRIVER CIRCUIT - A line driver circuit for a High Definition Multimedia Interface (HDMI) transmitter is disclosed. The line driver circuit includes a pre-driver circuit having a pair of pre-driver differential inputs and a pair of pre-driver differential outputs. A driver circuit having a pair of driver differential inputs and a pair of driver differential outputs is also included. Each of the pair of pre-driver differential outputs is coupled to a respective one of the pair of driver differential inputs. Each of the pair of driver differential outputs is coupled to a respective one of a pair of output terminals. The pre-driver further includes a pair of pre-driver cascode transistors. Each of the pre-driver cascode transistors is arranged between one of the pre-driver differential outputs and a respective one of the output terminals and wherein the driver circuit and the pre-driver circuit are operable to receive a current supplied by a HDMI receiver coupled to the pair of output terminals. | 2014-03-27 |
20140084987 | SQUARING CIRCUIT, INTEGRATED CIRCUIT, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A squaring circuit has current mode triplet metal oxide semiconductor (MOS) devices, including a first MOS device, a second MOS device and a third MOS device each having a source operably coupled to a first current source; and a fourth MOS device, a fifth MOS device and a sixth MOS device each having a source operably coupled to a second current source. The drain of first and fourth MOS device is operably coupled to a first supply, the drain of second and fifth MOS device is operably coupled to a first differential output port and the drain of third and sixth MOS device is operably coupled to a second differential output port. The gate of first, second and sixth MOS device is connected to a first differential input port, and the gate of third, fourth and fifth MOS device is connected to a second differential input port. | 2014-03-27 |
20140084988 | SWITCH ARCHITECTURE AT LOW SUPPLY VOLTAGES - A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage. | 2014-03-27 |
20140084989 | REFERENCE VOLTAGE GENERATING CIRCUIT - A reference voltage generating circuit comprises a pair of variable resistors connected to a pair of bipolar transistors. A differential amplifier amplifies the band gap voltage difference between the bipolar transistors and outputs a reference voltage to an output terminal. An output stage resistor is connected to the output terminal and a resistance dividing circuit. The generating circuit includes temperature compensating circuits that receive tap voltages from resistance dividing circuit and a current proportional to the temperature, then output correction currents. The generating circuit additionally includes a current mirror circuit that outputs a mirror current depending on each correction current. The reference voltage generating circuit thus corrects the temperature dependence of the reference voltage. | 2014-03-27 |
20140084990 | DISPLAY WITH TOUCH SENSING SYSTEM - In one embodiment, a kit for making a touch-sensitive personalized display includes a first medium that is foldable according to score lines to form a cavity. The first medium includes an adhesion surface to receive a personalized second medium, and a back surface opposite the adhesion surface. The second medium includes a personalization surface to receive a user selected-image, and includes a rear surface opposite the personalization surface to adhere to the first medium's adhesion surface. The kit includes a conductive touch sensing system to detect a user touch at the personalization surface and to trigger an action at an electronic device responsive to detection of the touch. | 2014-03-27 |
20140084991 | TOUCH SENSOR CIRCUIT AND TOUCH DISPLAY DEVICE - A touch sensor circuit and a touch device are provided. The touch sensor circuit includes a charging capacitor, a first current supplying unit, a second current supplying unit, and a switch unit. Wherein, the charging capacitor is serially connected between a detecting terminal and a reference voltage. The first current supplying unit is coupled to the detecting terminal, and receives a first bias voltage signal, and generates a first charging current at the detecting terminal according to the first bias voltage signal. A second current supplying unit is coupled to the detecting terminal, and receives a second bias voltage signal, and generates a second charging current at the detecting terminal according to the second bias voltage signal. The second terminal and the third terminal of the switch respectively supply the first and the second bias voltage signal. | 2014-03-27 |
20140084992 | TOUCH PANEL - A touch panel includes a substrate, sensing electrode sets, first pads, second pads, first lines, second lines and connecting conductors. Each of the sensing electrode sets includes a first electrode pattern and a plurality of second electrode patterns disposed beside the first electrode pattern. The plurality of first lines electrically connects the first pads to the first electrode patterns respectively. Each second pad is electrically connected to one of the second electrode patterns through one of the second lines. Each connecting conductor electrically connects one second electrode pattern of one sensing electrode set to one second electrode pattern of another sensing electrode set. The first lines and the second lines do not cross over each other, and the connecting conductors do not cross over each other. | 2014-03-27 |
20140084993 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a substrate; a first circuit portion; and a second circuit portion. The first circuit portion includes: a first and a second switching elements, and a first and a second diodes. The second circuit portion includes a third and a fourth switching elements, and a third and a fourth diodes. The first switching element is juxtaposed with the second switching element in a first direction, and is juxtaposed with the fourth switching element in a second direction. The third switching element is juxtaposed with the fourth switching element in the first direction, and is juxtaposed with the second switching element in the second direction. A voltage is applied to electrodes of the first and third switching elements. A voltage of a polarity opposite the first voltage is applied to electrodes of the second and fourth switching elements. | 2014-03-27 |
20140084994 | Current Limiting Circuitry and Method for Pass Elements and Output Stages - Circuitry ( | 2014-03-27 |
20140084995 | ENVELOPE DETECTOR WITH ENHANCED LINEAR RANGE - An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED. | 2014-03-27 |
20140084996 | METHOD AND APPARATUS FOR CONTROLLING OR MANAGING BANDWIDTH OF A FILTER CIRCUIT WITHIN A SYSTEM HAVING TWO INTEGRATED CIRCUITS - A method and apparatus for an adjustable filter system comprises a first integrated circuit generating a reference value that represents a corner frequency of a filter within the first integrated circuit; sending the reference value that represents the corner frequency of the filter across an interface to a second integrated circuit; receiving, across the interface from the second integrated circuit, a filter adjustment value; and changing the corner frequency of the filter using the filter adjustment value to adjust a passband and a stopband of the filter. The apparatus and method also comprises a second integrated circuit detecting a filter adjustment event, wherein the filter adjustment event comprises receipt of the reference value; calculating the filter adjustment value to change a corner frequency of the filter within a first integrated circuit; and sending the filter adjustment value across the interface to the first integrated circuit. | 2014-03-27 |
20140084997 | TRANSMIT/RECEIVE SWITCH WITH SERIES, DOUBLY-FLOATING DEVICE AND SWITCHED BIAS VOLTAGE - An integrated circuit includes a node coupled between a terminal of the integrated circuit and a transmitter circuit. The integrated circuit includes a switch circuit coupled between the node and a receiver circuit. The switch circuit includes a bias circuit coupled to the node. The bias circuit is configured to provide a first bias voltage to the node in response to an indication of a transmit mode of the terminal. The bias circuit is configured to provide a second bias voltage to the node in response to an indication of a receive mode of the terminal. The switch circuit may include a plurality of n-type devices coupled in series. Each of the plurality of n-type devices may include a triple-well, doubly-floating n-type device. The plurality of n-type devices may include a resistively-biased bulk terminal and a resistively-biased n-well. | 2014-03-27 |
20140084998 | APPARATUS AND METHODS FOR CAPACITIVE LOAD REDUCTION - Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers and an envelope tracking module for generating a supply voltage for the power amplifiers. The power amplifier system further includes a switch and a decoupling capacitor operatively associated with a first power amplifier of the system. The switch is configured to electrically float an end of the decoupling capacitor when the first power amplifier is disabled so as to reduce capacitive loading of the envelope tracker and to operate as a dampening resistor when the power amplifier is enabled so as to improve the stability of the system. | 2014-03-27 |
20140084999 | APPARATUS AND METHOD FOR WIDE COMMON MODE DIFFERENCE - Apparatus and methods reduce increase the common mode range of a difference amplifier. A circuit uses one or more floating powers and one or more floating grounds coupled to an input stage of an amplifier to increase the common mode range of a difference amplifier. The floating power can be configured to select from the greater of the voltage level of one of the differential signals and the system power high source. The floating ground can be configured to select from the lesser of the voltage level of one of the differential signals and the system power low source. | 2014-03-27 |
20140085000 | DOHERTY AMPLIFIER WITH EFFICIENCY OPTIMIZATION - An amplifier comprises a main-amplifier circuit, an auxiliary-amplifier circuit and a signal-generating device. Output terminals of the main-amplifier circuit and of the auxiliary-amplifier circuit are connected according to the Doherty principle. The signal-generating device is configured to generate directly a main-amplifier signal as an input signal of the main-amplifier circuit and an auxiliary-amplifier signal as an input signal of the auxiliary-amplifier circuit. | 2014-03-27 |
20140085001 | LINEAR ROW ARRAY INTEGRATED POWER COMBINER FOR RF POWER AMPLIFIERS - A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers. | 2014-03-27 |
20140085002 | Two Dimensional Quad Integrated Power Combiner for RF Power Amplifiers - A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers. | 2014-03-27 |
20140085003 | REDUCING THE EFFECT OF PARASITIC MISMATCH AT AMPLIFIER INPUTS - A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier. | 2014-03-27 |
20140085004 | System and Method for Determining Location of Submerged Submersible Vehicle - An amplifier for use in a buoyant cable antenna operable to receive signals within a frequency band includes: a first amplifier operable to provide amplified signals based on the received signals; a bandpass filter arranged to pass filtered signals within a first portion of the frequency band, the filtered signals being based on the amplified signals; an attenuator arranged in parallel with said bandpass filter and operable to attenuate signals within a second portion of the frequency band, the attenuated signals being based on the amplified signals; and a second amplifier operable to provide an amplified output including first amplified signals within the first portion of the frequency band and to provide second amplified signals within the second portion of the frequency band. The first amplified signals have a first gain, the second amplified signals have a second gain, and the first gain is more than the second gain. | 2014-03-27 |
20140085005 | CIRCUIT TO PREVENT LOAD-INDUCED NON-LINEARITY IN OPERATIONAL AMPLIFIERS - Apparatus and methods for reducing load-induced non-linearity in amplifiers are provided. In certain implementations, an amplifier includes a current mirror, a buffer circuit, and an output stage. The buffer circuit can have a relatively high current gain and a voltage gain about equal to 1. The buffer circuit can amplify a mirrored current generated by the current mirror and provide the amplified mirrored current to the output stage, thereby helping to balance or equalize currents in the current mirror and avoiding the impact of load-induced offset error. | 2014-03-27 |
20140085006 | Efficient Linear Integrated Power Amplifier Incorporating Low And High Power Operating Modes - A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers. | 2014-03-27 |