13th week of 2009 patent applcation highlights part 42 |
Patent application number | Title | Published |
20090081809 | Monoclonal antibody specific to dentin-derived heparan sulfate - The present invention provides a monoclonal antibody displaying excellent specificity against heparan sulfate saccharide chains for the analysis of heparan sulfate saccharide chains specific to dentin. The invention also provides a method of evaluating reproductive dentin using the monoclonal antibody. The anti-heparan sulfate monoclonal antibody reacts against dentin-derived heparan sulfate and in particular the anti-heparan sulfate monoclonal antibody reacts strongly and specifically with uncalcified predentin regions. In the method of evaluating dentin, the antibody is reacted against an isolated dentin-derived sample and the reaction is used in order to evaluate the development of dentin. | 2009-03-26 |
20090081810 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus has a fluid supply means | 2009-03-26 |
20090081811 | DISTRIBUTED POWER ARRANGEMENTS FOR LOCALIZING POWER DELIVERY - A distributed power arrangement to provide local power delivery in a plasma processing system during substrate processing is provided. The distributed power arrangement includes a set of direct current (DC) power supply units. The distributed power arrangement also includes a plurality of power generators, which is configured to receive power from the set of DC power supply units. Each power generator of the plurality of power generators is coupled to a set of electrical elements, thereby enabling the each power generator of the plurality of power generators to control the local power delivery. | 2009-03-26 |
20090081812 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - The present invention is a production method for a semiconductor device equipped with a conductive film with predetermined film thickness on a sidewall of a concave portion formed in an insulating film, and comprises a step of forming the concave portion in the insulation film formed on a semiconductor substrate. Herein, the concave portion is a generic name of a via-hole and a trench. This production method comprises a step of forming a conductive film with film thickness, which is film thickness of a conductive film to be formed in the concave portion, and which is film thickness, calculated based upon the depth of the concave portion and a projected area of the sidewall of said concave portion when viewing the concave portion from the upper surface, and to be formed over the upper surface of the insulating film where the concave portion is formed. In other words, a film is formed taking the variation of configuration of these based upon a projected area of a via-hole or a trench into consideration. | 2009-03-26 |
20090081813 | Method and Apparatus for Measurement and Control of Photomask to Substrate Alignment - A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction mirror arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light. | 2009-03-26 |
20090081814 | INTEGRATED MANUFACTURING SYSTEM WITH TRANSISTOR DRIVE CURRENT CONTROL - An integrated manufacturing system comprising: providing a substrate; forming a gate over the substrate; measuring a gate length of the gate; forming a first spacer adjacent the gate; measuring a spacer critical dimension of the spacer; and adjusting a dose of an implant based on the gate length and the spacer critical dimension for a source/drain region. | 2009-03-26 |
20090081815 | Method and Apparatus for Spacer-Optimization (S-O) - The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures. | 2009-03-26 |
20090081816 | LIGHT EMITTING DEVICE AND PRODUCTION SYSTEM OF THE SAME - To provide a light emitting device without nonuniformity of luminance, a correcting circuit for correcting a video signal supplied to each pixel to a light emitting device. The correcting circuit is stored with data of a dispersion of a characteristic of a driving TFT among pixels and data of a change over time of luminance of a light emitting element. Further, by correcting a video signal inputted to the light emitting device in conformity with a characteristic of the driving TFT of each pixel and a degree of a deterioration of the light emitting element based on the over-described two data, nonuniformity of luminance caused by a deterioration of an electroluminescent layer and nonuniformity of luminance caused by dispersion of a characteristic of the driving TFT are restrained. | 2009-03-26 |
20090081817 | PATTERNING METHOD - A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile. | 2009-03-26 |
20090081818 | METHOD OF WIRE BOND ENCAPSULATION PROFILING - A method for profiling a bead of encapsulant extending along an edge of a die mounted to a supporting structure, by depositing a bead of encapsulant onto wire bonds along the edge of the die, positioning a profiling surface over the die at a predetermined spacing from the die, moving the profiling surface across the bead before the bead of encapsulant has cured to reshape the bead profile and, curing the bead of encapsulant. The invention has found that the encapsulant can be effectively shaped by a profiling surface without stripping the encapsulant from the wire bonds. The normally convex-shaped upper surface of the encapsulant bead can be pushed to one side of the bead with the profiling surface. With a lower encapsulant bead, the active surface can be brought into closer proximity with another surface without making contact. For example, the nozzle array on a printhead IC can be 300 microns to 400 microns from the paper path. By collapsing or flattening the wire bond arcs before applying and profiling a bead of encapsulant, the nozzle array on the printhead IC can be less than 100 microns from the paper path. | 2009-03-26 |
20090081819 | METHOD AND APPARATUS FOR MANAGING MANUFACTURING EQUIPMENT, METHOD FOR MANUFACTURING DEVICE THEREBY - Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in each of the processes, the method including: acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed; performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device; measuring a property of the comparison device; comparing the measured properties between the reference and the comparison devices; and judging whether the manufacturing apparatus used in the at least one manufacturing process is defective or not, based on a property difference between the reference and the comparison devices. | 2009-03-26 |
20090081820 | Method for manufacturing liquid crystal display device - A method for manufacturing a liquid crystal display device is disclosed. The method includes forming a gate electrode, a gate pad, a gate line on a substrate by using a first mask; forming a gate insulating film, an active layer, an ohmic contact layer and a conductive layer in sequence above the substrate including the gate electrode, the gate line and the gate pad; forming an active pattern, an ohmic contact pattern, source/drain electrodes, a data line and a data pad by using a second mask; forming a pixel electrode on the gate insulating film in a pixel region by using a third mask, to contact with the drain electrode; exposing the active pattern by etching the ohmic contact pattern using the source/drain electrodes as an etching mask; forming a passivation film above the substrate including the source/drain electrodes, the data line and the data pad; forming a first contact hole for exposing the gate pad and a second contact hole for exposing the data pad by etching the passivation and/or gate insulating films using a fourth mask; and forming a common electrode having a plurality of holes on the substrate by using a fifth mask. | 2009-03-26 |
20090081821 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor layer is provided on a surface of a sapphire substrate, the sapphire substrate having smooth surfaces. A support substrate is mounted on an electrode formation surface of the semiconductor layer. A surface portion of the semiconductor layer is melted, and the sapphire substrate is separated from the semiconductor layer at an interface between the sapphire substrate and the semiconductor layer, thereby exposing the semiconductor layer. While the surface portion of the exposed semiconductor layer is melted, the holding substrate with projections/depressions or stripe grooves is pressed against the surface portion of the semiconductor layer, so that the projections/depressions or stripe grooves formed in the holding substrate are transferred onto the surface portion of the semiconductor layer. The support substrate is separated from the semiconductor layer at an interface between the semiconductor layer and the support substrate. | 2009-03-26 |
20090081822 | OPTICAL ENHANCEMENT OF INTEGRATED CIRCUIT PHOTODETECTORS - A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device integral with a semiconductor substrate, a cover dielectric layer disposed over the light sensitive device, and a lens-formation dielectric layer disposed over the cover dielectric layer. Light is transmittable though the cover dielectric layer, and through the lens-formation dielectric layer. The lens-formation dielectric layer forms an embedded convex microlens. The microlens directs light onto the light sensitive device. | 2009-03-26 |
20090081823 | ELECTROFORMED STENCILS FOR SOLAR CELL FRONT SIDE METALLIZATION - A method for providing metallization upon a semiconductor substrate utilizing a stencil having at least one aperture extending from the contact side to the fill side, the contact side of the stencil being substantially flat and forming a sharp edge with a wall of the at least one aperture, the at least one aperture being tapered such that an area of a cross-section of the at least one aperture at the fill side is larger than an area of the cross-section of the at least one aperture at the contact side. A method of forming a stencil for depositing metallization lines on a semiconductor substrate is also disclosed. | 2009-03-26 |
20090081824 | STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING - The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device. | 2009-03-26 |
20090081825 | Phase change memory device and method for fabricating - A phase change memory device is provided. The phase change memory device includes a substrate with a first electrode layer formed thereon. A first phase change memory structure is on the first electrode layer and electrically connected to the first electrode layer. A second phase change memory structure is on the first phase change memory structure and electrically connected to the first phase change memory structure, wherein the first or second phase change memory structure includes a cup-shaped heating electrode. A first insulating layer covers a portion of the cup-shaped heating electrode along a first direction. A first electrode structure covers a portion of the first insulating layer and the cup-shaped heating electrode along a second direction. The first electrode structure includes a pair of phase change material sidewalls on a pair of sidewalls of the first electrode structure and covering a portion of the cup-shaped heating electrode. | 2009-03-26 |
20090081826 | PROCESS FOR MAKING DOPED ZINC OXIDE - The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate, wherein the third gaseous material is inert and wherein a volatile indium-containing compound is introduced into the first reactive gaseous material or a supplemental gaseous material. | 2009-03-26 |
20090081827 | PROCESS FOR SELECTIVE AREA DEPOSITION OF INORGANIC MATERIALS - An atomic-layer-deposition process for forming a patterned thin film comprising providing a substrate, applying a deposition inhibitor material to the substrate, wherein the deposition inhibitor material is an organic compound or polymer; and patterning the deposition inhibitor material either after step (b) or simultaneously with applying the deposition inhibitor material to provide selected areas of the substrate effectively not having the deposition inhibitor material. An inorganic thin film material is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material. | 2009-03-26 |
20090081828 | MEMS Fabrication Method - The present invention provides methods for singulating microelectromechanical systems (MEMS) die from a wafer. A plurality of MEMS devices are formed on the top surface of a wafer, and a plurality of intersecting scribe lanes are then formed, on the bottom surface of the wafer, to define a plurality of dies, each including at least one MEMS device. The intersecting scribe lanes penetrate the wafer to a depth of about 80%, and the wafer is cleaved along the scribe lanes to separate each of the plurality of dies from the wafer. | 2009-03-26 |
20090081829 | METHOD OF ADHERING WIRE BOND LOOPS TO REDUCE LOOP HEIGHT - A method of reducing wire bond loop heights in wire bonds electrically connecting an integrated circuit die with a contact pad to a printed circuit board with a conductor, by mounting the integrated circuit die such that the contact pad is spaced from the conductor, positioning an adhesive surface between the contact pad and the conductor on the printed circuit board, attaching wire to one of the contact pad or the conductor, drawing the wire towards the other of the contact pad or the conductor, allowing the wire to contact the adhesive surface, and, attaching the wire to the other of the contact pad of the conductor to form a wire bond adhered to the adhesive surface and a point intermediate its ends. | 2009-03-26 |
20090081830 | Semiconductor Device and Method of Laser-Marking Wafers with Tape Applied to its Active Surface - A method of laser-marking a semiconductor device involves providing a semiconductor wafer having a plurality of solder bumps formed on contact pads disposed on its active surface. The solder bumps have a diameter of about 250-280 μm. A backgrinding tape is applied over the solder bumps. The tape is translucent to optical images. A backside of the semiconductor wafer, opposite the active surface, undergoes grinding to reduce wafer thickness. The backside of the semiconductor wafer is laser-marked while the tape remains applied to the solder bumps. The laser-marking system including an optical recognition device, control system, and laser. The optical recognition device reads patterns on the active surface through the tape to control the laser. The tape reduces wafer warpage during laser-marking to about 0.3-0.5 mm. The tape is removed after laser-marking the backside of the semiconductor wafer. | 2009-03-26 |
20090081831 | WARPAGE CONTROL USING A PACKAGE CARRIER ASSEMBLY - A method for curing an encapsulant that surrounds a plurality of integrated circuits on a strip that forms a strip assembly is provided. The strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit. The strip assembly is placed on a shelf. Pressure from deformable material or springs is applied to the strip assembly in regions of the strip. The regions are located at one of a group of locations consisting of along unit edges and centered between unit edges. Heat of sufficient temperature is applied for a sufficient duration to cure the encapsulant. The step of applying pressure continues during the application of heat for curing. | 2009-03-26 |
20090081832 | METHOD OF REDUCING WIRE BOND PROFILE HEIGHT IN INTEGRATED CIRCUITS MOUNTED TO CIRCUIT BOARDS - A method of profiling a wire bond between a contact pad on a die, and a conductor on a supporting structure, by electrically connecting the contact pad on the die to the conductor on the supporting structure with a wire bond, the wire bond extending in an arc from the contact pad to the conductor, pushing on the wire bond to collapse the arc and plastically deform the wire bond, and then releasing the wire bonds such that the plastic deformation maintains the wire bond in a flatter profile shape. The strength of the wire bond is known to be relatively small; of the order of 3 to 5 grams force. However, the Applicant's work has found that the wire bond structure is robust enough to withstand a certain degree of work hardening from plastic deformation. The arc of the wire bond can be deformed into a flatter profile without compromising the electrical connection with the PCB. | 2009-03-26 |
20090081833 | WIRE BOND ENCAPSULANT APPLICATION CONTROL - A method of applying encapsulant to a die mounted to a support structure by providing a die mounted to the support structure, the die having a back surface in contact with the support structure and an active surface opposing the back surface, the active surface having electrical contact pads, positioning a barrier proximate the electrical contact pads and spaced from the active surface to define a gap and, depositing a bead of encapsulant onto the electrical contact pads such that one side of the bead contacts the barrier and a portion of the bead extends into the gap and onto the active surface. Placing a barrier over the active surface so that it defines a narrow gap allows the geometry of the encapsulant front (the line of contact between the encapsulant and the active surface) can be more closely controlled. Any variation in the flowrate of encapsulant from the needle tends to cause bulges or valleys in the height of the bead and or the PCB side of the bead. The fluidic resistance generated by the gap between the barrier and the active surface means that the amount of encapsulant that flows into the gap and onto the active surface is almost constant. The reduced flow variations make the encapsulant front closely correspond to the shape of the barrier. Greater control of the encapsulant front allows the functional elements of the active surface of the die to be closer to the contact pads. | 2009-03-26 |
20090081834 | METHOD OF APPLYING ENCAPSULANT TO WIRE BONDS - A method of applying encapsulant to wire bonds between a die and conductors on a supporting substrate, by forming a bead of the encapsulant on a profiling surface, positioning the profiling surface such that the bead contacts the die and, moving the profiling surface relative to the die to cover the wire bonds with the encapsulant. Wiping the encapsulant over the wire bonds with a profiling surface provides control of the encapsulant front as well as the height of the encapsulant relative to the die. The movement of the profiling surface relative to the die can closely controlled to shape the encapsulant to a desired form. Using the example of a printhead die, the encapsulant can be shaped to present an inclined face rising from the nozzle surface to a high point over the wire bonds. This can be used by the printhead maintenance facilities to maintain contact pressure on the wiping mechanism. However, it will be appreciated that the encapsulant can be shaped to have ridges, gutters, grooves and so on by using a particular shape of profiling surface and relative movement with the die. | 2009-03-26 |
20090081835 | Non-Volatile Memory Devices and Methods of Forming the Same - A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate. | 2009-03-26 |
20090081836 | METHOD OF FORMING CMOS WITH SI:C SOURCE/DRAIN BY LASER MELTING AND RECRYSTALLIZATION - A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved. | 2009-03-26 |
20090081837 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EXTENDED STRESS LINER - The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress. | 2009-03-26 |
20090081838 | SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A semiconductor memory includes memory cell transistors including a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors having a first p-type source region and a first p-type drain region, a first gate insulating film, and a first gate electrode of an n conductivity type having the same dose of a first p-type impurity as with the first p-type source region; and high-voltage transistors having a second p-type source region and a second p-type drain region, a second gate insulating film thicker than the first gate insulating film, and a second gate electrode of an n conductivity type having the same dose of a second p-type impurity as with the second p-type source region. | 2009-03-26 |
20090081839 | HIGH SPEED GE CHANNEL HETEROSTRUCTURES FOR FIELD EFFECT DEVICES - A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable. | 2009-03-26 |
20090081840 | Method of Forming Field Effect Transistors Using Diluted Hydrofluoric Acid to Remove Sacrificial Nitride Spacers - Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel. | 2009-03-26 |
20090081841 | Non-Volatile Memory Device and Manufacturing Method Thereof - A non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically in a horizontal direction, and a method of manufacturing the same. The charge trap layer that traps electric charges toward the source and the drain is physically divided. It can fundamentally prevent the charges at both sides from being moved mutually. It is therefore possible to prevent interference between charges at both sides although the cell size is reduced. | 2009-03-26 |
20090081842 | PROCESS FOR ATOMIC LAYER DEPOSITION - The present invention relates to a process of making thin film electronic components and devices, such as thin film transistors, environmental barrier layers, capacitors, insulators and bus lines, where most or all of the layers are made by an atmospheric atomic layer deposition process. | 2009-03-26 |
20090081843 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film ( | 2009-03-26 |
20090081844 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A plurality of single crystal semiconductor substrates are arranged and then the plurality of single crystal semiconductor substrates which have been arranged are overlapped with a base substrate, so that the base substrate and the plurality of single crystal semiconductor substrates are bonded to each other. Then, each of the plurality of single crystal semiconductor substrates is separated to form a plurality of single crystal semiconductor layers over the base substrate. Next, in order to reduce crystal defects in the plurality of single crystal semiconductor layers, the plurality of single crystal semiconductor layers are irradiated with a laser beam. The plurality of single crystal semiconductor layers are thinned by being etched before or after irradiation with a laser beam. | 2009-03-26 |
20090081845 | MANUFACTURING METHOD OF SUBSTRATE PROVIDED WITH SEMICONDUCTOR FILMS - A plurality of rectangular single crystal semiconductor substrates are prepared. Each of the single crystal semiconductor substrates is doped with hydrogen ions and a damaged region is formed at a desired depth, and a bonding layer is formed on a surface thereof. The plurality of single crystal substrates with the damaged regions formed therein and the bonding layers formed thereover are arranged on a tray. Depression portions for holding the single crystal semiconductor substrates are formed in the tray. With the single crystal semiconductor substrates arranged on the tray, the plurality of single crystal semiconductor substrates with the damaged regions formed therein and the bonding layers formed thereover are bonded to a base substrate. By performing heat treatment and dividing the single crystal semiconductor substrates along the damaged regions, the plurality of single crystal semiconductor layers that are sliced are formed over the base substrate. | 2009-03-26 |
20090081846 | METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor device includes applying a coating oxide film to a surface of a substrate including a semiconductor substrate so that a recess formed in the surface is filled with the coating oxide film, applying a steam oxidation treatment to the substrate at a first temperature, soaking the substrate in heated water while applying a megasonic wave to the substrate in the heated water, and applying a steam oxidation treatment to the substrate at a second temperature higher than the first temperature. | 2009-03-26 |
20090081847 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a nonvolatile semiconductor memory device comprising: forming a trench in a silicon substrate; forming a silicon dioxide film along an internal surface of the trench of the silicon substrate; removing the silicon dioxide film formed on a bottom surface of the trench of the silicon substrate by an anisotropic etching process; and forming an ozone tetraethyl orthosilicate (O | 2009-03-26 |
20090081848 | WAFER BONDING ACTIVATED BY ION IMPLANTATION - A method for wafer bonding two substrates activated by ion implantation is disclosed. An in situ ion bonding chamber allows ion activation and bonding to occur within an existing process tool utilized in a manufacturing process line. Ion activation of at least one of the substrates is performed at low implant energies to ensure that the wafer material below the thin surface layers remains unaffected by the ion activation. | 2009-03-26 |
20090081849 | METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER - To provide a method for manufacturing an SOI substrate having a single crystal semiconductor layer having a small and uniform thickness over an insulating film. Further, time of adding hydrogen ions is reduced and time of manufacture per SOI substrate is reduced. A bond layer is formed over a surface of a first semiconductor wafer and a separation layer is formed below the bond layer by irradiating the first semiconductor wafer with H | 2009-03-26 |
20090081850 | METHOD FOR MANUFACTURING SOI SUBSTRATE - The method includes steps of adding first ions to a predetermined depth from a main surface of a semiconductor substrate by irradiation of the semiconductor substrate with a planar, linear, or rectangular ion beam, so that a separation layer is formed; adding second ions to part of the separation layer formed in the semiconductor substrate; disposing the main surface of the semiconductor substrate and a main surface of a base substrate to face each other in order to bond a surface of an insulating film and the base substrate; and cleaving the semiconductor substrate using the separation layer as a cleavage plane, so that a single crystal semiconductor layer is formed over the base substrate. The mass number of the second ions is the same as or larger than that of the first ions. | 2009-03-26 |
20090081851 | Laser processing method - A laser processing method is provided, which, when cutting an object to be processed comprising a substrate and a multilayer part, formed on a front face of the substrate, including a functional device, can cut the multilayer part with a high precision in particular. | 2009-03-26 |
20090081852 | HOLDING JIG, SEMICONDUCTOR WAFER GRINDING METHOD, SEMICONDUCTOR WAFER PROTECTING STRUCTURE AND SEMICONDUCTOR WAFER GRINDING METHOD AND SEMICONDUCTOR CHIP FABRICATION METHOD USING THE STRUCTURE - A backgrinding machine | 2009-03-26 |
20090081853 | PROCESS FOR DEPOSITING LAYERS CONTAINING SILICON AND GERMANIUM - The invention relates to a method for depositing at least one semiconductor layer on at least one substrate in a processing chamber ( | 2009-03-26 |
20090081854 | Method of forming nanowire and method of manufacturing semiconductor device comprising the nanowire - A method of forming a nanowire and a semiconductor device comprising the nanowire are provided. The method of forming a nanowire includes forming a patterned Si | 2009-03-26 |
20090081855 | FABRICATION METHOD OF POLYSILICON LAYER - A fabrication method of a polysilicon layer is provided. First, a substrate is provided. Then, an amorphous silicon layer is formed on the substrate. After that, a patterned photomask having a light transmitting area and a light shielding area is provided, and the amorphous silicon layer is irradiated with a light by using the patterned photomask as a mask, wherein the amorphous silicon layer corresponding to the light transmitting area is transformed into a hydrophilic amorphous silicon layer, and the amorphous silicon layer corresponding to the light shielding area remains as a hydrophobic amorphous silicon layer. Next, a hydrophilic metal catalyst is provided and disposed on the hydrophilic amorphous silicon layer. After that, an annealing process is performed to transform the hydrophilic metal catalyst into a metal catalyst layer, and the metal catalyst layer reacts with the amorphous silicon layer to form a polysilicon layer. | 2009-03-26 |
20090081856 | SINGLE CRYSTAL SILICON WAFER FOR INSULATED GATE BIPOLAR TRANSISTORS AND PROCESS FOR PRODUCING THE SAME - A single crystal silicon wafer for use in the production of insulated gate bipolar transistors is made of single crystal silicon grown by the Czochralski method and has a gate oxide with a film thickness of from 50 to 150 nm. The wafer has an interstitial oxygen concentration of at most 7.0×10 | 2009-03-26 |
20090081857 | Non-polar and semi-polar GaN substrates, devices, and methods for making them - Non-polar or semi-polar (Al, Ga, In)N substrates are fabricated by re-growth of (Al, Ga, In)N crystal on (Al, Ga, In)N seed crystals, wherein the size of the seed crystal expands or is increased in the lateral and vertical directions, resulting in larger sizes of non-polar and semi-polar substrates useful for optoelectronic and microelectronic devices. One or more non-polar or semi-polar substrates may be sliced from the re-grown crystal. The lateral growth rate may be greater than the vertical growth rate. The seed crystal may be a non-polar seed crystal. The seed crystal may have crystalline edges of equivalent crystallographic orientation | 2009-03-26 |
20090081858 | Sputtering-Less Ultra-Low Energy Ion Implantation - Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering effect is provided. | 2009-03-26 |
20090081859 | Metallization process - A metallization process is provided. The metallization process comprises the following steps. First, a semiconductor base having at least a silicon-containing conductive region is provided. Afterwards, nitrogen ions are implanted into the silicon-containing conductive region. Next, a first thermal process is performed on the semiconductor base for repairing the surface of the semiconductor base. Then, a metal layer is formed on the surface of the semiconductor base and the metal layer covers the silicon-containing conductive region. Lastly, a second thermal process is performed on the semiconductor base covered with the metal layer so as to form a metal silicide layer on the silicon-containing conductive region. | 2009-03-26 |
20090081860 | METHOD OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES USING HALO IMPLANT SHADOWING - The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures. | 2009-03-26 |
20090081861 | MANUFACTURING METHOD OF SOLDER BALL DISPOSING SURFACE STRUCTURE OF PACKAGE SUBSTRATE - A manufacturing method of a solder ball disposing surface structure on a core board including: providing a core board with a first metal layer and an opposing metal bump-equipped second metal layer; forming resists on the first and second metal layers respectively; forming third, fourth and fifth openings in the resists; removing the first and second metal layers in the third and fourth openings to form first and second circuit layers and metal pads respectively; removing the metal bumps in the fifth openings to form metal flanges; removing the resists; forming first and second insulative protection layers on the first and second circuit layers and metal pads respectively; forming first and second openings in the first and second insulative protection layers to expose the first circuit layer as electrical connecting pads and expose the metal flanges respectively. Accordingly, increased contact surface area for mounting conductive elements prevents detachment thereof. | 2009-03-26 |
20090081862 | AIR GAP STRUCTURE DESIGN FOR ADVANCED INTEGRATED CIRCUIT TECHNOLOGY - A method for forming air gaps between interconnect structures in semiconductor devices provides a sacrificial layer formed over a dielectric and within openings formed therein. The sacrificial layer is a blanket layer that is converted to a material that is consumable in an etchant composition that the dielectric material and a subsequently formed interconnect material are resistant to. After the interconnect material is deposited a planarized surface including portions of the dielectric material, vertical sections of the converted material and portions of the interconnect material is produced. The etchant composition then removes the converted material thereby forming voids. A capping layer is formed over the structure resulting in air gaps. A sidewall protection layer may be optionally formed between the interconnect structure and the sacrificial material. In some embodiments an ARC layer may be formed over the dielectric and form part of the planar surface. | 2009-03-26 |
20090081863 | METHOD OF FORMING METAL WIRING LAYER OF SEMICONDUCTOR DEVICE - A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring. | 2009-03-26 |
20090081864 | SiC Film for Semiconductor Processing - A silicon carbide (SiC) film for use in backend processing of integrated circuit manufacturing, is generated by including hydrogen in the reaction gas mixture. This SiC containing film is suitable for integration into etch stop layers, dielectric cap layers and hard mask layers in interconnects of integrated circuits. | 2009-03-26 |
20090081865 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of: (a) forming a first insulating film having moisture absorbency on a substrate; (b) forming a dummy contact hole and a contact hole in the first insulating film; (c) heat-treating the substrate, thereby removing water contained in the first insulating film; and (d) forming a contact and a dummy contact. The heat treatment in the step (c) removes water contained in the first insulating film through the contact hole and the dummy contact hole. | 2009-03-26 |
20090081866 | VAPOR DEPOSITION OF TUNGSTEN MATERIALS - Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes to provide tungsten films having significantly improved surface uniformity while increasing the production level throughput. In one embodiment, a method is provided which includes depositing a tungsten silicide layer on the substrate by exposing the substrate to a continuous flow of a silicon precursor while also exposing the substrate to intermittent pulses of a tungsten precursor. The method further provides that the substrate is exposed to the silicon and tungsten precursors which have a silicon/tungsten precursor flow rate ratio of greater than 1, for example, about 2, about 3, or greater. Subsequently, the method provides depositing a tungsten nitride layer on the tungsten suicide layer, depositing a tungsten nucleation layer on the tungsten nitride layer, and depositing a tungsten bulk layer on the tungsten nucleation layer. | 2009-03-26 |
20090081867 | METHOD OF MANUFACTURING SUBSTRATE - The present disclosure relates to a method of manufacturing a substrate. The method includes: (a) forming through holes by applying an anisotropic etching to a silicon substrate from a first surface of the silicon substrate; (b) forming a first insulating film to cover the first surface of the silicon substrate, surfaces of the silicon substrate exposed from the through holes, and a second surface of the silicon substrate opposite to the first surface; (c) forming an opening in a portion of the first insulating film provided on the second surface, the portion of the first insulating film corresponding to an area in which the through holes are formed; (d) etching the silicon substrate using the first insulating film provided on the second surface as a mask, thereby forming a cavity in the silicon substrate; and (e) removing the first insulating film. | 2009-03-26 |
20090081868 | VAPOR DEPOSITION PROCESSES FOR TANTALUM CARBIDE NITRIDE MATERIALS - Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate. The method further provides that the tantalum carbide nitride material is crystalline and contains interstitial carbon and elemental carbon having an interstitial/elemental carbon atomic ratio of greater than 1, such as about 2, 3, 4, or greater. | 2009-03-26 |
20090081869 | Process for producing silicon compound - A process for producing a silicon compound can minimize the number of steps and can form a desired compound in a low-temperature environment. The process comprises: allowing a radical of a halogen gas to act on a member | 2009-03-26 |
20090081870 | METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING COPPER WIRING LAYERS OF DIFFERENT WIDTHS HAVING METAL CAPPING LAYERS OF DIFFERENT THICKNESSES FORMED THEREON - In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer. | 2009-03-26 |
20090081871 | POLISHING COMPOSITION AND METHOD UTILIZING ABRASIVE PARTICLES TREATED WITH AN AMINOSILANE - The inventive method comprises chemically-mechanically polishing a substrate with an inventive polishing composition comprising a liquid carrier, a cationic polymer, an acid, and abrasive particles that have been treated with an aminosilane compound. | 2009-03-26 |
20090081872 | PLASMA ETCHING METHOD FOR ETCHING SAMPLE - The invention provides an etching method having selectivity of a high-K material such as Al | 2009-03-26 |
20090081873 | Methods of Patterning Insulating Layers Using Etching Techniques that Compensate for Etch Rate Variations - Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates. | 2009-03-26 |
20090081874 | METHOD FOR EXTENDING EQUIPMENT UPTIME IN ION IMPLANTATION - The invention features in-situ cleaning process for an ion source and associated extraction electrodes and similar components of the ion-beam producing system, which chemically removes carbon deposits, increasing service lifetime and performance, without the need to disassemble the system. In particular, an aspect of the invention is directed to an activating, catalytic, or reaction promoting species added to the reactive species to effectively convert the non-volatile molecular residue into a volatile species which can be removed by conventional means. | 2009-03-26 |
20090081875 | Chemical removal of oxide layer from chip pads - Methods are provided for removing an oxide layer from a metal pad on an integrated circuit in order to reduce contact resistance. In one embodiment, aluminum oxide, on the surface of a bond pad substantially comprised of aluminum, is reacted with a first chemical agent to form an inorganic salt, and the inorganic salt is then reacted with a second chemical agent leaving a substantially bare, that is, unoxidized, aluminum surface. | 2009-03-26 |
20090081876 | METHOD OF PREVENTING ETCH PROFILE BENDING AND BOWING IN HIGH ASPECT RATIO OPENINGS BY TREATING A POLYMER FORMED ON THE OPENING SIDEWALLS - High aspect ratio contact openings are etched while preventing bowing or bending of the etch profile by forming a highly conductive thin film on the side wall of each contact opening. The conductivity of the thin film on the side wall is enhanced by ion bombardment carried out periodically during the etch process. | 2009-03-26 |
20090081877 | METHOD OF CONTROLLING STRIATIONS AND CD LOSS IN CONTACT OXIDE ETCH - A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced. | 2009-03-26 |
20090081878 | Temperature control modules for showerhead electrode assemblies for plasma processing apparatuses - A temperature control module for a showerhead electrode assembly for a semiconductor material plasma processing chamber includes a heater plate adapted to be secured to a top surface of a top electrode of the showerhead electrode assembly, and which supplies heat to the top electrode to control the temperature of the top electrode; a cooling plate adapted to be secured to and thermally isolated from a surface of a top plate of the showerhead electrode assembly, and to cool the heater plate and control heat conduction between the top electrode and heater plate; and at least one thermal choke adapted to control heat conduction between the heater plate and cooling plate. | 2009-03-26 |
20090081879 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device including processing a substrate to be processed by using an amorphous carbon hard mask that includes processing an amorphous carbon film formed on the substrate to be processed to provide a hard mask, and forming a protective film comprising a silicon oxide film on a sidewall of the amorphous carbon film exposed during or after processing the amorphous carbon film; and the protective film preferably formed by sputtering an intermediate mask comprising at least a silicon oxide on the amorphous carbon film. | 2009-03-26 |
20090081880 | Method for manufacturing semiconductor device - The present invention provides a method for manufacturing a semiconductor device includes: a immersion process of immersing, in a fluoronitric acid solution, a lamination substrate, in which an SiC substrate formed of a silicon carbide (SiC) single crystal is applied to a silicon substrate or a quarts substrate with a larger hole diameter than the SiC substrate; and a peeling process of taking out the SiC substrate which is not dissolved and remains in the fluoronitric acid solution after the silicon substrate or the quartz substrate is dissolved and removed from the fluoronitric acid solution. | 2009-03-26 |
20090081881 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD FOR PERFORMING ETCHING PROCESS WITH PHOSPHORIC ACID SOLUTION - An additive containing a hexafluorosilicic acid solution (H | 2009-03-26 |
20090081882 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR DESIGNING PHOTOMASK PATTERN - A method for designing a photomask pattern is provided. First, all line ends of object patterns are determined with reference to layout data. Then, object patterns, front edge portions, and joints, which are aligned on the same line extending along the Y-axis, are connected to form first reticle data. Reticle pattern data having data representing binding portions serving as light blocking portions is formed. The front edge portions being adjacent to each other and aligned in the X-axis are connected and adjacent joints being aligned in the same manner as the front edge portions are also connected to form second reticle data. Then, portions are provided at central regions between the binding portions so as to connect the adjacent binding portions including the front edge portions and the joints. Then, reticle data having data representing the binding portions serving as transparent patterns is formed. | 2009-03-26 |
20090081883 | PROCESS FOR DEPOSITING ORGANIC MATERIALS - A process of making an organic thin film on a substrate by atomic layer deposition is disclosed, the process comprising simultaneously directing a series of gas flows along substantially parallel elongated channels, and wherein the series of gas flows comprises, in order, at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, optionally repeated a plurality of times, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material wherein the first reactive gaseous material, the second reactive gaseous material or both is a volatile organic compound. The process is carried out substantially at or above atmospheric pressure and at a temperature under 250° C., during deposition of the organic thin film. | 2009-03-26 |
20090081884 | METHOD OF IMPROVING OXIDE GROWTH RATE OF SELECTIVE OXIDATION PROCESSES - A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized. | 2009-03-26 |
20090081885 | DEPOSITION SYSTEM FOR THIN FILM FORMATION - A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material, wherein one or more of the gas flows provides a pressure that at least contributes to the separation of the surface of the substrate from the face of the delivery head. A system capable of carrying out such a process is also disclosed. | 2009-03-26 |
20090081886 | SYSTEM FOR THIN FILM DEPOSITION UTILIZING COMPENSATING FORCES - A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed. | 2009-03-26 |
20090081887 | Heat treatment method and heat treatment apparatus - The number of substrates held by a substrate holder is increased compared with conventional techniques while uniformity of a heat treatment is ensured. The substrate holder holds a plurality of substrates at predetermined vertical intervals. The substrate holder is carried into a heat treating furnace. A predetermined heat treatment is performed on the substrates. The substrate holder has two holder constituting bodies. Each of the holder constituting bodies has a plurality of columns and substrate holding sections. The columns are arranged on the circumference of the same imaginary circle. The substrate holding sections hold circumferential portions of the respective substrates. One of the holder constituting bodies holds the substrates under the condition that front surfaces of the substrates face upward, while the other of the holder constituting bodies holds the substrates under the condition that back surfaces of the substrates face upward. The substrate with the front surface facing upward and the substrate with the back surface facing upward are alternately arranged in a vertical direction. At least one of the holder constituting bodies moves in the vertical direction to change the positions of the holder constituting bodies relative to each other. A distance between one of a first pair of substrates that are vertically adjacent to each other and have the respective front surfaces facing each other and the other of the first pair of substrates is set to ensure uniformity of the treatment and larger than a distance between one of a second pair of substrates that are vertically adjacent to each other and have the respective back surfaces facing each other and the other of the second pair of substrates. | 2009-03-26 |
20090081888 | Powered patch panel - A powered communications patch panel is adapted to power network devices connected to the communications patch panel. Power is supplied to the network devices by the powered communications patch panel over the communication cabling. The powered communications patch panel may be provided with a management port to allow remote management of the patch panel via a network connection. Multiple management ports may be provided, allowing patch panels to be connected to one another in a daisy-chain configuration. | 2009-03-26 |
20090081889 | Providing variable sized contacts for coupling with a semiconductor device - In one embodiment, the present invention includes a circuit board having integrated contacts to mate with corresponding pads of a semiconductor device. At least some of the integrated contacts are of varying sizes to enable different contact resistances between the corresponding integrated contacts and pads, enabling reduced loading forces to adapt the semiconductor device to the circuit board. Other embodiments are described and claimed. | 2009-03-26 |
20090081890 | CARD CONNECTOR AND ELECTRONIC DEVICE - A card connector where a connector main body is fixed inside an electronic device and a tray is disposed so as to slide relative to the connector main body in a longitudinal direction. The tray is movable between an advanced position at which the entirety of the tray has advanced into the connector main body and a pulled-out position at which a part of the tray has been pulled out from the connector main body. A tilt pawl is disposed on the tray, and a slide groove for guiding the tilt pawl in the longitudinal direction and a tilt groove for guiding the tilt pawl upward at the pulled-out position are formed in the connector main body. When in the pulled-out position, the tray is inclined so that a gap between a card mounting surface of the tray and an upper plate portion of the connector main body is increased. According to the resulting card connector, the electronic device is not required to have a large opening, an excessive load is not applied to the card when the card is inserted or withdrawn, a reduction is size can be achieved, and the profile can be made thinner. | 2009-03-26 |
20090081891 | METHOD OF PRODUCING LAND GRID ARRAY (LGA) INTERPOSER GROUPS OF DIFFERENT HEIGHTS UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and interposer groupings of different height being mounted on a first surface of said carrier plane. Each interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of each hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 2009-03-26 |
20090081892 | Ellectrical connector with latchign portion - An electrical connector, for electrically connecting an IC package to a printed circuit board, includes an insulative housing and a number of terminals received in the insulative housing. The insulative housing has a base portion and four peripheral walls extending upwardly from the base portion. The insulative housing has four corners and three of the four corners have a latching portion extending inwardly from a top end of corresponding corner, respectively, and the rest one corner is formed with an indentation. The latching portion guides and resists the IC package in the insulative housing. Thus, the latching portions of the connector are molded easily. | 2009-03-26 |
20090081893 | PORTABLE TERMINAL - A mobile device including a first circuitry supporting substrate having an upper surface and a lower surface, a second circuitry supporting substrate having an upper surface and a lower surface, the second circuitry supporting substrate at least partially overlapping the first circuitry supporting substrate, and a metallic member extending from one of the lower surface of the first circuitry supporting substrate and the upper surface of the second circuitry supporting substrate, the metallic member contacting the other of the lower surface of the first circuitry supporting substrate and the upper surface of the second circuitry supporting substrate to define a shield region between the first circuitry supporting substrate and the second circuitry supporting substrate. | 2009-03-26 |
20090081894 | Insulative housing for configuring socket connector having pivotally mounted clip - A socket connector ( | 2009-03-26 |
20090081895 | UNIVERSAL ADAPTER - The universal adapter of the present invention comprises an adapter body having at least one set of power sockets, a power plug and a conductive unit, wherein the power plug has a fixed unit and a rotating unit that is located both ends of the fixed unit inside the adapter body. Each side of the fixed unit comprises male connectors, in which one end of every male connector is assembled with the rotating unit, and another end of every male connector can be protruded through the adapter body. The conductive unit comprises sets of connecting sockets that are corresponding to the set of power sockets, and a set of conductive flat pieces protruded from one end of the sets of connecting sockets, is in contact with the rotating units. The universal adapter is used as a travel adapter that it allows the user to plug their electrical appliances to various power plug standards by changing different male connectors. | 2009-03-26 |
20090081896 | Separable Electrical Connector with Reduced Risk of Flashover - A separable loadbreak connector system includes mating electrical connectors. At least one of the electrical connectors includes an electrically-resistive housing having a generally conically-shaped interior bore. A semiconductive insert is disposed within a portion of the interior bore and presents an inner radial surface that defines a generally conically-shaped recess. An elongated probe assembly is disposed within the housing and includes a probe and a sheath of insulative material disposed over at least a portion of a length of the probe. A portion of the sheath extends in a radially outward direction from a base of the probe. An electrically-resistive insulative layer extends from the conically-shaped interior bore, along at least a portion of the inner radial surface of the semiconductive insert. The insulative layer extends radially inwardly in overlapping engagement with a portion of the sheath. | 2009-03-26 |
20090081897 | Waterproof electrical connector - An electrical connector including a connector body having a plurality of conductor receiving areas; a plurality of set screws connected to the connector body for clamping conductors against the connector body in the conductor receiving areas; a seal casing on the connector body; and a valve on the connector body and in communication with at least one of the conductor receiving areas. The valve is configured to allow gas from inside the at least one conductor receiving area to vent out of the electrical connector. | 2009-03-26 |
20090081898 | Adapter for electrical device - Provided is an adapter for an electrical device such as a photographing device. In an embodiment, the adapter includes a base frame, a connector that is disposed in the base frame and can be connected to a power input terminal of the electrical device, and a power input jack that is disposed in the base frame and electrically connected to the connector and can be connected to an external power supply device. In yet another embodiment, the power input jack of the previously-mentioned embodiment is replaced with a power input cord having a plug that is configured to interface with an external power supply device such as an AC power outlet. | 2009-03-26 |
20090081899 | SELF-RETAINING AUDIO/VIDEO HIGH DEFINITION MULTI-CONTACT CONNECTOR AND CONNECTION METHOD - A self-retaining HDMI compatible connector comprises an inner plug section and at least one retaining portion resiliently expanded a distance away from the inner plug section and operably movable to be compressed for insertion and/or retraction during mating of the connector with a standard HDMI jack. The expanded retaining portion exerts a force against the jack receptacle and helps to impede removal of the connector once mated with the jack. | 2009-03-26 |
20090081900 | Electric connector - An electric connector | 2009-03-26 |
20090081901 | Cable connector, method of connecting a cable connector and a cable - A cable connector | 2009-03-26 |
20090081902 | COAXIAL CABLE CONNECTOR AND METHOD OF USE THEREOF - A coaxial cable connector is provided, the connector comprising: a connector body; a physical parameter sensing circuit, positioned within the connector body; and a status output component, configured to report an ascertained physical parameter status to a location outside of the connector body. A corresponding method of ascertaining a physical parameter status of a connector connection is disclosed. | 2009-03-26 |
20090081903 | Electrical connector - An electrical connector comprises an insulating housing of one piece and a plurality of contacts retained in the passageways. Said insulating housing comprises an engaging portion, a supporting portion and a plurality of passageways along a longitudinal direction of the insulating housing, said engaging portion and said supporting portion respectively define a mating surface and a supporting surface. Each contact comprises a base portion retained in the passageway, a male mating arm and a female mating arm respectively extend upwardly from said base portion. Said female mating arm has a spring leg extending apart from said male mating arm, said spring leg has a mating portion at a free tip end thereof curlily extending toward said male mating arm, said male mating arm projects upwards beyond the supporting surface of the supporting portion. The electrical connector mates with an identical connector, both of which can share with a same mold during the process of manufacturing to save the cost. | 2009-03-26 |
20090081904 | Electrical connector with switching terminals - An electrical connector includes an insulating housing defining a receiving cavity surrounded by opposite sidewalls and a top and bottom wall connecting with the sidewalls, a plurality of contacts retained on the housing, a couple of switching terminals including a first terminal and a second terminal, and a shell surrounding the insulating housing. One of said side wall defines two slots. The two terminals are received and retained in said two slots and mates with each others when a complementary connector is inserted into the receiving cavity. The first terminal defines a touching tab contacting with the shell. | 2009-03-26 |
20090081905 | Electrical connector - An electrical connector comprises an insulative housing and a plurality of terminals received in the insulative housing. Each terminal comprises a mounting portion, an engaging portion extending upwardly from the mounting portion and at least a tail portion extending downwardly from the mounting portion. The engaging portion defines a main plate, an extending portion extending upwardly from the main plate and a resilient contacting portion extending slantways and upwardly from the main plate. | 2009-03-26 |
20090081906 | SYSTEMS AND METHODS FOR PROVIDING A TRIMLESS ELECTRONIC DEVICE PORT - This invention is directed to systems and methods for providing a port in an electronic device housing that is electrically isolated from a conductive portion of a connector inserted in the port without the use of a nonconductive trim in the port. In some embodiments, the connector may include a non-conductive flange or ring operative to contact the housing and the portions of the housing within the port. In some embodiments, a thin layer of non-conductive material may be applied to the portions of the housing within the port to prevent conductive portions of the connector from coming into contact with the housing (e.g., and grounding the conductive portion. This invention may be of particular interest when the conductive portion that may come into contact with the housing is not used to ground the connector. | 2009-03-26 |
20090081907 | Electrical connector having an improved housing having a curved structure - An electrical connector ( | 2009-03-26 |
20090081908 | Connector With Redundant Terminal Locking - A connector is disclosed. The connector includes a connector housing having a terminal channel and a terminal positioned within the terminal channel. The connector includes a primary locking mechanism including a locking beam configured to engage a first terminal locking surface and a secondary locking mechanism including a locking hinge having a locking foot configured to engage a second terminal locking surface. The locking hinge is configured to pivot from a staging position to permit passage of the terminal into the connector through the terminal channel to an operative position to retain the terminal within the terminal channel and establish a position of maximum rearward travel of the terminal within the terminal channel. | 2009-03-26 |