| 13th week of 2009 patent applcation highlights part 26 |
| Patent application number | Title | Published |
|---|
| 20090080208 | DECORATIVE UNIT WITH ILLUMINABLE DECORATIVE ELEMENTS - The invention relates to a decorative unit with illuminable decorative elements ( | 2009-03-26 |
| 20090080209 | Colored and electroplated reflective vehicle lamp - A colored and electroplated reflective vehicle lamp includes a reflecting shield provided with a plurality of bowl-shaped cavities with reflecting surfaces respectively electroplated with a silvery reflecting layer. Then, the silvery reflecting layer is coated thereon with a clear lacquer layer having its surface sprayed with a colored layer. A transparent lamp lens covers the reflecting shield. By the colored reflecting shield and the transparent lamp lens, it is possible to maintain the color gradations and brightness of light illuminated by the vehicle lamp for matching with different colors of vehicles. | 2009-03-26 |
| 20090080210 | Motor Vehicle Headlight - A motor vehicle headlight ( | 2009-03-26 |
| 20090080211 | VEHICLE LIGHTING DEVICE - A vehicle lighting device is provided with: a lamp chamber defined by a lamp body and a cover; a light source unit including a semiconductor light emitting element as a light source and provided within the lamp chamber; a metallic heat transfer member attached to the lamp body and penetrating between an outside and an inside of the lamp chamber; and an air blower disposed between the light source unit and the heat transfer member so that an air blowing direction of the air blower directs toward the heat transfer member. | 2009-03-26 |
| 20090080212 | Socket for a Lamp - A socket for a lamp is disclosed, in particular for a vehicle lamp, comprising a socket housing and at least two contact elements fixed in the socket housing for housing and electrical contacting of the lamp. According to the invention, the contact elements of the socket housing are fixed by means of a positive or non-positive fit with a socket pin which may be fixed therein. | 2009-03-26 |
| 20090080213 | Light guide and image sensor module - An elongated and generally columnar light guide includes a light receiving surface provided at an longitudinal end portion of the light guide, a reflecting surface elongated in the longitudinal direction of the light guide for reflecting light entering through the light receiving surface in a light emitting direction, a ridge elongated in the longitudinal direction of the light guide, and a light emitting surface for emitting reflected light from the reflecting surface as linear light extending in the longitudinal direction of the light guide. The reflecting surface is provided on a distal end portion of the ridge. | 2009-03-26 |
| 20090080214 | ILLUMINATION APPARATUS AND ENDOSCOPE - An illumination apparatus includes a light source which generates heat when emitting an illumination light from a light-emitting surface, a light guide bundle which has a light-receiving surface opposed to the light-emitting surface of the light source, to receive the illumination light emitted from the light-emitting surface of the light source, and guides the illumination light from the light source received by the light-receiving surface, and a light guide connector which has an end face arranged along the light guide bundle and opposed to the light-emitting surface of the light source, and a contact part in which at least a part of the end face directly contacts the light-emitting surface, and absorbs the heat generated on the light-emitting surface of the light source. | 2009-03-26 |
| 20090080215 | UV based color pixel backlight for liquid crystal display - A ultra-violet based color pixel backlight system for Liquid Crystal Display, that does not contain the traditional color filters, comprising multiplicity of LEDs, emitting UV light in the wavelength range of 250 nm to 390 nm, assembled at one edge of a UV transmitting light guide, which has other three edges and bottom surface coated with UV reflecting layer and its top surface etched with UV extracting pixel patterns that contain phosphors that emit different colors of light in red, blue and green region when excited by UV light. A sheet of micro-lens is assembled between the light guide and the LCD to have the etched pixels in substantial alignment with the pixels of LCD and the lenses of the sheet of micro-lens. Thus red, blue and green pixels of light from the light guide passes through the intended red, blue and green pixels of LCD that has no traditional color filters, resulting in color pixel backlighting that enhances the optical efficiency of LCD. | 2009-03-26 |
| 20090080216 | LIGHT GUIDE PLATE, SURFACE LIGHT SOURCE, AND LIQUID CRYSTAL DISPLAY DEVICE - A light guide plate has a light exit plane and a light entrance plane arranged on the periphery of the light exit plane. Light incident on the light entrance plane is outputted from the light exit plane. The light entrance plane includes a plurality of first end surfaces and a plurality of second end surfaces protruding in an external direction beyond the first end surfaces in plan view. The first end surfaces and the second end surfaces are alternately arranged along the periphery of the light exit plane. | 2009-03-26 |
| 20090080217 | Encapsulant shapes for light emitting devices lacking rotational symmetry designed to enhance extraction of light with a particular linear polarization - The light-emitting device includes a light source and a transparent encapsulating material that is shaped to modify the polarization anisotropy of light emitted by the light source in at least one direction. | 2009-03-26 |
| 20090080218 | PRISM SHEET AND BACKLIGHT MODULE USING THE SAME - An exemplary prism sheet includes a transparent main body. The main body includes a first surface, a second surface and a plurality of spherical micro-depressions and a plurality of triangular pyramidal micro-depressions. The first surface and the second surface are on opposite sides of the main body. The spherical micro-depressions are formed in the first surface and the triangular pyramidal micro-depressions are formed in the second surfaces. A backlight module using the present prism sheet is also provided. | 2009-03-26 |
| 20090080219 | PRISM SHEET AND BACKLIGHT MODULE USING THE SAME - An exemplary prism sheet ( | 2009-03-26 |
| 20090080220 | Prism sheet and backlight module using the same - An exemplary prism sheet includes a transparent main body. The transparent main body includes a surface and a plurality of micro-depressions integrally formed in the surface. Each of the micro-depressions has connecting sidewalls. A transverse width of each sidewall progressively decreases with increasing distance from the surface thereof. A backlight module using the present prism sheet is also provided. | 2009-03-26 |
| 20090080221 | LIGHT RECEIVING ELEMENT - An exemplary aspect of the invention is a light receiving element comprising a substrate, a light receiver absorbing light on a surface of the substrate, and a reflector reflecting the light incoming from a side of the substrate to the light receiver, wherein a reflecting surface of the reflector is inclined toward the side of the substrate in a section parallel to the surface of the substrate. | 2009-03-26 |
| 20090080222 | System and Method for Power Saving Conversion Topology in Switch Mode Power Supplies - A power supply includes an input filter and rectifier module, a digital control module, and a converter module. The input filter and rectifier module is configured to rectify an input voltage. The digital control module is adapted to prevent a potential saturation of a transformer by setting a maximum allowable duty cycle for a control signal transmitted to the transistor based on an input voltage. The digital control model is further adapted to reduce switching losses in the power supply by setting the control signal switching frequency, based on the input voltage. The converter module is configured to convert the input voltage into a direct current output voltage based upon the control signal. | 2009-03-26 |
| 20090080223 | FORWARD CONVERTER WITH SELF-DRIVEN SYNCHRONOUS RECTIFIERS - The present invention relates to a forward converter with self-driven synchronous rectifiers, which utilizes a secondary driving winding and a secondary driving circuit to drive the synchronous rectifiers in the secondary power loop. The secondary driving circuit, which is composed of a level shifter and a signal distributor, can shift the voltage waveform across the secondary driving winding by a predetermined level and distribute proper driving signals to the synchronous rectifiers to reduce the rectifier conduction loss. Specially, the channel of the freewheeling synchronous rectifier still can be turned on during the dead interval to further reduce the body diode conduction loss. | 2009-03-26 |
| 20090080224 | AC TO DC CONVERSION CIRCUIT - A half-wave rectifier including an input port for receiving an incoming AC signal, an output port for outputting a half-wave rectified signal, an operational amplifier including inverting and non-inverting input terminals and an output terminal, the inverting input terminal connected to a ground reference and a non-inverting input terminal coupled to a negative feedback loop and a first resistor. The negative feedback loop including a second resistor coupled between a first node and a second node, the first node coupling the output terminal and the output port and the second node coupling the non-inverting input terminal and the second resistor. A capacitor is coupled to the input port and in series with the first resistor. | 2009-03-26 |
| 20090080225 | VOLTAGE SOURCE CONVERTER AND METHOD OF CONTROLLING A VOLTAGE SOURCE CONVERTER - A voltage source converter for conversion between dc and ac voltage includes at least two serially connected phase legs. The outputs of the conversion stages form phase outputs to be connected to a phase of an alternating voltage network via a respective transformer. The configuration of the conversion stages reduces the requirements on the individual components of the voltage source converter. | 2009-03-26 |
| 20090080226 | Method and apparatus for maximum power point tracking in power conversion based on dual feedback loops and power ripples - A method and apparatus for converting DC input power to AC output power. The apparatus comprises a conversion module comprising an input capacitor, and a first feedback loop for determining a maximum power point (MPP) and operating the conversion module proximate the MPP. The apparatus additionally comprises a second feedback loop for determining a difference in energy storage and delivery by the input capacitor, producing an error signal indicative of the difference, and coupling the error signal to the first feedback loop to adjust at least one operating parameter of the conversion module to drive toward the MPP. | 2009-03-26 |
| 20090080227 | Switching power supply - A current-mode switching power supply is provided, in which there is no unstable operation arising from the fact that signals to generate PWM signals are minute, even when a load is light and a switching frequency is high. In a switching power supply of this invention, an added slope signal is superposed in an early stage of a rise of a current detection signal, so that a combined signal Vsig is caused to reach a certain magnitude even when the load is light and the switching frequency is high, and consequently an output FB of an error amplifier ERRAMP which is balanced with the combined signal is also increased. By this means, even in a current mode, it is possible to eliminate unstable operation arising from the fact that the feedback signal FB which is the output of the error amplifier ERRAMP and the combined signal Vsig are minute. | 2009-03-26 |
| 20090080228 | INDUSTRIAL TRUCK WITH A CHARGER - Industrial truck with a charger, an asynchronous machine and a three-phase AC control unit which converts a DC voltage of a battery for the asynchronous machine, the charger having a switching power supply which is connected to the three-phase AC control unit via a transformer, the switching power supply, the three-phase AC control unit and the transformer forming a resonant converter, which converts a mains voltage into a charging voltage for the battery. | 2009-03-26 |
| 20090080229 | SINGLE-LAYER METAL CONDUCTORS WITH MULTIPLE THICKNESSES - A pattern that includes trenches of different depths is formed on a substrate using nanoimprint lithography. A subsequent metal deposition forms lines of different thicknesses according to trench depth, from a single metal layer. Vias extending down from lines are also formed from the same layer. Individual bit lines are formed having different thicknesses at different locations. | 2009-03-26 |
| 20090080230 | eDRAM Hierarchical Differential Sense AMP - In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches. | 2009-03-26 |
| 20090080231 | SEMICONDUCTOR MEMORY DEVICE - A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line. A gate of the first selecting transistor is connected to the 2·N−1th selecting line, and a gate of the second selecting transistor is connected to the 2·Nth selecting line. | 2009-03-26 |
| 20090080232 | AREA EFFICIENT PROGRAMMABLE READ ONLY MEMORY (PROM) ARRAY - A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row. | 2009-03-26 |
| 20090080233 | METHOD AND APPARATUS FOR PRINTED RESISTIVE READ ONLY MEMORY - A printed read only memory (ROM) device that consists of an array of memory resistors, a reference resistor, and analog-to-digital circuit is disclosed. Resistance values are dependent on the data to be stored in the read only memory. During read operation, a resistor in the array is powered, activating a voltage divider between the powered resistor and the reference resistor. The analog-to-digital circuit will read the divided voltage level between the two resistors, compare the voltage supply level and interpret it into bits of memory data. During the manufacturing of the ROM circuit, an array of memory resistors is printed as the means for storage of the data. Resistive inks of specific resistance values are selected and printed in a preferred layout that includes a reference resistor coupled to the determined array of memory resistors and an analog to digital converter so as to form a read only memory with the received data. | 2009-03-26 |
| 20090080234 | SEMICONDUCTOR DEVICE AND DRAM CONTROLLER - According to a semiconductor device of the present invention, a differential potential between a sense amplification level and a precharge level of a sense amplifier is set to a power supply potential (VCC-GND) so as to improve resistance against degradation of hold characteristics. Further, low power consumption can be realized along with the improvement. Additionally, the precharge level is set to a power supply of GND or VCC so as to realize a stable supply of the precharge level. Further, a chip size can be reduced since a power supply circuit for precharge is not needed. | 2009-03-26 |
| 20090080235 | COMPACT AND HIGHLY EFFICIENT DRAM CELL - A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node. | 2009-03-26 |
| 20090080236 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second transfer transistors is connected to each of the first and memory nodes respectively. The memory cell is connected to a bit line and complementary bit line via the first and second transfer transistors respectively wherein a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to the load transistors, and at least a memory-node-side end of a gate insulating film of the first driver transistor, second driver transistor, first load transistor, and the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part. | 2009-03-26 |
| 20090080237 | SRAM MEMORY WITH REFERENCE BIAS CELL - A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second storage node, a first gate of the first access transistor and a first gate of the second access transistor being linked to a first word line, a second gate of the first access transistor and a second gate of the second access transistor being linked to a second word line, the device being moreover equipped: with a reference memory cell provided to deliver a bias potential intended to be applied to one of the respective word lines of one or several given cells of said plurality of cells during reading access of said given cells. | 2009-03-26 |
| 20090080238 | MAGNETORESISTIVE ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME - The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between the tunnel barrier layer and the interfacial magnetic layer is adjusted. With this arrangement, it is possible to form a magnetoresistive element that has a low resistance so as to obtain a desired current value, and has a high TMR ratio. | 2009-03-26 |
| 20090080239 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element includes a first reference layer having magnetic anisotropy perpendicular to a film surface, and an invariable magnetization, a recording layer having a stacked structure formed by alternately stacking magnetic layers and nonmagnetic layers, magnetic anisotropy perpendicular to a film surface, and a variable magnetization, and an intermediate layer provided between the first reference layer and the recording layer, and containing a nonmagnetic material. The magnetic layers include a first magnetic layer being in contact with the intermediate layer and a second magnetic layer being not in contact with the intermediate layer. The first magnetic layer contains an alloy containing cobalt (Co) and iron (Fe), and has a film thickness larger than that of the second magnetic layer. | 2009-03-26 |
| 20090080240 | METHOD FOR PRODUCTION OF MRAM ELEMENTS - Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures. | 2009-03-26 |
| 20090080241 | Programming a phase change memory - A programming circuit of a phase change memory cell includes a controllable current generator to supply a programming pulse and an internal control unit coupled to the controllable current generator for stepwise modifying the programming pulse. The internal control unit, in turn, includes a control signal generator to provide the controllable current generator with a plurality of control signals. An oscillator provides a time reference signal and a driving module drives the control signal generator based on the time reference signal. As a result, a programming pulse with stepwise adjustable slope can be produced, including such a pulse with different leading and trailing edges. | 2009-03-26 |
| 20090080242 | Programming a multilevel phase change memory cell - Multilevel phase change memory cells may be programmed forming amorphous regions of amorphous phase change material in a storage region of the phase change memory cell. Crystalline paths of crystalline phase change material are formed through the amorphous regions of amorphous phase change material. Lengths of the crystalline paths are controlled so that at least a first crystalline path has a first length in a first programming state and a second crystalline path has a second length, different from the first length, in a second programming state. | 2009-03-26 |
| 20090080243 | DEVICE CONTROLLING PHASE CHANGE STORAGE ELEMENT AND METHOD THEREOF - Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period. | 2009-03-26 |
| 20090080244 | Refreshing Data of Memory Cells with Electrically Floating Body Transistors - A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle. | 2009-03-26 |
| 20090080245 | OFFSET NON-VOLATILE STORAGE - A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. | 2009-03-26 |
| 20090080246 | Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory - A method and device for trading off inhibit disturb against bit-line disturb in a non-volatile memory where a threshold shift per inhibit disturb is increased, a threshold shift per bit-line disturb is decreased and the total threshold shift over the expected lifetime of the non-volatile memory due to inhibit disturbs is approximately equalized with the total threshold shift over the expected lifetime of the non-volatile memory due to bit-line disturbs. | 2009-03-26 |
| 20090080247 | USING MLC FLASH AS SLC BY WRITING DUMMY DATA - A method for storing data includes designating, in a memory array including cells configured for writing a first number of bits per cell, a group of the cells to which input data are to be written at a second number of bits per cell, smaller than the first number. Dummy data that are independent of the input data are stored in a first set of one or more bits of the cells in the group. The input data are written to a second set of at least one other bit of the cells in the group. | 2009-03-26 |
| 20090080248 | DATA STORAGE AND PROCESSING ALGORITHM FOR PLACEMENT OF MULTI - LEVEL FLASH CELL (MLC) VT - A wireless device that includes a memory device having an engine to execute a voting algorithm to average a memory cell data sensing result over time to provide a charge placement in the memory cell. | 2009-03-26 |
| 20090080249 | Non-volatile memory cell endurance using data encoding - A method and apparatus for storing an n-bit (for n>=2) data block in an array of non-volatile memory cells utilizes a predetermined n+k-bit (for k>=1) encoding selected to reduce the number of programmed cells required to store the n-bit data block. | 2009-03-26 |
| 20090080250 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND OPERATION METHOD THEREOF - A multi-valued nonvolatile semiconductor storage device and an operation method thereof capable of setting a plurality of positive levels having positive threshold voltages and a plurality of negative levels having negative threshold voltages for storing information in a charge storage layer is provided. According to one aspect, there is provided a nonvolatile semiconductor storage device which comprises a storage element provided on a first surface of a semiconductor layer and including a charge storage layer provided with a plurality of positive levels having positive threshold voltages and a plurality of negative levels having negative threshold voltages to store information, and a back electrode provided on a second surface of the semiconductor layer to be opposite to the storage element, the back electrode being configured to apply a voltage which converts information stored in the negative level of the charge storage layer to information having a positive threshold voltage. | 2009-03-26 |
| 20090080251 | NAND FLASH MEMORY DEVICES AND METHODS OF LSB/MSB PROGRAMMING THE SAME - Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main register from the memory cell during a first verifying operation; storing a data bit into the cache register from the memory cell during a second verifying operation; and transferring the data bit to the main register from the cache register. | 2009-03-26 |
| 20090080252 | SEMICONDUCTOR MEMORY DEVICE - A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array. | 2009-03-26 |
| 20090080253 | DEVICE, SYSTEM, AND METHOD OF BIT LINE SELECTION OF A FLASH MEMORY - Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state. Other embodiments are described and claimed. | 2009-03-26 |
| 20090080254 | Gated Diode Nonvolatile Memory Cell Array - A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated. | 2009-03-26 |
| 20090080255 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell array including at least one memory cell, an address storage section containing address information, an address judging circuit for judging whether an input address matches the address information in the address storage section and outputting a result of the judgment, and a write or erase voltage generation circuit for generating a write or erase voltage to be applied to the memory cell are provided. The write or erase voltage generation circuit receives the output result from the address judging circuit and changes a write or erase voltage. | 2009-03-26 |
| 20090080256 | FLASH MEMORY DEVICE AND PROGRAMMING METHOD - Provided are a flash memory device and method of controlling certain program operation voltages. The flash memory device includes a high voltage generation circuit providing a high voltage to a block selection circuit and a program voltage to a row decoder. The high voltage generation circuit includes a charge pump, a high voltage control circuit controlling the charge pump to provide the high voltage, and a program voltage control circuit providing the program voltage in relation to the high voltage, wherein the high voltage control circuit and the program voltage control circuit operate in response to the same control code. | 2009-03-26 |
| 20090080257 | SEMICONDUCTOR DEVICE - The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged. | 2009-03-26 |
| 20090080258 | ERASE METHOD IN THIN FILM NONVOLATILE MEMORY - An erase method applicable to dual-gate memory strings has key advantages over erase methods for other thin-film non-volatile memory strings. The advantages include (a) fast erase without any source-to-body short; (b) flexible erase which erases any number of memory cells in a block (i.e., from none to all cells); (c) source voltage may be set to optimize non-selected string channel boosting; and (d) the thickness of the thin-film device's body can be optimized for scalability. The method uses the access devices of the dual-gate memory cells in a memory string to form inversion channels, so as to provide conductive paths between the memory cells to be erased and a node at a more positive voltage than the erase voltage applied to the gate electrodes of the memory devices to be erased. | 2009-03-26 |
| 20090080259 | Post-Facto Correction For Cross Coupling In A Flash Memory - A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that data are read from the cells by measuring those values. One of the cells and its neighbors are read. The data stored in the cell are estimated, based on the measurements and on respective extents to which the neighbors disturb the reading. Preferably, the method also includes determining those respective extents to which the neighbors disturb the reading, for example based on the measurements themselves. | 2009-03-26 |
| 20090080260 | Programmable CSONOS logic element - A complementary SONOS-type (CSONOS) logic device is programmed and erased with a common voltage. The CSONOS device retains data integrity over extended read endurance cycles. | 2009-03-26 |
| 20090080261 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires at a predetermined potential; and a determining circuit for determining presence or absence of a short circuit between the wires. | 2009-03-26 |
| 20090080262 | METHOD OF PROGRAMMING A NAND FLASH MEMORY DEVICE - A method of programming a NAND flash memory device includes providing a flash memory device, wherein word lines are disposed between a drain selecting line and a source selecting line, wherein a first word line is provided adjacent to the source selecting line and a last word line is provided adjacent to the drain selecting line; and selecting a word line to program memory cells coupled to the selected word line to perform an even LSB program operation and an odd LSB program operation for the selected first word line. Each of the word lines is selected until all of the word lines have been selected, so that the even LSB program operation and the odd LSB program operation can be performed for all of the word lines. The even LSB program operation is performed to store a lower rank data bit in memory cells coupled to an even bit line assigned a selected word line. The odd LSB program operation is performed to store a lower rank data bit in memory cells coupled to an odd bit line assigned to the selected word line. | 2009-03-26 |
| 20090080263 | REDUCING PROGRAMMING VOLTAGE DIFFERENTIAL NONLINEARITY IN NON-VOLATILE STORAGE - A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse. | 2009-03-26 |
| 20090080264 | SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS - In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable. | 2009-03-26 |
| 20090080265 | MULTIPLE BIT LINE VOLTAGES BASED ON DISTANCE - An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements. | 2009-03-26 |
| 20090080266 | DOUBLE DATA RATE (DDR) LOW POWER IDLE MODE THROUGH REFERENCE OFFSET - Embodiments of the invention are generally directed to systems, methods, and apparatuses for a double data rate (DDR) low power idle mode through reference offset. In some embodiments, a host offsets a reference voltage from a termination voltage of a command/address interconnect when the interconnect is tri-stated. Other embodiments are described and claimed. | 2009-03-26 |
| 20090080267 | Generating reference currents compensated for process variation in non-volatile memories - In a current reference generator device, a voltage reference generator stage generates a reference voltage (V | 2009-03-26 |
| 20090080268 | Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage - In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. | 2009-03-26 |
| 20090080269 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage. | 2009-03-26 |
| 20090080270 | MEMORY DEVICE HAVING TERMINALS FOR TRANSFERRING MULTIPLE TYPES OF DATA - A memory device includes terminals for transferring input data and output data to and from a memory array. The memory device also includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information and time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred. | 2009-03-26 |
| 20090080271 | Memory Cell, Memory Device, Device and Method of Accessing a Memory Cell - Implementations are presented herein that relate to a memory cell, a memory device, a device and a method of accessing a memory cell. | 2009-03-26 |
| 20090080272 | DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF GENERATING INFORMATION ABOUT A LOAD CONNECTED TO A DATA PIN OF A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE - A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal. | 2009-03-26 |
| 20090080273 | SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY MEMORY BLOCK AND CELL ARRAY STRUCTURE THEREOF - A semiconductor memory device having a redundancy memory block and a cell array structure thereof, the semiconductor memory device having a plurality of sub-mats constituting a memory cell array, wherein each of the plurality of sub-mats includes a plurality of normal memory blocks of which each includes a plurality of normal memory cells and that are disposed adjacent one another; and at least one redundancy memory block having the same structure as the plurality of normal memory blocks, being disposed adjacent at least one of the plurality of normal memory blocks and having a plurality of redundancy memory cells for a row and column repair, thereby enhancing a redundancy efficiency. | 2009-03-26 |
| 20090080274 | MEMORY CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE - A semiconductor device includes plural switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device, and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors. When the semiconductor device is in operation, ON and OFF of the switching transistors are determined by the data. | 2009-03-26 |
| 20090080275 | REDUCING BIT LINE LEAKAGE CURRENT IN NON-VOLATILE MEMORIES - In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations. | 2009-03-26 |
| 20090080276 | Temperature Dependent Bias for Minimal Stand-by Power in CMOS Circuits - A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the stand-by mode at any particular operating temperature. The disclosed circuit contains at least one monitor FET, which is kept in its off-state, and which has common properties with the large plurality of FET devices. The temperature dependent leakage current of the monitor FET is sensed, and used to generate the bias voltage in proportion to the leakage current. This bias voltage is received by the large plurality FET devices on their gate electrodes, or on their body terminals. | 2009-03-26 |
| 20090080277 | MEMORY CELL FUSE CIRCUIT AND CONTROLLING METHOD THEREOF - A controlling method of a memory cell fuse circuit is provided. The memory cell fuse circuit at least includes a reference cell fuse circuit and a plurality of normal cell fuse circuit. The reference cell fuse circuit includes a reference fuse cell and each the normal cell fuse circuit includes a normal fuse cell. The controlling method includes steps of: power on read and sensing digits of the memory cell fuse circuit; detecting if any normal fuse cell is non blank as failed; programming the reference fuse cell if at least one normal fuse cell is failed until all normal fuse cells are blank; programming and reading the normal fuse cell of each the normal cell fuse circuit; and outputting data of each the normal fuse cell. | 2009-03-26 |
| 20090080278 | CIRCUIT AND METHOD FOR REDUCING POWER IN A MEMORY DEVICE DURING STANDBY MODES - A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs for further reducing the power to portions of the memory device. | 2009-03-26 |
| 20090080279 | STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP - Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage. | 2009-03-26 |
| 20090080280 | Electronic memory device - An electronic memory device includes a bank of memories provided with a cache, a sequencer for providing physical access to said bank of memories, a physical interface for receiving high level memory access requests, a request manager between the physical interface and the sequencer, said request manager includes an input queue for storing the high level memory access requests and an arbitration function which takes account of the data of the cache and the data of the input queue to designate a request which is to be executed, thus allowing the memory bank, the sequencer and the request manager to be provided on a single chip, the physical interface providing the connection of the chip with the outside. | 2009-03-26 |
| 20090080281 | NEGATIVE VOLTAGE DETECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A negative voltage detection circuit including first and second MOS transistor circuits configured to change a dimension size of a transistor based on a control signal, a first comparator circuit, a gate electrode of the second MOS transistor circuit commonly coupled to the gate electrode of the first MOS transistor circuit forming a current mirror circuit, a resistive divider supplied with a negative voltage to be detected, and coupled to the end of the current path of the second MOS transistor circuit to generate a second voltage, a second voltage comparator circuit to compare the second voltage with a reference voltage and to generate a detection signal corresponding to the value of the negative voltage, and a detection circuit for detecting a temperature or power supply voltage, generate the control signal corresponding to the detection result, and supply the control signal to the first and second MOS transistor circuits. | 2009-03-26 |
| 20090080282 | Mixing Machine For Components - An extrusion conveying apparatus, including an extruder that operates as a mixing device and is laterally supplied with components that are to be mixed, in particular components of a rubber mixture or thermoplastic elastomer. A volumetrically operating conveyor, in particular a gear pump, is connected to the output side of the extruder. A rotational speed or feed rate of the extruder is adjustable independently of the feed rate and volume flow of the conveyor. n−1 volumetric subsidiary conveyors are provided for passage of components therethrough where there are n components of a mixture. In particular component n is supplied in an undosed manner. A rotational speed or feed rate of the subsidiary conveyors is adjustable independently of the feed rate of the volumetrically operating conveyor. | 2009-03-26 |
| 20090080283 | Dynamic mixer - A dynamic mixer comprising a rotor, which is coupled to a drive shaft and which is rotationally mounted in a mixing chamber provided inside a rotor housing; at least one first and one second constituent can be fed to said mixing chamber; the drive shaft comprises at least one wavy channel via which the second constituent can be introduced into the mixing chamber; the mixing device is simplified since the second constituent is fed through the channel provided in the drive shaft; no separate connection for supplying the second constituent is provided on the rotor housing whereby enabling the rotor housing to have a simple design and be economically produced; the assembly and disassembly of parts are also simplified, particularly of the rotor and rotor housing, which can be disposed of or cleaned after the mixer has been used, allowing the dynamic mixer to be repeatedly reused. | 2009-03-26 |
| 20090080284 | Device and method for mixing bone cement - Device and method for mixing bone cement, for injection into vertebra in particular, comprising a mixing beaker ( | 2009-03-26 |
| 20090080285 | Processor - An appliance configured to process food includes a primary motor and a secondary motor. The primary motor is configured to rotate a blade connected to a spindle and the blade and the spindle are positioned above a blade platform. The primary motor is mounted on a second platform. The second motor is configured to translate the blade platform and the spindle by a first linkage from a first position to a second position relative to the second platform. | 2009-03-26 |
| 20090080286 | Beater cleaner - Beater Cleaner is a kitchen gadget designed to clean beaters or other similarly shaped products. It consists of tongs that allow squeegee like devices on the ends of each tong to grip the blades of a beater or other similarly shaped object. To use the preferred embodiment of Beater Cleaner, a user uses his thumb and index finger to grab the flexible tongs at the finger grips. He can then tighten or loosen the tongs to fit over various sized and shaped beaters. The rubber squeegees are placed around the beater and the user can scrape the ingredients stuck on the beater into a mixing bowl to insure the maximum amount of ingredients is saved. The user can then use the brush on the opposite end from the squeegees to clean between the blades of the beater. | 2009-03-26 |
| 20090080287 | Method for Estimating Absorption Parameter Q(T) - A method and apparatus for a method for generating an estimated value of absorption parameter Q(t). In one embodiment, the method includes receiving an input seismic trace, applying a time variant Fourier transform to the input seismic trace to generate a time variant amplitude spectrum of the input seismic trace, dividing the natural logarithm of the time variant amplitude spectrum by −πf, and performing a power series approximation to the result with an index starting from one to generate an estimated value of R(t). R(t) is a ratio between traveltime t and the absorption parameter Q(t). The method further includes dividing t by R(t) to generate the estimated value of the absorption parameter Q(t). | 2009-03-26 |
| 20090080288 | METHOD FOR CORRECTING INPUT SEISMIC TRACES FROM DISSIPATIVE EFFECTS - A method and apparatus for correcting an input seismic trace. The method includes receiving the input seismic trace and creating a t by Q gather using the input seismic trace, where t represents traveltime, Q represents absorption parameter, and the t by Q gather has traveltime as the vertical axis and a ratio of t and Q as the horizontal axis. The ratio of t and Q is referred to as R. The method further includes applying an interpolation algorithm to the t by Q gather to derive a corrected input seismic trace. | 2009-03-26 |
| 20090080289 | Methods of hydrocarbon detection using wavelet dominant frequency and a measure of energy loss on the high-frequency side of wavelet dominant frequency - A method in accordance with one embodiment of the invention includes obtaining seismic trace data for a region of interest; processing the seismic trace data to calculate at least one spectrum for at least one sample from the seismic data; calculating at least one dominant frequency (ω | 2009-03-26 |
| 20090080290 | Method and apparatus for correcting the timing function in a nodal seismic data acquisition unit - A wireless seismic data acquisition unit with a wireless receiver providing access to a common remote time reference shared by a plurality of wireless seismic data acquisition units in a seismic system. The receiver is capable of replicating local version of remote time epoch to which a seismic sensor analog-to-digital converter is synchronized. The receiver is capable of replicating local version of remote common time reference for the purpose of time stamping local node events. The receiver is capable of being placed in a low power, non-operational state over periods of time during which the seismic data acquisition unit continues to record seismic data, thus conserving unit battery power. The system implements a method to correct the local time clock based on intermittent access to the common remote time reference. The method corrects the local time clock via a voltage controlled oscillator to account for environmentally induced timing errors. The invention further provides for a more stable method of correcting drift in the local time clock. | 2009-03-26 |
| 20090080291 | DOWNHOLE GAUGE TELEMETRY SYSTEM AND METHOD FOR A MULTILATERAL WELL - A downhole gauge telemetry system for a multilateral well includes a first wireless transceiver located in a primary borehole of the multilateral well, a second wireless transceiver located in a lateral borehole of the multilateral well, a wireless connection between the first wireless transceiver and the second wireless transceiver through which the first and second wireless transceivers exchange data, and a surface transceiver communicatively coupled to the first wireless transceiver. | 2009-03-26 |
| 20090080292 | Microfabricated acoustic transducer with a multilayer electrode - In a capacitive membrane ultrasound transducer, one or more electrodes include multiple layers of conductive or semiconductive material. The layers may be positioned adjacent an insulator or cavity in an arrangement to reduce electrical degradation. For example, a conductive layer with less work function and less resistivity is spaced from an insulator by a conductive layer with more work function and more resistivity. The different layers of electrode material may provide for less electrical degradation due to the type of material used and relative location. | 2009-03-26 |
| 20090080293 | CLOCK HAVING AN ELECTROLUMINESCENT LIGHT (EL) FACE PLATE AND METHOD THEREFOR - An electroluminescent (EL) clock has a face plate. An EL light panel is coupled to a front surface of the face plate. The EL light panel has a multi-color/sectional design. A control circuit is coupled to the EL light panel and attached to a rear surface of the face plate. The control circuit is used to individually control the lighting of each color/section of the multi-color/sectional design. A pair of clock hands is rotatably coupled to the face plate. A clock control device is coupled to the pair of clock hands to rotate the pair of clock hands. A power supply is coupled to the control circuit and the cock control device. | 2009-03-26 |
| 20090080294 | DIAL PLATE UNIT WITH INDICATING MEMBERS AND DIAL PLATE, AND DEVICE WITH THE DIAL PLATE UNIT - A dial plate unit includes a dial plate provided with an outside dial plate element having an opening, an inside dial plate element spaced at a predetermined distance from the outside dial plate element, and a frame member provided in the opening of the outside dial plate element and closing a gap between the periphery of the opening and a part of the inside dial plate element corresponding to the periphery of the opening. The unit further includes one indicating member disposed in a side of the outside dial plate element opposite to the inside dial plate element and being movable along the outside dial plate element, and one auxiliary indicating member disposed in the opening and being movable between the outside and inside dial plate elements. A device using the dial plate unit includes a indicating member operating module which operates the indicating member and auxiliary indicating member. | 2009-03-26 |
| 20090080295 | LIGHT-ASSISTED MAGNETIC HEAD APPARATUS, LIGHT-ASSISTED MAGNETIC RECORDING APPARATUS, AND LIGHT-ASSISTED MAGNETIC RECORDING METHOD - A light-assisted magnetic head apparatus is provided. The light-assisted magnetic head apparatus includes a focusing optical system and a thin magnetic head having a main magnetic pole. The focusing optical system includes a hemispherical or hyper-hemispherical solid immersion lens. The thin-film magnetic head includes a metal layer that causes surface plasmon resonance on a light-incident side of the main magnetic pole. | 2009-03-26 |
| 20090080296 | OPTICAL DISC - An optical disc includes an electromagnetic coupling module mounted therein. The electromagnetic coupling module includes a wireless IC chip and a feeder circuit substrate in which a feeder circuit including a resonant circuit having a predetermined resonant frequency is disposed. The electromagnetic coupling module is electromagnetically coupled to a reflective film defining a metal thin film of the optical disc, and the reflective film defines an antenna or radiation pattern of the electromagnetic coupling module. | 2009-03-26 |
| 20090080297 | FREQUENCY-MODULATED CODING AND DATA RECORDING AND STORAGE USING PLASMONIC NANOSTRUCTURES - A frequency-modulated coding and data recording and storage device that uses plasmonic-dielectric nanostructures of concentric two-layer core-shell design to store data includes a flat transparent substrate having a top surface divided into cells with side dimension d on the order of tens of nanometers and a core-shell plasmonic-dielectric nanostructure disposed in each cell. Each plasmonic nanostructure of concentric core-shell has a predetermined ratio of radii and a predetermined aspect ratio such that when an infrared or visible wavelength signal is applied to each said core-shell plasmonic-dielectric nanostructure a peak scattering amplitude of the applied signal is at different plasmonic resonance frequencies for core-shell plasmonic-dielectric nanostructures with different ratio of radii and different aspect ratios. The sampled values of a signal to be recorded are assigned to each cell and the ratio of radii and/or aspect ratios of the core-shell plasmonic-dielectric nanostructures in the assigned cells are selected to provide a corresponding plasmonic resonant frequency. | 2009-03-26 |
| 20090080298 | OPTICAL HEAD, OPTICAL HEAD MANUFACTURING METHOD AND OPTICAL DISC DEVICE - It is aimed to provide an optical head, an optical head manufacturing method and an optical disc device capable of correcting coma aberration generated due to different positions of emission points of a plurality of laser lights having different wavelengths. | 2009-03-26 |
| 20090080299 | CONTROL METHOD OF OPTICAL DISC DRIVE - The present invention provides a control method of an optical disc drive, including the steps of: (a) entering a writing state; (b) checking if a reading command for requesting recorded data is received, wherein when the reading command is not received, then continuing a writing process, and when the reading command is received, then going to step (c); (c) interrupting the writing process; (d) switching to a reading state; (e) reading the recorded data according to the reading command; and (f) switching to the writing state. | 2009-03-26 |
| 20090080300 | Data transmission method, optical disc recording method and optical disc recording apparatus - A data transmission method for a large amount of contents information, comprises the following steps of:
| 2009-03-26 |
| 20090080301 | Method of Recording Information On and Reproducing Information From Optical Disk and Apparatus for the Same - There is provided an information recording and reproducing method and an apparatus for the same capable of optimizing the shift adjustment of a recording pulse recorded in an optical disk even at the time of recording information on the optical disk at a high speed. The shift adjustment value of the recording pulse optimized at a low speed recording on an optical disk is multiplied by a constant value to be taken as the optimum shift conditions of the recording pulse at the high speed recording. | 2009-03-26 |
| 20090080302 | DISK DRIVE AND INFORMATION PROCESSING SYSTEM HAVING THE SAME - A disk drive controls the rotational speed of a disk to an appropriate value. A system controller of the drive stores data read from a disk and read-ahead data into buffer memory. A time interval ti at which the buffer memory becomes full is measured, and the time interval ti is compared with a predetermined lower limit value t | 2009-03-26 |
| 20090080303 | Storage Media Housing Device - A storage media housing device includes a housing means ( | 2009-03-26 |
| 20090080304 | INFORMATION RECORDING MEDIUM, RECORDING AND/OR REPRODUCING APPARATUS, AND RECORDING AND/OR REPRODUCING METHOD - An information recording medium, recording and/or reproducing apparatuses, and recording and/or reproducing methods which enable effective management of a last data recording address of a data area of the information recording medium. The information recording medium includes a data area for recording user data, temporary recording management information for managing a data recording status of the data area and temporary disc management information for managing the information recording medium, wherein the temporary disc management information includes first information regarding a last recorded location of data in the data area and second information regarding whether the information regarding the last recorded location is consistent with an actual last recorded location of the data area. | 2009-03-26 |
| 20090080305 | DISC DISCRIMINATION METHOD AND APPARATUS - A method for discriminating a type of disc. The method includes receiving a signal having at least first and second peak points generated by an optical beam reflected from a record layer of the disc, comparing amplitudes of the first and second peak points, and determining the type of the disc based on a result of the comparing step. | 2009-03-26 |
| 20090080306 | OPTICAL DISK DEVICE AND OPTICAL DISK DISCRIMINATING METHOD - An optical disk discriminating method and an optical disk device which can detect reflected rays for making discrimination among kinds of optical disks with high accuracies. By switching a plurality of lasers and moving a spherical aberration corrector while moving an objective lens to cause it to approach or keep away from an optical disk, rays reflected light from the optical disk can be detected with high accuracies. Discrimination among the kinds of a plurality of optical disks can be made on the basis of signals generated from the detected reflected rays. This ensures that the kind of an optical disk can be determined through one operation of sweeping. | 2009-03-26 |
| 20090080307 | Method of manufacturing optical head including the step of adjusting parallelism of light beam - A method for manufacturing an optical head having a laser beam emitting device that emits a light beam of a predetermined wavelength, an objective lens that focuses the light beam on an optical recording medium and a parallelism adjusting lens that is disposed on an optical path between the laser beam emitting device and the objective lens, wherein the parallelism adjusting lens is configured to change parallelism of the laser beam, is disclosed. The method comprise the step of adjusting the parallelism of the light beam that has passed through the parallelism adjusting lens by adjusting a distance between the laser beam emitting device and the parallelism adjusting lens while causing the laser beam emitting device to emit the light beam and causing the light beam to pass through the parallelism adjusting lens. | 2009-03-26 |
