12th week of 2010 patent applcation highlights part 45 |
Patent application number | Title | Published |
20100077175 | Method of Enhancing Command Executing Performance of Disc Drive - For decreasing seeks generated when switching an execution flow between commands to enhance read and write performances of a disc drive, a command is implemented with a specifically-designed data structure, and commands having neighboring physical addresses and the same type of read or write operations are grouped and linked together. With the aid of command groups, seeks between commands are significantly decreased, though starvation may arise. A few techniques are further provided for preventing starvation of command groups and for preserving the benefits of decreasing seeks. | 2010-03-25 |
20100077176 | METHOD AND APPARATUS FOR IMPROVED CALCULATION OF MULTIPLE DIMENSION FAST FOURIER TRANSFORMS - Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide. | 2010-03-25 |
20100077177 | Multiple Processor Core Vector Morph Coupling Mechanism - One embodiment of the invention provides a processor. The processor generally includes a first and second processor core, each having a plurality of pipelined execution units for executing an issue group of multiple instructions and scheduling logic configured to issue a first issue group of instructions to the first processor core for execution and a second issue group of instructions to the second processor core for execution when the processor is in a first mode of operation and configured to issue one or more vector instructions for concurrent execution on the first and second processor cores when the processor is in a second mode of operation. | 2010-03-25 |
20100077178 | Method and apparatus for extending processing time in one pipeline stage - A single channel or multi-channel system that requires the execution time of a pipeline stage to be extended to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port connected to a “bypass switch” (or multiplexer). Input date is sent either to a processor, for processing, or to a processor output port, in which case no processing is performed, through a register using at least one clock cycle to move date from register input to register output. For a single channel requiring an execution time twice the time interval between two consecutive input data, two processors are interconnected by the bypass switch. Data flows from the first processor at the input of the system, through the bypass switches of the interconnected processors, to the output. The bypass switches are configures with respect to the processors such that the system data rate is independent of processor number. | 2010-03-25 |
20100077179 | METHOD AND APPARATUS FOR COHERENT DEVICE INITIALIZATION AND ACCESS - A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket. | 2010-03-25 |
20100077180 | GENERATING PREDICATE VALUES BASED ON CONDITIONAL DATA DEPENDENCY IN VECTOR PROCESSORS - Embodiments of a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of conditions. During operation, a processor receives instructions for generating one or more predicate values based on actual dependencies, where a given predicate value indicates data elements that may be safely evaluated in parallel, and where the given actual dependency occurs when the pair of conditions matches one or more criteria. Then, the processor executes the instructions for generating the one or more predicate values. | 2010-03-25 |
20100077181 | System and Method for Issuing Load-Dependent Instructions in an Issue Queue in a Processing Unit of a Data Processing System - A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to indentifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction. | 2010-03-25 |
20100077182 | GENERATING STOP INDICATORS BASED ON CONDITIONAL DATA DEPENDENCY IN VECTOR PROCESSORS - Embodiments of a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of conditions. During operation, a processor receives instructions for generating one or more stop indicators based on actual dependencies, where a given stop indicator indicates the position of a given actual dependency that can lead to different results when the data elements are processed in parallel than when the data elements are processed sequentially, and where the given actual dependency occurs when the pair of conditions matches one or more criteria. Then, the processor executes the instructions for generating the one or more stop indicators. | 2010-03-25 |
20100077183 | CONDITIONAL DATA-DEPENDENCY RESOLUTION IN VECTOR PROCESSORS - Embodiments of a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of conditions. During operation, a processor receives instructions for generating a vector of tracked positions of actual dependencies, where a given tracked position indicates the position of a given actual dependency, and where the given actual dependency occurs when the pair of condition matches one or more criteria. Then, the processor executes the instructions for generating the vector of tracked positions. | 2010-03-25 |
20100077184 | METHOD AND APPARATUS FOR REMOVING A PIPELINE BUBBLE - One embodiment of the present invention provides a system for augmenting a pipeline with a bubble-removal circuit. During operation, the system generates a bubble-removal circuit which determines a clock-enable signal based at least on whether an upstream register has valid data and whether the pipeline is stalled. Next, the system gates the clock signal using the clock-enable signal. The augmented pipeline can determine whether a first register contains invalid data, which is associated with a bubble. Next, the augmented pipeline determines whether a second register contains valid data, wherein the second register is adjacent to and upstream from the first register. If the first register contains invalid data and the second register contains valid data, the augmented pipeline replaces the invalid data of the first register with valid data based on the valid data in the second register without propagating the invalid data to a downstream register. | 2010-03-25 |
20100077185 | MANAGING THREAD AFFINITY ON MULTI-CORE PROCESSORS - Embodiments of the invention intelligently associate processes with core processors in a multi-core processor. The core processors are asymmetrical in that the core processors support different features or provide different resources. The features or resources are published by the core processors or otherwise identified (e.g., via a query). Responsive to a request to execute an instruction associated with a thread, one of the core processors is selected based on the resource or feature supporting execution of the instruction. The thread is assigned to the selected core processor such that the selected core processor executes the instruction and subsequent instructions from the assigned thread. In some embodiments, the resource or feature is emulated until an activity limit is reached upon which the thread assignment occurs. | 2010-03-25 |
20100077186 | PROCESSING APPARATUS, PROCESSING SYSTEM, AND COMPUTER READABLE MEDIUM - A processing apparatus includes: an execution unit; an execution request accept unit; a process instruction unit; an information leakage preventing process execution unit; a recording unit; and a transmission unit. | 2010-03-25 |
20100077187 | System and Method to Execute a Linear Feedback-Shift Instruction - A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data. | 2010-03-25 |
20100077188 | EMERGENCY FILE PROTECTION SYSTEM FOR ELECTRONIC DEVICES - Disclosed is a method, system, and computer readable medium for completing critical write functions to a non-volatile memory (NVM) system within an electronic device upon experiencing a sudden or unexpected loss of the main power to the electronic device. A sudden loss of main external power is detected and determined if the loss of power crosses a minimum threshold level. If it does, an interrupt is generated to prevent new write requests. One embodiment uses a software interrupt and another embodiment uses a hardware interrupt. A switch over to a short term reserve internal power source occurs and the NVM write function in progress at the time of the power loss is completed. Upon completion of the NVM write operation, less critical shutdown activities can commence. | 2010-03-25 |
20100077189 | COMPUTER SYSTEM HAVING MUSIC PLAYING FUNCTION - A computer system includes an input output (I/O) device, an I/O control chip, an audio file processing unit, an audio interface, an audio chip, and a power supply. The I/O control chip is configured for receiving a music playing command from the I/O input device, and outputting an audio control signal according to the music playing command. The audio file processing unit stores audio files, and receives the audio control signal to read a corresponding audio file and output an audio processing signal. The audio interface is configured for connecting to an audio device. The audio chip is configured for receiving and processing the audio file according to the audio processing signal, and outputting an audio signal to the audio interface. The power supply supplies standby power to the I/O control chip, the audio file processing unit, and the audio chip when the computer system is not booted up. | 2010-03-25 |
20100077190 | Method To Retain Crucial Thin Client System Settings - A system comprises a first non-volatile storage device that contains an operating system. The system also comprises a second non-volatile storage device that contains basic input/output system (BIOS) code and at least one parameter used by the operating system or by a network interface, and not by the BIOS code. | 2010-03-25 |
20100077191 | INFORMATION PROCESSOR, EXTERNAL MEMORY AND CONTROL METHOD - An information processor includes a system control unit configured to start up one operating system, a drive unit configured to be driven in response to start-up of the one operating system, an external memory storing another operating system, and an interface (I/F) for the external memory which is connected to the external memory. The system control unit serves to stop the drive unit by being connected to the I/F for the external memory and to start up the other operating system from the external memory. | 2010-03-25 |
20100077192 | COMPUTER, BOOTING SOFTWARE PRODUCT AND COMPUTER BOOTING METHOD - A computer includes an application system, a storage device and a basic input output system (BIOS). The application system can be respectively coupled to the storage device and the BIOS, set at least a multimedia file as a preset playing file according to an input instruction and store the preset playing file into the storage device. The application system can further generate a log file according to the input instruction and the storage position of the preset playing file, wherein the log file is sent to the BIOS. The BIOS has a file access module, so that the BIOS can acquire the preset playing file from the storage device according to the log file for playing during booting the computer. | 2010-03-25 |
20100077193 | METHOD AND APPARATUS FOR ASSIGNING A MEMORY TO MULTI-PROCESSING UNIT - A memory mapping apparatus for a multi-processing unit includes at least one memory matching unit configured to perform matching between a plurality of processing units and a plurality of memories, a memory controller configured to perform access control and arbitration for the respective memories, a memory mapping unit configured to include a window map for the respective processing units, make correspond the memories to the respective processing units with reference to the window map, and assign part of the entire address region of the corresponding memory, and a window map change unit configured to change a window map for a processing unit in which a request to use the memory has occurred in response to a request to use the memory from any one of the processing units. | 2010-03-25 |
20100077194 | TURBO BOOT SYSTEMS AND METHODS - A computer system includes a hard disk drive and a non-volatile semiconductor memory. The hard disk drive stores a first set of data that includes boot up data. The non-volatile semiconductor memory is distinct from semiconductor memory of the hard disk drive and semiconductor memory of a host of the computer system. A turbo boot driver module stores the boot up data in the non-volatile semiconductor memory and transfers the boot up data from the non-volatile semiconductor memory to a file system of the host during a boot up mode of the host. | 2010-03-25 |
20100077195 | METHOD AND A MEMORY UNIT FOR BOOTING A SERVER - The invention relates to a server with at least one removable storage unit. This removable storage unit is designed to boot a server. The removable storage unit, which is for example a memory card, comprises a non-writable storage, which stores a boot-loader and reference installation files, and a writable secondary storage, which is designed to store installation files. The boot-loader checks a data content of the secondary storage and a data content of a primary storage of the server. In case the secondary storage is not empty and the primary storage is either empty or comprises a different data content than the secondary storage, the boot-loader stores the data content of the secondary storage in the primary storage of the server. | 2010-03-25 |
20100077196 | COMPUTER AND METHOD FOR CONNECTING COMPUTER TO NETWORK DISK - A computer includes a BIOS and a communication system. The BIOS includes a disk access interface module and a ram disk. The disk access interface module accesses a remote disk, and the ram disk stores data retrieved from the remote disk. The communication system includes a storage medium having a preset format and a communication protocol layer module. The storage medium having the preset format has a network chip driver to allow the BIOS to call and connect to the network. Thus, the computer may communicate with the remote disk. The communication protocol layer module makes the computer communicate with the remote disk through the network chip driver. | 2010-03-25 |
20100077197 | NON-VOLATILE MEMORY CACHE PERFORMANCE IMPROVEMENT - In order to provide a more efficient persistent storage device, one or more long-term storage media are included along with a non-volatile memory. In one embodiment, one portion of the non-volatile memory is used as a write buffer and a read cache for writes and reads to the long-term storage media. Interfaces are provided for controlling the use of the non-volatile memory as a write buffer and a read cache. Additionally, a portion of the non-volatile memory is used to provide a direct mapping for specified sectors of the long-term storage media. Descriptive data regarding the persistent storage device is stored in another portion of the non-volatile memory. | 2010-03-25 |
20100077198 | INSULIN PUMP PROGRAMMING SOFTWARE FOR SELECTIVELY MODIFYING CONFIGURATION DATA - Insulin pump programming software is disclosed that permits selectively modifying insulin pump configuration files. The software facilitates retrieving a source file consisting of a configuration file or portion thereof from a source location. The source file may include general configuration data and insulin delivery data. Once retrieved, the source file may be edited, then the entire source file or a portion thereof may be saved to a target configuration file at one or more target locations. Only the portion of the target configuration file corresponding to the saved source file or portion thereof is replaced by the source file. | 2010-03-25 |
20100077199 | Systems And Methods Of Secure BIOS Update - Systems and methods of securely updating BIOS are disclosed. One such system comprises a reprogrammable memory, a first and a second register, and comparison logic. The reprogrammable memory comprises a first portion and a protect input. The protect input is configured to disallow writes to at least the first portion when the memory protect input is at a first levels, and to allow writes to at least the first portion when the protect input is at a second level. The comparison logic is configured to drive a comparison output to a third level responsive to the first and second registers having equal values, and to drive the comparison output to a fourth level responsive to the first and second registers having different values. The comparison output is electrically coupled to the memory protect input. | 2010-03-25 |
20100077200 | METHOD AND APPARATUS FOR SWITCHING PERFORMANCE - A method and an apparatus for switching performance are provided. The method includes: providing a performance adjustable circuit working at a specific threshold frequency; determining a working power supply of the performance adjustable circuit; when the working power supply is higher or lower than a specific threshold level range corresponding to the specific threshold, adjusting the performance adjustable circuit to work at another specific threshold frequency. | 2010-03-25 |
20100077201 | INFORMATION PROCESSING UNIT, TERMINAL UNIT, INFORMATION PROCESSING METHOD, KEY GENERATION METHOD AND PROGRAM - There is provided an information processing unit enabling reduction of the number of keys to be held by a terminal unit and the amount of calculations necessary for decryption of encrypted data. The information processing unit configures an entire binary tree made up of n-number of leaf nodes, a root node and a plurality of intermediate nodes different from the root node and the leaf nodes and divides the entire tree into a plurality of base subtrees including n | 2010-03-25 |
20100077202 | DIGITAL RIGHTS MANAGEMENT PROVISION APPARATUS, SYSTEM, AND METHOD - Provided is digital rights management (DRM) provision technology, and more particularly, are an apparatus, system, and method which can easily provide content using one or more DRM systems. A DRM provision apparatus includes a content download unit which downloads encrypted real content and dummy content from a download server and which manages the downloaded real content and dummy content; a license management unit which manages a license issued by a license server; and a processing unit which manages the downloaded real content and dummy content and the issued license. | 2010-03-25 |
20100077203 | RELAY DEVICE - “Leakage”, “falsifying”, “masquerading”, “approach”, or “attack” of data on the Internet are prevented in a communication between a personal computer and the outside thereof without installing software or hardware in the personal computer. An intermediary apparatus includes NIC (Network Interface Card) drivers connected to networks respectively and a network layer and a transport layer which include “TCP/IP” defining a communication method for communicating while carrying out routing (ROUTING) between any two nodes and is provided for a physical layer and a data-link layer including the NIC drivers. Between the data-link layer and network layer, the function of “TCP2” can be provided. | 2010-03-25 |
20100077204 | INFORMATION PROCESSING APPARATUS, MANAGEMENT APPARATUS, COMMUNICATION SYSTEM AND COMPUTER READABLE MEDIUM - An information processing apparatus connected to a management apparatus via a communication line, includes: an other-apparatuses information acquisition unit that acquires information concerning a plurality of other information processing apparatuses from the management apparatus; a key registration unit that registers first keys to be used in encrypted communication between the information processing apparatus and each of the plurality of other information processing apparatuses, into a storage unit; a key transmitting unit that collectively transmits the first keys to the management apparatus; and a key acquisition unit that acquires from the management apparatus second keys that each has been transmitted to the management apparatus from the respective one of plurality of other information processing apparatuses. The key registration unit further registers the second keys acquired by the key acquisition unit into the storage unit. | 2010-03-25 |
20100077205 | System and Method for Cipher E-Mail Protection - The preferred embodiments of the present invention disclose a security transformation system which includes an e-mail client, a cipher proxy, a dictionary database and an Internet e-mail system. The system is capable of generating and receiving messages and performing a cipher substitution and encryption of key fields of messages when they are stored at a user's Internet e-mail system. When the messages are received or accessed the system permits deciphering and decrypting the message using a reverse security transformation The preferred embodiments of the method of the present invention comprises steps of generating and receiving messages at an Internet e-mail system, performing a security transformation on said messages, encrypting said messages, updating a cipher dictionary at a cipher proxy, and decoding and decrypting the messages when accessed by a user. | 2010-03-25 |
20100077206 | DIGITAL RIGHTS MANAGEMENT PROVISION APPARATUS, SYSTEM, AND METHOD - Provided is digital rights management (DRM) provision technology, and more particularly, are an apparatus, system, and method which can easily provide content using one or more DRM systems. A DRM provision apparatus includes a content download unit which downloads encrypted real content and dummy content from a download server and which manages the downloaded real content and dummy content; a license management unit which manages a license issued by a license server; and a processing unit which manages the downloaded real content and dummy content and the issued license. | 2010-03-25 |
20100077207 | COMMUNICATIONS APPARATUS, COMMUNICATIONS SYSTEM, AND METHOD OF SETTING CERTIFICATE - An apparatus in a system which includes at least a high-level apparatus and a plurality of low-level apparatuses, said apparatus being one of the low-level apparatuses. The apparatus includes a storage unit configured to store an individual certificate set and a common certificate set and a communication unit configured to transmit own authentication information to the high level apparatus to allow the high level apparatus to perform decryption to authenticate the validity of the apparatus. | 2010-03-25 |
20100077208 | CERTIFICATE BASED AUTHENTICATION FOR ONLINE SERVICES - In one embodiment, a client computer system receives user credentials from a computer user. The client computer system formulates a system identifier that uniquely identifies the system, and sends the received user credentials with the system identifier to an authentication service running on a datacenter server. The authentication service is configured to authenticate the user credentials and generate an authentication certificate based on the user credentials and the system identifier. The client computer system receives the generated authentication certificate from the authentication service and stores the received authentication certificate. The computer system receives an authentication request to authenticate the user subsequent to storing the certificate and, in response to the authentication request, automatically sends the stored authentication certificate to indicate to the datacenter server that the user is authorized to access the datacenter-provided information, without prompting the user to provide user credentials for authentication. | 2010-03-25 |
20100077209 | GENERATING HARD INSTANCES OF CAPTCHAS - Methods and systems are described for enhancing the difficulty of captchas and enlarging a core of available captchas that are hard for an automated or robotic user to crack. | 2010-03-25 |
20100077210 | CAPTCHA IMAGE GENERATION - Methods and systems are described for generating captchas and enlarging a core of available captchas that are hard for an automated or robotic user to crack. | 2010-03-25 |
20100077211 | BIT-ERROR RATE TESTER WITH PATTERN GENERATION - Identical random, or pseudorandom, test patterns in a peripheral device (“receiver”) to be tested, and in a transmitter that sends the test pattern to the receiver, are generated by using pattern generation circuitry in both the transmitter and the receiver that operates identically based on a pattern input value, or seed. The same seed is input to both the transmitter and the receiver. The pattern generation circuitry can be a linear-feedback shift register (“LFSR”), which generates pseudorandom numbers, and identical LFSRs in both the transmitter and the receiver are provided with the same seed. The LFSR may be reseeded periodically. The new seed can be an output of the LFSR itself, or a second LFSR is provided whose output is used to determine the new seed for the first LFSR. Alternatively, cryptographic modules are used in the transmitter and the receiver to generate the test pattern based on identical keys. | 2010-03-25 |
20100077212 | On-Demand Protection And Authorization Of Playback Of Media Assets - On-demand protection and authorization of playback of media assets includes receiving digital media at a server computer, storing intermediary data in a data store, and receiving a request from a client for the digital media. The method also includes generating a protected copy of the digital media from the digital media and the intermediary data. The method also includes storing a description of the protected copy in a database and sending the protected copy to the client. The method also includes receiving a request from the client to access the digital media and reading the description from the database based on information in the request. The method also includes sending a response to the client, the response indicating whether the client is authorized to access the digital media, and the response including cryptographic data to decrypt the protected digital media if the client is authorized to access the digital media. | 2010-03-25 |
20100077213 | TRUSTED NETWORK CONNECT SYSTEM BASED ON TRI-ELEMENT PEER AUTHENTICATION - A trusted network connect (TNC) system based on tri-element peer authentication (TePA) is provided. An network access requestor (NAR) of an access requestor (AR) is connected to a TNC client (TNCC), and the TNCC is connected to and integrity measurement collector (IMC | 2010-03-25 |
20100077214 | Host Device and Method for Protecting Data Stored in a Storage Device - The owner of proprietor interest is in a better position to control access to the encrypted content in the medium if the encryption-decryption key is stored in the medium itself and substantially inaccessible to external devices. Only those host devices with the proper credentials are able to access the key. An access policy may be stored which grants different permissions (e.g. to different authorized entities) for accessing data stored in the medium. A system incorporating a combination of the two above features is particularly advantageous. On the one hand, the content owner or proprietor has the ability to control access to the content by using keys that are substantially inaccessible to external devices and at the same time has the ability to grant different permissions for accessing content in the medium. Thus, even where external devices gain access, their access may still be subject to the different permissions set by the content owner or proprietor recorded in the storage medium. When implemented in a flash memory, the above features result in a particularly useful medium for content protection. Many storage devices are not aware of file systems while many computer host devices read and write data in the form of files. The host device provides a key reference or ID, while the storage device generates a key value in response which is associated with the key ID, which is used as the handle through which the memory retains complete and exclusive control over the generation and use of the key value for cryptographic processes, while the host retains control of files. | 2010-03-25 |
20100077215 | METHOD FOR TRANSMITTING INFORMATION WITH A SEMANTIC ACKNOWLEDGEMENT OF RECEIPT - The method for transmitting information between an emitter and a receiver includes a phase of authentication of the receiver using a pair of encryption keys of the private key/public key types, a phase of sending a series of information from the emitter to the receiver, a phase of retransmission by the receiver towards the emitter of an acknowledgement of receipt including at least one element semantically associated with the series of information transmitted. | 2010-03-25 |
20100077216 | METHOD FOR ENHANCING NETWORK APPLICATION SECURITY - A method for securing communications between a server and an application downloaded over a network onto a client of the server is disclosed. A first request is received from the client, and in response a session credential security token is generated and sent to the client. A second request is received from the client to download the application and includes the value of the session credential security token. The server verifies that the value of the session credential security token is valid and, if so, generates a second security token that is tied to the session credential security token. The second token is embedded in application code and then the application code is sent to the client. A subsequent request for data from the application running on the client includes the value of the session credential security token and the value of the embedded security token. Verification of validity of the values of the session credential security token and the second security token received with the data request then occurs at least in part by determining that the values are cryptographically tied to one another. Upon verification, the requested data is sent to the client. | 2010-03-25 |
20100077217 | DIGITAL RIGHTS MANAGEMENT SYSTEM AND METHOD - The present invention concerns application of digital rights management to industrial automation devices including programmable logic controllers (PLCs), I/O devices, and communication adapters. Digital rights management involves a set of technologies for controlling and managing access to device objects and/or programs such as ladder logic programs. Access to automation device objects and/or programs can be managed by downloading rules of use that define user privileges with respect to automation devices and utilizing digital certificates, among other things, to verify the identity of a user desiring to interact with device programs, for example. Furthermore, the present invention provides for secure transmission of messages to and amongst automation devices utilizing public key cryptography associated with digital certificates. | 2010-03-25 |
20100077218 | SYSTEM AND METHOD FOR ELECTRONIC DOCUMENT MANAGEMENT, ORGANIZATION, COLLABORATION, AND SUBMISSION IN CLINICAL TRIALS - According to the present invention, there is provided a system and method for the management, organization, collaboration, and submission of electronic files and documents associated with a clinical trial. The system of the present invention enables users to create and easily access a central document repository. The system of the present invention includes various tools for the management, organization, collaboration, and editing of the documents and files stored within the system, as well as tools which enable automated regulatory submissions of required documents and files. | 2010-03-25 |
20100077219 | Optimization methods for the insertion, protection, and detection of digital watermarks in digital data - Disclosed herein are methods and systems for encoding digital watermarks into content signals. Also disclosed are systems and methods for detecting and/or verifying digital watermarks in content signals. According to one embodiment, a system for encoding of digital watermark information includes: a window identifier for identifying a sample window in the signal; an interval calculator for determining a quantization interval of the sample window; and a sampler for normalizing the sample window to provide normalized samples. According to another embodiment, a system for pre-analyzing a digital signal for encoding at least one digital watermark using a digital filter is disclosed. According to another embodiment, a method for pre-analyzing a digital signal for encoding digital watermarks comprises: (1) providing a digital signal; (2) providing a digital filter to be applied to the digital signal; and (3) identifying an area of the digital signal that will be affected by the digital filter based on at least one measurable difference between the digital signal and a counterpart of the digital signal selected from the group consisting of the digital signal as transmitted, the digital signal as stored in a medium, and the digital signal as played backed. According to another embodiment, a method for encoding a watermark in a content signal includes the steps of (1) splitting a watermark bit stream; and (2) encoding at least half of the watermark bit stream in the content signal using inverted instances of the watermark bit stream. Other methods and systems for encoding/decoding digital watermarks are also disclosed. | 2010-03-25 |
20100077220 | Optimization methods for the insertion, protection, and detection of digital watermarks in digital data - Disclosed herein are methods and systems for encoding digital watermarks into content signals. Also disclosed are systems and methods for detecting and/or verifying digital watermarks in content signals. According to one embodiment, a system for encoding of digital watermark information includes: a window identifier for identifying a sample window in the signal; an interval calculator for determining a quantization interval of the sample window; and a sampler for normalizing the sample window to provide normalized samples. According to another embodiment, a system for pre-analyzing a digital signal for encoding at least one digital watermark using a digital filter is disclosed. According to another embodiment, a method for pre-analyzing a digital signal for encoding digital watermarks comprises: (1) providing a digital signal; (2) providing a digital filter to be applied to the digital signal; and (3) identifying an area of the digital signal that will be affected by the digital filter based on at least one measurable difference between the digital signal and a counterpart of the digital signal selected from the group consisting of the digital signal as transmitted, the digital signal as stored in a medium, and the digital signal as played backed. According to another embodiment, a method for encoding a watermark in a content signal includes the steps of (1) splitting a watermark bit stream; and (2) encoding at least half of the watermark bit stream in the content signal using inverted instances of the watermark bit stream. Other methods and systems for encoding/decoding digital watermarks are also disclosed. | 2010-03-25 |
20100077221 | System and Method for Wirelessly Transacting Access to a Set of Events and Associated Digital Content/Products - One or more content providers push data related to: movies, movie products, digital movie content over a network (e.g., a LAN, a WAN, the Internet, or a wireless network) onto an information filling station which, in turn, wirelessly transacts (over a network based on the 802.11b protocol) and transmits any requested data to a portable computer-based device (e.g., laptop, a pen-based computer device, a PDA, a wireless phone, or a pager). The portable device performs financial transactions for: purchasing movie tickets (directly or via auctions), downloading digital entertainment content of interest (e.g., copy of a movie of interest, copy of a movie identified based on a pre-stored profile, copy of soundtrack of a movie of interest), or movie related products. Any purchased digital content is either transferred wirelessly onto the portable device or, optionally, sent on a storage medium to a physical address associated with the profile. | 2010-03-25 |
20100077222 | METHOD FOR PRODUCING ACKNOWLEDGED TRANSACTION DATA AND CORRESPONDING DEVICE - A method and a display preparation unit are proposed for the execution of a transaction during which transaction data are processed which have to be confirmed by a user. The display preparation unit ( | 2010-03-25 |
20100077223 | AUTHENTICATION DEVICE, AUTHENTICATION SYSTEM, AUTHENTICATION METHOD, PROGRAM AND RECORDING MEDIUM - To prevent an input password from being stolen by an invalid authentication device. An authentication device | 2010-03-25 |
20100077224 | MULTIPLATFORM INDEPENDENT BIOMETRIC IDENTIFICATION SYSTEM - An independent biometric identification system having an independent biometric identification server and a capture device connected to a user's system to receive biometric characteristics of a user. The independent biometric identification server causes the user to identify its capture device to the server and provides biometric identification of the user independently of individual applications implemented on the user's system. The system further includes a biometric capture agent application chosen by the independent biometric identification server and individually developed for the identified capture device. Finally, the system includes a biometric database storing the biometric characteristics of the user. | 2010-03-25 |
20100077225 | Protection Against Side Channel Attacks with an Integrity Check - The invention relates to a method for protecting a sensitive operation by checking the integrity of at least a subset of the data manipulated by the sensitive operation. Data to be checked are divided into blocks, an intermediate integrity check value being computed for each block, the intermediate integrity check values being computed in random order. The invention also relates to a cryptographic device wherein at least one sensitive operation of the cryptographic device is protected by a method according to the invention. | 2010-03-25 |
20100077226 | ENCRYPTION DEVICE AND ENCRYPTION OPERATION METHOD - Provided is an encryption device which can effectively use a hardware encryption engine and reduce a packet processing delay of a real time application. In this device, an approval unit ( | 2010-03-25 |
20100077227 | CRYPTOGRAPHIC PROCESSING DEVICE AND METHOD FOR ADAPTING TO SHARED-CACHE ATTACKS - Embodiments of a cryptograph processing device and method for adapting to shared-cache attacks are generally described herein. Other embodiments may be described and claimed. In some embodiments, the cryptographic processing device comprises first and second processing units, and a cache that is shared by the first and second processing units. The first processing unit may monitor a number of cache misses that occur during the performance of a first cryptographic process and may switch to performing a second cryptographic process after the number of cache misses exceeds a threshold. | 2010-03-25 |
20100077228 | Implementing Portable Content Protection to Secure Secrets - A source-level compiler may randomly select compilation conventions to implement portable content protection, securing the secrets embedded in a program by shuffling associated data. The program may be developed using a source language that is applicative on the associated data. To obscure the embedded secrets, in one embodiment, pre-compiler software may be deployed for compiling the program in a random-execution-order based on a random seed indication that randomly selects compilation conventions and a shuffling algorithm that moves the associated data across the program during execution. | 2010-03-25 |
20100077229 | METHOD FOR EMPLOYING USB RECORD CARRIERS AND A RELATED MODULE - A method of utilizing USB record carriers is disclosed. A USB security drive is serially connected with at least a USB drive to encrypt/decrypt stored data in the USB drive and to integrate a plurality of data regions or even a plurality of encrypted data regions to provide multi-level security protections. In a more specific embodiment, the USB security drive further enables the automatic backup of data stored in the USB drive. A related assembled module by the implementation is also disclosed. | 2010-03-25 |
20100077230 | PROTECTING A PROGRAMMABLE MEMORY AGAINST UNAUTHORIZED MODIFICATION - This disclosure provides an apparatus including a programmable memory, a data write path for writing data into the memory and a data read path for reading data from the memory. The memory comprises at least one protected memory field. The data write path comprises a decryption unit that is adapted for receiving encrypted data, decrypting the encrypted data, and writing resulting plain data into the at least one protected memory field. The data read path is adapted for reading out the plain data stored in the protected memory field. The at least one protected memory field is only writable by applying the data to be written into the at least one protected memory field in encrypted form to the data write path. | 2010-03-25 |
20100077231 | METHOD AND SYSTEM FOR MAINTAINING SECURE DATA INPUT AND OUTPUT - Methods and systems for enhancing the security of data during input and output on a client computer system are provided to prevent attempts by unauthorized code to access, intercept, and/or modify data. Example embodiments provide a plurality of obfuscation techniques and security enhanced drivers that use these obfuscation techniques to prohibit unauthorized viewing/receiving of valid data. When the drivers are used together with the various obfuscation techniques, the security enhanced drivers provide mechanisms for “scheduling” the content of the storage areas used to store the data so that valid data is not available to unauthorized recipients. When unauthorized recipients attempt to access the “data,” they perceive or receive obfuscated data. The obfuscation techniques described include “copy-in,” “replace and restore,” and “in-place replacement” de-obfuscation/re-obfuscation techniques. In one embodiment, a security enhanced display driver, a security enhanced mouse driver, a security enhanced keyboard driver, and a security enhanced audio driver are provided. To complement the security enhancements, the methods and systems also provide for a watchdog mechanism to ensure that the driver is functioning as it should be and various user interface techniques for denoting security on a display device. | 2010-03-25 |
20100077232 | Processor power consumption control and voltage drop via micro-architectural bandwidth throttling - A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor. | 2010-03-25 |
20100077233 | SYSTEMS AND METHODS FOR CONTROL OF INTEGRATED CIRCUITS COMPRISING BODY BIASING SYSTEMS - Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition. | 2010-03-25 |
20100077234 | CONTROL OF AWAKE TIME IN MOBILE DEVICE - A method of operating a mobile device comprises operating the mobile device in a low power mode, switching the mobile device to a high power mode in response to an event, identifying the event as specific type of event, selecting a time period according to the identified type of event, preventing an algorithm for switching the mobile device to the low power mode from executing, for the time period, and (ultimately) executing the algorithm. | 2010-03-25 |
20100077235 | MOBILE COMMUNICATION DEVICE AND CONTROLLING METHOD THEREOF - A mobile communication device includes a control circuit unit, a first interface, a status change detecting circuit, and an embedded controller. The control circuit unit is operated in either a normal working mode or a power-saving mode. The first interface is connected with the data card and the control circuit unit. The status change detecting circuit is connected with the first interface. The embedded controller is connected with the status change detecting circuit and the control circuit unit. If the control circuit unit is operated in the power-saving mode and the data card is switched from a standby status to a working status, the data card generates a status-changing signal to the status change detecting circuit. In response to the status-changing signal, the control circuit unit is controlled to be switched from the power-saving mode to the normal working mode by the embedded controller. | 2010-03-25 |
20100077236 | Method, system, and apparatus for dynamic thermal management - A method, apparatus, article of manufacture, and system, the method including, in some embodiments, processing a computational load by a first core of a multi-core processor, and dynamically distributing at least a portion of the computational load to a second core of the multi-core processor to reduce a power density of the multi-core processor for the processing of the computational load. | 2010-03-25 |
20100077237 | Bi-Directional Control of Power Adapter and Load - A system comprises a computer and an external power adapter configured to be connected to the computer to provide power to the computer. The computer comprises a computer control circuit that generates a computer control signal that is provided to the external power adapter and causes a change in an output voltage of the external power adapter. The external power adapter comprises an adapter control circuit that generates an adapter control signal that is provided to the computer and causes the computer to change its power draw. The computer and adapter control circuits generate the control signals on a common conductor interconnecting the computer and the external power adapter. | 2010-03-25 |
20100077238 | ENERGY EFFICIENCT POWER SUPPLY SYSTEM - An energy efficient power supply system is disclosed. The energy efficient power supply system comprises a plurality of power supply units and the power supply system may be coupled to the control logic. The control logic may be coupled to the power monitor unit. The power monitor unit may determine a power consumption value, which may represent power requirement of a power consuming system such as a computer system. The control logic may determine the power supply units of the plurality of power supply units that are to be activated to provide power to match the power requirement. The control logic may identify the power supply units that may be activated to operate at a maximum efficiency value while providing power specified by the power consumption value. | 2010-03-25 |
20100077239 | System and Method for Controlling Power Delivered to a Powered Device Based on Cable Characteristics - A system and method for discovering a cable type and resistance for Power over Ethernet (PoE) applications. Cabling power loss in PoE applications is related to the resistance of the cable itself. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, etc.) of the Ethernet cable to enable determination of the cable resistance. The determined resistance can be used in powering decisions and in adjusting power budgets allocated to power source equipment ports. | 2010-03-25 |
20100077240 | METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION OF FULLY-BUFFERED DUAL INLINE MEMORY MODULES - Methods and apparatuses are presented for reducing the power consumed in an in-line memory module. In some embodiments, the method may include monitoring a memory requirement of a computer system, the computer system comprising a plurality of memory modules. In the event that the memory requirement changes, unmapping at least one of the plurality of memory modules and maintaining a low power state for the at least one unmapped memory module. The method may further comprise selectively re-initializing the plurality of memory modules such that the at least one unmapped memory module remains in a low power state while the remainder of the plurality of memory modules are in a non-low power state. Where, in the event that the memory requirement changes again, the method also may comprise re-programming the memory controller with an identifier associated with the at least one unmapped memory module. | 2010-03-25 |
20100077241 | BUSINESS ENERGY MANAGEMENT BASED ON USER NETWORK ACCESS AND CALENDAR DATA - A method and computer program product for controlling energy utilization includes receiving user activities from each of a plurality of users into one or more software application, associating each user activity with a defined workspace having one or more remotely controllable electronic devices, and controlling energy utilization of the one or more electronic devices within each defined workspace according to the user activities associated with the defined workspace. Energy utilization is reduced in a defined workspace during a time period that there is no user activity associated with the workspace. Optionally, the step of receiving user activities may include detecting that a user has logged onto a remote computer that is not located within the defined workspace, or users inputting activities into a software application, such as one or more instances of an electronic calendar. | 2010-03-25 |
20100077242 | DATA PROCESSOR - In order to reduce an electric power necessary to reproduce data in real time, a data processor includes: a data input unit ( | 2010-03-25 |
20100077243 | CONSERVING POWER IN A COMPUTER SYSTEM - A power management unit (PMU) may determine an optimal power saving state using a break-even period of a power saving state and an expected idle duration based on a first policy. The PMU may determine the optimal power saving state using a first break even period and actual idle duration based on a second policy. The break-even period may equal a minimum time a computer system should remain in a power saving state to compensate for the power consumed by the system to enter and exit that power saving state. The expected idle time duration is determined as an average of idle duration and a recent sample of idle duration. The actual idle duration is the difference of a first and second time point that represents entry and exit points to and from the power saving state. The PMU may transition the system to the optimal power saving state. | 2010-03-25 |
20100077244 | LOW POWER ELECTRONIC SYSTEM ARCHITECTURE USING NON-VOLATILE MAGNETIC MEMORY - A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit. | 2010-03-25 |
20100077245 | SYSTEM AND METHOD OF CLASSIFICATION IN POWER OVER ETHERNET SYSTEMS - A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number. | 2010-03-25 |
20100077246 | Microprocessor system having a plurality of microprocessors which are connected to one another by signaling technology - A microprocessor system includes a plurality of microprocessors which are connected to one another by signaling technology. In order to temporally synchronize the microprocessors in a relatively simple manner, it is proposed in at least one embodiment that provision be made of a central clock generator which outputs a clock signal in the form of temporally successive pulses to all microprocessors in a parallel manner, that provision be made of a master which can switch the output of the clock signal on and off, that all microprocessors sum the clock signal from the central clock generator in the form of a counter reading in each case, that the master be able to reset the counter readings of all microprocessors. In at least one embodiment, in order to synchronize all microprocessors, the master first of all interrupt the output of the clock signal, then set all counter readings to a defined value, and then cancel the interruption of the output of the clock signal again. | 2010-03-25 |
20100077247 | COMPUTER AUDIO INTERFACE UNITS AND SYSTEMS - A computer audio interface unit ( | 2010-03-25 |
20100077248 | CLOCK GENERATING DEVICE, METHOD THEREOF AND COMPUTER SYSTEM USING THE SAME BACKGROUND OF THE INVENTION - A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned. | 2010-03-25 |
20100077249 | RESOURCE ARBITRATION FOR SHARED-WRITE ACCESS VIA PERSISTENT RESERVATION - Described is a technology by which an owner node in a server cluster maintains ownership of a storage mechanism through a persistent reservation mechanism, while allowing non-owning nodes read and write access to the storage mechanism. An owner node writes a reservation key to a registration table associated with the storage mechanism. Non-owning nodes write a shared key that gives them read and write access. The owner node validates the shared keys against cluster membership data, and preempts (e.g., removes) any key deemed not valid. The owner node also defends ownership against challenges to ownership made by other nodes, so that another node can take over ownership if a (formerly) owning node is unable to defend, e.g., because of a failure. | 2010-03-25 |
20100077250 | VIRTUALIZATION BASED HIGH AVAILABILITY CLUSTER SYSTEM AND METHOD FOR MANAGING FAILURE IN VIRTUALIZATION BASED HIGH AVAILABILITY CLUSTER SYSTEM - Provided are a virtualization based high availability cluster system and a method for managing failures in a virtualization based high availability cluster system. The high availability cluster system includes a plurality of virtual nodes, and a plurality of physical nodes each including a message generator for generating a message denoting that the virtual nodes are in a normal state and transmitting the generated message to virtual nodes in a same physical node. One of the virtual nodes not included in a first physical node among the plurality of the physical nodes takes over resources related to a service if a failure is generated in one of virtual nodes included in the first physical node | 2010-03-25 |
20100077251 | METHOD AND SYSTEM FOR RELIABLY AND EFFICIENTLY TRANSPORTING DATA OVER A NETWORK - A data transport system for transporting data between a server ( | 2010-03-25 |
20100077252 | Systems and Methods for Detection, Isolation, and Recovery of Faults in a Fail-in-Place Storage Array - Systems and methods for recovering from a fault in an array of data storage devices are provided. Fault recovery includes determining that a first data storage device of the array of data storage devices is more likely to fail that other storage devices of the array of data storage devices. A second data storage device in the array of data storage devices is selected to be used in recovering from a failure of the first data storage device. Data from the first data storage device is stored at the second storage device. In the event of a failure at the first data storage device, data storage operations are performed using the second storage device. | 2010-03-25 |
20100077253 | MEMORY CONTROL DEVICE AND METHODS THEREOF - A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event indicator, a third link is established between the first processor device and the second memory module at a third time, the third time after the first time and the second time. | 2010-03-25 |
20100077254 | METHOD AND APPARATUS FOR REPLACING A DEVICE IN A NETWORK - The invention relates to a method for replacing a device in a network comprising a plurality of devices. The method includes a step of storing ( | 2010-03-25 |
20100077255 | CATALOG RECOVERY THROUGH SYSTEM MANAGEMENT FACILITIES REVERSE TRANSVERSAL - A method for forward recovery of a catalog of a data storage system, comprising providing a recovery catalog and SMF records. In reverse chronological order, the (i)th entry of the record is checked for a data set change command. If none, the next entry is examined. Otherwise, the (j)th data set is identified and checked for inclusion in the recovery catalog. If it already is, the next entry is selected. If not, a data set location record is added. This process is repeated for each entry in the SMF record. Next, a (h)th data set on the (k)th volume is selected and checked for inclusion in the recovery catalog. If that (h)th data set has been added to the recovery catalog, a next data set is selected. Otherwise, a data set location record for the (h)th data set is added. The process is repeated for each data set on each volume. | 2010-03-25 |
20100077256 | STORAGE CONTROLLER AND DATA ERASING METHOD FOR STORAGE DEVICE - A storage controller changes a block size to carry out a shredding process. A data shredder uses a large block size set by a block size setting part to write shredding data in a storage area of a disk drive and erase data stored therein. An error arising during the writing operation of the shredding data is detected by an error detecting part. When the error is detected, the block size setting part sets the block size smaller by one stage than the initial block size to the data shredder. Every time the error arises, the block size used in the shredding process is diminished. Thus, the number of times of writings of the shredding data is reduced as much as possible to improve a processing speed and erase the data of a wide range as much as possible. | 2010-03-25 |
20100077257 | METHODS FOR DISASTER RECOVERABILITY TESTING AND VALIDATION - Exemplary methods and computer recovery readiness evaluation process relate to a virtual recovery testing process for Disaster Recovery Plans (DRPs) that can be executed by technical generalists. As such, by implementing the DRP virtual testing process a technical generalist can be charged with the tasks of evaluating and validating documented DRP assumptions, plan execution steps, interoperability dependencies/requirements in addition to the availability of applications, application specific vaulted vital records, and hardware systems that are referenced within the recovery logic of a DRP. Further, the use of established DRP problem management processes to addresses anomalies & deficiencies can also be accomplished. | 2010-03-25 |
20100077258 | GENERATE DIAGNOSTIC DATA FOR OVERDUE THREAD IN A DATA PROCESSING SYSTEM - Disclosed is a computer implemented method, computer program product, and apparatus for generating diagnostic data for a thread. A service processor may begin by executing the computer usable program code to allocate a first thread to a monitoring function. The service processor determines if a second thread is running, wherein the second thread is associated with an operation. The service processor obtains an object pointer from a list of running threads, wherein the object pointer references a time data structure associated with the second thread, the time data structure comprising a maximum running time interval and a check time. The service processor calculates the check time as a maximum running time interval added to an initially sampled timestamp. The service processor determines if a current time exceeds the check time. In addition, the service processor generates an error log, responsive to a determination that the current time exceeds the check time. | 2010-03-25 |
20100077259 | APPARATUS AND METHOD FOR PERFORMING A SCREENING TEST OF SEMICONDUCTOR INTEGRATED CIRCUITS - An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information. | 2010-03-25 |
20100077260 | TESTING MACHINE WITH WORKFLOW BASED TEST PROCEDURE - A test machine system and a method for operating a test machine system includes using a readily available workflow program to a test procedure created using a graphical user interface to arrange test procedure elements. | 2010-03-25 |
20100077261 | APPARATUS AND METHOD FOR ENCODING THE FIVE SENSES INFORMATION, SYSTEM AND METHOD FOR PROVIDING REALISTIC SERVICE USING FIVE SENSES INTEGRATION INTERFACE - The present invention relates to a realistic service and system using a five senses integrated interface, and more particularly, to an apparatus and method for encoding the five senses and a system and method for providing realistic service using a five senses integrated interface, to allow a user to select a product to sensorially experience through an integrated interface in a remote location, which includes a integration recognizer detecting data selected by the user and recognizing an object, and transmitting five senses data of the object through a network, a five senses data analyzer receiving a five senses data packet including the five senses data of the object through the network, and extracting and analyzing the five senses data packet in terms of data on each of the five senses, and a five senses integration representer representing five senses using the data on each of the five senses. | 2010-03-25 |
20100077262 | INFORMATION PROCESSING DEVICE AND ERROR PROCESSING METHOD - An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit. | 2010-03-25 |
20100077263 | Autonomously Configuring Information Systems to Support Mission Objectives - Disclosed is a method, system, and computer program product for automatically configuring information systems to support mission objectives. A Mission SoulPad is connected to an information system via a communication bus, such as a USB bus connection. The Mission SoulPad may autonomously detect and configure components of the information system (e.g., displays, sensors, emitters, transceivers) to support the defined objectives of the Mission SoulPad. The Mission SoulPad may also identify malfunctioning components of the information system needing repair or replacement. Typical operations of malfunctioning components may be dynamically re-routed to functional components. Entire sensor and information display suites may be transitioned simply by moving the Mission SoulPad between available information systems. This ensures that mission critical information is consistently available regardless of the type of system the Mission SoulPad is connected to. | 2010-03-25 |
20100077264 | SERIALIZATION ALGORITHM FOR FUNCTIONAL ESD ROBUSTNESS - An apparatus and method are described for sending serialized command in an environment where ESD or other phenomenon might cause malfunctions. Commands are encoded where there are at least two bit changes between any two commands. In this example, each command code that is different from legal commands by only one bit is an illegal command, Illustratively, if six bits provide 64 codes for commands, and only eight codes are used for legal commands, there will be 56 illegal command codes. Illustratively, any command code, that is only one bit different from a legal command, will be an illegal command. In practice a illegal command may be detected, and the system may recover. An illegal command due to and ESD event may be defined, and when detected a recovery process may be entered. When data (not command) are being sent, error detecting and correcting bits may be employed. | 2010-03-25 |
20100077265 | Turbo interleaver for high data rates - Techniques for supporting high decoding throughput are described. A transmitter may encode a code block of data bits with a Turbo encoder. A receiver may perform decoding for the code block with a Turbo decoder having multiple soft-input soft-output (SISO) decoders. A contention-free Turbo interleaver may be used if the code block size is larger than a threshold size. A regular Turbo interleaver may be used if the code block size is equal to or smaller than the threshold size. The contention-free Turbo interleaver reorders the data bits in the code block such that information from the multiple SISO decoders, after interleaving or deinterleaving, can be written in parallel to multiple storage units in each write cycle without encountering memory access contention. The regular Turbo interleaver can reorder the data bits in the code block in any manner without regard to contention-free memory access. | 2010-03-25 |
20100077266 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector. | 2010-03-25 |
20100077267 | Memory System with Point-to-Point Request Interconnect - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices. | 2010-03-25 |
20100077268 | APPARATUS AND METHOD FOR TESTING SETUP/HOLD TIME - An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units. | 2010-03-25 |
20100077269 | REDUCED SIGNALING INTERFACE METHOD AND APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. | 2010-03-25 |
20100077270 | Concurrent Testing of Multiple Communication Devices - Testing a plurality of communication devices. A plurality of signals may be received from the plurality of communication devices. The plurality of signals may include a signal from each of the plurality of communication devices, where a first subset of the plurality of signals has a different frequency than a second subset of the plurality of signals. The received signals may be combined into a combined signal. The combined signal may be downconverted to a combined signal, e.g., by mixing the combined signal with an output from at least one local oscillator. The downconverting may generate a plurality of lower frequency signals, each corresponding to one of the plurality of received signals. Testing may be performed on each of the plurality of lower frequency signals. | 2010-03-25 |
20100077271 | Method of achieving convergence of hold time error, device and program therefor - A method that achieves convergence of a hold time error in a relatively easy way without causing a setup time error even when the hold time error occurs in a large circuit, a device and a computer-readable storage medium storing a program therefor are provided. Group a first error path and a second error path in error paths which a hold time error occurs if there is a sharing path that shares its start point with the first error path and also shares its end point with the second error path, and insert a delay element without causing a setup time error per the grouped error paths. Convergence of a hold time error can be achieved without taking into account of a node that is not included in the group and there is no worry about causing a setup time error in a path that is not included in the group. | 2010-03-25 |
20100077272 | HARDQ SYNCHRONIZATION METHOD FOR LTE - A method and apparatus according to the present invention addresses and/or prevents lost protocol synchronization in HARQ systems caused by ACK/NACK errors. One embodiment detects lost synchronization errors for NDI-based retransmission protocols and restores synchronization by sending an explicit RESET message. In response to the RESET message, the transmitter aborts the transmission of a current PDU and transmits a new PDU and corresponding NDI. Another embodiment prevents protocol synchronization errors by sending scheduling grants on a packet by packet basis. The receiver sends a subsequent explicit scheduling grant to the transmitter based on an error evaluation of a received PDU. The transmitter will not send the next PDU unless it receives the subsequent explicit scheduling grant. | 2010-03-25 |
20100077273 | PACKET RETRANSMISSION CONTROL METHOD AND APPARATUS IN MULTICAST COMMUNICATION - In a multicast distribution system in which terminal devices on a distribution path are hierarchically grouped, a first terminal device which has detected a loss of a receiving packet transmits to a second terminal device located upstream of the first terminal device a retransmission request for a packet retransmission to the first terminal device and a third terminal device which receives a packet first in a group located downstream of a group to which the first terminal device belongs. The second terminal device which has received the retransmission request transmits a retransmission packet to both the first and third terminal devices. | 2010-03-25 |
20100077274 | Hybrid automatic repeat request and channel information feedback for relay - Operations of a relay are disclosed. To perform a hybrid automatic repeat request (HARQ), the relay receives a plurality of codewords from a base station and transmits a status indicator with respect to the plurality of codewords to the base station. The status indicator is a signal informing the base station about whether or not the configuration of an HARQ has been changed. Although a backhaul link and an access link are asymmetric, HARQ operation can be achieved. | 2010-03-25 |