12th week of 2016 patent applcation highlights part 58 |
Patent application number | Title | Published |
20160086965 | Self-Aligned Split Gate Flash Memory - The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced. | 2016-03-24 |
20160086966 | SEMICONDUCTOR MEMORY ARRAY WITH AIR GAPS BETWEEN ADJACENT GATE STRUCTURES AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device is provided. Gate structures are formed on a substrate, and a first dielectric layer having grooves is formed between two adjacent gate structures. An upper surface of the first dielectric layer is lower than an upper surface of the gate structures. Afterwards, an intermediate layer is formed to cover the gate structures, the first dielectric layer, and the grooves, and openings are formed therein. Each opening is formed between two adjacent gate structures, and the first dielectric layer is removed through the opening. Next, a second dielectric layer is foamed on the intermediate layer, so as to define an air gap between two adjacent gate structures. Furthermore, a semiconductor device is provided. | 2016-03-24 |
20160086967 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device. | 2016-03-24 |
20160086968 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of stack structures, and a plurality of support layers. The stack structures are disposed on the substrate, and a trench is formed between adjacent two stack structures. Each of the stack structures includes a plurality of conductor layers and a plurality of dielectric layers. The dielectric layers and the conductor layers are disposed alternately. The support layers are disposed in the stack structures respectively. | 2016-03-24 |
20160086969 | THREE DIMENSIONAL NAND DEVICE HAVING NONLINEAR CONTROL GATE ELECTRODES AND METHOD OF MAKING THEREOF - A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region. | 2016-03-24 |
20160086970 | THREE-DIMENSIONAL NON-VOLATILE NOR-TYPE FLASH MEMORY - The present invention provides a design of three-dimensional non-volatile NOR flash memory devices consisting of arrays of basic NOR memory group in which individual memory cells (field-effect-transistors) are stacked along a direction (or directions) either out of or parallel to the plane of the substrate and electrically connected in parallel to achieve high storage densities approaching 1 TB with lower manufacturing cost. Offering full random access to every individual memory cells and also capability of parallel programming/erasing in blocks of memory cells, such three-dimensional non-volatile NOR flash memory can be widely used for both executable-code storage and mass data storage applications. | 2016-03-24 |
20160086971 | MULTI-LAYER MEMORY ARRAY AND MANUFACTURING METHOD OF THE SAME - A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes. | 2016-03-24 |
20160086972 | MONOLITHIC THREE-DIMENSIONAL NAND STRINGS AND METHODS OF FABRICATION THEREOF - A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers. | 2016-03-24 |
20160086973 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers. | 2016-03-24 |
20160086974 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING TRANSISTOR CHANNELS HAVING DIFFERENT STRAIN STATES, AND RELATED SEMICONDUCTOR STRUCTURES - Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer. | 2016-03-24 |
20160086975 | SCHOTTKY CLAMPED RADIO FREQUENCY SWITCH - Various methods and devices that involve radio frequency (RF) switches with clamped bodies are provided. An exemplary RF switch with a clamped body comprises a channel that separates a source and a drain. The RF switch also comprises a clamp region that spans the channel, extends into the source and drain, and has a lower dopant concentration than both the source and drain. The RF switch also comprises a pair of matching silicide regions formed on either side of the channel and in contact with the clamp region. The clamp region forms a pair of Schottky diode barriers with the pair of matching silicide regions. The RF switch can operate in a plurality of operating modes. The pair of Schottky diode barriers provide a constant sink for accumulated charge in the clamped body that is independent of the operating mode in which the RF switch is operating. | 2016-03-24 |
20160086976 | Display Device and Manufacturing Method Thereof - Disclosed are a display device and the manufacturing method thereof. In the display device, the pixel unit of the display substrate comprises: a gate line material layer, a transparent electrode layer, a semiconductor layer, and a metal layer; the semiconductor layer and the metal layer are disposed between the gate line material layer and the transparent electrode layer; the metal layer is located above the semiconductor layer. The present invention could cause the storage capacitor of the display device to be smaller, thereby reducing the RC delay of the scanning signal of the gate line. | 2016-03-24 |
20160086977 | DISPLAY DEVICE - A display device includes a first substrate having an active area, a circuit area extending outwardly from the active area, and a cell seal area extending outwardly from the circuit area, a second substrate covering the first substrate, a sealing part between the first substrate and the second substrate, the sealing part covering at least a portion of the circuit area, a wiring part in the circuit area of the first substrate and electrically connected to elements in the active area of the first substrate, the wiring part including at least one level-difference compensation part, and a stepped part between the sealing part and at least a portion of the wiring part, the at least one level-difference compensation part of the wiring part being adjacent to the stepped part. | 2016-03-24 |
20160086978 | DISPLAY - A display is disclosed. The display includes a display panel including pixel units in an image-displaying region. Each of the pixel units includes an AND gate and a pixel electrode electrically connected to an output terminal of the AND gate. | 2016-03-24 |
20160086979 | Semiconductor Device - One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor. The other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit. The other terminal of the integrated circuit is electrically connected to the second power supply terminal. | 2016-03-24 |
20160086980 | GAN TRANSISTORS WITH POLYSILICON LAYERS USED FOR CREATING ADDITIONAL COMPONENTS - A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer. | 2016-03-24 |
20160086981 | FABRICATION METHODS OF TRANSPARENT CONDUCTIVE ELECTRODE AND ARRAY SUBSTRATE - Fabrication methods of a transparent conductive electrode ( | 2016-03-24 |
20160086982 | DISPLAY DEVICE - Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided. | 2016-03-24 |
20160086983 | SOLAR-POWERED ENERGY-AUTONOMOUS SILICON-ON-INSULATOR DEVICE - A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures. | 2016-03-24 |
20160086984 | Approach for Reducing Pixel Pitch using Vertical Transfer Gates and Implant Isolation Regions - An active pixel sensor (APS) with a vertical transfer gate and a pixel transistor (e.g., a transfer transistor, a source follower transistor, a reset transistor, or a row select transistor) electrically isolated by an implant isolation region is provided. A semiconductor substrate has a photodetector buried therein. The vertical transfer gate extends into the semiconductor substrate with a channel region in electrical communication with the photodetector. The pixel transistor is arranged over the photodetector and configured to facilitate the pixel operation (e.g., reset, signal readout, etc.). The implant isolation region is arranged in the semiconductor substrate and surrounds and electrically isolates the pixel transistor. A method for manufacturing the APS is also provided. | 2016-03-24 |
20160086985 | PIXEL FOR CMOS IMAGE SENSOR AND IMAGE SENSOR INCLUDING THE SAME - A pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a semiconductor substrate having a first surface and a third surface formed by removing part of the semiconductor substrate from a second surface, an active region which is formed between the first surface and the third surface and which contains a photoelectric conversion element generating charges in response to light incident on the substrate at the third surface, and a trench-type isolation region formed from either of the first and third surfaces to isolate the active region from an adjacent active region. The trench-type isolation region is filled with first material in a process that leaves a void in the material, the void is filled or partially filled with second material, and then a layer of third material is formed over the resulting structure composed of the first and second materials. | 2016-03-24 |
20160086986 | METHOD FOR MANUFACTURING IMAGE PICKUP MODULE - The present invention achieves reduction in size and thickness while removing the cause of defective image and the like. According to an image pickup module ( | 2016-03-24 |
20160086987 | Image Sensor Bending By Induced Substrate Swelling - In some examples, techniques and architectures for fabricating an image sensor chip having a curved surface include placing a substrate on a first surface of an image sensor chip, wherein the first surface of the image sensor chip is opposite a second surface of the image sensor chip, and wherein the second surface of the image sensor chip includes light sensors to generate electrical signals in response to receiving light. Fabricating also includes modifying a volume of the substrate so as to impart forces on the image sensor chip to produce a curved image sensor chip. | 2016-03-24 |
20160086988 | IMAGING APPARATUS - An imaging apparatus includes a plurality of pixels, a signal holding unit, first and second control electrodes. Each of the plurality of pixels includes a photoelectric conversion unit, and an amplification element to amplify signals based on signal charges generated by the photoelectric conversion unit, in which the plurality of pixels output signals for performing a phase contrast detection type of focal point detection. The signal holding unit is in an electrical pathway between an output node of the photoelectric conversion unit and an input node of the amplification element, in which signals for performing the phase contrast detection type of focal point detection are held. The first control electrode is configured to transfer a signal of the photoelectric conversion unit to the signal holding unit. The second control electrode is configured to transfer a signal for performing the phase difference detection type of focal point detection. | 2016-03-24 |
20160086989 | ULTRAVIOLET SENSOR AND ULTRAVIOLET DETECTING DEVICE - An ultraviolet sensor includes a silicon photodiode array having a plurality of first pixel regions and a plurality of second pixel regions. A filter film is disposed on each of the first pixel regions so as to cover each first pixel region, except on each second pixel region. The filter film lowers transmittance in a detection target wavelength range in the ultraviolet region. Each of each first pixel region and each second pixel region includes at least one pixel having an avalanche photodiode to operate in Geiger mode, and a quenching resistor connected in series to the avalanche photodiode. Each of the quenching resistors in the plurality of first pixel regions is connected through a first signal line to a first output terminal. Each of the quenching resistors in the plurality of second pixel regions is connected through a second signal line to a second output terminal. | 2016-03-24 |
20160086990 | PIXEL ARRAY OF IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - A pixel array of an image sensor includes multiple red, green, blue and panchromatic pixels. The red, green and blue pixels are formed on a substrate during a first process. Planarization material is deposited to form the panchromatic pixels on the substrate and to form a planarization layer on the red, green and blue pixels during the same second process subsequent to the first process. The planarization material of the panchromatic pixels and the planarization layer is characterized in high transmittance and high aspect ratio. | 2016-03-24 |
20160086991 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of pixels each of which includes a photoelectric conversion unit that generates charges by photoelectrically converting light, and a transistor that reads a pixel signal of a level corresponding to the charges generated in the photoelectric conversion unit. A phase difference pixel which is at least a part of the plurality of pixels is configured in such a manner that the photoelectric conversion unit is divided into a plurality of photoelectric conversion units and an insulated light shielding film is embedded in a region for separating the plurality of photoelectric conversion units, which are divided, from each other. | 2016-03-24 |
20160086992 | SOLID-STATE IMAGE PICKUP DEVICE, IMAGE PICKUP SYSTEM USING SOLID-STATE IMAGE PICKUP DEVICE, AND METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE - In a solid-state image pickup device including a pixel that includes a photoelectric conversion portion, a carrier holding portion, and a plurality of transistors, the solid-state image pickup device further includes a first insulating film disposed over the photoelectric conversion portion, the carrier holding portion, and the plurality of transistors, a conductor disposed in an opening of the first insulating film and positioned to be connected to a source or a drain of one or more of the plurality of transistors, and a light shielding film disposed in an opening or a recess of the first insulating film and positioned above the carrier holding portion. | 2016-03-24 |
20160086993 | SOLID-STATE IMAGE PICKUP APPARATUS, AND IMAGE PICKUP SYSTEM USING SOLID-STATE IMAGE PICKUP APPARATUS - A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a semiconductor substrate. The solid-state image pickup apparatus further includes a first gate electrode disposed on the semiconductor substrate and extending between the photoelectric conversion unit and charge storage unit, and a second gate electrode disposed on the semiconductor substrate and extending between the charge storage unit and the floating diffusion unit. The solid-state image pickup apparatus further includes a light shielding member including a first part and a second part, wherein the first part is disposed over the charge storage unit and at least over the first gate electrode or the second gate electrode, and the second part is disposed between the first gate electrode and the second gate electrode such that the second part extends from the first part toward a surface of the semiconductor substrate. | 2016-03-24 |
20160086994 | Image Sensor Bending Using Tension - Techniques for fabricating an image sensor chip having a curved surface include placing a bending substrate on a first surface of an imaging sensor chip. The first surface of the imaging sensor chip includes light sensors to generate electrical signals in response to receiving light. Fabricating also includes bending the bending substrate so as to impart forces on the image sensor chip to produce a curved imaging sensor chip. A second surface of the curved imaging sensor chip may be adhered to a backside substrate. The second surface is opposite the first surface. The bending substrate may be removed from the first surface of the imaging sensor chip. | 2016-03-24 |
20160086995 | SOLID-STATE IMAGE PICKUP DEVICE, ELECTRONIC APPARATUS, AND MANUFACTURING METHOD - A solid-state image pickup device includes: a filter section including filters that are disposed corresponding to respective pixels, and each allowing light of a color that corresponds to corresponding one of the pixels to transmit therethrough, in which the pixels are each configured to receive the light of the predetermined color; and a microlens array section including a plurality of microlenses each configured to collect the light for corresponding one of the pixels, in which the microlenses are stacked with respect to the filter section, and are arranged in an array pattern corresponding to the respective pixels. The microlenses have two or more shapes that are different from one another corresponding to the respective colors of the light to be received by the pixels, and each having an end that is in contact with the end of adjacent one of the microlenses. | 2016-03-24 |
20160086996 | Dual-Side Illumination Image Sensor Chips and Methods for Forming the Same - A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light from a second direction opposite the first direction. | 2016-03-24 |
20160086997 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer. | 2016-03-24 |
20160086998 | PIN DIODE STRUCTURE HAVING SURFACE CHARGE SUPPRESSION - A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes. | 2016-03-24 |
20160086999 | HIGH NEAR INFRARED SENSITIVITY IMAGE SENSOR - An image sensor includes a plurality of photodiodes disposed proximate to a frontside of a first semiconductor layer to accumulate image charge in response to light directed into the frontside of the first semiconductor layer. A plurality of pinning wells is disposed in the first semiconductor layer. The pinning wells separate individual photodiodes included in the plurality of photodiodes. A plurality of dielectric layers is disposed proximate to a backside of the first semiconductor layer. The dielectric layers are tuned such that light having a wavelength substantially equal to a first wavelength included in the light directed into the frontside of the first semiconductor layer is reflected from the dielectric layers back to a respective one of the plurality of photodiodes disposed proximate to the frontside of the first semiconductor layer. | 2016-03-24 |
20160087000 | INFRARED IMAGE SENSOR - An infrared image sensor includes a bias circuit receiving a timing signal, the bias circuit generating a bias voltage having a first value and a second value in response to the timing signal; a semiconductor light-receiving device including a photodiode, the semiconductor light-receiving device receiving the bias voltage; a read-out circuit including a read-out electrode connected to the photodiode, the read-out electrode receiving electrical signal from the photodiode; and a signal processing circuit processing a read-out signal from the read-out circuit synchronously with the timing signal. The photodiode includes an optical absorption layer made of a III-V group compound semiconductor. The optical absorption layer has a type II multi quantum well structure including first compound semiconductor layers containing antimony as a constituent element and second compound semiconductor layers that are stacked alternately. | 2016-03-24 |
20160087001 | TWO-TERMINAL MULTI-MODE DETECTOR - A two-terminal detector has a back-to-back p/n/p SWIR/MWIR stack structure, which includes P-SWIR absorber, N-SWIR, wide bandgap bather, N-MWIR absorber, and P-MWIR layers, with contacts on the P-MWIR and P-SWIR layers. The junction between the SWIR layers and the junction between the MWIR layers are preferably passivated. The detector stack is preferably arranged such that a negative bias applied to the top of the stack reverse-biases the MWIR junction and forward-biases the SWIR junction, such that the detector collects photocurrent from MWIR radiation. A positive bias forward-biases the MWIR junction and reverse-biases the SWIR junction, such that photocurrent from SWIR radiation is collected. A larger positive bias induces electron avalanche at the SWIR junction, thereby providing detector sensitivity sufficient to provide low light level passive amplified imaging. Detector sensitivity in this mode is preferably sufficient to provide high resolution 3-D eye-safe LADAR imaging. | 2016-03-24 |
20160087002 | SOLID STATE IMAGING DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor substrate has a first region in which a photoelectric conversion device is provided, a second region which is provided around the first region, and in which a device is provided, and a third region which is provided between the first region and the second region, and in which the photoelectric conversion device is provided. A first interlayer insulating film is provided on the first region and the third region. A second interlayer insulating film is provided on the second region, and is thicker than the first interlayer insulating film. A resin material is provided on the first interlayer insulating film of the first region, and provided so as to cover a groove of a surface of the first interlayer insulating film of the third region. | 2016-03-24 |
20160087003 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate and a plurality of light emitting cells disposed on the substrate. Each light emitting cell includes a first semiconductor layer and a second semiconductor layer, an active layer between the first and the second semiconductors, a conductive material on the second semiconductor layer, an inclined surface, a first insulation layer overlaps each light emitting cell, an electrically conductive material overlaps the first insulation layer to couple two of the plurality of light emitting cells, and a second insulation layer overlaps the electrically conductive material. A light-transmitting material is used in both the first insulation layer and the second insulation layer. The inclined surface is continuous and has a slope of approximately 20° to approximately 80° from a horizontal plane based on the substrate. | 2016-03-24 |
20160087004 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic memory includes a magnetic element, and a metal layer stacked on the magnetic element. H/D>1.47 is satisfied, where H denotes a sum of thicknesses of the magnetic element and the metal layer in a first direction in which the magnetic element and the metal layer are stacked, and D denotes a width of the magnetic element in a second direction perpendicular to the first direction. | 2016-03-24 |
20160087005 | Semiconductor Device with Variable Resistive Element - A semiconductor device includes a semiconductor body including a drift zone that forms a pn junction with an emitter region. A first load electrode is at a front side of the semiconductor body. A second load electrode is at a rear side of the semiconductor body opposite to the front side. One or more variable resistive elements are electrically connected in a controlled path between the drift zone and one of the first and second load electrodes. The variable resistive elements activate and deactivate electronic elements of the semiconductor device in response to a change of the operational state of the semiconductor device. | 2016-03-24 |
20160087006 | 3-DIMENSIONAL STACK MEMORY DEVICE - A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type. | 2016-03-24 |
20160087007 | Diode/Superionic Conductor/Polymer Memory Structure - A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode. | 2016-03-24 |
20160087008 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a semiconductor substrate and a first pillar-shaped semiconductor layer, a first dummy gate layer and a second pillar-shaped semiconductor layer, and a second dummy gate layer. Third and fourth dummy gate layers are formed on sidewalls of the first dummy layer gate, the first pillar-shaped semiconductor layer, the second dummy gate layer and the second pillar-shaped semiconductor layer. An interlayer insulating film is deposited, the dummy gate layers are removed, and a gate insulator is formed film around the first and second pillar-shaped semiconductor layers. A first metal is deposited and a gate electrode and a gate line are formed around the first pillar-shaped semiconductor layer. Second and third metals are deposited and a first contact and a pillar-shaped resistance-changing layer, a lower electrode, and a reset gate are formed. | 2016-03-24 |
20160087009 | RESISTIVE RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHODS - A resistive memory storage device includes a lower electrode, an upper electrode and a plurality of composite material layers disposed between the lower electrode and the upper electrode. Each composite material layer includes a first layer and a second layer. The first layer is a metal-based high-K dielectric material layer having a first metal element, and the second layer is a metal layer having the first metal element. | 2016-03-24 |
20160087010 | Semiconductor Constructions, and Methods of Forming Cross-Point Memory Arrays - Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode. | 2016-03-24 |
20160087011 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit line contacts. | 2016-03-24 |
20160087012 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - An image sensor includes a semiconductor substrate integrated with at least a photo-sensing device, a plurality of first electrodes disposed on the semiconductor substrate, an organic photoelectric conversion layer disposed on the first electrodes, and a second electrode disposed on the organic photoelectric conversion layer. The first electrodes include a light-transmitting electrode and a metal layer interposed between the semiconductor substrate and the light-transmitting electrode. The organic photoelectric conversion layer disposed on the first electrodes and the photo-sensing device absorb and/or sense light in different wavelength regions from each other. An electronic device including the image sensor is also provided. | 2016-03-24 |
20160087013 | DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - A display device includes: a supporting member including a body, and a supporter rotatably coupled to a side surface of the body; a display substrate on the supporting member, the display substrate including a first region, and a second region at an outer periphery of the first region; an emission layer on the first region and the second region of the display substrate; a polarizer on the emission layer and on the first region of the display substrate; a touch panel on the polarizer; and a window on the touch panel. The supporter is configured to support the second region of the display substrate such that the second region of the substrate is in a bent-state in a non-display region of the device. | 2016-03-24 |
20160087014 | DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - A display panel includes a plurality of unit pixels, where each of the unit pixels has a hexagonal-shape and includes: a first sub-pixel configured to emit a first color light, where the first sub-pixel has a rhombus-shape; a second sub-pixel configured to emit a second color light, where the second sub-pixel has the rhombus-shape; and a third sub-pixel configured to emit a third color light, where the third sub-pixel has the rhombus-shape, where first sub-pixels, second sub-pixels or third sub-pixels of neighboring unit pixels in a same row are arranged to adjoin each other. | 2016-03-24 |
20160087015 | ORGANIC LIGHT EMITTING DISPLAY DEVICES AND METHODS OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICES - An organic light emitting display device and a method of manufacturing an organic light emitting display device are disclosed. The organic light emitting display device includes a first substrate, on which a display region and a non-display region surrounding the display region are defined, a second substrate disposed opposite to the first substrate, an organic light emitting element disposed in the display region between the first substrate and the second substrate, a third substrate disposed opposite to the second substrate, and a microphone disposed between the second substrate and the third substrate. | 2016-03-24 |
20160087016 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display (OLED) device is disclosed. The OLED device includes a substrate configured to include a sub-pixel defined into an emission region and a driving region. A first bank pattern configured to define the emission region of the sub-pixel is formed on the substrate. A second bank pattern configured to include an opening, which exposes the emission region and a part of the driving region, is formed on a part of an upper surface of the first bank pattern. An organic emission layer is formed in the opening. As such, the occupied area of the organic emission layer becomes wider. Therefore, the thickness deviation of the organic emission layer is prevented or minimized. | 2016-03-24 |
20160087017 | ORGANIC LIGHT EMITTING DISPLAY DEVICES AND METHODS OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICES - An organic light emitting display device including a substrate, a semiconductor device disposed on the substrate, an insulation layer including an inclined structure disposed on the semiconductor device, a first electrode disposed on the insulation layer, a pixel defining layer disposed on the insulation layer and the first electrode, the pixel defining layer having a pixel opening exposing the first electrode positioned on the inclined structure, an organic light emitting layer disposed on the exposed first electrode and the pixel defining layer, and a second electrode disposed on the organic light emitting layer and the pixel defining layer. Light generated from the organic light emitting layer may be directed in different directions by the inclined structure. | 2016-03-24 |
20160087018 | ORGANIC LIGHT EMITTING DIODE DEVICE - An OLED display includes a first substrate, a first electrode on the first substrate, a pixel defining layer having a first aperture exposing the first electrode, an organic light emitting layer on the first electrode, a second electrode on the organic light emitting layer, a second substrate disposed to face the first substrate, a black matrix disposed on the second substrate and having a second aperture, and a lens disposed to cover at least a part of the second aperture and protruding toward the first substrate. | 2016-03-24 |
20160087019 | DISPLAY DEVICE - A display device includes a plurality of pixel electrodes which are provided separately from each other on an insulative surface; a first layer which is provided separately from each other on the respective plurality of pixel electrodes, and includes a plurality of first carrier transport layers or a plurality of first carrier injection layers; a pixel separation film which is provided on the first layer, and includes a plurality of opening portions in each region which overlaps with the respective plurality of pixel electrodes in a planar view; a light emitting layer which is provided so as to cover at least one of the plurality of opening portions; a second layer which is provided on the light emitting layer, and includes a second carrier transport layer or a second carrier injection layer; and a counter electrode which is provided on the second layer. | 2016-03-24 |
20160087020 | FLEXIBLE DISPLAY PANEL AND ELECTRO-OPTICAL APPARATUS - A first etching stop layer and an active layer are formed on an inner surface of a first glass substrate, and a second etching stop layer and a cover layer are formed on an inner surface of a second glass substrate. A display media is formed between the first glass substrate and the second glass substrate. A first passivation layer is formed on an outer surface of the second glass substrate. A first etching process is performed to expose the first etching stop layer. A first flexible substrate is formed on the exposed first etching stop layer, and a second passivation layer is formed on the first flexible substrate. The first passivsation layer is removed. A second etching process is performed to expose the second etching stop layer. A second flexible substrate is formed on the exposed second etching stop layer, and the second passivation layer is removed. | 2016-03-24 |
20160087021 | LIGHT EMITTING ELEMENT DISPLAY DEVICE - A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor. | 2016-03-24 |
20160087022 | Silicon and Semiconducting Oxide Thin-Film Transistor Displays - An electronic device display may have an array of pixel circuits. Each pixel circuit may include an organic light-emitting diode and a drive transistor. Each drive transistor may be adjusted to control how much current flows through the organic light-emitting diode. Each pixel circuit may include one or more additional transistors such as switching transistors and a storage capacitor. Semiconducting oxide transistors and silicon transistors may be used in forming the transistors of the pixel circuits. The storage capacitors and the transistors may be formed using metal layers, semiconductor structures. and dielectric layers. Some of the layers may be removed along the edge of the display to facilitate bending. The dielectric layers may have a stepped profile that allows data lines in the array to be stepped down towards the surface of the substrate as the data lines extend into an inactive edge region. | 2016-03-24 |
20160087023 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, AND AN INSPECTION METHOD OF A DISPLAY DEVICE - A display device including a pixel region provided with a plurality of pixels, and a terminal region provided on an outer side of the pixel region, each of the plurality of pixels including a first electrode, an organic layer including a light emitting layer above the first electrode, and a second electrode having a transparency above the organic layer, the terminal region including a first wiring layer and a second wiring layer above the first wiring layer, and the first electrode and the second wiring layer having a same laminated structure. | 2016-03-24 |
20160087024 | Display Device with Micro Cover Layer and Manufacturing Method for the Same - There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display. | 2016-03-24 |
20160087025 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view. | 2016-03-24 |
20160087026 | Resistor Formed Using Resistance Patterns and Semiconductor Devices Including the Same - Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer. | 2016-03-24 |
20160087027 | CHIP RESISTOR AND ELECTRONIC EQUIPMENT HAVING RESISTANCE CIRCUIT NETWORK - A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value. | 2016-03-24 |
20160087028 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - One semiconductor device includes a capacitor having a lower electrode which is arranged on a semiconductor substrate, a second protective film, a dielectric film which has a defect that extends in the film thickness direction from an upper surface that faces the second protective film, a third protective film which has at least a defect filling film that is formed of an insulating body filling the defect, a first protective film which covers the dielectric film and the third protective film, and an upper electrode which covers the first protective film. | 2016-03-24 |
20160087029 | MIM CAPACITOR - Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove. | 2016-03-24 |
20160087030 | CAPACITOR CELL AND METHOD FOR MANUFACTURING SAME - Capacitor technology that provides a high density, high reliability capacitor that is capable of operating at high temperature, for example for use in downhole tools. The capacitive cells have an insulating dielectric of crystalline diamond deposited on a substrate of silicon. Methods of manufacturing capacitor cells are also disclosed, as are stacked configurations of single die capacitors. | 2016-03-24 |
20160087031 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device including a terminal region that can suppress a resist collapse in manufacturing and effectively relieve a concentration of electric fields and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor element formed in a semiconductor substrate made of a silicon carbide semiconductor of a first conductivity type and a plurality of ring-shaped regions of a second conductivity type formed in the semiconductor substrate while surrounding the semiconductor element in plan view. At least one of the plurality of ring-shaped regions includes one or more separation regions of the first conductivity type that cause areas of the first conductivity type on an inner side and an outer side of one of the ring-shaped regions to communicate with each other in plan view. | 2016-03-24 |
20160087032 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to the first main surface, forming an epitaxial layer on the first main surface, the epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which the silicon carbide substrate is located, forming a trench, which includes side walls intersecting with the third main surface and a bottom portion connected to the side walls, in the epitaxial layer, widening an opening of the trench, and forming an embedded region, which has a second conductivity type different from the first conductivity type, in the trench. The epitaxial layer adjacent to the embedded region and the embedded region constitute a superjunction structure. | 2016-03-24 |
20160087033 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region. | 2016-03-24 |
20160087034 | TERMINATION OF SUPER JUNCTION POWER MOSFET - The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths. | 2016-03-24 |
20160087035 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer. | 2016-03-24 |
20160087036 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a SiC layer, an electrode electrically connected to the SiC layer and an impurity region provided between the SiC layer and the electrode. The impurity region includes first position and second position, the first position having highest concentration of an impurity in the impurity region, the highest concentration being not lower than 1×10 | 2016-03-24 |
20160087037 | SEMICONDUCTOR STRUCTURE WITH STRAINED SOURCE AND DRAIN STRUCTURES AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a first gate structure and a second gate structure formed over the substrate. The semiconductor structure further includes first recesses formed in the substrate adjacent to the first gate structure and first strained source and drain structures formed in the first recesses. The semiconductor structure further includes second recesses formed in the substrate adjacent to the second gate structure and second strained source and drain structures formed in the second recesses. In addition, each of the first recesses has a shape of a trapezoid, and each of the second recesses has a shape of an inverted trapezoid. | 2016-03-24 |
20160087038 | SEMICONDUCTOR DEVICE, ANTENNA SWITCH CIRCUIT, AND RADIO COMMUNICATION APPARATUS - A semiconductor device includes: a laminated body including a channel layer that is configured of a compound semiconductor; and at least one gate electrode that is provided on a top surface side of the laminated body, wherein the laminated body includes a first low-resistance region that is provided on the top surface side of the laminated body, the first low-resistance region facing the at least one gate electrode, and a second low-resistance region that is provided externally of the first low resistance region on the top surface side of the laminated body, the second low-resistance region being continuous with the first low-resistance region. | 2016-03-24 |
20160087039 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A high voltage semiconductor device includes a well region of a first conductive type formed at a surface portion of a substrate, a gate electrode disposed on the well region, a source region formed at a surface portion of the well region adjacent to the gate electrode, a drain region formed at a surface portion of the well region adjacent to the gate electrode, and a drift region of a second conductive type disposed under the drain region. | 2016-03-24 |
20160087040 | METHODS FOR HIGH-K METAL GATE CMOS WITH SiC AND SiGe SOURCE/DRAIN REGIONS - A method of manufacturing a semiconductor device includes forming a PMOS region and an NMOS region in a semiconductor substrate, forming dummy gate structures in the PMOS and NMOS regions, and forming a gate hard mask layer overlying top portions and sidewalls of the dummy gate structures. The method includes forming silicon carbon regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the NMOS region, removing the hard mask layer on top of the dummy gate in the NMOS region, and forming silicon germanium regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the PMOS region. After forming the silicon carbon regions and the silicon germanium regions, while retaining the hard mask layer on top of the dummy gates in the PMOS region, performing ion implant to form source/drain regions in the NMOS region and the PMOS region. | 2016-03-24 |
20160087041 | Method and Structure for FinFET Device - The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion. | 2016-03-24 |
20160087042 | FIN-TYPE GRAPHENE DEVICE - Example embodiments relate to a fin-type graphene device. The fin-type graphene device includes a substrate, a graphene channel layer substantially vertical to the substrate, a gate insulating layer that covers one side surface of the graphene channel layer, a gate electrode on the gate insulating layer, and a source electrode and a drain electrode that are formed separately from each other on other side surface of the graphene channel layer. | 2016-03-24 |
20160087043 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a p-type SiC layer and a contact electrode electrically connected to the SiC layer. The contact electrode includes metal. And a region is provided in the SiC layer adjacent to the contact electrode. The region having an oxygen concentration not lower than 1×10 | 2016-03-24 |
20160087044 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a SiC layer including a first region provided at a surface. The first region satisfies N | 2016-03-24 |
20160087045 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a SiC layer, a gate electrode, a gate insulating film provided between the SiC layer and the gate electrode, a first region provided between the SiC layer and the gate insulating film, and a second region provided in the SiC layer. The first region contains at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine). The second region provided adjacent to the first region, and the second region has a higher oxygen concentration than a concentration of the at least one element. | 2016-03-24 |
20160087046 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. | 2016-03-24 |
20160087047 | QUANTUM ROD AND METHOD OF FABRICATING THE SAME - A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one side of a length direction of the core. | 2016-03-24 |
20160087048 | GALLIUM NITRIDE SEMICONDUCTOR SUBSTRATE WITH SEMICONDUCTOR FILM FORMED THEREIN - A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a minor polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An qaxis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface. | 2016-03-24 |
20160087049 | EPITAXIAL SILICON WAFER - An epitaxial silicon wafer includes: a silicon wafer; and a silicon epitaxial layer formed on the silicon wafer, in which a W concentration obtained by a metal analysis of a surface of the silicon epitaxial layer using an inductively coupled plasma mass spectrometry is 1×10 | 2016-03-24 |
20160087050 | POWER SEMICONDUCTOR DEVICES HAVING A SEMI-INSULATING FIELD PLATE - A power semiconductor device comprising a first metal electrode and a second metal electrode formed on a first substrate surface of a semiconductor substrate, a semi-insulating field plate interconnecting said first and second metal electrodes, and an insulating oxide layer extending between said first and second metal electrodes and between said field plate and said semiconductor substrate, wherein said semi-insulating field plate is a titanium nitride (TiN) field plate. | 2016-03-24 |
20160087051 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A manufacturing method of a semiconductor device, includes: a stacking process of forming an electrode by stacking a plurality of electrode layers on a semiconductor layer; and a anneal treatment process of treating the electrode. The stacking process including processes of forming a first electrode layer mainly made of aluminum (Al) as one of the plurality of electrode layers; forming a second electrode layer mainly made of a conductive material that has a higher melting point than that of aluminum (Al) and reacts with aluminum (Al) at 450° C. or higher temperature, as one of the plurality of electrode layers, on the first electrode layer; and forming a third electrode layer mainly made of palladium (Pd) as an electrode layer most distant from the semiconductor layer among the plurality of electrode layers, on the second electrode layer. | 2016-03-24 |
20160087052 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a nitride semiconductor layer, a plurality of source electrodes provided on the nitride semiconductor layer, a plurality of drain electrodes, a plurality of gate electrodes, a first interconnection having a first distance from the nitride semiconductor layer and electrically connecting the source electrodes, a second interconnection electrically connecting the gate electrodes, and a third interconnection having a third distance from the nitride semiconductor layer and electrically connecting the drain electrodes. Each of the drain electrodes are provided between the source electrodes. Each of the gate electrodes are provided between each of the source electrodes and each of the drain electrodes. The third distance is larger than the first distance. | 2016-03-24 |
20160087053 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided. | 2016-03-24 |
20160087054 | Self-Aligned Wrapped-Around Structure - An vertical gate-all-around transistor and method of making is provided. The vertical gate-all-around transistor includes a first semiconductor structure extending above a substrate, and a gate structure extending completely around the first semiconductor structure in a plan view. An outermost perimeter of the gate structure comprises a first protruding arcuate section interposed between linear sections, the first protruding arcuate section aligned with the first semiconductor structure. | 2016-03-24 |
20160087055 | 3D MEMORY HAVING NAND STRINGS SWITCHED BY TRANSISTORS WITH ELONGATED POLYSILICON GATES - A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components. | 2016-03-24 |
20160087056 | SPLIT GATE MEMORY DEVICE FOR IMPROVED ERASE SPEED - Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device. | 2016-03-24 |
20160087057 | Low Resistance Polysilicon Strap - A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region. | 2016-03-24 |
20160087058 | INTEGRATION OF A NON-VOLATILE MEMORY (NVM) CELL AND A LOGIC TRANSISTOR AND METHOD THEREFOR - A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate. | 2016-03-24 |
20160087059 | Semiconductor Device and Method - A vertical gate all around (VGAA) is provided. In embodiments, the VGAA has a nanowire with a first contact pad and a second contact pad. A gate electrode is utilized to help define a channel region within the nanowire. In additional embodiments multiple nanowires, multiple bottom contacts, multiple top contacts, and multiple gate contacts are utilized. | 2016-03-24 |
20160087060 | SEMICONDUCTOR DEVICE WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A transistor includes a substrate and a gate over the substrate. The transistor further includes a source and a drain over the substrate on opposite sides of the gate. The transistor further includes a channel region beneath the gate separating the source from the drain, the channel region having a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The transistor further includes a silicide over a first portion of the drain, wherein a second portion of the drain, closer to the gate than the first portion, is an unsilicided region. | 2016-03-24 |
20160087061 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - A titanium layer and a nickel layer are sequentially formed on a back surface of a SiC wafer. Next, by high-temperature heat treatment, the SiC wafer is heated and the titanium layer and the nickel layer are sintered forming a nickel silicide layer that includes titanium carbide. By this high-temperature heat treatment, an ohmic contact of the SiC wafer and the nickel silicide layer is formed. Thereafter, on the nickel silicide layer, a back surface electrode multilayered structure is formed by sequentially stacking a titanium layer, a nickel layer, and a gold layer. Here, in forming the nickel layer that configures a back surface electrode multilayered structure, the nickel layer is formed under a condition that satisfies 0.02016-03-24 | |
20160087062 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor device includes: a plurality of fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of fin structures, wherein the gate stack structure includes a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of fin structures and beneath the gate stack structure; and source/drain regions on the plurality of fin structures and at both sides of the gate stack structure along the first direction. | 2016-03-24 |
20160087063 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is provided that has a plurality of Fin structures extending on a substrate along a first direction; a gate stack structure extending on the substrate along a second direction and across the plurality of Fin structures, wherein the gate stack structure comprises a gate conductive layer and a gate insulating layer, and the gate conductive layer is formed by a doped poly-semiconductor; trench regions in the plurality of Fin structures and beneath the gate stack structure; and source/drain regions on the plurality of Fin structures and at both sides of the gate stack structure along the first direction. A method of manufacturing a semiconductor device is also provided. | 2016-03-24 |
20160087064 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a wide bandgap semiconductor layer, a gate electrode and a gate insulating film provided between the wide bandgap semiconductor layer and the gate electrode. The gate insulating film includes a first insulating film having a thickness of 7 nm or greater, a fixed charge film provided on the first insulating film, the fixed charge film containing fixed charge and a second insulating film provided on the fixed charge film, the second insulating film having a thickness of 7 nm or greater. The gate insulating film has a total thickness of 25 nm or greater. | 2016-03-24 |