12th week of 2016 patent applcation highlights part 56 |
Patent application number | Title | Published |
20160086765 | ELECTRON DETECTION SYSTEM - An electron detection system for detecting secondary electrons emitted from a sample irradiated by a Focused Ion Beam (FIB). The FIB emanates from a FIB column and travels along a beam axis within a beam region, which extends from the FIB column to the sample. The system comprises an electron detector configured for detecting the secondary electrons, and a deflecting field configured to deflect a trajectory of the secondary electrons, which were propagating towards the FIB column, to propel away from the beam axis and towards the electron detector. The deflecting field may be configured to divert the trajectory of secondary electrons while the secondary electrons are generally within the beam region. | 2016-03-24 |
20160086766 | Charged Particle Beam Device - An evacuation structure of a charged particle beam device includes: a vacuum chamber provided with a charged particle source; vacuum piping connected to the vacuum chamber; a main vacuum pump which is connected via the vacuum piping and evacuates the inside of the vacuum chamber; a non-evaporable getter pump disposed at a position between the vacuum chamber and the main vacuum pump in the vacuum piping; and a coarse evacuation port connected at a position between the vacuum chamber and the non-evaporable getter pump in the vacuum piping The coarse evacuation port includes: a coarse evacuation valve that opens and closes the coarse evacuation port; and a leak valve to open the vacuum chamber to the atmosphere. | 2016-03-24 |
20160086767 | Information Processing Device and Information Processing Method - An information processing device includes a placement section that places a result display area within a display screen based on operation information, a setting section that sets at least one data processing method designated by the user to the result display area, and a data processing section that assigns measurement data to the result display area based on the operation information, performs data processing on the measurement data assigned to the result display area using the data processing method set to the result display area, and displays the data processing results within the result display area. | 2016-03-24 |
20160086768 | OZONE SUPPLYING APPARATUS, OZONE SUPPLYING METHOD, AND CHARGED PARTICLE BEAM DRAWING SYSTEM - An ozone supplying apparatus according to an embodiment of the present invention is an ozone gas supplying apparatus which supplies an ozone gas to a vacuum apparatus. The ozone supplying apparatus includes an ozone generator configured to generate the ozone gas, a first flow controller configured to control a flow rate of the ozone gas generated by the ozone generator, a second flow controller configured to control a flow rate of the ozone gas supplied to the vacuum apparatus, and a main pipe provided on a secondary side of the first flow controller and on a primary side of the second flow controller, with the ozone gas being introduced into the main pipe at such a flow rate that an internal pressure of the main pipe is controlled to be lower than atmospheric pressure by the first flow controller. | 2016-03-24 |
20160086769 | SEMICONDUCTOR INSPECTION SYSTEM AND METHODS OF INSPECTING A SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor inspection system including an ion beam milling unit configured to irradiate at least one cluster-ion beam onto a surface of a sample wafer and etch the surface of the sample wafer and an image acquisition unit configured to irradiate an electron beam onto the etched surface of the sample wafer and acquire an image of the etched surface may be provided. | 2016-03-24 |
20160086770 | ARC EVAPORATION SOURCE - Provided is an arc evaporation source for melting and evaporating a cathode material by arc discharge for film formation on a surface of a substrate, and including a cathode formed in a substantially disc shape and a magnetic field generating apparatus, disposed at a back side of the cathode. The magnetic field generating apparatus generates a magnetic field which forms magnetic lines that form an acute angle with respect to a substrate direction at an outer circumferential surface of the cathode, magnetic lines that are substantially perpendicular to the discharge surface at an outermost circumference part of the discharge surface of the cathode, and magnetic lines that form an acute angle with respect to a center direction of the cathode at a region towards the outer circumferential surface of the discharge surface of the cathode, by at least one permanent magnet disposed at the back side of the cathode. | 2016-03-24 |
20160086771 | SILICON DIOXIDE-POLYSILICON MULTI-LAYERED STACK ETCHING WITH PLASMA ETCH CHAMBER EMPLOYING NON-CORROSIVE ETCHANTS - Multilayered stacks having layers of silicon interleaved with layers of a dielectric, such as silicon dioxide, are plasma etched with non-corrosive process gas chemistries. Etching plasmas of fluorine source gases, such as SF | 2016-03-24 |
20160086772 | AUTO FREQUENCY TUNED REMOTE PLASMA SOURCE - A remote plasma source is disclosed that includes a core element and a first plasma block including one or more surfaces at least partially enclosing an annular-shaped plasma generating region that is disposed around a first portion of the core element. The remote plasma source further comprises one or more coils disposed around respective second portions of the core element. The remote plasma source further includes an RF power source configured to drive a RF power signal onto the one or more coils that is based on a determined impedance of the plasma generating region. Energy from the RF power signal is coupled with the plasma generating region via the one or more coils and the core element. | 2016-03-24 |
20160086773 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a reaction chamber for performing a plasma process on a substrate. A pedestal to receive the substrate thereon is provided in the reaction chamber. The reaction chamber includes an area A to generate the plasma therein, an exhaust area, and an area B provided between the area A and the exhaust area. The plasma is generated in the area B. An inner wall of the area A is covered with a first gasifying material. A plurality of partition members made of a second gasifying material is provided downstream of a surface of the substrate on the pedestal so as to divide an inside of the chamber into the area A and the area B to prevent a first particle present in the area B from diffusing into the area A. | 2016-03-24 |
20160086774 | PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - In an inductively-coupled plasma torch unit, a coil, a first ceramic block, and a second ceramic block are arranged, parallel to one another, and an elongated chamber has an annular shape. Plasma generated inside the chamber is ejected toward a substrate through an opening portion in the chamber. The substrate is processed by relatively moving the elongated chamber and the substrate in a direction perpendicular to a longitudinal direction of the opening portion. A rotating ceramic pipe having a cylindrical shape is provided so as to cause a refrigerant to flow into a cavity formed inside the ceramic pipe. Accordingly, it becomes possible to apply greater high-frequency power, thereby enabling fast plasma processing. | 2016-03-24 |
20160086775 | APPARATUS AND METHOD FOR DEPOSITING ELECTRONICALLY CONDUCTIVE PASTING MATERIAL - A method and apparatus are described for reducing particle contamination in a plasma processing chamber. In one embodiment, a pasting disk is provided which includes a disk-shaped base of high-resistivity material that has an electrically conductive pasting material layer applied to a top surface of the base so that the pasting material layer partially covers the top surface of the base. The pasting disk is sputter etched to deposit conductive pasting material over a wide area on the interior surfaces of a plasma processing chamber while minimizing deposition on dielectric components that are used to optimize the sputter etch process during substrate processing. | 2016-03-24 |
20160086776 | EDGE-CLAMPED AND MECHANICALLY FASTENED INNER ELECTRODE OF SHOWERHEAD ELECTRODE ASSEMBLY - An inner electrode of a showerhead electrode assembly useful for plasma etching includes features providing improved positioning accuracy and reduced warping, which leads to enhanced uniformity of plasma processing rate. The assembly can include a thermal gasket set and fasteners such as bolts or cam locks located on a radius of ¼ to ½ the radius of the inner electrode. A method of assembling the inner electrode and gasket set to a supporting member is also provided. | 2016-03-24 |
20160086777 | SPUTTERING TARGET-BACKING PLATE ASSEMBLY - The present invention is a sputtering target-backing plate assembly in which the sputtering target is made from Ta having a 02% proof stress of 150 to 200 MPa, and the backing plate is made from a Cu alloy having a 0.2% proof stress of 60 to 200 MPa. The present invention aims to increase the uniformity of the film thickness as well as increase the deposition rate and improve the productivity by reducing, as much as possible, the plastic deformation of the sputtering target caused by the repeated thermal expansion and contraction of the sputtering target-backing plate assembly as a bimetal. | 2016-03-24 |
20160086778 | SPUTTERING TARGET AND METHOD FOR MANUFACTURING TRANSPARENT CONDUCTIVE FILM USING THE SAME - A sputtering target includes: a first crystal comprising In | 2016-03-24 |
20160086779 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SPUTTERING APPARATUS - Reliability of a semiconductor device is improved, and use efficiency of a sputtering apparatus is increased. When depositing thin films over a main surface of a semiconductor wafer using a magnetron sputtering apparatus in which a collimator is installed in a space between the semiconductor wafer and a target installed in a chamber, a region inner than a peripheral part of the collimator is made thinner than the peripheral part. Thus, it becomes possible to suppress deterioration in uniformity of the thin film in a wafer plane, which may occur as the integrated usage of the target increases. | 2016-03-24 |
20160086780 | MULTI-SEGMENT INJECTION-CAPILLARY ELECTROPHORESIS-MASS SPECTROMETRY (MSI-CE-MS): A MULTIPLEXED SCREENING PLATFORM AND DATA WORKFLOW FOR CHEMICAL ANALYSIS - Various embodiments illustrating a multiplexed method for high throughput screening of ions in biological samples within a single capillary when using capillary electrophoresis mass spectrometry (CE-MS) are illustrated. The method includes sequential injection of multiple sample segments in series within a single capillary, the sample segments being separated by a spacer plug of buffer, and multiplexed analysis of the sample segments simultaneously within a single capillary electrophoresis (CE) run. The method also includes application of voltage to the single capillary subsequent to sequential injection and zonal separation of polar metabolites within each sample segment by CE such that each analyte zone migrates within its characteristic electrophoretic mobility offset in time by the spacer. The incorporation of a quality control/reference sample and the use of dilution patterning with specific injection configurations also enables encoding of information temporally for enhanced data processing with quality assurance. | 2016-03-24 |
20160086781 | RARE EVENT DETECTION USING MASS TAGS - The invention generally relates to methods for rare event detection using mass tags. In certain embodiments, the invention provides methods for detecting a target analyte in a sample that involve conducting an assay that specifically associates a mass tag with a target analyte in a sample, generating ions of the mass tag, and analyzing the generated ions of the mass tag, thereby detecting the target analyte from the sample. | 2016-03-24 |
20160086782 | Species Detection Using Mass Spectrometry - Systems and methods are provided for species detection using mass spectrometry. In various embodiments, a multiple reaction monitoring (MRM) experiment is performed on a sample targeting one or more peptide transitions that are unique to one or more species using a tandem mass spectrometer. One or more measured product ion spectra are received from the tandem mass spectrometer using the processor. The one or more measured product ion spectra are compared to product ions of the one or more peptide transitions that are unique to one or more species using the processor. One or more species of the sample are detected by reporting product ions of the one or more peptide transitions that are unique to one or more species that match the one or more measured product ion spectra using the processor. | 2016-03-24 |
20160086783 | Improved Data Quality after Demultiplexing of Overlapped Acquisition Windows - Systems and methods are provided for identifying missing product ions after demultiplexing product ion spectra produced by overlapping precursor ion transmission windows in sequential windowed acquisition tandem mass spectrometry. Overlapping sequential windowed acquisition is performed on a sample. A first precursor mass window and the corresponding first product ion spectrum are selected from a plurality of overlapping stepped precursor mass windows and their corresponding product ion spectra. A product ion spectrum is demultiplexed for each overlapped portion of the first precursor mass window producing two or more demultiplexed first product ion spectra for the first precursor mass window. The two or more demultiplexed first product ion spectra are added together producing a reconstructed summed demultiplexed first product ion spectrum. Missing product ions are identified in the summed demultiplexed first product ion spectrum by comparing the summed demultiplexed first product ion spectrum and the first product ion spectrum. | 2016-03-24 |
20160086784 | IONIZATION CHAMBER WITH TEMPERATURE-CONTROLLED GAS FEED - The invention relates to an ionization chamber for connection to a mass spectrometer. The ionization chamber has a temperature-control block with a gas inlet and a gas channel which starts at the gas inlet and leads into a gas outlet. A temperature-control device is positioned along the gas channel and ensures that a gas flowing in the gas channel is brought to a specific temperature, i.e. it is heated or cooled, before it enters the ionization chamber. The temperature-control block has a formed part into which a structure of the gas channel is incorporated and which is fabricated by means of a sol-gel process, for example out of a glass or ceramic material. | 2016-03-24 |
20160086785 | METHODS AND DEVICES FOR GENERATING DOUBLE EMULSIONS - The present disclosure describes devices and methods capable of generating multi-phase emulsions, including double emulsion droplets in a gas phase. The present disclosure also describes interfaces for coupling a multi-phase emulsion droplet source to an analytical instrument such as a mass spectrometer. The present disclosure further describes methods, systems, and apparatuses for using the devices and interfaces described to perform analysis, including mass spectrometry. The present disclosure also describes methods, systems, and apparatuses for generating and using multi-phase emulsions to perform analysis. | 2016-03-24 |
20160086786 | ISOLATION OF CHARGED PARTICLE OPTICS FROM VACUUM CHAMBER DEFORMATIONS - A charged particle processing apparatus includes a vacuum chamber, an optics plate, charged particle optics mounted to the optics plate, and mounting members coupled between the optics plate and a chamber wall. The mounting members are configured for isolating the optics plate from deformation of the chamber wall, as may occur due to a pressure differential between the chamber interior and the environment outside the chamber. The isolation may prevent deformation from affecting the alignment and positioning of the charged particle optics. The charged particles may, for example, be ions or electrons. Thus, the apparatus may be utilized, for example, in analytical instruments such as for mass spectrometry, or inspection instruments such as for electron microscopy. | 2016-03-24 |
20160086787 | DETECTION OF IONS IN AN ION TRAP - An ion trap such as an ion cyclotron resonance analyzer cell (trap) is described wherein the ion trap comprises a plurality of electrodes and has at least one integrated ion detector, preferably a position-sensitive and/or time-sensitive ion detector, wherein at least part of said ion detector is configured as an electrode of said ion trap. Methods of position-sensitive detection of ions in such ion trap are described as well. | 2016-03-24 |
20160086788 | ELLIPTICAL AND DUAL PARABOLIC LASER DRIVEN SEALED BEAM LAMPS - The invention is directed to a sealed high intensity illumination device configured to receive a laser beam from a laser light source. A sealed chamber is configured to contain an ionizable medium. The chamber includes a reflective chamber interior surface having a first parabolic contour and parabolic focal region, a second parabolic contour and parabolic focal region, and an interface surface. An ingress surface is disposed within the interface surface configured to admit the laser beam into the chamber, and an egress surface disposed within the interface surface configured to emit high intensity light from the chamber. The first parabolic contour is configured to reflect light from the first parabolic focal region to the second parabolic contour, and the second parabolic contour is configured to reflect light from the first parabolic contour to the second parabolic focal region. | 2016-03-24 |
20160086789 | AUTOMOTIVE FRONT LIGHTING LAMP WITH BAFFLE - A lamp for automotive vehicle front lighting is described. The lamp | 2016-03-24 |
20160086790 | COMPONENT PREPARATION INSTRUCTION SYSTEM, COMPONENT PREPARATION INSTRUCTION METHOD, AND PORTABLE TERMINAL - A component preparation instruction system performs a component preparation instruction for preparing a reel member to be supplied to a component mounting line in an off-line set-up area set outside the component mounting line, in a component mounting system. The component preparation instruction system includes a management section that manages production data including information about the reel members and information about the component mounters to which the reel members is attached, a reading section that reads reel information relating to the reel members, a collating section that collates the reel information read by the reading section with the information about the reel members included in the production data, and an output section that outputs attachment position information for a matching reel member, including information about at least one component mounter to which the matching reel member is to be attached. | 2016-03-24 |
20160086791 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - The present invention increases controllability of a composition ratio of a multi-element film that contains a predetermined element and at least one element selected from the group consisting of boron, oxygen, carbon and nitrogen. There is provided a method of manufacturing a semiconductor device, including: forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) forming the first film being free of borazine ring structure and including a predetermined element and at least one element selected from the group consisting of oxygen, carbon and nitrogen; and (b) forming the second film having a borazine ring structure and including at least boron and nitrogen. | 2016-03-24 |
20160086792 | METHOD FOR EVALUATING SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for evaluating a semiconductor film of a semiconductor device which is configured to include an insulating film, the semiconductor film, and a conductive film and to have a region where the semiconductor film and the conductive film overlap with each other with the insulating film provided therebetween, includes a step of performing plasma treatment after formation of the insulating film, and a step of calculating a peak value of resistivity of a microwave in the semiconductor film by a microwave photoconductive decay method after the plasma treatment, so that the hydrogen concentration in the semiconductor film is estimated. | 2016-03-24 |
20160086793 | METHOD AND A PROCESSING DEVICE FOR PROCESSING AT LEAST ONE CARRIER - According to various embodiments, a method may include: filling a chamber and a tube coupled to the chamber with a first liquid, the tube extending upwards from the chamber; introducing a portion of a second liquid into the first liquid in the tube; and at least partially removing the first liquid from the chamber to empty the tube into the chamber so that a continuous surface layer from the introduced second liquid is provided on the first liquid in the chamber. | 2016-03-24 |
20160086794 | NITROGEN DOPED AMORPHOUS CARBON HARDMASK - Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided. The method comprises positioning a substrate in a substrate processing chamber, introducing a nitrogen containing hydrocarbon source into the processing chamber, introducing a hydrocarbon source into the processing chamber, introducing a plasma-initiating gas into the processing chamber, generating a plasma in the processing chamber, and forming a nitrogen doped amorphous carbon layer on the substrate. | 2016-03-24 |
20160086795 | INTERNAL PLASMA GRID APPLICATIONS FOR SEMICONDUCTOR FABRICATION - The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes. | 2016-03-24 |
20160086796 | SELF-FORMING SPACERS USING OXIDATION - A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin. | 2016-03-24 |
20160086797 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A manufacturing method of a semiconductor device includes generating hydrogen radicals by plasma excitation of hydrogen gas and exposing a surface of a substrate on which silicon and metal are exposed to a reducing atmosphere created with the hydrogen radicals, and generating hydrogen radicals and hydroxyl radicals by plasma excitation of a mixed gas of hydrogen gas and oxygen-containing gas and oxidizing the silicon exposed on the surface of the substrate by exposing the surface of the substrate to the hydrogen radicals and hydroxyl radicals to obtain the substrate on which the metal and oxidized silicon are formed. | 2016-03-24 |
20160086798 | SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the following steps. There is prepared a silicon carbide single crystal substrate having a first main surface, a second main surface, and a first side end portion, the second main surface being opposite to the first main surface, the first side end portion connecting the first main surface and the second main surface to each other, the first main surface having a width with a maximum value of more than 100 mm. A silicon carbide epitaxial layer is formed in contact with the first side end portion, the first main surface, and a boundary between the first main surface and the first side end portion. The silicon carbide epitaxial layer formed in contact with the first side end portion and the boundary is removed. | 2016-03-24 |
20160086799 | Method of Producing Silicon Carbide Epitaxial Substrate, Silicon Carbide Epitaxial Substrate, and Silicon Carbide Semiconductor Device - A method of producing a silicon carbide epitaxial substrate includes steps of: preparing a silicon carbide substrate; and forming a silicon carbide layer on the silicon carbide substrate. In this production method, in the step of forming the silicon carbide layer, a step of growing an epitaxial layer and a step of polishing a surface of the epitaxial layer are repeated twice or more. | 2016-03-24 |
20160086800 | TUNNELING FIELD EFFECT TRANSISTORS AND TRANSISTOR CIRCUITRY EMPLOYING SAME - A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature molecular beam epitaxy at a growth temperature at or below 500° C. | 2016-03-24 |
20160086801 | METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of processing a substrate includes: growing a first layer including a first element and a second element by supplying a first precursor containing the first element and a second precursor containing the second element to the substrate; and growing a second layer including the second element and a third element by supplying the second precursor and a third precursor containing the third element to the substrate. The act of growing the first layer and the act of growing the second layer are alternately performed a predetermined number of times, and the act of growing the first layer is performed before the act of growing the second layer to selectively grow a laminated film on a conductive film exposed on the surface of the substrate. The first layer and the second layer are laminated to form the laminated film. | 2016-03-24 |
20160086802 | LASER ANNEALING TECHNIQUE FOR METAL OXIDE TFT - This disclosure provides methods and apparatuses for annealing an oxide semiconductor in a thin film transistor (TFT). In one aspect, the method includes providing a substrate with a partially fabricated TFT structure formed on the substrate. The partially fabricated TFT structure can include an oxide semiconductor layer and a dielectric oxide layer on the oxide semiconductor layer. The oxide semiconductor layer is annealed by heating the dielectric oxide layer with an infrared laser under ambient conditions to a temperature below the melting temperature of the oxide semiconductor layer. The infrared laser radiation can be substantially absorbed by the dielectric oxide layer and can remove unwanted defects from the oxide semiconductor layer at an interface in contact with the dielectric oxide layer. | 2016-03-24 |
20160086803 | METHOD FOR FABRICATING SEMICONDUCTOR LAYERS INCLUDING TRANSISTOR CHANNELS HAVING DIFFERENT STRAIN STATES, AND RELATED SEMICONDUCTOR LAYERS - Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods. | 2016-03-24 |
20160086804 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - First, a first resist mask for forming an n | 2016-03-24 |
20160086805 | METAL-GATE WITH AN AMORPHOUS METAL LAYER - A particular semiconductor device includes a substrate, a source contact, a drain contact, and a metal-gate. The substrate includes a source region, a drain region, and a channel. The source contact is coupled to the source region. The drain contact is coupled to the drain region. The metal-gate is coupled to the channel. The metal-gate includes an amorphous metal layer. | 2016-03-24 |
20160086806 | Method for Disconnecting Polysilicon Stringers During Plasma Etching - A method of fabricating wordlines in semiconductor memory structures is disclosed that eliminates stringers between wordlines while maintaining a stable distribution of threshold voltage. A liner is deposited before performing a wordline etch, and a partial wordline etch is then performed. Remaining portions of the liner are removed, and the wordline etch is completed to form gates having vertical or tapered profiles. | 2016-03-24 |
20160086807 | SILICON ETCH PROCESS WITH TUNABLE SELECTIVITY TO SiO2 AND OTHER MATERIALS - A tunable plasma etch process includes generating a plasma in a controlled flow of a source gas including NH | 2016-03-24 |
20160086808 | PROCEDURE FOR ETCH RATE CONSISTENCY - Methods of conditioning interior processing chamber walls of an etch chamber are described. A fluorine-containing precursor may be remotely or locally excited in a plasma to treat the interior chamber walls periodically on a preventative maintenance schedule. The treated walls promote an even etch rate when used to perform gas-phase etching of silicon regions following conditioning. Alternatively, a hydrogen-containing precursor may be remotely or locally excited in a plasma to treat the interior chamber walls in embodiments. Regions of exposed silicon may then be etched with more reproducible etch rates from wafer-to-wafer. The silicon etch may be performed using plasma effluents formed from a remotely excited fluorine-containing precursor. | 2016-03-24 |
20160086809 | PATTERNING METHOD AND SEMICONDUCTOR STRUCTURE - A patterning method is provided. A substrate including a material layer thereon is provided. A patterned hard mask layer, having a plurality of first holes, is formed on the material layer. Afterward, a mask layer, including a plurality of line pattern masks extending in a direction and dividing each first hole into a second hole and a third hole, is formed. The material layer is patterned using the patterned hard mask layer and the mask layer as masks to form a patterned material layer having a plurality of fourth and fifth holes. Furthermore, a semiconductor structure is provided. | 2016-03-24 |
20160086810 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a rotating holder for a substrate, a first nozzle used to eject a jet flow, a second nozzle used to discharge a continuous flow, and a nozzle moving unit integrally moving the first and second nozzles. A landing position of the continuous flow is located closer to a rotation center than a landing position of the jet flow is. At least movement paths of the landing positions of the jet flow and the continuous flow or flow directions of the continuous flow and the jet flow are different from each other. The movement paths are made to be different from each other by locating the landing position of the continuous flow downstream of the movement path of the landing position of the jet flow. The flow directions are made to be different from each other by tilting the continuous flow. | 2016-03-24 |
20160086811 | VERTICAL NO-SPIN PROCESS CHAMBER - A processing chamber includes a base, a cover, and grippers. The base includes a body, a mating surface, an inner zone cavity extending into the body, a divider substantially surrounding the inner zone cavity, and an outer zone cavity extending into the body and substantially surrounding the divider. The cover includes a mating surface that contacts the body mating surface when the processing chamber is closed. The grippers hold the wafer in the inner zone cavity when the processing chamber is closed. | 2016-03-24 |
20160086812 | METHOD FOR TREATING ETCHING SOLUTION - A method for treating an etching solution in order to circulate and reuse an etching solution used in etching treatment of silicon includes (1) selectively removing multivalent ions having a valence of two or more, or (2) removing multivalent ions having a valence of two or more, 20-50% of alkali metal ions having a valence of one relative to a total amount of the alkali metal ions, and hydroxide ions, through a membrane separation unit comprising a nanofiltration membrane. A permeated solution of the membrane separation unit is circulated to the etching bath. | 2016-03-24 |
20160086813 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming an active region in a semiconductor substrate, forming a plurality of dummy gates on the active region, the plurality of dummy gates having a gate mask disposed thereon, forming an interlayer insulating layer on the gate mask, and performing a one-time chemical mechanical polishing (CMP) process by using a slurry composition capable of polishing the interlayer insulating layer and the gate mask until top surfaces of the dummy gates are exposed. | 2016-03-24 |
20160086814 | ETCHING METHOD - An etching method includes loading a target substrate W into a chamber | 2016-03-24 |
20160086815 | FLUORINE-BASED HARDMASK REMOVAL - A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a fluorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. | 2016-03-24 |
20160086816 | CHLORINE-BASED HARDMASK REMOVAL - A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a chlorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. | 2016-03-24 |
20160086817 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS - A plasma etching method for plasma-etching an object including an etching target film and a patterned mask. The plasma etching method includes a first step of plasma-etching the etching target film using the mask, and a second step of depositing a silicon-containing film using plasma of a silicon-containing gas on at least a part of a side wall of the etching target film etched by the first step. | 2016-03-24 |
20160086818 | SUBSTRATE PROCESSING APPARATUS AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The temperature of a substrate is elevated rapidly while improving the temperature uniformity of the substrate. The substrate is loaded into a process chamber, the loaded substrate is supported on a first substrate support unit, a gas is supplied to the process chamber, the temperature of the substrate supported on the first substrate support unit is elevated in a state of increasing the pressure in the process chamber to higher than the pressure during loading of the substrate or in a state of increasing the pressure in the process chamber to higher than the pressure during processing for the surface of the substrate, the substrate supported on the first substrate support unit is transferred to the second substrate support unit and supported thereon after lapse of a predetermined time, and the surface of substrate is processed while heating the substrate supported on the second substrate support unit. | 2016-03-24 |
20160086819 | CMP POLISHING SOLUTION AND POLISHING METHOD USING SAME - A CMP polishing liquid for polishing a ruthenium-based metal, comprising polishing particles, an acid component, an oxidizing agent, and water, wherein the acid component contains at least one selected from the group consisting of inorganic acids, monocarboxylic acids, carboxylic acids having a plurality of carboxyl groups and having no hydroxyl group, and salts thereof, the polishing particles have a negative zeta potential in the CMP polishing liquid, and the pH of the CMP polishing liquid is less than 7.0. | 2016-03-24 |
20160086820 | LOCALIZED FIN WIDTH SCALING USING A HYDROGEN ANNEAL - Transistors and methods for fabricating the same include annealing channel portions of one or more semiconductor fins that are uncovered by a protective layer in a gaseous environment to reduce fin width, to produce a fin profile that is widest at the bottom and tapers toward the top, and to round corners of the one or more semiconductor fins. | 2016-03-24 |
20160086821 | PROCESS FOR MANUFACTURING A COMBINATION ANTI-THEFT AND TRACKING TAG - Manufacturing antennas for a dual tag by: providing a web structure having a dielectric layer between a first metal layer and a second metal layer; depositing a first resist on the first metal layer to define a radio frequency (RF) coil and a first electrode of an RF capacitor; depositing the first resist on the second metal layer to define a second electrode of the RF capacitor; depositing a second resist on the second metal layer to define connection pads for a near field antenna, wherein one of the first resist and the second resist on the second metal layer defines a far field antenna and the near field antenna; and etching the first and second metal layers to form the RF coil, the electrodes of the RF capacitor, the far field antenna, the near field antenna, and the connection pads. | 2016-03-24 |
20160086822 | PACKAGING SUBSTRATE HAVING A HOLDER, METHOD OF FABRICATING THE PACKAGING SUBSTRATE, PACKAGE STRUCTURE HAVING A HOLDER, AND METHOD OF FABRICATING THE PACKAGE STRUCTURE - A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided. | 2016-03-24 |
20160086823 | Systems and Methods for Mechanical and Electrical Package Substrate Issue Mitigation - Systems and methods are provided for an integrated circuit package. A plurality of electrical contacts are configured to provide a structure for electrically connecting the integrated circuit package to a printed circuit board. A package substrate includes at least one patterned metallic layer formed to electrically interconnect I/O contacts of an integrated circuit to the plurality of electrical contacts, and at least one generally uniform metallic layer having a plurality of voids that are respectively situated in axial alignment with corresponding ones of the electrical contacts, and one or more dielectric layers disposed between the plurality of electrical contacts and the metallic layers. Further, the package substrate includes a plurality of metallic elements disposed within the plurality of voids and electrically isolated from the generally uniform metallic layer, the metallic elements configured to reduce a physical size of respective voids without electrically contacting the generally uniform metallic layer. | 2016-03-24 |
20160086824 | BIO-IMPLANTABLE HERMETIC INTEGRATED ULTRA HIGH DENSITY DEVICE - An implantable bio-compatible integrated circuit device and methods for manufacture thereof are disclosed herein. The device includes a substrate having a recess. An input/output device including at least one bio-compatible electrical contact is coupled to the substrate in the recess. A layer of hermetic bio-compatible, hermetic insulator material is deposited on a portion of the input/output device. An encapsulating layer of bio-compatible material encapsulates at least a portion of the implantable device, including the input/output device. At least one bio-compatible electrical contact of the input/output device is then exposed. The encapsulating layer and the layer of bio-compatible, hermetic insulator material form a hermetic seal around the at least one exposed bio-compatible electrical contact. | 2016-03-24 |
20160086825 | SEMICONDUCTOR DEVICE AND METHOD OF ADAPTIVE PATTERNING FOR PANELIZED PACKAGING - An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns. | 2016-03-24 |
20160086826 | RESIN-ENCAPSULATD SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading end portions thereof are opposed to the die pad portion, and thin metal wires for connecting together electrodes of the semiconductor element and the lead portions. Those members are partially encapsulated by a resin. A bottom surface part of the die pad portion and a lead bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulation resin. After a cutout part devoid of the encapsulation resin is formed above a lead upper end part, a plating layer is formed on the lead bottom surface part and the lead upper end part. | 2016-03-24 |
20160086827 | METHODS FOR FORMING COLOR IMAGES ON MEMORY DEVICES AND MEMORY DEVICES FORMED THEREBY - A memory device including graphical content and a method of making the memory device with graphical content are disclosed. The graphical content is formed on a release media. The release media and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the graphical content is transferred from the release media to the encapsulated memory device. | 2016-03-24 |
20160086828 | MAGAZINE AND PROCESS EQUIPMENT INCLUDING THE SAME - A magazine includes a main body unit having a front side and a rear side, at least one of which is open, a plurality of slots formed inside two sidewalls of the main body unit, and at least one support member extending to the two sidewalls of the main body unit in a first direction. | 2016-03-24 |
20160086829 | SYSTEMS AND METHODS FOR DRYING HIGH ASPECT RATIO STRUCTURES WITHOUT COLLAPSE USING STIMULI-RESPONSIVE SACRIFICIAL BRACING MATERIAL - Systems and methods for drying a substrate including a plurality of high aspect ratio (HAR) structures is performed after at least one of wet etching and/or wet cleaning the substrate using at least one of wet etching fluid and/or wet cleaning fluid, respectively, and without drying the substrate. Fluid between the plurality of HAR structures is displaced using a solvent including a bracing material. After the solvent evaporates, the bracing material precipitates out of solution and at least partially fills the plurality of HAR structures. The plurality of HAR structures are exposed to non-plasma based stimuli to remove the bracing material. | 2016-03-24 |
20160086830 | DIE BONDING TOOL AND SYSTEM - Disclosed is a die bonding tool comprising: a rigid body; and a collet having a die-holding portion; wherein the collet is mechanically coupled to the rigid body by a flexible element which is configured to angularly deflect relative to the rigid body on application of a torque to the collet and/or to a die held by the collet. Also disclosed is a die bonding system comprising the die bonding tool, and an adhesive dispenser for a die bonding system. | 2016-03-24 |
20160086831 | METHODS AND APPARATUSES FOR DEUTERIUM RECOVERY - Novel methods, systems, and apparatuses for reclaiming annealing gases from a high pressure annealing processing system are disclosed. According to an embodiment, the exhaust gasses from the high pressure annealing processing system are directed into a gas reclaiming system only when a precious gas, e.g., deuterium is used. The annealing gas is the separated from other gasses used in the high pressure annealing processing system and is then pressurized, filtered, and purified prior to transferring the gas to a bulk storage distribution unit. In one embodiment, the reclaimed gas is then again provided to the high pressure annealing processing system to anneal the wafers. | 2016-03-24 |
20160086832 | Laser annealing systems and methods with ultra-short dwell times - Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 μs to about 100 μs. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed. | 2016-03-24 |
20160086833 | Mounting System and Charging Method for Disc-Shaped Objects - The invention relates to a mounting system ( | 2016-03-24 |
20160086834 | Multi-Stepped Boat Assembly for Receiving Semiconductor Packages - A multi-stepped boat assembly includes a stack boat having at least one stack hole configured to receive a first semiconductor package and a second semiconductor package vertically stacked on the first semiconductor package in the stack hole. A guide boat has at least one guide hole vertically aligned with the at least one stack hole. The guide boat is removably attachable to the stack boat. An inner sidewall of the stack hole includes a first step configured to receive the first semiconductor package, and a second step provided on the first step and configured to receive the second semiconductor package. The guide hole extends toward the stack hole to guide movement of the first semiconductor package to the first step. | 2016-03-24 |
20160086835 | COVER OPENING/CLOSING APPARATUS AND COVER OPENING/CLOSING METHOD - Disclosed is a cover opening/closing apparatus including a plurality of placement tables provided in a vertical direction. Each placement table is configured to place thereon a substrate accommodation container including a takeout port in one side surface and a cover that covers the takeout port. The apparatus includes a cover opening/closing mechanism provided to face the cover of the substrate accommodation container placed on each of the placement tables. At least the cover opening/closing mechanism at a placement table side of an upper stage includes: a latch key driven at a time of mounting/removing the cover; a suction port configured to suck gas within a space between the cover opening/closing mechanism and the cover; a cover holding unit configured to suck and hold the cover; and a packing provided at a more outer periphery side than the latch key and the suction port. | 2016-03-24 |
20160086836 | APPARATUS FOR FLIPPING SEMICONDUCTOR DEVICE - A method for automatically transferring multiple semiconductor devices from a first substrate to a second substrate comprises steps of providing a first substrate on which the semiconductor device is formed, providing a second substrate directly under the first substrate, automatically moving the first substrate toward the second substrate such that the semiconductor devices are close to the second substrate; connecting the semiconductor devices to the second substrate by exerting force to the second substrate, and taking out the semiconductor devices simultaneously from the first substrate. | 2016-03-24 |
20160086837 | COMPLIANT BIPOLAR MICRO DEVICE TRANSFER HEAD WITH SILICON ELECTRODES - A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes. | 2016-03-24 |
20160086838 | WAFER ARRANGEMENT AND METHOD FOR PROCESSING A WAFER - A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably attachable to one another. | 2016-03-24 |
20160086839 | Method For The Production Of A Wafer With A Carrier Unit - The invention relates to a method for the production of layers of solid material, in particular for use as wafers, comprising the following steps: providing a workpiece ( | 2016-03-24 |
20160086840 | Isolation Structure of Semiconductor Device - The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench. | 2016-03-24 |
20160086841 | METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FORMED USING THE SAME - A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other. | 2016-03-24 |
20160086842 | Method for Producing a Semiconductor Device - A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench. | 2016-03-24 |
20160086843 | Shallow Trench Isolation Structures in Semiconductor Device and Method for Manufacturing the Same - Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed. | 2016-03-24 |
20160086844 | Method for Manufacturing a Composite Wafer having a Graphite Core, and Composite Wafer having a Graphite Core - A composite wafer is manufactured by providing a carrier wafer including graphite and a protective layer, forming a bonding layer, and bonding the carrier wafer to a semiconductor wafer through the bonding layer. | 2016-03-24 |
20160086845 | A METHOD FOR PROCESSING AN INNER WALL SURFACE OF A MICRO VACANCY - There is provided a method for processing an inner wall surface of a micro vacancy, capable of reliably etching or cleaning even if the hole provided to the substrate to be processed is narrow and deep. The substrate has a surface and a micro vacancy with an opening on the surface. An aspect ratio of the micro vacancy being at least 5, or the aspect ratio being less than 5 and a ratio of a micro vacancy volume to a surface area of the opening being at least 3. The micro vacancy is exposed to an atmosphere for forming a silicon oxide film so as to form a silicon oxide film on the inner wall surface of the micro vacancy. Subsequently a processing solution with a wettability with respect to silicon oxide is introduced into the micro vacancy so as to perform processing of the inner wall surface. | 2016-03-24 |
20160086846 | Global Dielectric and Barrier Layer - Methods of fabricating a semiconductor device are described. The method includes forming a patterned oxide layer having a plurality of openings over a substrate, depositing a metal layer in the openings to form metal plugs, depositing a global transformable (GT) layer on the oxide layer and the metal plugs, and depositing a capping layer directly on the GT layer without exposing the GT layer to ambient air. The GT layer on the oxide layer transforms into a dielectric oxide and the GT layer on the metal plugs remains conductive during deposition of the capping layer. | 2016-03-24 |
20160086847 | METHOD OF ELECTRODEPOSITING GOLD ON A COPPER SEED LAYER TO FORM A GOLD METALLIZATION STRUCTURE - An electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first device terminal. A seed layer is formed on the barrier layer. The seed includes a noble metal other than gold. The substrate is masked so that a first mask opening is laterally aligned with the first terminal. An unmasked portion of the seed layer is electroplated using a gold electrolyte solution so as to form a first gold metallization structure in the first mask opening. The mask, the masked portions of the seed layer, and the barrier layer are removed. The noble metal from the unmasked portion of the seed layer is diffused into the first gold metallization structure. The first gold metallization structure is electrically connected to the first terminal via the barrier layer. | 2016-03-24 |
20160086848 | Conductive Line Structure with Openings - Wide and narrow mandrels that are used to form sidewall spacers for patterning are formed in a sacrificial layer with openings in wide mandrels near sides of the wide mandrels. Sidewall spacers are formed on the sides of mandrels and the sacrificial layer is removed. The sidewall spacers are then used for patterning of underlying layers. | 2016-03-24 |
20160086849 | CONSTRAINED NANOSECOND LASER ANNEAL OF METAL INTERCONNECT STRUCTURES - In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material. | 2016-03-24 |
20160086850 | SELECTIVE AREA DEPOSITION OF METAL FILMS BY ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) - Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material. | 2016-03-24 |
20160086851 | HYBRID WAFER DICING APPROACH USING AN ADAPTIVE OPTICS-CONTROLLED LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an adaptive optics-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits. | 2016-03-24 |
20160086852 | PROXIMITY CONTACT COVER RING FOR PLASMA DICING - Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly. | 2016-03-24 |
20160086853 | WAFER PROCESSING METHOD - A wafer is divided along a plurality of crossing division lines to obtain a plurality of individual devices. The division lines are formed on the front side of the wafer to define a plurality of separate device regions. An adhesive film is applied to the back side of the wafer and the other side of the adhesive film is attached to a dicing tape composed of a base sheet and an ultraviolet curable adhesive layer formed on the base sheet. The adhesive film is attached to the ultraviolet curable adhesive layer of the dicing tape. Ultraviolet light is applied to the dicing tape to thereby cure the adhesive layer. A rotating cutting blade cuts the wafer together with the adhesive film along the division lines, dividing the wafer into the individual devices. The cutting blade is positioned so that its cutting edge cuts into the cured adhesive layer. | 2016-03-24 |
20160086854 | Semiconductor Device and Method of Manufacturing a Semiconductor Device Having a Glass Piece and a Single-Crystalline Semiconductor Portion - A semiconductor device includes a glass piece and an active semiconductor element formed in a single-crystalline semiconductor portion. The single-crystalline semiconductor portion has a working surface, a rear side surface opposite to the working surface and an edge surface connecting the working and rear side surfaces. The glass piece has a portion extending along and in direct contact with the edge surface of the single-crystalline semiconductor portion. | 2016-03-24 |
20160086855 | SYSTEMS AND METHODS FOR CONTROLLING RELEASE OF TRANSFERABLE SEMICONDUCTOR STRUCTURES - The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a destination substrate, a native substrate is formed with micro devices thereon. The micro devices can be distributed over the native substrate and spatially separated from each other by an anchor structure. The anchors are physically connected/secured to the native substrate. Tethers physically secure each micro device to one or more anchors, thereby suspending the micro device above the native substrate. In certain embodiments, single tether designs are used to control the relaxation of built-in stress in releasable structures on a substrate, such as Si (1 0 0). Single tether designs offer, among other things, the added benefit of easier break upon retrieval from native substrate in micro assembly processes. In certain embodiments, narrow tether designs are used to avoid pinning of the undercut etch front. | 2016-03-24 |
20160086856 | Metal Gate Structure and Method - A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the substrate, depositing a plurality of films on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a gate electrode layer over the plurality of films and removing an upper portion of the gate electrode layer until the gate electrode layer is removed from the resistor trench. | 2016-03-24 |
20160086857 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction. | 2016-03-24 |
20160086858 | STRUCTURE AND METHOD FOR ADVANCED BULK FIN ISOLATION - A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant. | 2016-03-24 |
20160086859 | Dummy Gate for a High Voltage Transistor Device - The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other. | 2016-03-24 |
20160086860 | METHODS FOR MAKING ROBUST REPLACEMENT METAL GATES AND MULTI-THRESHOLD DEVICES IN A SOFT MASK INTEGRATION SCHEME - A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer. | 2016-03-24 |
20160086861 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING A NANOWIRE CHANNEL STRUCTURE - A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different. | 2016-03-24 |
20160086862 | CMOS Devices with Reduced Leakage and Methods of Forming the Same - A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a ( | 2016-03-24 |
20160086863 | SEMICONDUCTOR DEVICE FOR TESTING LARGE NUMBER OF DEVICES AND COMPOSING METHOD AND TEST METHOD THEREOF - Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors. | 2016-03-24 |
20160086864 | MOVABLE GAS NOZZLE IN DRYING MODULE - Provided herein are methods and apparatuses for cleaning wafers by coating an active surface of the wafer with a film of water to clean the wafer, delivering gas from a gas nozzle to the center of the active surface to break a film of water on the active surface to form a wet-dry boundary while spinning the wafer, and moving the gas nozzle radially outward from the center to the edge of the active surface of the wafer by following the wet-dry boundary. Tracking devices, such as cameras or charge-coupled devices, and systems may be used with an apparatus for cleaning wafers by tracking the wet-dry boundary on the wafer to move the gas nozzle to follow the wet-dry boundary. Cleaning apparatuses provided herein may be integrated with etching tools. | 2016-03-24 |