12th week of 2011 patent applcation highlights part 47 |
Patent application number | Title | Published |
20110072174 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN ONE-TO-ONE COMMUNICATION - An apparatus and method for transmitting and receiving data in one-to-one communication are provided. A first buffer for temporarily storing file data and a second buffer for temporarily storing message data are connected to a data transmitter for transmitting data and a data receiver for receiving data, respectively or vice versa, according to a request for data transmission or reception. The buffer for storing file data and the buffer for storing message data are differently constructed, thereby reducing the waste of memories of the buffers and achieving the miniaturization and high-speed data transmission of a portable terminal device. | 2011-03-24 |
20110072175 | Multimedia-capable computer management system for selectively operating a plurality of computers - The present invention provides an intelligent, modular multimedia computer management system for coupling a series of remote computers to one or more user workstations to allow each user workstation to selectively access and control one or more remote computers. The computer management system incorporates a centralized switching system that receives keyboard, cursor control device, audio, and auxiliary peripheral device signals from the user workstation and transmits and applies the signals to the remote computer in the same manner as if the keyboard, cursor control device, audio input source, or auxiliary peripheral device of the user workstation were directly coupled to the remote computer. Also, the user workstation receives audio signals and auxiliary peripheral device signals from the remote computer. In addition, the multimedia computer management system transmits video signals from the remote computer over an extended range for display on the video monitor of the user workstation. | 2011-03-24 |
20110072176 | METER SYSTEM WITH MASTER/SLAVE METERS - A meter system includes a CAN-Bus, a master meter, a slave bus, and a slave meter. The master meter includes a first CAN module, a master display, a master communication interface, and a master processor. The master meter is for receiving a signal transmitted from the CAN-Bus and for transforming the signal to a message signal, so as to control the master display to display the corresponding information or to transfer the message signal to the salve bus. The slave meter includes a slave communication interface, a slave display, and a slave processor. The slave meter is for receiving the message signal transmitted from the slave bus and for controlling the slave display to display the corresponding information. | 2011-03-24 |
20110072177 | VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER - The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled. | 2011-03-24 |
20110072178 | Data processing apparatus and a method for setting priority levels for transactions - A data processing apparatus and method for setting priority levels for transactions is provided. The data processing apparatus has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The at least one master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry is used to apply an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource, the arbitration policy using the priority level associated with each of the multiple transactions when performing the selection. Adaptive priority circuitry is associated with at least one of the sources, the adaptive priority circuitry monitoring throughput indication data for previously issued transactions from the associated source, and for each new transaction from the associated source, setting the priority level to one of a plurality of predetermined priority levels dependent on the throughput indication data. Through such a mechanism, the adaptive priority circuitry sets the lowest priority level from amongst the plurality of predetermined priority levels that will enable a specified target throughput to be achieved. The adaptive priority circuitry hence uses a feedback mechanism to control the priority level assigned to each new transaction from a source in order to target a specified throughput for the source, and through this mechanism finds the lowest priority necessary to achieve the throughput objectives independent of the activity of other sources within the system. | 2011-03-24 |
20110072179 | PACKET PRIORITIZATION SYSTEMS AND METHODS USING ADDRESS ALIASES - A switch fabric includes input links, output links, and at least one switching element. The input links are configured to receive data items that include destination addresses. At least some of the data items have different priority levels. The output links are configured to output the data items. Each of the output links is assigned multiple ones of the destination addresses. Each of the destination addresses corresponds to one of the priority levels. The switching element(s) is/are configured to receive the data items from the input links and send the data items to ones of the output links without regard to the priority levels of the data items. | 2011-03-24 |
20110072180 | INTERRUPT ON/OFF MANAGEMENT APPARATUS AND METHOD FOR MULTI-CORE PROCESSOR - Provided are an interrupt on/off management apparatus and method for a multi-core processor having a plurality of central processing unit (CPU) cores. The interrupt on/off management apparatus manages the multi-core processor such that at least one of two or more CPU cores included in a target CPU set can execute an urgent interrupt. For example, the interrupt on/off management apparatus controls the movement of each CPU core from a critical section to a non-critical section such that at least one of the CPU cores is located in the non-critical section. The critical section may include an interrupt-disabled section or a kernel non-preemptible section, and the non-critical section may include an interrupt-enabled section or include both of the interrupt-enabled section and a kernel preemptible section. | 2011-03-24 |
20110072181 | ABNORMAL STATUS DETECTING METHOD OF INTERRUPT PINS - An abnormal status detecting method of interrupt pins is provided. In the invention, an advanced configuration and power interface (ACPI) table is looked up for obtaining an interrupt status bit of each interrupt pin in a computer system. Afterwards, the interrupt status bit is continuously checked whether it is maintained at a specific value during a fixed time. When the interrupt status bit of one of the interrupt pins is maintained at the specific value during the fixed time, the interrupt pin is determined to be abnormal. | 2011-03-24 |
20110072182 | I/O CONNECTION SYSTEM, METHOD AND PROGRAM - In execution of hot-plug processing consisting of a plurality of processing steps for connecting an I/O to a host, the hot-plug processing is temporarily stopped upon completion of predetermined processing steps in the hot-plug processing, and the hot-plug processing is resumed once it is detected that connection between the host and the I/O has been established and the host has been enabled to access the I/O. | 2011-03-24 |
20110072183 | INITIATOR AND TARGET FIREWALLS - A system comprising a first logic adapted to use qualifiers received from a component to determine which of a plurality of storages matches the qualifiers, the first logic generates a first signal indicative of a storage matching the qualifiers. The system also comprises a second logic coupled to the first logic and adapted to use a target address received from the component to determine which of the plurality of storages matches the target address, the second logic generates a second signal indicative of a storage matching the target address. Another logic is adapted to determine whether the storage associated with the first signal matches the storage associated with the second signal. The qualifiers indicate security mode attributes associated with the component. | 2011-03-24 |
20110072184 | DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data processing device is configured so that a USB host module to be coupled to a plurality of central processing units has a plurality of pipes to communicate with an arbitrary end point of a USB device coupled from the outside of the data processing device, the data processing device also includes an access control register to specify which central processing unit should have a right to control the pipe and specify to which extent a range of the content of setting of a function for the pipe should be allowed, and a USB host interface is controlled in accordance with the content of setting of the access control register. | 2011-03-24 |
20110072185 | MULTI-PROTOCOL STORAGE DEVICE BRIDGE - A bridge includes a host interface via which data/commands are received from and transferred to a host, and a storage device interface via which data/commands are received from and transferred to a storage device. The bridge also includes one SDPC, a controller and a switching system that is configurable by the controller to connect the protocol converter to the host interface and the storage device interface if the storage device protocol used by the host device differs from the storage device protocol used by the storage device, and to connect the host device interface to the storage device interface, not via the bi-directional protocol converter, if the two storage device protocols are the same. The bridge may include two SDPCs, each for converting a different protocol to the host protocol and vice versa, with the switching system being configurable to switch between the two SDPCs. The bridge may omit the SDPC altogether, with the switching system being configurable to switch between connecting (1) the host device interface to the storage device interface, and (2) bypassing the storage device interface. | 2011-03-24 |
20110072186 | PORTABLE COMPUTER CAPABLE OF CONVERTING INTERNAL STORAGE DEVICE INTO EXTERNAL STORAGE DEVICE - A portable computer capable of converting an internal storage device into an external storage device and, without being booted up, functioning as the external storage device is disclosed. The portable computer includes: an external interface connector; a switcher connected to an internal storage device, a south bridge chip, and an interface converter, and is configured to switch between the south bridge chip and the interface converter and thus allow one of the south bridge chip and the interface converter to be electrically conducted to the internal storage device; the interface converter connected to the switcher and an external interface controller to allow an interface of the external interface controller to be changed and thus be fit for use with the internal storage device; and the external interface controller connected to an interface switcher and the external interface connector and configured to process signals from the external interface connector. | 2011-03-24 |
20110072187 | DYNAMIC STORAGE OF CACHE DATA FOR SOLID STATE DISKS - Described embodiments provide a media controller that determines the size of a cache of data being transferred between a host device and one or more sectors of a storage device. The one or more sectors are segmented into a plurality of chunks, and each chunk corresponds to at least one sector. The contents of the cache are managed in a cache hash table. At startup of the media controller, a buffer layer module of the media controller initializes the cache in a buffer of the media controller. During operation of the media controller, the buffer layer module determines a number of chunks allocated to the cache. Based on the number of chunks allocated to the cache, the buffer layer module updates the size of the of the cache hash table. | 2011-03-24 |
20110072188 | MEMORY SYSTEM INCLUDING NON-VOLATILE STORAGE MEDIA, COMPUTING SYSTEM INCLUDING MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM - In one aspect, meta data corresponding to a non-volatile storage media is read from the non-volatile storage media. Meta data to be updated is detected from the read meta data. Based on the read meta data and the detected meta data to be updated, storage areas of the non-volatile storage media are invalidated. | 2011-03-24 |
20110072189 | METADATA REDUNDANCY SCHEMES FOR NON-VOLATILE MEMORIES - Systems and methods are provided for storing data to or reading data from a non-volatile memory (“NVM”), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, flags, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. This way, even if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location. | 2011-03-24 |
20110072190 | MEMORY DEVICE AND METHOD - A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of non-volatile memory comprises a plurality of word locations and an address decoder coupled to a first access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block comprising a plurality of word locations and an address decoder coupled to a second access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the second access port. The memory controller comprising an input coupled to the programmable storage location, and to access, in response to the programmable configuration information having a first value, a first portion of the first memory block and a first portion of the second memory block as interleaved memory, a second portion of the first memory block as non-interleaved memory, and a second portion of the second memory block as non-interleaved memory. | 2011-03-24 |
20110072191 | Uniform Coding System for a Flash Memory - A uniform coding system for a flash memory is disclosed. A statistic decision unit determines a coding word according to a plurality of inputs. An inverse unit controllably inverts input data to be encoded. The input data are then encoded into encoded data according to a statistic determined by the statistic decision unit. | 2011-03-24 |
20110072192 | SOLID STATE MEMORY WEAR CONCENTRATION - A memory system includes a volatile memory and a non-volatile memory. The volatile memory is configured as a random access memory or cache for the nonvolatile memory. Wear concentration logic targets one or more selected devices of the nonvolatile memory for accelerated wear. | 2011-03-24 |
20110072193 | DATA READ METHOD, AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened. | 2011-03-24 |
20110072194 | Logical-to-Physical Address Translation for Solid State Disks - Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device. | 2011-03-24 |
20110072195 | METHOD FOR MANAGING A MEMORY DEVICE HAVING MULTIPLE CHANNELS AND MULTIPLE WAYS, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a memory device having multiple channels and multiple ways includes: with regard to a logical page, finding a Flash memory chip for being written from a plurality of Flash memory chips according to a predetermined order of the Flash memory chips, and during finding the Flash memory chip, omitting any Flash memory chip that is busy or not suitable for writing; and writing data belonging to the logical page and a serial number for indicating a writing order into a corresponding physical page within a block of the Flash memory chip that is found. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory chips. | 2011-03-24 |
20110072196 | Cache Synchronization for Solid State Disks - Described embodiments provide a media controller that synchronizes data cached in a buffer and corresponding data stored in one or more sectors of a storage device. A buffer layer module of the media controller caches data transferred between the buffer and the storage device. One or more contiguous sectors are associated with one or more chunks. The buffer layer module updates a status corresponding to each chunk of the cached data and scans the status corresponding to a first chunk of cached data. If, based on the status, the first chunk of cached data is more recent than the corresponding data stored on the storage device, a media layer module synchronizes the data on the storage device with the cached data. The status corresponding to the group of one or more sectors is updated. The media layer module scans a next chunk of cached data, if present. | 2011-03-24 |
20110072197 | Buffering of Data Transfers for Direct Access Block Devices - Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers. | 2011-03-24 |
20110072198 | ACCESSING LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION DATA FOR SOLID STATE DISKS - Described embodiments provide a media controller for a storage device having sectors, the sectors organized into blocks and superblocks. The media controller stores, on the storage device, logical-to-physical address translation data in N summary pages, where N corresponds to the number of superblocks of the storage device. A buffer layer module of the media controller initializes a summary page cache in a buffer. The summary page cache has space for M summary page entries, where M is less than or equal to N. For operations that access a summary page, the media controller searches the summary page cache for the summary page. If the summary page is stored in the summary page cache, the buffer layer module retrieves the summary page from the summary page cache. Otherwise, the buffer layer module retrieves the summary page from the storage device and stores the retrieved summary page to the summary page cache. | 2011-03-24 |
20110072199 | STARTUP RECONSTRUCTION OF LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION DATA FOR SOLID STATE DISKS - Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory. | 2011-03-24 |
20110072200 | Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command. | 2011-03-24 |
20110072201 | Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command. | 2011-03-24 |
20110072202 | METHOD FOR WEAR LEVELING IN A NONVOLATILE MEMORY - A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased. | 2011-03-24 |
20110072203 | METHOD AND DEVICES FOR INSTALLING AND RETRIEVING LINKED MIFARE APPLICATIONS - A method for installing linked MIFARE applications (TK | 2011-03-24 |
20110072204 | MEMORY SERVER - A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers. | 2011-03-24 |
20110072205 | MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell. | 2011-03-24 |
20110072206 | Distributed content storage and retrieval - Distributed content storage and retrieval is disclosed. A set of features associated with a content object is determined. A storage location is selected to perform an operation with respect to the content object, from a plurality of storage locations comprising a distributed content storage system, based at least in part on probability data indicating a degree to which the selected storage location is associated statistically with a feature comprising the set of features determined to be associated with the content object. | 2011-03-24 |
20110072207 | APPARATUS AND METHOD FOR LOGGING OPTIMIZATION USING NON-VOLATILE MEMORY - A logging optimization technology using a non-volatile memory is provided. A log record has a first link connected based on a page unit and a second link connected based on a transaction unit. The log record is stored in a non-volatile memory buffer. The log record stored in the non-volatile memory buffer is deleted or moved to a disk, if necessary. | 2011-03-24 |
20110072208 | Distributed Storage Resource Scheduler and Load Balancer - Distributed storage resources are managed based on data collected from online monitoring of workloads on the storage resources and performance characteristics of the storage resources. Load metrics are calculated from the collected data and used to identify workloads that are migration candidates and storage units that are migration destinations, so that load balancing across the distributed storage resources can be achieved. | 2011-03-24 |
20110072209 | Processing Diagnostic Requests for Direct Block Access Storage Devices - Described embodiments provide a media controller for processing a diagnostic request received from a diagnostic source. The received diagnostic request is parsed by a corresponding request handling module of the media controller, where each diagnostic source type has a corresponding request handling module. If the received diagnostic request requires allocation of buffer space, a common diagnostic handling module of the media controller allocates buffer space in a buffer for the received diagnostic request. The common diagnostic handling module is common for all diagnostic source types. The common diagnostic handling module provides the received diagnostic request to a corresponding one of a plurality of end diagnostic handling modules. The end diagnostic handling module performs the diagnostic tasks. If the received diagnostic request requires a transfer of data to the diagnostic source, the common diagnostic handling module performs the data transfer between the media controller and the diagnostic source. | 2011-03-24 |
20110072210 | PESSIMISTIC DATA READING IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a data retrieval request and determining a read threshold number of dispersed storage (DS). The method continues with the processing module sending read request messages to DS units and receiving encoded data slices to produce received encoded data slices. The method continues with the processing module determining an incremental number of encoded data slices based on the number of received encoded data slices, determining an incremental number of DS units, and sending a read request message to each of the incremental number of DS units when the number of received encoded data slices compares unfavorably to a decode threshold number. The method continues with the processing module dispersed storage error decoding the received encoded data slices to produce data when the number of received encoded data slices compares favorably to the decode threshold number of encoded data slices. | 2011-03-24 |
20110072211 | Hardware For Parallel Command List Generation - A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit. | 2011-03-24 |
20110072212 | CACHE MEMORY CONTROL APPARATUS AND CACHE MEMORY CONTROL METHOD - A cache memory controller searches a second cache tag memory holding a cache state information indicating whether any of multi-processor cores storing a registered address of information registered within its own first cache memory exists. When a target address coincides with the obtained registered address, the cache memory controller determines whether an invalidation request or a data request to a processor core including a block is necessary based on the cache status information. Once it is determined that invalidation or a data request for the processor including the block, the cache memory controller determines whether a retry of instruction based on a comparison result of the first cache tag memory is necessary, if it is determined that invalidation or a data request for the processor including the block. | 2011-03-24 |
20110072213 | INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY - A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier. | 2011-03-24 |
20110072214 | Read and Write Aware Cache - A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy. | 2011-03-24 |
20110072215 | Cache system and control method of way prediction for cache memory - A cache device according to an exemplary aspect of the present invention includes a way information buffer that stores way information that is a result of selecting a way in an instruction that accesses a cache memory; and a control unit that controls a storage processing and a read processing, while a series of instruction groups are repeatedly executed, the storage processing being for storing the way information in the instruction groups to the way information memory, the read processing being for reading the way information from the way information memory. | 2011-03-24 |
20110072216 | Memory control device and memory control method - Address information of target data is stored in an ELA register at the start of a cache excluding process performed by BackEviction, and a request processing unit continuously re-executes a data acquiring process while an address of data requested to be acquired by a processor is present in the ELA register. The address information of the target data is stored in an EWB buffer at the start of autonomous move-out performed by a processor, and the cache excluding process performed by BackEviction is stopped when the address of data subjected to BackEviction is present in the EWB buffer. | 2011-03-24 |
20110072217 | Distributed Consistent Grid of In-Memory Database Caches - A plurality of mid-tier databases form a single, consistent cache grid for data in a one or more backend data sources, such as a database system. The mid-tier databases may be standard relational databases. Cache agents at each mid-tier database swap in data from the backend database as needed. Consistency in the cache grid is maintained by ownership locks. Cache agents prevent database operations that will modify cached data in a mid-tier database unless and until ownership of the cached data can be acquired for the mid-tier database. Cache groups define what backend data may be cached, as well as a general structure in which the backend data is to be cached. Metadata for cache groups is shared to ensure that data is cached in the same form throughout the entire grid. Ownership of cached data can then be tracked through a mapping of cached instances of data to particular mid-tier databases. | 2011-03-24 |
20110072218 | PREFETCH PROMOTION MECHANISM TO REDUCE CACHE POLLUTION - A processor is disclosed. The processor includes an execution core, a cache memory, and a prefetcher coupled to the cache memory. The prefetcher is configured to fetch a first cache line from a lower level memory and to load the cache line into the cache. The cache is further configured to designate the cache line as a most recently used (MRU) cache line responsive to the execution core asserting N demand requests for the cache line, wherein N is an integer greater than 1. The cache is configured to inhibit the cache line from being promoted to the MRU position if it receives fewer than N demand requests. | 2011-03-24 |
20110072219 | MANAGING COHERENCE VIA PUT/GET WINDOWS - A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements. | 2011-03-24 |
20110072220 | METHOD AND APPARATUS FOR DETERMINING ACCESS PERMISSIONS IN A PARTITIONED DATA PROCESSING SYSTEM - In a data processing system having a plurality of resources and plurality of partitions, each partition including one or more resources of the plurality of resources, a method includes receiving an access request to a target resource of the plurality of resources; using a first set of transaction attributes of the access request to determine a partition identifier for the access request in which the partition identifier indicates a partition of the plurality of partitions which includes the target resource; using the partition identifier to determine access permissions for the partition indicated by the partition identifier; and based on the access permissions, determining whether or not the access request is permitted. | 2011-03-24 |
20110072221 | METHOD FOR WRITING AND READING DATA IN A NONVOLATILE MEMORY, BY MEANS OF METADATA - A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A | 2011-03-24 |
20110072222 | METHOD FOR SECURE DATA READING AND DATA HANDLING SYSTEM - A method for secure data reading and a data handling system is provided. The method protects the data reading from fault attacks by repeating read request in an interleaved manner, in particular the method comprises the steps of (M | 2011-03-24 |
20110072223 | METHOD AND SYSTEM FOR MANAGING COOKIES IN WEB COMMUNICATIONS - A system and method which may allow a Web application to manage cookies and prevent important data in cookies from being arbitrarily deleted. Cookie data may be separated into a number of tiers according to their importance. When a request to write new data to a cookie is received, the tier to which the new data belongs may be determined and compared to the tier(s) of existing data in the cookie, and existing data may be deleted from the cookie to free room for the new data only when the existing data is not more important than the new data. | 2011-03-24 |
20110072224 | SNAPSHOT METADATA MANAGEMENT IN A STORAGE SYSTEM - Methods and systems for improving performance in a storage system utilizing snapshots are disclosed by using metadata management of snapshot data. Specifically, various metadata structures associated with snapshots are utilized to reduce the number of IO operations required to locate data within any specific snapshot. The number of IO operations are reduced by allowing the various metadata structures associated with the temporally current snapshot to locate data directly within any temporally earlier snapshot or on the original root volume. | 2011-03-24 |
20110072225 | APPLICATION AND TIER CONFIGURATION MANAGEMENT IN DYNAMIC PAGE REALLOCATION STORAGE SYSTEM - For storage management in a tiered storage environment in a system having one or more applications running on a host computer which is connected to a storage system, the storage system comprises storage volumes in a pool which are divided into a plurality of tiers having different tier levels, the tiers being organized according to a tier configuration rule; and a controller. The controller allocates the pool to a plurality of virtual volumes based on a change of the tier levels against the physical storage devices. The controller stores a relation between data in the storage system being accessed by each application running on the host computer and an application ID of the application accessing the data. The tier level of a portion of a storage volume of the plurality of storage volumes is changed based at least in part on the application accessing data in the storage volume. | 2011-03-24 |
20110072226 | SNAPSHOTTING OF A PERFORMANCE STORAGE SYSTEM IN A SYSTEM FOR PERFORMANCE IMPROVEMENT OF A CAPACITY OPTIMIZED STORAGE SYSTEM - A system for storing data comprises a performance storage system for storing one or more data items. A data item of the one or more data items comprises a data file or a data block. The system further comprises a segment storage system for storing a snapshot of a stored data item of the one or more data items in the performance storage system. The taking of the snapshot of the stored data item enables recall of the stored data item as stored at the time of the snapshot. At least one newly written segment is stored as a reference to a previously stored segment. | 2011-03-24 |
20110072227 | PERFORMANCE IMPROVEMENT OF A CAPACITY OPTIMIZED STORAGE SYSTEM USING A PERFORMANCE SEGMENT STORAGE SYSTEM AND A SEGMENT STORAGE SYSTEM - A system for storing data comprises a performance storage unit for storing a data stream or a data block in. The data stream or the data block comprises one or more data items. The system further comprises a segment storage system for automatically storing a stored data item of the one or more data items as a set of segments. The system further comprises a performance segment storage unit for storing the set of segments in the event that the stored data item has been stored using the segment storage system. | 2011-03-24 |
20110072228 | STORAGE CONTROLLER AND CONTROL METHOD FOR THE SAME - An object of the invention is to provide a storage controller and control method that can efficiently and easily prevent reduced data I/O processing performance due to an imbalance between loads on controllers. In the storage controller and control method for providing, to a host computer, logical volumes created in a storage area provided by a storage device and controlling data I/O to/from the logical volumes, the state of loads on the control units for controlling data I/O to/from the logical volumes is monitored, and a control unit allocated to a logical volume is changed to another control unit to equalize loads on the control units. | 2011-03-24 |
20110072229 | METHOD OF MIRRORING DATA BETWEEN CLUSTERED NAS SYSTEMS - Data of a global file system spread over multiple local NAS systems may be consolidated as a copy into a single remote NAS system. When remote copy is set up, the local NAS systems replace referrals within the global file system with directories and send these in place of the referrals to the remote NAS system. Then, other local NAS systems referred to by the referrals send files and directories under the directories replacing the referrals on the remote NAS system. Alternatively, to split copy data of a locally-stored global file system amongst multiple remote NAS systems, the local NAS system replaces specified directories with referrals, and sends the referrals with the data to one of the remote NAS systems. Then, the local NAS system sends files and directories under the directories replaced with referrals to one or more other remote NAS systems as referred to by the referrals. | 2011-03-24 |
20110072230 | ON DEMAND STORAGE GROUP MANAGEMENT WITH RECAPTURE - A method to dynamically adjust the amount of free space in a storage group is disclosed herein. In certain embodiments, such a method may include monitoring the amount of free space in an active storage group. The method may further include maintaining an overflow storage group containing unused volumes. When the free space in the active storage group falls below a lower threshold value, the method may automatically move a volume from the overflow storage group to the active storage group. Conversely, when the free space in the active storage group exceeds an upper threshold value, the method may automatically transfer data from a volume in the active storage group to other volumes in the active storage group, and move the volume from the active storage group to the overflow storage group. A corresponding computer program product and apparatus are also disclosed herein. | 2011-03-24 |
20110072231 | Device, method and computer-readable medium relocating remote procedure call data in heterogeneous multiprocessor system on chip - Disclosed is a device, method and computer-readable medium relocating Remote Procedure Call (RPC) data in a heterogeneous multiprocessor System-on-Chip (MPSoC). The method, for example, includes determining a memory where data is to be stored based on a use of a parameter of a function, and data access patterns of a function caller and a function callee, and storing the data in the determined memory. | 2011-03-24 |
20110072232 | DISK DRIVE INCLUDING A HOST INTERFACE SUPPORTING DIFFERENT SIZES OF DATA SECTORS AND METHOD FOR WRITING DATA THERETO - A method for writing data to a disk drive. The method includes: receiving a write command; and, determining whether a beginning and an end of a rewrite area specified by the write command agree with boundaries of large-sized data sectors on a disk. The method also includes: reading head and tail data sectors and making a backup of the head and tail data sectors in first and second non-volatile memory areas, respectively, if the beginning of the rewrite area does not agree with the boundaries. The method includes starting a rewrite of the rewrite area after completing backups into first and second non-volatile memory areas. Moreover, the method includes: determining a state stage by using data in first, second, third and fourth non-volatile memory areas if a power shut-down occurs during execution of the write command; and, executing a recovery process in accordance with the determined state stage. | 2011-03-24 |
20110072233 | Method for Distributing Data in a Tiered Storage System - This disclosure provides a method for assigning data in a plurality of physical storage resources for an information handling system. The plurality of physical storage resources includes a first tier of physical storage resources and a second tier which has a lower performance and cost relative to capacity than each of the first tier. A tier manager may be hosted on the information handling system and in electronic communication with the plurality physical storage resources. The tier manager may: determine a seek distance value for each page, determine an operation rate for each page, determine an operation size value for each page, determine an elapsed time value for each page; and calculate a relative randomness value for each page using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page. A classification module may assign a physical location for each page such that the relative randomness value for each page in the first tier is greater than the relative randomness value for each page in the second tier. | 2011-03-24 |
20110072234 | Providing Hardware Support For Shared Virtual Memory Between Local And Remote Physical Memory - In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed. | 2011-03-24 |
20110072235 | EFFICIENT MEMORY TRANSLATOR WITH VARIABLE SIZE CACHE LINE COVERAGE - One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills. | 2011-03-24 |
20110072236 | Method for efficient and parallel color space conversion in a programmable processor - The present invention relates to an efficient implementation of color space conversion in a SIMD processor as part of converting output of video decompression to interface to a display unit. | 2011-03-24 |
20110072237 | Methods and apparatus for efficiently sharing memory and processing in a multi-processor - A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any source operand addresses or target operand addresses. The source operands and target operands for arithmetic/logic execution units are provided by independent load instruction operations and independent store instruction operations. | 2011-03-24 |
20110072238 | Method for variable length opcode mapping in a VLIW processor - The present invention provides a method for reducing program memory size required for a dual-issue processor with a scalar processor plus a SIMD vector processor. Coding the map of next group of instruction pairs in a no-operation (NOP) instruction of scalar and vector processor reduces the cases where one of the scalar or vector opcode being a NOP opcode. NOP for either scalar or vector processor defines the next 13 instructions as scalar-plus-vector, scalar-followed-by-scalar, or vector-followed-by-vector so that execution unit performs accordingly until next NOP or a branch instruction. | 2011-03-24 |
20110072239 | DATA MULTICASTING IN A DISTRIBUTED PROCESSOR SYSTEM - Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions. The providing target routing instructions may further comprise the selected information utilizing a subset of bits that is commonly shared by the target instructions and being identified as a left operand, right operand or predicate operand, and may include the selection of one of a plurality of multiple-instruction subsets of the target instructions. | 2011-03-24 |
20110072240 | Self-Similar Processing Network - Self-similar processing by unit processing cells may together solve a problem. A unit processing cell may include a processor, a memory and a plurality of Input/Output (IO) channels coupled to the processor. The memory may include a dictionary having one or more instructions that configure the processor to perform at least one function. The plurality of IO channels may be used to communicably couple the unit processing cell with a plurality of other unit processing cells each including their own respective dictionary. The unit processing cell and the plurality of other unit processing cells may be independent of one another and may perform together without a centralized control. The processor may update the dictionary so that the unit processing cell builds a different dictionary from the plurality of other unit processing cells, thereby being self-similar to the plurality of other unit processing cells. | 2011-03-24 |
20110072241 | FAST CONCURRENT ARRAY-BASED STACKS, QUEUES AND DEQUES USING FETCH-AND-INCREMENT-BOUNDED AND A TICKET LOCK PER ELEMENT - Implementation primitives for concurrent array-based stacks, queues, double-ended queues (deques) and wrapped deques are provided. In one aspect, each element of the stack, queue, deque or wrapped deque data structure has its own ticket lock, allowing multiple threads to concurrently use multiple elements of the data structure and thus achieving high performance. In another aspect, new synchronization primitives FetchAndIncrementBounded (Counter, Bound) and FetchAndDecrementBounded (Counter, Bound) are implemented. These primitives can be implemented in hardware and thus promise a very fast throughput for queues, stacks and double-ended queues. | 2011-03-24 |
20110072242 | CONFIGURABLE PROCESSING APPARATUS AND SYSTEM THEREOF - A configurable processing apparatus includes a plurality of processing units, at least an instruction synchronization control circuit, and at least a configuration memory. Each processing apparatus has a stall-output signal generating circuit to output a stall-output signal, wherein the stall-output signal indicates that an unexpected stall is occurred in the processing unit. The processing unit has a stall-in signal, and an external circuit of the processing unit can control whether the processing unit is stalled according to the stall-in signal. The instruction synchronization control circuit generates the stall-in signals to the processing units in response to a content stored in the configuration memory and the stall-output signals of the processing units, so as to determine operation modes and instruction synchronization of the processing units. | 2011-03-24 |
20110072243 | Unified Collector Structure for Multi-Bank Register File - One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles. | 2011-03-24 |
20110072244 | Credit-Based Streaming Multiprocessor Warp Scheduling - One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution. | 2011-03-24 |
20110072245 | HARDWARE FOR PARALLEL COMMAND LIST GENERATION - A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit. | 2011-03-24 |
20110072246 | NODE CONTROL DEVICE INTERPOSED BETWEEN PROCESSOR NODE AND IO NODE IN INFORMATION PROCESSING SYSTEM - A node control device is interposed between processor nodes and IO nodes in an information processing system, wherein each IO node subordinates at least one IO device. The node control device includes a register storing a base address of a mapping destination of an IO space, a table describing a plurality of entries retaining a plurality of IO space numbers and address ranges, and an IO space access detection circuit. The table stores an identification flag as to whether or not IO spaces are each mapped onto a memory space. The IO space access detection circuit decodes a command code and an address of an FRTT signal output from a processor node, thus detecting a target IO space and detecting whether the processor node is accessing an IO space mapped onto the memory space or another IO space. | 2011-03-24 |
20110072247 | FAST APPLICATION PROGRAMMABLE TIMERS - Methods, systems, and computer program products for implementing fast application programmable timers are provided. A computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a request to set a user accessible timer, the request received from an application thread. The user accessible timer is set in response to receiving the request, the setting including initializing a counter. The counter is decremented until an interrupt threshold has been reached. An interrupt signal is transmitted to the application thread in response to detecting that the interrupt threshold has been reached. | 2011-03-24 |
20110072248 | UNANIMOUS BRANCH INSTRUCTIONS IN A PARALLEL THREAD PROCESSOR - One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch. | 2011-03-24 |
20110072249 | UNANIMOUS BRANCH INSTRUCTIONS IN A PARALLEL THREAD PROCESSOR - One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch. | 2011-03-24 |
20110072250 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 2011-03-24 |
20110072251 | PILE PROCESSING SYSTEM AND METHOD FOR PARALLEL PROCESSORS - A system, method and computer program product are provided for processing exceptions. Initially, computational operations are processed in a loop. Moreover, exceptions are identified and stored while processing the computational operations. Such exceptions are then processed separate from the loop. | 2011-03-24 |
20110072252 | COMPUTER SYSTEM AND MOTHERBOARD AND MONITOR THEREOF - A first terminal of a first switch, a first idling pin, a third idling pin, and a power pin are connected together. A second terminal of the first switch, a first ground pin, a second ground pin, and a third ground pin are electrically connected together. A first terminal of the second switch, a second idling pin, a fourth idling pin, and a reset pin are electrically connected together. A second terminal of the second switch, a first ground pin, a second ground pin, and a third ground pin are electrically connected together. The first switch controls the motherboard to power on or power off, and the second switch controls the motherboard to reset. | 2011-03-24 |
20110072253 | METHOD, SYSTEM AND PROGRAM PRODUCT FOR DETERMINING AN OPTIMAL CONFIGURATION AND OPERATIONAL COSTS FOR IMPLEMENTING A CAPACITY MANAGEMENT SERVICE - A method, system and program product for determining an optimal configuration and operational costs for implementing a capacity management service. The method includes storing in a knowledge management system factual data and business rules for determining an optimal configuration for implementing the capacity management service, and inputting into the knowledge management system a plurality of business-technical variables supplied by an end user. The method further includes selecting a priority level for one or more of the business-technical variables inputted based on a set of business-technical factors, harmonizing the priority level selected for the one or more business-technical variables in order to minimize any inconsistencies among the priority level selected and determining the optimal configuration and associated operational costs for implementing the capacity management service, using the business-technical variables inputted and using the factual data and the business rules stored in the knowledge management system. | 2011-03-24 |
20110072254 | METHOD AND SYSTEM FOR SECURED DYNAMIC BIOS UPDATE - In some embodiments, the invention involves providing a secure BIOS update to selective user operating systems in a platform conforming to virtualization technology. In an embodiment, a provision agent in a service operating system identifies requests for BIOS updates received from a management console and forwards authorized update requests to a virtual machine monitor (VMM) for processing the updates according to platform policy. An update may be applied immediately to some user operating systems and be delayed in others. Some updates may require an immediate reboot of the platform. Other embodiments are described and claimed. | 2011-03-24 |
20110072255 | PROVISIONING OF OPERATING ENVIRONMENTS ON A SERVER IN A NETWORKED ENVIRONMENT - The illustrative embodiments disclose a computer implemented method, apparatus, and computer program product for provisioning a server on a network. In one embodiment, the process sends a server identifier to a management server in response to receiving a boot command. The management server uses the server identifier for identifying a designated operating environment for the server to form a designated operating environment identifier. The process then receives, from the management server, the designated operating environment identifier and a first bootstrap code. The process uses the first bootstrap code to extract information for identifying a local operating environment on the server. Thereafter, the process compares the local operating environment to the designated operating environment and initiates a final boot sequence of the server based on the comparison of the local operating environment and the designated operating environment. | 2011-03-24 |
20110072256 | EFFICIENT METHOD FOR OPERATING SYSTEM DEPLOYMENT - Method and computer storage media for efficiently deploying an operating system are provided. A virtual hard drive file is communicated by a computing device, such as a server. The virtual hard drive file may be compounded with a boot manager enhancer and/or a translator. Upon receipt of the virtual hard drive file, a computing device is enhanced to expose and mount the virtual hard drive as a drive and boot option for the computing device. Thereafter, an initial boot sequence may be commenced utilizing the virtual hard drive file as the boot source. In some embodiments, a boot manager enhancer and a translator are utilized to do one or more of expose, mount, and translate the virtual hard drive file. In some embodiments, a virtual SCSI miniport driver is utilized to do one or more of expose, mount, and translate the virtual hard drive file. | 2011-03-24 |
20110072257 | METHOD AND DEVICE FOR IMPROVING ACCESSABILITY TO INFORMATION DISPLAYED ON A COMPUTER - A method is described for providing a user of a Personal Computer having one or more physical and/or cognitional limitations, with an improved PC experience, wherein said method comprises: a. evaluating one or more physical or cognitional limitations of the user; b. assigning values to a plurality of pre-defined parameters based on the user own evaluation, wherein at least one of the plurality of pre-defined parameters is a member of a group consisting of: brightness value, contrast value, background color, text size value, text color preference, time duration between two consecutive mouse clicks (double click), cursor size value, icons size value, Keyboard sensitivity value and mouse sensitivity value; and c. adjusting at least one of the settings' values associated with the PC used by the user, based on the value of the one or more pre-defined parameters selected out of the plurality of pre-defined parameters, to enable providing a tailored PC experience to the user. | 2011-03-24 |
20110072258 | Modular Secure Data Transfer - A method and system that modularizes a message by separating the message definition data from the message data. The message definition data and message data are transmitted over a secure channel to a target computing device. The message definition data and message data are recombined to form the original message at the target computer using a process corresponding to the modularization process. A key is used to track the associated definitions and message data and determine the corresponding combination process. Separate transmission of the data definitions and message data provides an added level of security. If message data is intercepted and decrypted by a third party, then the data is not easily utilized, because the definition data is absent. Similarly, interception of the message definition is not useful without the message data. | 2011-03-24 |
20110072259 | VIRTUAL PAD - A system and method for communicating information over an insecure communications network include one or more computing devices that may access a first server via the communication network. In operation the first server displays an authentication Web page having a virtual pad with a plurality of characters that may be selected directly from a display of the computing device. | 2011-03-24 |
20110072260 | METHOD AND SYSTEM OF DOWNLOADABLE CONDITIONAL ACCESS USING DISTRIBUTED TRUSTED AUTHORITY - Disclosed is a downloadable conditional access system (DCAS) and an operational method thereof that distributes a part of a function of a Trusted Authority to each multiple system operator (MSO) to enable the MSO server to process authentication with respect to a secure micro (SM) chip and a transport processor (TP) chip, and thus, a normal DCAS service is possible even when there is a problem with a security, and a DCAS host terminal for rental use is effectively operated. | 2011-03-24 |
20110072261 | PROVIDING SECURITY BETWEEN NETWORK ELEMENTS IN A NETWORK - A first network element receives a message from a second network element. The message is modified by the first network element by inserting a certificate into the message, wherein the certificate includes an identity of the first network element and a digital signature produced by the first network element. The modified message is sent to a third network element. | 2011-03-24 |
20110072262 | System and Method for Identifying Security Breach Attempts of a Website - The present invention is a method, circuit and system for detecting, reporting and preventing an attempted security breach of a commercial website (for example a banking website), such as identity theft, website duplication (mirroring/Phishing), MITB (man in the browser) attacks, MITM (man in the middle) attacks and so on. | 2011-03-24 |
20110072263 | Device Pairing Based on Graphically Encoded Data - In a computing device, both an address of a first device and a secret are graphically encoded to generate one or more images that can be captured by a second device. The second device captures and decodes the one or more images, and sends a communication initiation request to the address of the first device. The communication initiation request includes the address of the second device and identifies the secret. Communication between the first and second device continues only if the first device verifies, based on the communication initiation request, that the second device knows the secret. | 2011-03-24 |
20110072264 | Secure information storage and retrieval apparatus and method - A user using a client computer registers with a server computer over a computer network by submitting a biometric scan of a body part of the user. The user commands the client computer to encrypt an electronic file. The client computer generates a private key, encrypts the electronic file and transmits the key to the server computer. The client computer saves the encrypted file. The encrypted file and the key are saved at different physical locations. The owner of the file is able to grant permission to other registered users to unlock the encrypted file. | 2011-03-24 |
20110072265 | System And Method Of Non-Centralized Zero Knowledge Authentication For A Computer Network - Zero-knowledge authentication proves identity without revealing information about a secret that is used to prove that identity. An authentication agent performs authentication of a prover agent without knowledge or transfer of the secret. A non-centralized zero-knowledge authentication system contains multiple authentication agents, for access by multiple computers seeking access on a computer network through local prover agents. Once authenticated, those multiple computers may also implement authentication agents. The secret may periodically expire by publishing a new encrypted secret by a trusted source, thwarting attempts to factor or guess information about the secret. | 2011-03-24 |
20110072266 | INFORMATION PROCESSING DEVICE, AUTHENTICATION SYSTEM, AUTHENTICATION DEVICE, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING PROGRAM, RECORDING MEDIUM, AND INTEGRATED CIRCUIT - The present invention provides an information processing device, an authentication system, etc. that save a server the trouble of updating a database, etc., even when a software module in a client device is updated, and that are capable of verifying whether software modules that have been started in the client device are valid. The terminal device A | 2011-03-24 |
20110072267 | METHOD, MOBILE AND NETWORK NODES FOR SHARING CONTENT BETWEEN USERS AND FOR TRACKING MESSAGES - A method for sharing multimedia content protected by RM by a first subscriber with at least one second subscriber of a communication system comprises: receiving the protected multimedia content by the at least one second subscriber from the first subscriber, who previously received the multimedia content; and requesting a license key for unlocking the protected multimedia content by the at least one second subscriber; wherein requesting the license key allows for correlating the license key with the multimedia content. | 2011-03-24 |
20110072268 | SERVER APPARATUS, LICENSE DISTRIBUTION METHOD, AND CONTENT RECEPTION APPARATUS - [Object] To stabilize an operation of a license server by avoiding concentration of license acquisition requests from a large number of clients at a time right after a broadcast start time of a content. | 2011-03-24 |
20110072269 | NETWORK AV CONTENTS PLAYBACK SYSTEM, SERVER, PROGRAM AND RECORDING MEDIUM - A system, including: an audio-visual terminal; and a storage terminal, wherein the audio-visual terminal establishes a first connection protected by authentication and encryption, to server providing AV contents on a network; acquires an authorization to use of the contents by the first connection, concurrently acquires download control information including contents location information that indicates a location of the AV contents on the network and license information about the AV contents; and transmits the acquired download control information to the storage terminal, and the storage terminal acquires the download control information from the audio-visual terminal, downloads the contents from the server based on the contents location information via the network and stores the contents; acquires a license of the contents from the server based on the license information and stores the license; and uses the contents for a predetermined period based on the stored license. | 2011-03-24 |
20110072270 | SYSTEM AND METHOD FOR SUPPORTING MULTIPLE CERTIFICATE STATUS PROVIDERS ON A MOBILE COMMUNICATION DEVICE - A method and system for supporting multiple digital certificate status information providers are disclosed. An initial service request is prepared at a proxy system client module and sent to a proxy system service module operating at a proxy system. The proxy system prepares multiple service requests and sends the service requests to respective multiple digital certificate status information providers. One of the responses to the service requests received from the status information providers is selected, and a response to the initial service request is prepared and returned to the proxy system client module based on the selected response. | 2011-03-24 |
20110072271 | DOCUMENT AUTHENTICATION AND IDENTIFICATION - Computer-implemented methods, systems, and computer program products for document authentication and identification using encoding and decoding are provided. A method includes receiving a digitized document and comparing the digitized document to a set of markers to determine whether the digitized document is an encoded document with one or more characters replaced. In response to determining that the digitized document is encoded, information is extracted from the set of markers using a decoder according to an encoding strategy. The extracted information and the set of markers are compared with data stored in encoding history to authenticate and identify the received digitized document. Markers in the encoded document may be hidden in plain sight, such that the encoding is not readily apparent to a casual observer. | 2011-03-24 |
20110072272 | LARGE-SCALE DOCUMENT AUTHENTICATION AND IDENTIFICATION SYSTEM - Computer-implemented methods, systems, and computer program products for document authentication and identification using a large-scale distributed system are provided. A method includes receiving a digitized document at a trusted system managed by a trusted third-party that is separate from a creator of content in the digitized document. The digitized document is compared to a set of markers to determine whether the digitized document includes one or more of the markers, and in response thereto, information associated with the one or more markers is extracted using a decoder on the trusted system according to encoding strategies. The method further includes generating a comparison registration identifier on the trusted system as a summary of the extracted information and the one or more markers, and comparing the comparison registration identifier with a stored registration identifier in an encoding history via the trusted system to authenticate and identify the received digitized document. | 2011-03-24 |
20110072273 | DATE-PROVABLE REGISTRATION SYSTEM FOR PUBLISHED DOCUMENTS - A system and method are disclosed for rendering published documents tamper evident. Embodiments render classes of documents tamper evident with cryptographic level security or detect tampering, where such security was previously unavailable, for example, documents printed using common printers without special paper or ink. Embodiments enable proving the date of document content without the need for expensive third party archival, including documents held, since their creation, entirely in secrecy or in untrustworthy environments, such as on easily-altered, publicly-accessible internet sites. Embodiments can extend, by many years, the useful life of currently-trusted integrity verification algorithms, such as hash functions, even when applied to binary executable files. Embodiments can efficiently identify whether multiple document versions are substantially similar, even if they are not identical, thus potentially reducing storage space requirements. | 2011-03-24 |