12th week of 2020 patent applcation highlights part 64 |
Patent application number | Title | Published |
20200091267 | DISPLAY APPARATUS, MANUFACTURING METHOD OF DISPLAY APPARATUS, AND ELECTRONIC DEVICE - A display apparatus including: a display region provided with a plurality of pixel portions; wires installed to the respective pixel portions within the display region from an outside of the display region for transmitting a signal to drive the respective pixel portions; connection pads provided on the outside of the display region and serving as input portions to provide the wires with a signal while electrically conducting with the wires; switch elements provided on the outside of the display region in a middle of the wires; and a light shielding covering portion shielding the switch elements from light and formed to cover the connection pads while electrically conducting with the connection pads. | 2020-03-19 |
20200091268 | DISPLAY DEVICE - Provided is a display device including: a substrate having a display area and a peripheral area outside the display area; a first transistor and a second transistor each located over the display area of the substrate and arranged at different levels on the substrate; and a plurality of wirings located over the peripheral area of the substrate, wherein the plurality of wirings include first wirings and second wirings, the first wirings and the second wirings being located at different levels on the substrate and are alternately arranged with each other. | 2020-03-19 |
20200091269 | DISPLAY DEVICE, DISPLAY DEVICE MANUFACTURING METHOD, AND DISPLAY DEVICE MANUFACTURING APPARATUS - A display device includes a TFT layer provided with a terminal configured to receive a signal inputted from an external source, and a terminal wiring line in a lower layer underlying the terminal, and a light emitting element layer in an upper layer overlying the TFT layer. The terminal includes a main portion and a peripheral portion surrounding the main portion. The peripheral portion is covered by a cover film, the terminal wiring line and a lower face of the peripheral portion are in contact, and the main portion and the terminal wiring line overlap via at least one terminal base film. | 2020-03-19 |
20200091270 | DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE - A display device includes a display module and a circuit board. The display module includes a base substrate, which includes a display area and a non-display area adjacent to the display area, and a first pad positioned on the base substrate and overlapping the non-display area. The circuit board includes a first board and a second pad positioned on the first board and contacting the first pad, wherein the second pad is provided with a first metal layer of a single material. | 2020-03-19 |
20200091271 | LIGHT-EMITTING DEVICE COMPRISING FLEXIBLE SUBSTRATE AND LIGHT-EMITTING ELEMENT - The light-emitting device includes a flexible substrate, a lower barrier layer positioned above the flexible substrate, a light-emitting element and a thin-film transistor controlling the light-emitting element positioned above the lower barrier layer, a first upper barrier layer positioned above the light-emitting element and including a first inorganic material, and a second upper barrier layer positioned above the thin-film transistor and including a second inorganic material. The first upper barrier layer and the second upper barrier layer are spaced from each other at least in a region between the light-emitting element and the thin-film transistor. | 2020-03-19 |
20200091272 | FLEXIBLE DISPLAY PANEL, FLEXIBLE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE FLEXIBLE DISPLAY PANEL - The present invention discloses a flexible display panel, a flexible display device and a method of manufacturing the flexible display panel, the metal patterns of the bent region of the flexible display panel of the present invention has a double-layer structure, and the second metal layer pattern is designed with a wavy pattern, which can reduce the stress on the metal layer patterns during pad bending process, decrease the breakage probability of metal layer patterns in the bent region of the flexible display, and ensure the resistance stability of the metal layer patterns. Furthermore, the connection portion between the first metal layer pattern and the second metal layer pattern can improve the reliability, reduce the abnormal probability of display caused by the pattern breakage, and ensure normal signal transmission. | 2020-03-19 |
20200091273 | TILING DISPLAY DEVICE - A tiling display device includes a plurality of display modules arranged on one plane. The display module includes a substrate, a signal line, an open hole, a filling layer, and a circuit board. The substrate has a display area in which subpixels are defined. The signal line is positioned on the top surface of the substrate within the display area to deliver a predetermined signal to the subpixels. The open hole is provided to penetrate the substrate within the display area. The filling layer fills the open hole. The circuit board is positioned on the back surface of the substrate and electrically connected to the signal line through the filling layer. | 2020-03-19 |
20200091274 | NON-LINEAR GATE DIELECTRIC MATERIAL FOR THIN-FILM TRANSISTORS - Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed. | 2020-03-19 |
20200091275 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material. | 2020-03-19 |
20200091276 | MEMORY DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a capacitor structure, a first contact plug, and a spacer. The capacitor structure is over the semiconductor substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric, and a top electrode. The bottom electrode is over the semiconductor substrate. The capacitor dielectric is over a first portion of the bottom electrode. The top electrode is over the capacitor dielectric. The first contact plug is on and connected to a second portion of the bottom electrode. The spacer is on at least a sidewall of the second portion of the bottom electrode. | 2020-03-19 |
20200091277 | Integrated Circuits with Capacitors - Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric. | 2020-03-19 |
20200091278 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a first electrode, forming a preliminary dielectric layer on the first electrode, forming a second electrode on the preliminary dielectric layer, and at least partially phase-changing the preliminary dielectric layer to form a dielectric layer. An interfacial energy between the first electrode and the dielectric layer may be less than an interfacial energy between the first electrode and the preliminary dielectric layer. | 2020-03-19 |
20200091279 | INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME - In a capacitor of an integrated circuit, a crystallization induction film is obtained by oxidizing a surface of an electrode, and a dielectric structure is formed on the crystallization induction film, to reduce defect density generated in the dielectric film, improve leakage current, and reduce equivalent oxide thickness. | 2020-03-19 |
20200091280 | SEMICONDUCTOR DEVICE - A semiconductor memory device includes an n-type source/drain formed in a surface region of a p-type active region, and a gate. The semiconductor memory device also includes a withstand voltage improvement layer provided with a preset distance maintained from at least one end of the source/drain. N-type impurities are diffused in the withstand voltage improvement layer, and a withstand voltage improvement voltage is applied to the withstand voltage improvement layer to expand a depletion layer to reach the source/drain, so that the maximum withstand voltage value of a transistor is increased. | 2020-03-19 |
20200091281 | SILICON CARBIDE SCHOTTKY DIODES - A silicon carbide (SiC) Schottky diode comprises a layer of N-type SiC and a layer of P-type SiC in contact with the layer of N-type SiC creating a P-N junction. An anode is in contact with both the layer of N-type SiC and the layer of P-type SiC creating Schottky contacts between the anode and both the layer of N-type SiC and the layer of P-type SiC. An edge of the layer of P-type SiC is electrically active and comprises a tapered negative charge density at the P-N junction, which can be achieved by a tapered or sloping edge the layer of P-type SiC. | 2020-03-19 |
20200091282 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer that has a main surface and that includes an active region, a first-conductivity-type first impurity region formed at a surface layer portion of the main surface of the semiconductor layer, a second-conductivity-type field limit region formed along a peripheral edge of the active region in a surface layer portion of the first impurity region, and a second-conductivity-type low concentration region that has a second-conductivity-type impurity concentration lower than a second-conductivity-type impurity concentration of the field limit region and that is formed along a peripheral edge of the field limit region in a region on a side opposite to the active region with respect to the field limit region in the surface layer portion of the first impurity region. | 2020-03-19 |
20200091283 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type. The semiconductor substrate includes a first semiconductor region of a second conductivity type at a surface thereof, a second semiconductor region of the second conductivity type at the surface and surrounding the first semiconductor region, a third semiconductor region of the second conductivity type provided in the second semiconductor region at the surface and surrounding the first semiconductor region. The third semiconductor region has a concentration of a second conductivity type impurity higher than that of the second semiconductor region. A first insulating film is provided on a part of the first surface at which the second semiconductor region is provided. the first insulating film having an opening that exposes. A first electrode is provided on the first insulating film and electrically connected to the third semiconductor region via the opening. | 2020-03-19 |
20200091284 | Semiconductor Device with a Dopant Source - A semiconductor device includes a semiconductor body having a first surface. A first trench extends in a vertical direction into the semiconductor body. The semiconductor device also includes a first interlayer in the first trench and a first dopant source in the first trench. The first interlayer is arranged between the first dopant source and the semiconductor body, and the first dopant source includes a first dopant species. The semiconductor device also includes a semiconductor area doped with the first dopant species and which completely surrounds the first trench at least at a depth in the semiconductor body and adjoins the first trench. | 2020-03-19 |
20200091285 | III-N METAL-INSULATOR-SEMICONDUCTOR FIELD EFFECT TRANSISTORS WITH MULTIPLE GATE DIELECTRIC MATERIALS - Integrated circuits with III-N metal-insulator-semiconductor field effect transistor (MISFET) structures that employ one or more gate dielectric materials that differ across the MISFETs. Gate dielectric materials may be selected to modulate dielectric breakdown strength and/or threshold voltage between transistors. Threshold voltage may be modulated between two MISFET structures that may be substantially the same but for the gate dielectric. Control of the gate dielectric material may render some MISFETs to be operable in depletion mode while other MISFETs are operable in enhancement mode. Gate dielectric materials may be varied by incorporating multiple dielectric materials in some MISFETs of an IC while other MISFETs of the IC may include only a single dielectric material. Combinations of gate dielectric material layers may be selected to provide a menu of low voltage, high voltage, enhancement and depletion mode MISFETs within an IC. | 2020-03-19 |
20200091286 | SEMICONDUCTOR DEVICES - A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope. | 2020-03-19 |
20200091287 | GERMANIUM-RICH NANOWIRE TRANSISTOR WITH RELAXED BUFFER LAYER - A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body. | 2020-03-19 |
20200091288 | INNER SPACER FORMATION AND CONTACT RESISTANCE REDUCTION IN NANOSHEET TRANSISTORS - A nanosheet field effect transistor device includes a semiconductor substrate including a stack of semiconductor nanosheets and a gate structure. The gate structure has an electrically conductive gate contact on the nanosheets and defines a channel region interposed between opposing source or drain (S/D) regions. The nanosheet field effect transistor further includes an electrically conductive cladding layer that encapsulates an outer surface of the S/D regions, and inner spacers on the sidewalls of the gate structure. The inner spacers are interposed between the cladding layer and the gate contact. | 2020-03-19 |
20200091289 | SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FORMATION IN STACKED-CHANNEL FETS - Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material. | 2020-03-19 |
20200091290 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor body; a first electrode on the semiconductor body; control electrodes provided in the semiconductor body along the surface thereof; and first films electrically insulating the control electrodes from the semiconductor body. The semiconductor body includes first, third, sixth layers of a first conductivity type, and second, fourth, fifth layers of a second conductivity type. The second to sixth layers are provided between the first electrode and the first layer. The second and third layers are positioned between two adjacent control electrodes. The fourth to sixth layers are positioned between other two adjacent control electrodes. The sixth layer positioned between the fourth layer and the fifth layer. The sixth layer includes a major portion and a boundary portion between the major portion and one of the first films. An impurity concentration in the boundary portion is lower than that in the major portion. | 2020-03-19 |
20200091291 | SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS - Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M | 2020-03-19 |
20200091292 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane opposite to the first plane; a gate electrode; a gate insulating layer provided between the first plane and the gate electrode; and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, containing boron, carbon, and germanium, having a bond structure of boron and carbon, having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and having a distance between the first p-type impurity regions being a first distance. | 2020-03-19 |
20200091293 | SEMICONDUCTOR DEVICE - Among multiple drain regions, a contact surface area between second contacts and a drain region most proximal to a central portion of an element region in a second direction is less than a contact surface area between second contacts and a drain region disposed on an outermost side of the element region in the second direction. The multiple drain regions are arranged in the second direction. | 2020-03-19 |
20200091294 | SILICON-ON-INSULATOR BACKSIDE CONTACTS - In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer. | 2020-03-19 |
20200091295 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode. | 2020-03-19 |
20200091296 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; a first silicon carbide region; second and third silicon carbide regions between the first silicon carbide region and the first plane; a fourth silicon carbide region between the second silicon carbide region and the first plane; a first and second gate electrodes; a suicide layer on the fourth silicon carbide region; a first electrode on the first plane having a first portion and a second portion, the first portion being in contact with the first silicon carbide region, the second portion being in contact with the suicide layer; a second electrode on the second plane; and an insulating layer between the first portion and the second portion having a first side surface and a second side surface, an angle of the first side surface being smaller than that of the second side surface. | 2020-03-19 |
20200091297 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer provided between the silicon carbide layer and the gate electrode; and a region located between the silicon carbide layer and the gate insulating layer, the region having a first bonding structure, the first bonding structure including a threefold coordinated first nitrogen atom bonded to three first silicon atoms, a threefold coordinated second nitrogen atom bonded to three second silicon atoms, and a threefold coordinated third nitrogen atom bonded to three third silicon atoms, the first to third nitrogen atoms being adjacent to each other in the first bonding structure. | 2020-03-19 |
20200091298 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane; a first silicon carbide region of a first conductivity type in the silicon carbide layer; a second silicon carbide region of a second conductivity type between the first silicon carbide region and the first plane; a third silicon carbide region of the second conductivity type between the first silicon carbide region and the first plane, the third silicon carbide region extending in a first direction parallel to the first plane; a first electrode provided on a side of the first plane; a second electrode provided on a side of the second plane; and a metal silicide layer provided between the first electrode and the second silicon carbide region, the metal silicide layer having a portion being in contact with the first plane, and a shape of the portion being an octagon. | 2020-03-19 |
20200091299 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - At an upper surface of a gate electrode, a recess occurs due to etching back of poly-silicon for forming the gate electrode. At an upper surface of an interlayer insulating film, a recess occurs in a portion that opposes in a depth direction, the recess of the upper surface of the gate electrode. A barrier metal includes sequentially stacked first to fourth metal films. The first metal film is a titanium nitride film that covers the surface of the interlayer insulating film and has an opening that exposes the recess of the upper surface of the interlayer insulating film. The second metal film is a titanium film that covers the first metal film and the source electrode, and is in contact with the interlayer insulating film, in the opening of the first metal film. The third and fourth metal films are a titanium nitride film and a titanium film, respectively. | 2020-03-19 |
20200091300 | Transistor Device - A transistor device includes, in a semiconductor body, a drift region, a body region, and a source region separated from the drift region by the body region and connected to a source node. The transistor device further includes a gate electrode dielectrically insulated from the body region by a gate dielectric, and a field electrode structure. The field electrode structure includes: a first field electrode connected to the source node and dielectrically insulated from the drift region by a first field electrode dielectric; a second field electrode dielectrically insulated from the drift region by a second field electrode dielectric; and a coupling circuit connected between the second field electrode and the source node and configured to connect the second field electrode to the source node dependent on a voltage between the source node and the second field electrode. | 2020-03-19 |
20200091301 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, comprising: a semiconductor substrate; a source, a gate and a drain fabricated on one side of the semiconductor substrate; a via hole region reserved in the region of the source; and an etching stopping layer made in the via hole region as well as a via hole under the etching stopping layer penetrating through the semiconductor substrate. | 2020-03-19 |
20200091302 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, an active region and an inactive region surrounding the active region, a gate electrode, a drain electrode and a source electrode on the active region, a drain interconnection including a drain finger and a drain bar, and a source interconnection including a source finger and a source bar. The source bar is located on an opposite side of the drain bar across the active region in a first direction. The source electrode includes a first side facing the drain bar in the first direction and a first depression in a middle of the first side. A first depth of the first depression in the first direction is equal or more than a first interval between the drain bar and the first side in the first direction. | 2020-03-19 |
20200091303 | SEMICONDUCTOR DEVICE HAVING GATE INSULATING LAYER - A semiconductor device includes gate trench, an upper gate insulating layer on an inner surface of an upper region of the gate trench, a lower gate insulating layer on an inner surface and a lower surface of a lower region of the gate trench and connected to the upper gate insulating layer, a first gate barrier layer on an inner side of the lower gate insulating layer, a gate electrode on an inner side of the first gate barrier layer and configured to fill the lower region of the gate trench, and a gate buried portion on the gate electrode. A diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer. | 2020-03-19 |
20200091304 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor portion of a first conductivity type, an insulating portion provided in an upper layer portion of the semiconductor portion, a source region, a drain region and a gate electrode. The insulating portion surrounds an active area. The source region and the drain region are provided inside the active area and separated from each other along a first direction parallel to an upper surface of the semiconductor portion. The source region and the drain region are of a second conductivity type. The gate electrode is provided above the semiconductor portion. The gate electrode is disposed in a region directly above a region between the source region and the drain region, and disposed in a region directly above an end portion in a second direction of the active area. The second direction is orthogonal to the first direction. | 2020-03-19 |
20200091305 | INTEGRATED CIRCUIT DEVICE INCLUDING GATE SPACER STRUCTURE - An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer. | 2020-03-19 |
20200091306 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp | 2020-03-19 |
20200091307 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a slit-side end portion of an insulating layer includes a main body of the insulating layer, a first thin layer thinner than the main body and extending from an end portion closer to an upper surface of the main body, the end portion facing the slit, toward the slit, and a second thin layer thinner than the main body and extending from an end portion closer to a lower surface of the main body, the end portion facing the slit, toward the slit, and the insulating layer includes an air gap layer surrounded by the main body, the first thin layer, and the second thin layer in the slit-side end portion. | 2020-03-19 |
20200091308 | IMPROPER FERROELECTRIC ACTIVE AND PASSIVE DEVICES - A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure. | 2020-03-19 |
20200091309 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING AIR-GAP SPACERS - Methods of fabricating semiconductor devices are provided. The method includes forming a gate structure over a substrate, forming a disposable spacer on a sidewall of the gate structure, and forming a source region and a drain region at opposite sides of the gate structure. The method also includes depositing an interlayer dielectric layer around the disposable spacer, and forming a first hard mask on the interlayer dielectric layer. The method further includes removing an upper portion of the gate structure, and removing the disposable spacer to form a trench between the gate structure and the interlayer dielectric layer. In addition, the method includes sealing the trench to form an air-gap spacer, and forming a second hard mask on the gate structure. | 2020-03-19 |
20200091310 | A METHOD AND RELATED APPARATUS FOR REDUCING GATE-INDUCED DRAIN LEAKAGE IN SEMICONDUCTOR DEVICES - In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure. | 2020-03-19 |
20200091311 | FinFET with Dummy Fins and Methods of Making the Same - A semiconductor structure includes semiconductor fins protruding out of a substrate, dielectric fins protruding out of the substrate and disposed among the semiconductor fins, and gate stacks disposed over the semiconductor fins and the dielectric fins. The dielectric fins include a first dielectric material layer, a second dielectric material layer disposed over the first dielectric material layer, and a third dielectric material layer disposed over the second dielectric material layer, where the first and second dielectric material layers have different compositions and the first and the third dielectric material layers have the same compositions. | 2020-03-19 |
20200091312 | Epitaxial Features Confined by Dielectric Fins and Spacers - A method includes receiving a substrate; forming on the substrate a semiconductor fin; an isolation structure surrounding the semiconductor fin; and first and second dielectric fins above the isolation structure and sandwiching the semiconductor fin; depositing a spacer feature filling spaces between the semiconductor fin and the first and second dielectric fins; performing an etching process to recess the semiconductor fin, resulting in a trench between portions of the spacer feature; and epitaxially growing a semiconductor material in the trench. | 2020-03-19 |
20200091313 | HEMT TRANSISTOR OF THE NORMALLY OFF TYPE INCLUDING A TRENCH CONTAINING A GATE REGION AND FORMING AT LEAST ONE STEP, AND CORRESPONDING MANUFACTURING METHOD - A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer. | 2020-03-19 |
20200091314 | REPLACEMENT METAL GATE STRUCTURES - Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material. | 2020-03-19 |
20200091315 | Semiconductor Device and Methods of Manufacture - A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material. | 2020-03-19 |
20200091316 | VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED GATE-TO-BOTTOM SOURCE/DRAIN PARASITIC CAPACITANCE - A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess. | 2020-03-19 |
20200091317 | VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH REDUCED TOP SOURCE/DRAIN VARIABILITY AND LOWER RESISTANCE - A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins. | 2020-03-19 |
20200091318 | Fabrication Of Vertical Field Effect Transistor Structure With Strained Channels - A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall. | 2020-03-19 |
20200091319 | OXIDE ISOLATED FIN-TYPE FIELD-EFFECT TRANSISTORS - According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins. | 2020-03-19 |
20200091320 | Fin and Gate Dimensions for Optimizing Gate Formation - Integrated circuit devices having optimized fin and gate dimensions are disclosed herein. An exemplary integrated circuit device includes a first multi-fin structure and a fourth multi-fin structure. A first gate structure traverses the first multi-fin structure, such that the first gate structure is disposed over a first channel region. A fourth gate structure traverses the fourth multi-fin structure, such that the fourth gate structure is disposed over a fourth channel region. The first gate structure includes a first gate dielectric having a first thickness, and the fourth gate structure includes a fourth gate dielectric having a fourth thickness. The first thickness is greater than the fourth thickness. The first multi-fin structure has a first pitch in the first channel region, and the fourth multi-fin structure has a fourth pitch in the fourth channel region. The first pitch is greater than the fourth pitch. | 2020-03-19 |
20200091321 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a channel region in a semiconductor substrate. The channel region is made of a first material. The method also includes forming source and drain regions in the semiconductor substrate. The method further includes forming a recess between the channel region and the drain region. The method further includes forming a tunnel barrier layer in the recess. The tunnel barrier layer is made of a second material, and a bandgap of the second material is greater than a bandgap of the first material. The method further includes forming a gate stack on the channel region. | 2020-03-19 |
20200091322 | SINGLE COLUMN COMPOUND SEMICONDUCTOR BIPOLAR JUNCTION TRANSISTOR WITH ALL-AROUND BASE - A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact. | 2020-03-19 |
20200091323 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer having a first plane and a second plane; an emitter electrode on a side of the first plane; at least one collector electrode on a side of the second plane; a first gate electrode on the side of the first plane; at least one second gate electrode on the side of the second plane; a drift region of a first conductivity-type in the semiconductor layer; a collector region of a second conductivity-type in the semiconductor layer; and a first conductivity-type region of the first conductivity-type provided between a part of the collector region and the second plane, wherein the semiconductor device has a first effective gate distance and a second effective gate distance different from the first effective gate distance. | 2020-03-19 |
20200091324 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a second electrode disposed at a position opposing the first electrode, and a semiconductor body provided between the first electrode and the second electrode. The semiconductor body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a third semiconductor layer of the second conductivity type; the second semiconductor layer is provided between the first semiconductor layer and the first electrode; and the third semiconductor layer is selectively provided inside the first semiconductor layer and disposed at a position separated from the second semiconductor layer. The first electrode is electrically connected to the second semiconductor layer and includes an extension portion; and the extension portion pierces the second semiconductor layer, extends in a first direction toward the second electrode, and is connected to the third semiconductor layer. | 2020-03-19 |
20200091325 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor body including first to fourth semiconductor layers. The second semiconductor layer of second conductivity type is provided on the first semiconductor layer of first conductivity type; the third semiconductor layer of first conductivity type is provided selectively on the second semiconductor layer; and the fourth semiconductor layer of second conductivity type is provided selectively on the second semiconductor layer. The semiconductor device further includes first and second control electrodes. The first and second control electrodes are provided inside the semiconductor body and oppose the second semiconductor layer with first and second insulating films interposed, respectively, and are arranged alternately with a third insulating layer interposed. The first control electrode contacts the third insulating layer at a first surface thereof, and the second control electrode contacts the third insulating layer at a second surface opposite to the first surface. | 2020-03-19 |
20200091326 | SEMICONDUCTOR CIRCUIT AND CONTROL CIRCUIT - A semiconductor circuit of an embodiment includes semiconductor device and a control circuit. The semiconductor device includes a semiconductor layer that has a first region of a first-conductivity type, a second region of a second-conductivity type, a third region of the first-conductivity type, fourth region of the second-conductivity type, first and second trench, first and second gate electrode, a first gate insulating film in contact with the fourth region, and a second gate insulating film spaced away from the fourth region. The semiconductor device includes a first gate electrode pad connected to the first gate electrode, and a second gate electrode pad connected to the second gate electrode. Prior to changing a first gate voltage from a turn-ON voltage to a turn-OFF voltage, a second gate voltage changed from a first voltage to a second voltage. The second voltage is a negative voltage when the first-conductivity type is p-type. | 2020-03-19 |
20200091327 | INSULATED GATE BIPOLAR TRANSISTOR - An insulated gate bipolar transistor may include a gate electrode provided in a rectangular trench. An emitter region is in direct contact with a straight trench constituting one side of the rectangular trench. A surface layer body region is in direct contact with the straight trench in a range adjacent to the emitter region. A body contact region is in direct contact with the emitter region from an opposite side to the straight trench. The body contact region includes a first part and a second part protruding toward the emitter region than the first part. A width of the emitter region between the second part and the straight trench is narrower than a width of the emitter region between the first part and the straight trench. | 2020-03-19 |
20200091328 | A SEMICONDUCTOR DEVICE WITH A LOCOS TRENCH - A gate controlled semiconductor device comprising a collector region of a first conductivity type; a drift region of a second conductivity type located over the collector region; a body region of a first conductivity type located over the drift region; at least one first contact region of a second conductivity type located above the body region and having a higher doping concentration compared to the body region. The device further comprises at least one second contact region of a first conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the body region. The device further comprises at least one active trench extending from a surface into the drift region, in which the at least one first contact region adjoins the at least one active trench so that, in use, a channel region is formed along said at least one active trench and within the body region. The at least one active trench comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer along at least one vertical side wall comprises different thicknesses; at least one auxiliary trench extending from the surface into the drift region. The at least one auxiliary trench comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer along at least one vertical side wall comprises a constant thickness. | 2020-03-19 |
20200091329 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region. | 2020-03-19 |
20200091330 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device comprises a first nitride semiconductor layer on a substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer. Source and drain electrodes are on the second nitride semiconductor layer. A gate electrode is between the source electrode and the drain electrode. A third nitride semiconductor layer of p-type conductivity is on the second nitride semiconductor layer between the drain electrode and the gate electrode and spaced from the drain electrode. | 2020-03-19 |
20200091331 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second nitride semiconductor layers, a first electrode electrically connected to the first nitride semiconductor layer, a second electrode electrically connected to the first nitride semiconductor layer, a gate electrode between the first and second electrodes, a first field plate electrode electrically connected to the first electrode, a second field plate electrode between the gate electrode and the second electrode and electrically connected to the first electrode, a first conductive layer on the gate electrode, and a second conductive layer on the first conductive layer. A distance between the gate electrode and the second field plate electrode in a lateral direction is shorter than a distance between the first conductive layer and the second field plate electrode in the lateral direction, and is equal to or shorter than a distance between the second conductive layer and the second field plate electrode. | 2020-03-19 |
20200091332 | SEMICONDUCTOR DEVICE - In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region. | 2020-03-19 |
20200091333 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a conductive portion, a gate electrode, and a second electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided selectively on the second semiconductor region. The conductive portion is provided inside the first semiconductor region. The gate electrode is separated from the conductive portion in a first direction. The gate electrode includes a first portion and a second portion. The first portion is provided on the conductive portion. A lower surface of the first portion is positioned higher than a lower end of an interface between the second semiconductor region and the third semiconductor region. The second portion opposes the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction. | 2020-03-19 |
20200091334 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; first and second trenches extending in a first direction; first and second gate electrodes; a first silicon carbide region of a first conductivity type; a plurality of second silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane, located between the first trench and the second trench, and separated from each other in the first direction; a fourth silicon carbide region of the second conductivity type between two of the second silicon carbide regions and contacting the second silicon carbide region; a fifth silicon carbide region of the second conductivity type between the two second silicon carbide regions and contacting the second silicon carbide region; a first electrode contacting the first silicon carbide region; and a second electrode. | 2020-03-19 |
20200091335 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions. | 2020-03-19 |
20200091336 | FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES - A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion. | 2020-03-19 |
20200091337 | MULTIPLE GATED POWER MOSFET DEVICE - The present disclosure provides a power MOSFET device including a multiple gated transistor disposed over a substrate. The multiple gated transistor includes a first transistor cell having a first drain pillar, a first source pillar, and a first gate conductor disposed between the first drain pillar and the first source pillar. The multiple gated transistor further includes a second transistor cell having a second drain pillar, a second source pillar, and a second gate conductor disposed between the second drain pillar and the second source pillar. The multiple gated transistor further includes a first insulator disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically insulates the second gate conductor from the first gate conductor. During operation, the first transistor cell and the second transistor cell share a common source and a common drain, and conductive states of the first gate conductor and the second gate conductor are controlled separately. | 2020-03-19 |
20200091338 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of the first conductive type, being provided on the first semiconductor layer and including a first trench, a plurality of holes, a plurality of second trenches, and a plurality of third trenches; a first semiconductor region of a second conductive type, being provided on the second semiconductor layer; a second semiconductor region of the first conductive type, being provided on the first semiconductor region; a first electrode electrically connected to the second semiconductor region; a second electrode disposed in the first trench via a first insulation film; a plurality of first field plate electrodes having a column shape, being electrically connected to the first electrode, interposing the second electrode, and being disposed in the holes via a second insulation film; a plurality of third electrodes extending from ends of the first insulation films in a first direction to the first direction, being disposed in the second trenches via third insulation films and extending from ends of the second electrodes in the 1st direction to the first direction; a plurality of second field plate electrodes extending in the first direction, being apart from the first field plate electrodes, being disposed in the third trenches via fourth insulation films, being electrically connected to the first field plate electrode via the first electrode, and interposing the third electrode; and a fourth electrode electrically connecting the second electrode and the third electrode. | 2020-03-19 |
20200091339 | SEMICONDUCTOR DEVICE - In an inactive region of an active region, a gate pad, a gate poly-silicon layer, and a gate finger are provided at a front surface of a semiconductor substrate, via an insulating film. The gate poly-silicon layer is provided beneath the gate pad, sandwiching the insulating film therebetween. The gate pad, the gate poly-silicon layer, a gate finger, gate electrodes of a trench gate structure, a gate finger, and a second measurement pad are electrically connected in the order stated. As a result, the gate electrodes where parasitic resistance occurs and the gate poly-silicon layer where built-in resistance occurs are connected in series between the second measurement pad and the gate pad. A resistance value of the overall gate resistance that is a combined resistance of the built-in resistance and the parasitic resistance may be measured by the second measurement pad. | 2020-03-19 |
20200091340 | Laterally Diffused MOSFET with Low Rsp*Qg Product - An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm | 2020-03-19 |
20200091341 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer of a first conductivity type, a first element including a second semiconductor layer of a second conductivity type, a second element including a third semiconductor layer of the second conductivity type, a first conductive member disposed in the first semiconductor layer between the first element and the second element, and a first semiconductor region of the second conductivity type provided inside the first semiconductor layer and contacting the first conductive member. A portion of the first element and a portion of the second element are formed in an upper layer portion of the first semiconductor layer. An upper end of the first conductive member is positioned higher than an upper end of the second semiconductor layer. A lower end of the first conductive member is positioned lower than lower ends of the second and third semiconductor layers. | 2020-03-19 |
20200091342 | BOOSTED VERTICAL FIELD-EFFECT TRANSISTOR - Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins. | 2020-03-19 |
20200091343 | Dopant Concentration Boost in Epitaxially Formed Material - A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer. | 2020-03-19 |
20200091344 | ASYMMETRIC THRESHOLD VOLTAGE FINFET DEVICE BY PARTIAL CHANNEL DOPING VARIATION - A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region. | 2020-03-19 |
20200091345 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME - A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap in such a way that the mask layer and the fin structure are separated by an air gap in the gap. | 2020-03-19 |
20200091346 | COMPOSITE AND TRANSISTOR - A novel material is provided. A composite oxide semiconductor in which a first region and a plurality of second regions are mixed is provided. Note that the first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc, and the plurality of second regions contain indium and zinc. Since the plurality of second regions have a higher concentration of indium than the first region, the plurality of second regions have a higher conductivity than the first region. An end portion of one of the plurality of second regions overlaps with an end portion of another one of the plurality of second regions. The plurality of second regions are three-dimensionally surrounded with the first region. | 2020-03-19 |
20200091347 | NANOWIRE TRANSISTOR WITH SOURCE AND DRAIN INDUCED BY ELECTRICAL CONTACTS WITH NEGATIVE SCHOTTKY BARRIER HEIGHT - A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region. | 2020-03-19 |
20200091348 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN CONTACT STRUCTURES - Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure. | 2020-03-19 |
20200091349 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction. | 2020-03-19 |
20200091350 | TFT SUBSTRATE AND LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor (TFT) substrate comprises a TFT located on a substrate and including a gate electrode, a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer, the gate electrode and the second semiconductor layer vertically stacked, and the first and second semiconductor layers are made of polycrystalline silicon, and wherein the first and second semiconductor layers are electrically connected to each other in series and respectively include first and second channel portions, and at least one of the first and second channel portions has a bent structure in a plan view. | 2020-03-19 |
20200091351 | SOLAR CELL AND SOLAR CELL PANEL INCLUDING THE SAME - A solar cell panel includes a plurality of solar cells including first and second solar cells, and a plurality of wiring members electrically connecting the first and second solar cells. A first electrode of each of the first and second solar cells includes a first bus bar including a plurality of first pad portions. The plurality of first pad portions include a first end pad positioned on one end side of the first bus bar and on which an end of the wiring member is positioned, and a first extension pad positioned on the other end side of the first bus bar and on an extension of the wiring member. An area of the first end pad is different from an area of the first extension pad. | 2020-03-19 |
20200091352 | MULTI-DIMENSIONAL INTEGRATED CIRCUITS AND MEMORY STRUCTURE FOR INTEGRATED CIRCUITS AND ASSOCIATED SYSTEMS AND METHODS - Monolithic multi-dimensional integrated circuits and memory architecture are provided. Exemplary integrated circuits comprise an electronic board having a first side and a second side, a multi-dimensional electronic package having multiple planes, and one or more semiconductor wafers mounted on the first side and the second side of the electronic board and on the multiple planes of the electronic package. Exemplary monolithic multi-dimensional memory architecture comprises one or more tiers, one or more monolithic inter-tier vias spanning the one or more tiers, at least one multiplexer disposed in one of the tiers, and control logic determining whether memory cells are active and which memory cells are active and controlling usage of the memory cells based on such determination. Each tier has a memory cell, and the inter-tier vias act as crossbars in multiple directions. The multiplexer is communicatively coupled to the memory cell in the respective tier. In exemplary embodiments, the one or more semiconductor wafers include one or more solar cells. The solar cells may comprise MEMS and/or on-chip solar cells. | 2020-03-19 |
20200091353 | SOLAR CELL WITH REDUCED SURFACE RECOMBINATION - A solar cell is provided. The solar cell includes a p-n junction and a coating. The p-n junction includes upper and lower layers. The coating overlies the upper layer of the p-n junction. The coating includes a transparent conductive layer and a gate dielectric layer, which is interposed between the transparent conductive layer and the upper layer of the p-n junction. The solar cell further includes a front-contact and a back-contact, which are electrically communicative with each other. The front-contact is electrically communicative with the upper layer of the p-n junction through the coating. The back-contact is electrically communicative with the lower layer of the p-n junction. The solar cell can also include a contact via electrically communicative with the back-contact and with the transparent conductive layer. | 2020-03-19 |
20200091354 | LIGHT SCATTERING STRUCTURES FOR THIN-FILM SOLAR CELLS AND METHODS OF MAKING THE SAME - The present disclosure relates to a method that includes contacting a surface of a first layer that includes a Group III element and a Group V element with a gas that includes HCl, where the first layer is positioned in thermal contact with a wafer positioned in a chamber of a reactor, and the contacting results in a roughening of the surface. | 2020-03-19 |
20200091355 | METHOD AND SYSTEM FOR MULTILAYER TRANSPARENT ELECTRODE FOR TRANSPARENT PHOTOVOLTAIC DEVICES - A transparent photovoltaic device includes a transparent substrate and a transparent bottom electrode coupled to the transparent substrate. The transparent photovoltaic device also includes an active layer coupled to the transparent bottom electrode and a transparent multilayer top electrode that includes a seed layer coupled to the active layer and a metal layer coupled to the seed layer. The transparent photovoltaic device is characterized by an average visible transmission (AVT) greater than 25% and a top electrode sheet resistance that is less than 100 Ohm/sq. | 2020-03-19 |
20200091356 | LASER BEAM SHAPING FOR FOIL-BASED METALLIZATION OF SOLAR CELLS - Approaches for foil-based metallization of solar cells and the resulting solar cells are described. For example, a method of fabricating a solar cell involves locating a metal foil above a plurality of alternating N-type and P-type semiconductor regions disposed in or above a substrate. The method also involves laser welding the metal foil to the alternating N-type and P-type semiconductor regions. The method also involves patterning the metal foil by laser ablating through at least a portion of the metal foil at regions in alignment with locations between the alternating N-type and P-type semiconductor regions. The laser welding and the patterning are performed at the same time. | 2020-03-19 |
20200091357 | SOLAR CELL, MULTI-JUNCTION SOLAR CELL, SOLAR CELL MODULE, AND SOLAR POWER GENERATION SYSTEM - According to one embodiment, a solar cell includes a first electrode, a second electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode. When a transmittance of the solar cell is measured in a wavelength range of 700 to 1000 nm, an average of the transmittance of the solar cell is 60% or more. | 2020-03-19 |
20200091358 | TOUCH SENSOR, METHOD OF MANUFACTURING THE SAME AND IMAGE DISPLAY DEVICE INCLUDING THE SAME - A touch sensor includes a substrate, and an electrode formed from a conductive stack structure including a first conductive oxide layer, a copper-containing metal layer and a second conductive oxide layer sequentially stacked from the substrate. The first conductive oxide layer and the second conductive oxide layer each include a copper-metal oxide. Chemical and mechanical stability of an electrode may be improved by the first and second conductive oxide layers. | 2020-03-19 |
20200091359 | LIGHT ABSORPTION LAYER, METHOD OF MANUFACTURING SAME, DISPERSION LIQUID, PHOTOELECTRIC CONVERSION ELEMENT, AND INTERMEDIATE BAND-TYPE SOLAR CELL - The present invention relates to a light absorption layer for forming a photoelectric conversion element and an intermediate-band solar cell excellent in quantum efficiency of two-step light absorption, a photoelectric conversion element having the light absorption layer, and an intermediate-band solar cell. The present invention also relates to a method for manufacturing a light absorption layer having an intermediate-band, using a “wet process”, which method can be expected to greatly reduce costs and expand to use for flexible substrates. The light absorption layer of the present invention has an intermediate-band, wherein quantum dots are dispersed in a matrix of a bulk semiconductor having a band gap energy of 2.0 eV or more and 3.0 eV or less. | 2020-03-19 |
20200091360 | PHOTO DETECTION ELEMENT, PHOTO DETECTOR, PHOTO DETECTION SYSTEM, LIDAR DEVICE AND VEHICLE - In one embodiment, a photo detection element includes a first region of a first conductivity type, a second region of a second conductivity type, a third region of the first conductivity type provided between the second region and the first region, and a plurality of structure bodies of the first conductivity type which are provided between the first region and the third region separately in a second direction crossing with a first direction from the third region toward the second region. | 2020-03-19 |
20200091361 | MULTI-JUNCTION SOLAR CELL - According to one embodiment, a multi-junction solar cell includes a first solar cell, a second solar cell, and an insulating layer. The first solar cell includes a first photoelectric conversion element. The second solar cell is connected in parallel with the first solar cell. The second solar cell includes multiple second photoelectric conversion elements connected in series. The insulating layer is provided between the first solar cell and the second solar cell. The second photoelectric conversion element includes a p-electrode and an n-electrode. The p-electrode is connected to a p | 2020-03-19 |
20200091362 | SOLAR CELL MODULE AND METHOD FOR PRODUCING SAME - A solar cell module having low resistance loss between a collector electrode and a connection wiring line, and a method for producing the solar cell module. A solar cell includes a finger electrode portion extending in a predetermined direction, the finger electrode portion being a region in which a collector electrode is disposed, in plan view of a photoelectric conversion section. The finger electrode portion has a stacked structure in which a first conductive layer and a second conductive layer having a lower resistance than the first conductive layer are stacked on the photoelectric conversion section. A wiring member is arranged on the collector electrode in a manner to intersect the finger electrode portion. An intersecting region between the finger electrode portion of the solar cell and the wiring member has a lamination structure in which the first conductive layer and the wiring member are stacked. | 2020-03-19 |
20200091363 | NOVEL LIGHTING SYSTEM USING A SOLAR COLLECTOR PANEL - A novel lighting system includes a solar collector panel comprising a plurality of reflector elements configured to track and be oriented optimally to receive electromagnetic radiation from the sun and reflect the received electromagnetic radiation toward a skylight in a roof of a building, a dichroic mirror disposed in the skylight and oriented and configured to receive the reflected electromagnetic radiation from the solar collector panel, the dichroic mirror being configured to reflect electromagnetic radiation of a first specific range of wavelengths downward into the building and pass through electromagnetic radiation of a second specific range of wavelengths, and a photovoltaic panel oriented and configured to receive electromagnetic radiation of the second specific range of wavelengths that passed through the dichroic mirror and convert it to electricity. | 2020-03-19 |
20200091364 | METAMORPHIC LAYERS IN MULTIJUNCTION SOLAR CELLS - A method of forming a multijunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell comprising providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on said substrate having a first band gap; forming a second solar subcell over said first subcell having a second band gap smaller than said first band gap; and forming a grading interlayer over said second sub cell having a third band gap larger than said second band gap forming a third solar subcell having a fourth band gap smaller than said second band gap such that said third subcell is lattice mis-matched with respect to said second subcell. | 2020-03-19 |
20200091365 | SOLAR CELL, MULTI-JUNCTION SOLAR CELL, SOLAR CELL MODULE, AND SOLAR POWER GENERATION SYSTEM - According to one embodiment, a solar cell includes a first electrode, a second electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode. In a case where a photoluminescence spectrum of the photoelectric conversion layer is measured at a temperature of 100 K or lower, a first maximum value (A) which is a maximum value of emission intensity in a wavelength range of more than 650 nm and 1000 nm or less is 100 times or less of a second maximum value (B) which is a maximum value of emission intensity in a wavelength range of 600 nm or more and 650 nm or less (A≤100B). | 2020-03-19 |
20200091366 | SOLAR CELL HAVING AN EMITTER REGION WITH WIDE BANDGAP SEMICONDUCTOR MATERIAL - Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate. | 2020-03-19 |