12th week of 2020 patent applcation highlights part 63 |
Patent application number | Title | Published |
20200091167 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device, and a method of manufacturing a semiconductor device, includes first stack structures enclosing first channel structures and spaced apart from each other. The first channel structures are spaced apart from each other at a first distance in each of the first stack structures and the first stack structures are spaced apart from each other at a second distance. | 2020-03-19 |
20200091168 | SINGLE-POLY NON-VOLATILE MEMORY CELL AND OPERATING METHOD THEREOF - A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line. | 2020-03-19 |
20200091169 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line. | 2020-03-19 |
20200091170 | VERTICAL MEMORY DEVICE AND METHOD OF FABRICATION THE SAME - A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate. | 2020-03-19 |
20200091171 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a stacked body including insulating layers and gate electrode layers alternately stacked in a direction, a semiconductor layer extending in the direction, and a gate insulating layer provided between the semiconductor layer and the gate electrode layer, and including a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer includes a first insulator, the second layer includes at least one oxide selected from aluminum oxide, yttrium oxide, lanthanum oxide, gadolinium oxide, ytterbium oxide, hafnium oxide, and zirconium oxide, the third layer includes at least one material selected from silicon, germanium, silicon germanium and silicon carbide, and the third layer is positioned between the semiconductor layer and the insulating layer. | 2020-03-19 |
20200091172 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers. | 2020-03-19 |
20200091173 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to one embodiment includes a semiconductor substrate and a stack body including first films and second films alternately stacked in a first direction perpendicular to the semiconductor substrate, and including a stepped end portion. Each of the first films has a thick film portion located on the end portion, and an eave portion hanging over from a upper part of the thick film portion to the side in a second direction parallel to the semiconductor substrate. | 2020-03-19 |
20200091174 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE - An example semiconductor device includes: n conductive layers including first to n | 2020-03-19 |
20200091175 | MEMORY SYSTEM AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a memory system includes: a semiconductor memory device; and a controller. The semiconductor memory device includes: first interconnection layers; second interconnection layers; a semiconductor pillar. The semiconductor memory device executes an operation in a first mode or in a second mode. In the first mode, the device selects a third interconnection layer among the first interconnection layers independently with a fourth interconnection layer among the second interconnection layers. In the second mode, the device selects a fifth interconnection layer among the first interconnection layers and sixth interconnection layer among the second interconnection layers in a batch. The controller sends an instruction to the device to execute the operation in the first mode or the second mode. | 2020-03-19 |
20200091176 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit device includes word line structures, insulating structures, a channel hole, and charge trap patterns. The word line structures and the insulating structures are interleaved with each other and extend in a horizontal direction parallel to a main surface of a substrate, and overlap one another in a vertical direction. The channel hole passes through the word line structures and the insulating structures in the vertical direction. The charge trap patterns are located in the channel hole, and are spaced apart from one another in the vertical direction with a local insulating region therebetween. | 2020-03-19 |
20200091177 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first conductive layers stacked and second conductive layers stacked in a first direction. The second conductive layers spaced from the first conductive layers in a second direction intersecting the first direction. A first memory pillar is between the first conductive layers and the second conductive layers in the second direction. The first memory pillar extends in the first direction and has a first length in the second direction. A second memory pillar is between the first conductive layers and the second conductive layers in the second direction. The second memory pillar is adjacent to the first memory pillar. The second memory pillar extends in the first direction and has a second length greater than the first length in the second direction. | 2020-03-19 |
20200091178 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes electrode layers and insulating layers alternately provided on a substrate and stacked in a first direction perpendicular to a surface of the substrate, and semiconductor layers provided in the electrode layers and insulating layers, extending in the first direction, and adjacent to each other in a second direction parallel to the surface of the substrate. The device further includes first and second charge trapping layers provided between the semiconductor layers and electrode layers sandwiching the semiconductor layers in a third direction parallel to the surface of the substrate. The device further includes insulators provided between the semiconductor layers being adjacent to each other in the second direction, and including a first insulator having a first width, and a second insulator having a second width longer than the first width and having nitrogen concentration different from that in the first insulator. | 2020-03-19 |
20200091179 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor layer, a charge storage layer provided on a surface of the semiconductor layer via a tunnel insulating film, and an electrode layer provided on a surface of the charge storage layer via a block insulating film. The tunnel insulating film includes a plurality of first silicon oxynitride films which are provided between the semiconductor layer and the charge storage layer. The tunnel insulating film further includes a silicon oxide film provided between the first silicon oxynitride films and/or a second silicon oxynitride film which is provided between the first silicon oxynitride films and has an oxygen concentration higher than an oxygen concentration in the first silicon oxynitride film. | 2020-03-19 |
20200091180 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a first interconnect layer; a second interconnect layer adjacent to the first interconnect layer; a semiconductor layer between the first and second interconnect layers; a first charge storage layer between the first interconnect layer and the semiconductor layer; and a second charge storage layer between the second interconnect layer and the semiconductor layer. A first distance between the first and second interconnect layers is shorter than a second distance between the first and second charge storage layers. | 2020-03-19 |
20200091181 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: stacked bodies adjacent to each other in a second direction, each comprising conductive layers stacked in a first direction; semiconductor portions arranged in a third direction between the stacked bodies, and comprising semiconductor layers facing the conductive layers, and a first insulating layer; and a second insulating layer provided between the semiconductor portions. The smallest distance from a geometrical center of gravity of the second insulating layer to the stacked body on a predetermined first cross-section being represented by D | 2020-03-19 |
20200091182 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape. | 2020-03-19 |
20200091183 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members. | 2020-03-19 |
20200091184 | SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including a stacked body, a semiconductor columnar member, an insulating film, and a structure. The stacked body is disposed above a semiconductor substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. The semiconductor columnar member penetrates the stacked body in the stacking direction. The insulating film surrounds the semiconductor columnar member and penetrates the stacked body in the stacking direction. The structure is disposed in a peripheral circuit region on the semiconductor substrate. The peripheral circuit region is a region including a plurality of circuit blocks. The structure has a plate-shaped portion extending at least between the plurality of circuit blocks. | 2020-03-19 |
20200091185 | SEMICONDUCTOR DEVICE INCLUDING MULTI-STACK STRUCTURE - A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers. | 2020-03-19 |
20200091186 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure. | 2020-03-19 |
20200091187 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present disclosure relates to a semiconductor device having improved structural stability and a method of manufacturing such a semiconductor device. The semiconductor device includes a first stacked structure and a second stacked structure. The semiconductor device further includes a first support including a first upper pillar passing through the second stacked structure and including at least two first lower pillars extending from the first upper pillar and passing through the first stacked structure. | 2020-03-19 |
20200091188 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a serniconductor device includes forming holes passing through a stacked structure, surrounding channel structures, and replacing some of the materials of the stacked structure through the holes. | 2020-03-19 |
20200091189 | MEMORY DEVICE - A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate. | 2020-03-19 |
20200091190 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction. | 2020-03-19 |
20200091191 | ARRAY SUBSTRATE AND METHOD OF MAKING THE SAME - The invention provides an array substrate and a method of making the same, wherein the array substrate includes: a base substrate; a metal layer formed on the base substrate; a passivation layer formed on the base substrate and the metal layer; a planarization layer formed on the passivation layer; a contact hole formed by etching the planarization layer and the passivation layer on the metal layer, to make the metal layer at least partially exposed by the contact hole, wherein a hole wall of the contact hole at the passivation layer is coplanar with the hole wall at the planarization layer or the hole wall of the contact hole at the passivation layer and the hole wall at the planarization layer form an obtuse angle; a continuous pixel electrode layer formed on the planarization layer and the contact hole, wherein the pixel electrode layer is connected to the metal layer. | 2020-03-19 |
20200091192 | ARRAY SUBSTRATES, DISPLAY PANELS, AND DISPLAY APPARATUSES - The present disclosure discloses an array substrate, a display panel, and a display apparatus. The array substrate includes a first signal line and a second signal line as well as a first TFT and a second TFT electrically connected to the first signal line and the second signal line. The first TFT has a gate located on its first conductive layer, a source located on its second conductive layer which is connected to the first conductive layer through a first via hole, and a drain located on a fourth conductive layer of the second TFT. The second TFT has a gate located on its third conductive layer, a drain located on the second conductive layer of the first TFT, and a source located on its fourth conductive layer which is connected to the third conductive layer through a second via hole. | 2020-03-19 |
20200091193 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL - An array substrate, a manufacturing method thereof and a display panel are provided, the array substrate includes a base substrate and a first conductive layer, a first insulating layer, a second conductive layer and a third conductive layer which are sequentially stacked on the base substrate, the first insulating layer insulates the first conductive layer from the second conductive layer, the first conductive layer includes a first signal line, the second conductive layer includes a second signal line and a first connection part spaced apart from each other, the third conductive layer includes a second connection part, the first connection part is electrically connected with the first signal line through a first via hole in the first insulating layer; the second connection part is electrically connected with the first connection part and the second signal line to constitute a connection structure electrically connecting the first signal line with the second signal line. | 2020-03-19 |
20200091194 | DISPLAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE - The present disclosure provides a display substrate, a method for preparing the same, and a display device. The display substrate includes a driving thin-film transistor and a pixel electrode, in which a drain of the driving thin-film transistor is electrically connected to the pixel electrode through a conductive pattern made of a metal having a chemical activity weaker than Cu. | 2020-03-19 |
20200091195 | DISPLAY DEVICE - A display device includes: a substrate; a semiconductor layer of a transistor, on the substrate; a gate electrode of the transistor on the semiconductor layer; and a conductive layer element corresponding to the transistor. The conductive layer element is both electrically connected to a constant voltage source and contacts the substrate. | 2020-03-19 |
20200091196 | THIN-FILM TRANSISTOR SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND LIQUID CRYSTAL DISPLAY - A TFT substrate is provided with a pixel TFT and a drive-circuit TFT disposed on a substrate. The pixel TFT includes a source electrode and a drain electrode that are disposed on the surface of the semiconductor layer and separated from each other. The drive-circuit TFT includes an etch stopper layer disposed on the semiconductor layer, and a source electrode and a drain electrode that are disposed on the surfaces of the etch stopper layer and the semiconductor layer and separated from each other. | 2020-03-19 |
20200091197 | ARRAY SUBSTRATE - The present invention provides an array substrate comprising a substrate, an inorganic layer formed on the substrate, a metal wiring formed on the inorganic layer, and an organic layer on the inorganic layer and covering the metal wiring; wherein the metal wiring and/or the inorganic layer include a bending performance enhancement structure. In this invention, by means of providing the bending performance enhancement structure in the metal wiring and/or the inorganic layer, the stress in the bending region is released when the flexible display is bent, so as to prevent the bending region from fracture or damage and improve the bending performance. | 2020-03-19 |
20200091198 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure relates to the technical field of display, and discloses an array substrate, a manufacturing method thereof, and a display device. The manufacturing method of the array substrate comprises: forming a first active layer, a material of which is polysilicon; injecting ions at least into an area to be doped of the first active layer to form a doped area, which is utilized to be electrically connected to corresponding source electrode and drain electrode; forming a second active layer, a material of which is an amorphous metal oxide; and after injecting ions at least into the area to be doped of the first active layer and forming the second active layer, performing an activation process to activate the ions injected into the first active layer and to convert the material of the second active layer from an amorphous state to a microcrystalline state. | 2020-03-19 |
20200091199 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME, ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, DISPLAY DEVICE - A thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device are provided, the method of fabricating a thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the active layer; and processing the metal layer to form a source electrode, a drain electrode, and a metal oxide layer, the metal oxide layer covering the source electrode, the drain electrode, and the active layer, the source electrode and the drain electrode being spaced apart and insulated from each other by the metal oxide layer. | 2020-03-19 |
20200091200 | E-BOOK READER - An e-book reader including a display panel having a thin film transistor with stable electrical characteristics is provided. Alternatively, an e-book reader capable of holding images for a long time is provided. Alternatively, a high-resolution e-book reader is provided. Alternatively, an e-book reader with low power consumption is provided. Display on the display panel of the e-book reader is controlled by a thin film transistor whose channel formation region is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor by removal of an impurity that might be an electron donor in the oxide semiconductor and has a larger energy gap than a silicon semiconductor. | 2020-03-19 |
20200091201 | SEMICONDUCTOR DEVICE - Two dual-gate transistors, which are electrically connected in parallel and provided in a compact design, are disclosed. | 2020-03-19 |
20200091202 | DISPLAY DEVICE - A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved. | 2020-03-19 |
20200091203 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor. | 2020-03-19 |
20200091204 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A method for manufacturing the array substrate includes: forming a gate metal layer on a base by a first patterning process and forming a gate insulating layer on the gate metal layer; forming a semiconductor layer and a source/drain metal layer by a second patterning process on the resulted base, the source/drain metal layer including a data line and a metal electrode connected to the data line; forming a first electrode on the resulted base and forming a channel region by a third patterning process, the channel region causing the metal electrode to form a source electrode and a drain electrode; forming a passivation layer and an organic insulating layer by a fourth patterning process on the resulted base; the organic insulating layer at least corresponding to the data line; and forming a second electrode by a fifth patterning process on the resulted base. | 2020-03-19 |
20200091205 | LIGHT DETECTION APPARATUS, PHOTOELECTRIC CONVERSION SYSTEM, AND MOVABLE BODY - A light detection apparatus according to an embodiment includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type, a third semiconductor region having the first conductivity type, and a circuit unit configured to count the number of generation times of an avalanche current, wherein a reverse bias voltage for causing avalanche multiplication of the signal charge is applied to the second semiconductor region and the third semiconductor region, and the signal charge is accumulated in the first semiconductor region when the potential barrier is formed, wherein the control unit controls the height of the potential barrier. | 2020-03-19 |
20200091206 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT - A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film. | 2020-03-19 |
20200091207 | METHOD FOR FABRICATING IMAGE SENSOR - A method includes depositing a first reflective layer over a substrate. A first dielectric layer is deposited over the first reflective layer. A second dielectric layer is deposited over the first dielectric layer. The second dielectric layer, the first dielectric layer, and the first reflective layer are etched to form a grid isolation structure that defines a recess. The recess is filled with a color filter. | 2020-03-19 |
20200091208 | PHOTODETECTOR - A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode. | 2020-03-19 |
20200091209 | BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A backside illuminated image sensor includes pixel regions disposed in a substrate, an insulating layer disposed on a frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, and an anti-reflective layer disposed on a backside surface of the substrate. The substrate has a first opening for partially exposing a backside surface of the insulating layer, and the insulating layer has a third opening for partially exposing a backside surface of the bonding pad. The anti-reflective layer comprises a first portion disposed on an inner side surface of the first opening and a second portion disposed on a portion of the backside surface of the insulating layer exposed by the first opening and having a second opening connecting the first opening with the third opening, and a first spacer is disposed on inner side surfaces of the second opening and the third opening. | 2020-03-19 |
20200091210 | SEMICONDUCTOR IMAGE SENSOR - A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, an isolation structure surrounding the pixel sensor and disposed in the substrate, a dielectric layer disposed over the pixel sensor on the front side of the substrate, and a plurality of conductive structures disposed in the dielectric layer and arranged to align with the isolation structure. | 2020-03-19 |
20200091211 | Semiconductor Image Sensor Device Having Back Side Illuminated Image Sensors with Embedded Color Filters - Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed. | 2020-03-19 |
20200091212 | IMAGE SENSOR HAVING P-TYPE ISOLATION STRUCTURE - An image sensor includes a first active region including a first floating diffusion region, a first transistor active region, and a first isolation structure for electrically isolating the first floating diffusion region from the first transistor active region, wherein the first isolation structure comprises a first P-type doped region disposed on one corner of the first active region and a second P-type doped region disposed in a center of the first active region, the first P-typed doped region and the second P-type doped region being electrically coupled to each other. | 2020-03-19 |
20200091213 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD OF DRIVING THE SAME - Imaging sensors, imaging apparatuses, and methods of driving an image sensor are provided. An image sensor can include a semiconductor substrate with a photoelectric conversion element and a charge-conversion element. The sensor can further include a capacitance switch. A charge accumulation element is located adjacent the photoelectric conversion element. At least a portion of the charge accumulation element overlaps a charge accumulation region of the photoelectric conversion element. The charge accumulation element is selectively connected to the charge-voltage conversion element by the capacitance switch. | 2020-03-19 |
20200091214 | IMAGING DEVICE AND ELECTRONIC DEVICE - An imaging device that generates a pulse signal by utilizing photoelectric conversion operation is provided. | 2020-03-19 |
20200091215 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips. | 2020-03-19 |
20200091216 | SOLID STATE IMAGING DEVICE - According to one embodiment, the interconnect layers include a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the first interconnect layer. The insulating layer is provided between the plurality of interconnect layers. The barrier metal film is provided at a surface of the first interconnect layer but not provided at a surface of the second interconnect layer. The plugs connect the first interconnect layer and the second interconnect layer, and are provided between the first interconnect layer and the second interconnect layer. The plugs are arranged at a spacing of 200 μm or less along a longitudinal direction of the second interconnect layer. | 2020-03-19 |
20200091217 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other. The solid-state imaging device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other. The first coupling structure includes a via in which one through hole electrically couples a predetermined wiring line in the first multi-layered wiring layer, and a predetermined wiring line in the second multi-layered wiring layer or the third multi-layered wiring layer to each other. The one through hole is provided by penetrating at least the first substrate from a back surface side of the first substrate. | 2020-03-19 |
20200091218 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE - A semiconductor device comprising a first circuit component and a second circuit component, the first circuit component having a first wiring structure formed by stacking one or more wiring layers and one or more insulating layers on a first semiconductor substrate, the second circuit component having a second wiring structure formed by stacking one or more wiring layers and one or more insulating layers on a second semiconductor substrate, the first and second wiring structures being bonded to each other, their bonding planes being composed of oxygen atoms and carbon atoms and/or nitrogen atoms bonded to silicon atoms, and, numbers of their atoms satisfying a predetermined equation. | 2020-03-19 |
20200091219 | PHOTOELECTRIC CONVERSION ELEMENT AND OPTICAL SENSOR INCLUDING THE SAME - A photoelectric conversion element and an optical sensor including the same are disclosed. The photoelectric conversion element may include a plurality of lattice stacks repeatedly stacked on top of each other on a substrate and configured to have an effective band gap. The plurality of lattice stacks may each include a first active layer and a second active layer on the first active layer. The first active layer may include a first two-dimensional material having a first band gap. The second active layer may include a second two-dimensional material having a second band gap not overlapping the first band gap. An effective band gap may be adjusted based on the first two-dimensional materials and thicknesses of the first active layer and the second active layer and a number of times of plurality of lattice stacks. | 2020-03-19 |
20200091220 | ACTIVE MATRIX SUBSTRATE, X-RAY IMAGING PANEL WITH THE SAME, AND METHOD OF MANUFACTURING THE SAME - An active matrix substrate includes a photoelectric conversion element, an electrode provided on at least one main surface of the photoelectric conversion element, and a first inorganic film covering a side surface of the photoelectric conversion element. The electrode includes an extending section covering the side surface of the photoelectric conversion element through intermediation of the first inorganic film. | 2020-03-19 |
20200091221 | ACTIVE MATRIX SUBSTRATE AND IMAGING PANEL WITH SAME - An active matrix substrate includes a photoelectric conversion element | 2020-03-19 |
20200091222 | ACTIVE MATRIX SUBSTRATE AND IMAGING PANEL WITH SAME - An active matrix substrate includes a photoelectric conversion element | 2020-03-19 |
20200091223 | ABSORPTION ENHANCEMENT STRUCTURE FOR IMAGE SENSOR - The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions. | 2020-03-19 |
20200091224 | METHOD OF MANUFACTURING AN OPTOELECTRONIC DEVICE COMPRISING A PLURALITY OF DIODES - A method of manufacturing an optoelectronic device, including: a) transferring, onto a connection surface of a control circuit, an active diode stack including at least first and second semiconductor layers of opposite conductivity types, so that the second semiconductor layer in the stack faces the connection surface of the control circuit and is separated from the connection surface of the control circuit by at least one insulating layer; b) forming in the active stack trenches delimiting a plurality of diodes, the trenches extending through the insulating layer and emerging onto the connection surface of the control circuit; and c) forming in the trenches metallizations connecting the second semiconductor layer to the connection surface of the control circuit. | 2020-03-19 |
20200091225 | MICRO LED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A Micro LED display panel and manufacturing method thereof are provided. The Micro LED display panel includes TFT substrate, bottom electrode positioned on top of the TFT substrate, Micro LED chip positioned on the bottom electrode, top electrode positioned on top of the Micro LED chip, and first passivation layer covering the TFT substrate and the Micro LED chip. A plurality of the bottom electrode is provided, and positioned at interval on top of the TFT substrate; the bottom of the bottom electrode is extending and conducting with a source or a drain of the TFT substrate. This disclosure directly manufacturing Micro LED chip connecting the bottom electrode and the top electrode for greatly decreases thickness of the display panel, and also achieves narrow frame. Furthermore, beside the Micro LED chip is entire passivation layer such that it does not need to multiple manufacturing method, simplify the manufacturing steps. | 2020-03-19 |
20200091226 | DISPLAY DEVICE - A display device includes a substrate, an emissive layer; a plurality of color converting layers that share the emissive layer; and an insulating layer provided between the emissive layer and the plurality of color converting layers and having a smaller refractive index than the emissive layer. | 2020-03-19 |
20200091227 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a first memory cell which includes a first stacked structure including a magnetic layer, and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer, wherein each of the first stacked structure and the second stacked structure has a structure in which a plurality of layers including a predetermined layer are stacked, and the predetermined layer included in the first stacked structure and the predetermined layer included in the second stacked structure have different thicknesses. | 2020-03-19 |
20200091228 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect provided on the upper layer side of the first interconnect, a third interconnect provided on the upper layer side of the second interconnect, a first memory cell provided between the first interconnect and the second interconnect and including a first stacked structure including a magnetic layer, a second memory cell provided between the second interconnect and the third interconnect and including a second stacked structure including a magnetic layer, and a light reflection layer provided on the upper layer side of the first interconnect and on the lower layer side of the third interconnect and having optical reflectance higher than optical transmittance. | 2020-03-19 |
20200091229 | MAGNETORESISTIVE RANDOM ACESS MEMORY WHEREIN NUMBER OF MEMORY CELLS IN EACH STRING IS EQUAL TO NUMBER OF STRINGS CONNECTED IN PARALLEL - A magnetic random access memory (MRAM) includes device strings coupled in parallel, each comprising magnetic tunnel junctions (MTJs) coupled in serial, wherein a quantity of the MTJs of each of the device strings is equal to a quantity of the device strings, and an equivalent resistance (R | 2020-03-19 |
20200091230 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present disclosure provides a semiconductor structure having a memory region. The semiconductor structure includes an N | 2020-03-19 |
20200091231 | VERTICAL ARRAY OF RESISTIVE SWITCHING DEVICES HAVING A TUNABLE OXYGEN VACANCY CONCENTRATION - Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a conductive horizontal electrode, an opening extending through the horizontal electrode, a filament region positioned within the opening and communicatively coupled to a sidewall of the horizontal electrode, and a conductive vertical electrode positioned within the opening and communicatively coupled to the filament region. The vertical electrode includes a first conductive alloy material. Oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode. A room temperature resistivity of the first conductive alloy material is below about 5×10 | 2020-03-19 |
20200091232 | Shared Three-Dimensional Vertical Memory - In a shared three-dimensional vertical memory (3D-M | 2020-03-19 |
20200091233 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory cell including a first two-terminal resistance change memory element storing memory cell information, and a second two-terminal resistance change memory element, connected in series to the first two-terminal resistance change memory element, and functioning as a selector element, word and bit lines connected to the memory cell. When memory cell information is to be written, if the memory cell is a selected memory cell, the second two-terminal resistance change memory element is set to the low resistance state and, if the memory cell is an unselected memory cell, the second two-terminal resistance change memory element is set to the high resistance state. | 2020-03-19 |
20200091234 | SWITCHING ELEMENT, VARIABLE RESISTANCE MEMORY DEVICE, AND METHOD OF MANUFACTURING THE SWITCHING ELEMENT - A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern. | 2020-03-19 |
20200091235 | STORAGE DEVICE - A storage device includes: a first conductive layer; a second conductive layer; and a resistance-variable layer disposed between the first conductive layer and the second conductive layer, and including a first chalcogenide containing a first element which is either silicon or germanium. An insulating layer is disposed in a second direction perpendicular to a first direction from the first conductive layer to the second conductive layer with respect to the resistance-variable layer. A first region is disposed between the resistance-variable layer and the insulating layer, and has a third concentration of the first element higher than both a first concentration of the first element in the resistance-variable layer and a second concentration of the first element in the insulating layer. | 2020-03-19 |
20200091236 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate, a plurality of first wirings arranged in a first direction, a second wiring extending in the first direction, a resistance change film provided between the first wiring and the second wiring, a third wiring which extends in the second direction, a first semiconductor layer connected to the second wiring and the third wiring, a first electrode, a fourth wiring connected to the second wiring, and extends in the third direction, a fifth wiring provided between the fourth wiring and the substrate, extending in the first direction, and connected to the fourth wiring, a sixth wiring provided between the fifth wiring and the substrate, a second semiconductor layer provided between the fifth wiring and the sixth wiring and connected to the fifth wiring and the sixth wiring, and a second electrode. | 2020-03-19 |
20200091237 | STEEP-SWITCH VERTICAL FIELD EFFECT TRANSISTOR - Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade. | 2020-03-19 |
20200091238 | STORAGE DEVICE - According to one embodiment, a storage device includes a first conductor extending along a first direction, first variable-resistance elements on the first conductor, and a second conductor on the first variable-resistance elements and extending along a second direction. A plurality of second variable-resistance elements is on the second conductor. A third conductor is on the plurality of second variable-resistance elements. The third conductor extends along the first direction. A first switching element is connected between the second conductor and a corresponding one of the first variable-resistance elements. A second switching element is connected between the third conductor and a corresponding one of second variable-resistance elements. | 2020-03-19 |
20200091239 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first conductive lines in a first wiring layer, a plurality of second conductive lines in a second wiring layer, and a plurality of memory cells between the first and second conductive lines in a first direction in a first region. A plurality of third conductive lines in the first wiring layer, a plurality of fourth conductive lines in the second wiring, and a plurality of first memory lines are in a second region. The third conductive lines extends in a second direction and are spaced from each other in a third direction. The fourth conductive lines extend in the second direction and are spaced in the third direction. The first memory lines are between the third conductive lines and the fourth conductive lines in the first direction. The first memory lines comprise the same materials as the memory cells. | 2020-03-19 |
20200091240 | MEMORY DEVICE HAVING PUC STRUCTURE - A memory device includes first and second peripheral regions in which peripheral circuits related to data input/output are disposed, a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed, and a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed. | 2020-03-19 |
20200091241 | MEMORY DEVICE AND METHOD OF MANUFACTURING MEMORY DEVICE - A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers that are different in wiring pitches is stacked; and a memory element that is provided between the plurality of wiring layers. | 2020-03-19 |
20200091242 | PHASE CHANGE MEMORY WITH IMPROVED RECOVERY FROM ELEMENT SEGREGATION - A method is presented for reducing element segregation of a phase change material (PCM). The method includes forming a bottom electrode, constructing a layered stack over the bottom electrode, the layered stack including the PCM separated by one or more electrically conductive and chemically stable materials, and forming a top electrode over the layered stack. The PCM is Ge—Sb—Te (germanium-antimony-tellurium or GST) and the one or more electrically conductive and chemically stable materials are titanium nitride (TiN) segments. | 2020-03-19 |
20200091243 | STORAGE DEVICE AND MANUFACTURING METHOD FOR THE SAME - A storage device according to embodiments includes a substrate, a stacked body, a first region, a second region, and first to nth electrodes. The stacked body is provided on the substrate and having first to nth (n is an integer of 3 or more) conductive layers stacked in a direction perpendicular to a surface of the substrate. The first region includes a part of the stacked body, and has a first step structure including the first to the nth conductive layers. The second region includes a part of the stacked body, and has a second step structure different from the first step structure including at least a part of the first to nth conductive layers. The first to nth electrodes are provided in the first region and connected to the first to nth conductive layers and extend in a direction perpendicular to the surface of the substrate. | 2020-03-19 |
20200091244 | METHODS OF FORMING METAL ON INHOMOGENEOUS SURFACES AND STRUCTURES INCORPORATING METAL ON INHOMOGENEOUS SURFACES - The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material. | 2020-03-19 |
20200091245 | SEMICONDUCTOR MEMORY DEVICE HAVING A VERTICAL ACTIVE REGION - Embodiments of the invention provide a semiconductor memory device. In some embodiments, the device includes a bottom electrode extending in a y-direction relative to top surface of a substrate and a top electrode extending in an x-direction relative to the top surface of the substrate. An active area is located at the cross-section between the bottom electrode and the top electrode and is located on vertical side walls extending in a z-direction of the semiconductor memory device with respect to the top surface of the substrate. An insulating layer is located in the active area in between the top electrode and the bottom electrode. | 2020-03-19 |
20200091246 | PHOTOSENSITIVE SENSOR, MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC DEVICE - A photosensitive sensor and a method of manufacturing the photosensitive sensor are disclosed. The photosensitive sensor includes a thin film transistor and a photosensitive element on a substrate, wherein the photosensitive element includes a first electrode, a second electrode, and a photosensitive layer between the first electrode and the second electrode. The second electrode is connected to a drain electrode of the thin film transistor. An orthographic projection of an active layer of the thin film transistor on the substrate is within an orthographic projection of the second electrode on the substrate. The second electrode includes at least two stacked conductive layers, at least one of the at least two stacked conductive layers being a light shielding metal layer. | 2020-03-19 |
20200091247 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An OLED display according to an exemplary embodiment includes: a substrate that includes a display area and a non-display area; a pixel circuit that is disposed in the display area; organic light emitting diodes and barrier ribs that are disposed on the pixel circuit; an encapsulation layer that covers the pixel circuit, the organic light emitting diodes, and the barrier ribs; and a color filter that is disposed on the encapsulation layer, wherein the encapsulation layer comprises an edge area that is adjacent to the non-display area in the display area and a center area not directly adjacent to the non-display area and having the edge area disposed therebetween, the color filter comprises a first color filter, a second color filter, a third color filter, and color filter overlapped portions where the first color filter, the second color filter, and the third color filter are overlapped, and the color filter overlapped portions are disposed in areas where the barrier ribs are disposed, and a thickness of the color filter is greater in the edge area than in the center area. | 2020-03-19 |
20200091248 | ELECTRONIC DEVICE - An electronic device includes a first electronic unit and a second electronic unit. The first electronic unit emits a first light having a first spectrum. A main peak of the first spectrum corresponds to a first wavelength ranged from 461 nm to 473 nm. The second electronic unit emits a second light having a second spectrum different from the first spectrum. A sub peak of the second spectrum corresponds to a second wavelength ranged from 300 nm to 460 nm. A difference between the first wavelength and the second wavelength is greater than or equal to 5 nm. | 2020-03-19 |
20200091249 | ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL, METHOD FOR FABRICATING THE SAME, AND DISPLAY DEVICE - Disclosed are an organic light-emitting diode display panel, a method for fabricating the same, and a display device. The panel includes: a base substrate, a reflecting metal layer located on the base substrate, and a protruding layer located on the reflecting metal layer; a material of the protruding layer is an inorganic material, the protruding layer comprises a plurality of pixel openings distributed in an array, and the plurality of pixel openings constitute a plurality of sub-pixel areas in different colors, the display panel further comprising an anode layer, an organic functional layer, and a cathode layer stacked in each of the sub-pixel areas sequentially; a structure with a micro-resonant chamber effect is formed between a upper surface of the reflecting metal layer and a lower surfaces of the cathode layer in each of the sub-pixel areas; anode layers in the sub-pixel areas in the different colors have different thicknesses. | 2020-03-19 |
20200091250 | PIXEL ARRANGEMENT STRUCTURE AND DISPLAY DEVICE - A pixel arrangement structure and a display device are provided. The pixel arrangement structure includes a plurality of repeating units. The repeating units include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. Center points of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel in a same repeating unit form a quadrilateral. Four adjacent sub-pixels in adjacent repeating units constitute a shared pixel, and the shared pixel includes at most two sub-pixels belonging to the same repeating unit. | 2020-03-19 |
20200091251 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, DISPLAY DEVICE - A display substrate has a display area and a non-display area. The non-display area includes a dummy pixel area located in a periphery of the display area. The display substrate includes a substrate; a first pixel defining layer disposed on the substrate and located in the display area, the first pixel defining layer having a plurality of first openings; and a second pixel defining layer disposed on the substrate and located in the dummy pixel area, the second pixel defining layer having a plurality of second openings. A capacity of a second opening is greater than a capacity of a first opening, and an open area of a second opening is less than or equal to an open area of a first opening. | 2020-03-19 |
20200091252 | DISPLAY DEVICE - A display device includes: a base layer including a display area (DA) and a non-DA; a circuit element layer on the base layer and including: a power supply electrode (PSE) overlapping the non-DA, circuit elements, and a shielding electrode connected to the PSE and overlapping some of the circuit elements; a display element layer on the circuit element layer and including: a light emitting element including a first electrode, a light emitting unit, and a second electrode, and a connection electrode connecting the second electrode to the PSE and including first through-holes; a thin film encapsulation layer (TFEL) on the display element layer and including an organic layer overlapping the DA; and an input sensing layer on the TFEL and including sensing electrodes and sensing signal lines connected to the sensing electrodes. The sensing signal lines overlap the connection electrode. Some of the first through-holes overlap the shielding electrode. | 2020-03-19 |
20200091253 | ARRAY SUBSTRATE, DISPLAY PANEL AND OPERATING METHOD THEREOF - An array substrate, a display panel and an operating method thereof are disclosed. The array substrate includes a base substrate; an imaging array disposed on the substrate, wherein the imaging array includes a photoelectric detection circuit and a temperature detection circuit, the photoelectric detection circuit includes a photosensitive sensor configured to detect light for imaging, and the temperature detection circuit includes a temperature sensitive sensor configured to detect temperature. | 2020-03-19 |
20200091254 | Display substrate, manufacturing method thereof, and display device - Embodiments of the present application provide a display substrate comprising a plurality of first banks distributed in a first direction and a plurality of second banks distributed in a second direction. Two adjacent first banks define a group of sub-pixel units of the display substrate, and two adjacent second banks define one sub-pixel unit. The first bank has a height greater than a height of the second bank. Embodiments of the present application also disclose a manufacturing method of a display substrate and a display device. | 2020-03-19 |
20200091255 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - A display substrate, a method of manufacturing the same and a display device are provided. The display substrate includes: a base substrate including an emission area and a transmission area; an electroluminescent device on the base substrate, the electroluminescent device including a first electrode in the emission area; a thin film transistor for controlling the electroluminescent device, the thin film transistor including an active layer; and a conductive member on the base substrate. The conductive member electrically connects the first electrode of the electroluminescent device with the active layer, the conductive member includes a contact portion in contact with the active layer, and the contact portion is located in the transmission area. | 2020-03-19 |
20200091256 | DISPLAY APPARATUS - A display apparatus includes a base layer, on which a display area and a non-display area disposed to surround the display area are defined, a circuit layer disposed on the base layer and including a plurality of insulation layers, a pixel layer disposed on the display area and including a plurality of organic light-emitting diodes, an encapsulation layer disposed on the pixel layer to cover the pixel layer, and a protruding member disposed between the circuit layer and the encapsulation layer on the non-display area. A bank coupling hole is defined in the circuit layer on the non-display area, and the bank coupling hole is defined through at least an uppermost insulation layer of the insulation layers and overlaps the protruding member on a plane. | 2020-03-19 |
20200091257 | OLED DISPLAY PANEL, DISPLAY APPARATUS AND METHOD OF MANUFACTURING OLED DISPLAY PANEL - An OLED display panel, a display apparatus having the OLED display panel, and a method of manufacturing an OLED display panel are disclosed. The OLED display panel includes: a substrate; a pixel defining layer disposed on the substrate and defining a pixel region and a non-pixel region outside the pixel region; a spacer layer disposed in the non-pixel region defined by the pixel defining layer; and an organic light-emitting layer including: a first portion disposed in the pixel region defined by the pixel defining layer, and a second portion disposed in the non-pixel region defined by the pixel defining layer. A surface of at least one of the pixel defining layer or the spacer layer has a contact portion which is in contact with the organic light-emitting layer and which is rough. | 2020-03-19 |
20200091258 | DISPLAY DEVICE, DISPLAY DEVICE PRODUCTION METHOD, DISPLAY DEVICE PRODUCTION APPARATUS, AND CONTROLLER - A display device configured so that a light-emitting element layer ( | 2020-03-19 |
20200091259 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - The present disclosure provides an organic light-emitting display device having a plurality of pixels arranged along first and second directions that intersect each other. Each of the pixels includes: a transistor; at least one insulating layer on the transistor, and a pixel contact hole extends through the insulating layer and exposes part of the transistor; a first electrode on the at least one insulating layer and connected to the transistor via the pixel contact hole; and a filling layer on the first electrode and filling the pixel contact hole. A first bank has a plurality of first openings, and each of the first openings exposes at least one of the first electrodes. A second bank has a plurality of second openings, and each of the second openings exposes a plurality of the first electrodes arranged along the second direction. | 2020-03-19 |
20200091260 | DISPLAY APPARATUS HAVING A LIGHT-EMITTING DEVICE ON AN OVER-COAT LAYER, AND METHOD OF FORMING THE SAME - A display apparatus having a light-emitting device and a method of forming the same are provided. The light-emitting device may include a lower electrode, a light-emitting layer and an upper electrode, which are sequentially stacked on an over-coat layer. The over-coat layer may include a step compensation groove. An end portion of the lower electrode may be disposed in the step compensation groove. A bank insulating layer covering the end portion of the lower electrode may be disposed in the step compensation groove of the over-coat layer. An upper surface of the bank insulating layer opposite to the over-coat layer may be a flat surface. Thus, in the display apparatus and the method, peeling and/or damage of the upper electrode due to external force may be prevented. | 2020-03-19 |
20200091261 | DISPLAY DEVICE INCLUDING A PASSIVATION LAYER HAVING AN UNEVEN SURFACE - A display device includes a substrate, a transistor, a pad portion, a passivation layer, and a pixel definition layer. The substrate includes a display area and a peripheral area disposed at an edge of the display area. The transistor is disposed on the display area. The pad portion is disposed on the peripheral area. The passivation layer is disposed on the transistor. The pixel definition layer is disposed on the passivation layer. A portion of the passivation layer extends to the peripheral area. An upper surface of the portion of the passivation layer disposed on the display area is substantially flat. An upper surface of the portion of passivation layer disposed at the peripheral area has an uneven structure. The uneven structure includes a recess portion and a convex portion. The pixel definition layer covers the portion of the passivation layer disposed on the peripheral area. | 2020-03-19 |
20200091262 | DISPLAY DEVICE - A display device includes a substrate including an outer area neighboring a border; and an insulating layer positioned over the substrate and including a plurality of openings positioned over the outer area. The openings are arranged to be spaced from each other in a direction. The display device further includes a wavy line extending in the direction and passing the plurality of openings. | 2020-03-19 |
20200091263 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISLAY DEVICE - The present discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a first transistor and a second transistor. The first transistor includes a first active layer, a first gate, a first source and a first drain. The second transistor includes a second active layer, a second gate, a second source and a second drain. An orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap. One of the second source and the second drain is in the same layer as and made from the same material as the first gate. The first source and the first drain are in the same layer as and made from the same material as the other of the second source and the second drain. | 2020-03-19 |
20200091264 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device comprises a substrate, a driving thin-film transistor including an active layer on the substrate, source and drain electrodes directly contacting the active layer, and a gate electrode on the active layer, and an organic light-emitting element connected to the driving thin-film transistor. Each of the source and drain electrodes of the driving thin-film transistor exposes a respective side surface of the active layer. | 2020-03-19 |
20200091265 | ORGANIC EL DISPLAY DEVICE - An organic EL display device includes a photosensitive resin composition including an (A) alkali-soluble resin, a (B) coloring agent, a (C) radical polymerizable compound, and a (D) photopolymerization initiator. The (A) alkali-soluble resin is an (A-1) alkali-soluble resin having a carboxy group. A sum of the content of at least one of a metal element and a halogen element in a non-volatile component measured by time-of-flight secondary ion mass spectrometry in a cured product formed by curing the photosensitive resin composition is 1×10 | 2020-03-19 |
20200091266 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a substrate, active switches disposed on the substrate, a color filter layer disposed on the substrate, and a passivation layer disposed on the substrate, wherein the passivation layer covers the substrate, the active switches, and the color filter layer. | 2020-03-19 |