12th week of 2020 patent applcation highlights part 62 |
Patent application number | Title | Published |
20200091067 | LINER-FREE AND PARTIAL LINER-FREE CONTACT/VIA STRUCTURES - A liner-free or partial liner-free contact/via structure that is embedded within a dielectric capping layer and positioned between an electrically conductive structure and an overlying contact structure is provided. | 2020-03-19 |
20200091068 | Selective Formation of Conductor Nanowires - A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias. | 2020-03-19 |
20200091069 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops. | 2020-03-19 |
20200091070 | CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided. | 2020-03-19 |
20200091071 | SEMICONDUCTOR DEVICE INCLUDING GATE PATTERN HAVING PAD REGION - A semiconductor device includes a gate pattern disposed over a lower structure, and including a gate electrode region and a gate pad region extending from the gate electrode region; and a vertical channel semiconductor layer having a side surface facing the gate electrode region of the gate pattern. The gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region. The first pad region includes an upper surface, a lower surface opposing the upper surface, and an outer side surface. The outer side surface has a lower outer side surface and an upper outer side surface, divided from each other by a boundary portion. The lower outer side surface extends from the lower surface, and a connection portion of the lower outer side surface and the lower surface has a rounded shape. | 2020-03-19 |
20200091072 | Method and Apparatus for Supplying Power to VLSI Silicon Chips - An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate. | 2020-03-19 |
20200091073 | SEMICONDCUTOR DEVICES, SEMICONDCUTOR PACKAGES AND METHODS OF FORMING THE SAME - Semiconductor devices, semiconductor packages and methods of forming the same are provided. One of the semiconductor device includes a dielectric layer and a connector. The dielectric layer includes a dielectric material and an additive, wherein the additive includes a compound represented by Chemical Formula 1. The connector is disposed in the dielectric layer. | 2020-03-19 |
20200091074 | CONTROLLING WARP IN SEMICONDUCTOR LAMINATED SUBSTRATES WITH CONDUCTIVE MATERIAL LAYOUT AND ORIENTATION - This invention is a laminated structure and methods used for electrically connecting one or more semiconductor chips to various external electrical connections where stresses within the laminated structure due to thermal cycle are reduced by adding conductive material to selected subareas of upper and lower layers in the structure such that the volume of conductive material in corresponding subareas is equal in amount and orientation within a threshold. This reduces differential stresses between the layers as temperature changes and accordingly reduces failures of materials and/or connections in the structure during manufacturing and operation. | 2020-03-19 |
20200091075 | Pad Structure Design in Fan-Out Package - A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated. | 2020-03-19 |
20200091076 | EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE - Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure. | 2020-03-19 |
20200091077 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure. | 2020-03-19 |
20200091078 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a multilayer wiring layer on the semiconductor substrate, an insulation layer above the multilayer wiring layer, first and second metal wirings on the insulation layer, and a resin film that covers the insulation layer and the first second metal wirings. The resin film has a thickness about three times a thickness of the first and second metal wirings in a direction perpendicular to the semiconductor substrate, and a thickness of each of the first and second metal wirings is greater than a thickness of a wiring included in the multilayer wiring layer. | 2020-03-19 |
20200091079 | HYBRID DIELECTRIC SCHEME FOR VARYING LINER THICKNESS AND MANGANESE CONCENTRATION - A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric. | 2020-03-19 |
20200091080 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate. The semiconductor device further includes a wiring layer provided on the substrate, the wiring layer including a molybdenum layer including oxygen atoms as an impurity. | 2020-03-19 |
20200091081 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to one embodiment includes a semiconductor substrate, a stack body including metal films and first insulating films alternately stacked on the semiconductor substrate and including a stepped end portion, conducting films respectively protruding from the metal films on all steps of the end portion, contact portions respectively provided above the conducting films, a second insulating film surrounding side surfaces of the contact portions, and a barrier metal film provided between the second insulating film and the contact portions and between the conducting films and the contact portions. The entire top surfaces of the conducting films are covered by the barrier metal film and the second insulating film. | 2020-03-19 |
20200091082 | METALLIC CARBON QUANTUM WIRE FROM SELF-ASSEMBLED ALPHALTENE - The present disclosure is related to a method of fabricating a stacked nanographene structure which is assembled into quantum wires or ribbons. While it has been demonstrated that nanowires can be fabricated from various raw carbon materials including PAHs, research and industry has not produced a self-assembled nanowire produced from asphaltene materials that exhibits a metallic character and electronic structure. The following methods and materials can be used to produce new class of materials consisting of a self-assembled quantum wire out of asphaltene. | 2020-03-19 |
20200091083 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature. | 2020-03-19 |
20200091084 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer. | 2020-03-19 |
20200091085 | Fiducial-Filtering Automatic Wafer Centering Process and Associated System - Each sensor in an array of sensors detects and signals when an edge of a wafer passes by the sensor on a wafer handling component of a robot. A number (N) of detected wafer edge locations is determined. Each detected wafer edge location is a set of coordinates (x, y) in a coordinate system of the wafer handling component. For each unique set of (N−1) of the number (N) of detected wafer edge locations, an estimated wafer offset is determined that substantially minimizes a performance index value. The estimated wafer offset is a vector extending from a center of the coordinate system of the wafer handling component to an estimated center location of the wafer. A final wafer offset is identified as the estimated wafer offset that has a smallest corresponding performance index value. The final wafer offset is used to center the wafer at a target station. | 2020-03-19 |
20200091086 | Alignment Mark Design for Packages - A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. | 2020-03-19 |
20200091087 | SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY MANUFACTURING METHOD - A semiconductor memory includes a substrate having a first surface, a memory device mounted on the first surface, a controller mounted on the first surface, and a shielding layer between the first surface and at least a part of the controller, the shielding layer having a thickness that is large enough to block most of the alpha radiation from the substrate from reaching the part of the controller. | 2020-03-19 |
20200091088 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms. | 2020-03-19 |
20200091089 | SILICON WAFER MANUFACTURING METHOD - Provided is a silicon wafer manufacturing method capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer manufacturing method according to the present invention is provided with calculating a target thickness of the silicon wafer required for ensuring a warpage reduction amount of a silicon wafer warped during a device process from a relationship between an amount of warpage of a silicon wafer and a thickness thereof occurring due to application of the same film stress to a plurality of silicon wafers having mutually different thicknesses; and processing a silicon single crystal ingot to thereby manufacture silicon wafers having the target thickness. | 2020-03-19 |
20200091090 | PACKAGE STRUCTURE - A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die. | 2020-03-19 |
20200091091 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided. | 2020-03-19 |
20200091092 | SUBSTRATE TREATMENT APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND WORKPIECE SUBSTRATE - In one embodiment, a substrate treatment apparatus includes a substrate holder configured to hold a substrate provided with a film. The apparatus further includes a film treatment module configured to treat the film in accordance with warpage of the substrate such that the film includes a first region having a first film quality or a first film thickness and a second region having a second film quality or a second film thickness different from the first film quality or the first film thickness. | 2020-03-19 |
20200091093 | FLEXIBLE SHIELD FOR SEMICONDUCTOR DEVICES AND METHODS - An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield. | 2020-03-19 |
20200091094 | INTEGRATED FILTER TECHNOLOGY WITH EMBEDDED DEVICES - A filter including an insulating die having a plurality of MIM (Metal Insulator Metal) capacitors disposed within the die is disclosed. A | 2020-03-19 |
20200091095 | ANTENNA MODULE - An antenna module includes an antenna substrate including a glass substrate having first and second surfaces opposing each other, an antenna pattern disposed on the first surface, and a wiring structure connected to the antenna pattern and extending to the second surface, and a semiconductor package including a semiconductor chip, having an inactive surface and an active surface, on which a connection pad is disposed, an encapsulant encapsulating the semiconductor chip, a connection member including a redistribution layer connected to the connection pad, and a through-via penetrating the encapsulant and connecting the redistribution layer and the wiring structure to each other. | 2020-03-19 |
20200091096 | PAD STRUCTURE AND MANUFACTURING METHOD THEREOF IN SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a conductive pad region electrically coupled to the substrate, a first dielectric layer over the conductive pad region, and a passivation layer over the first dielectric layer, wherein the passivation layer includes a laterally-extending portion covering the first dielectric layer and a vertically-extending portion on a sidewall of the first dielectric layer. The laterally-extending portion and the vertically-extending portion of the passivation layer are joined along a vertically-extending boundary. | 2020-03-19 |
20200091097 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped. | 2020-03-19 |
20200091098 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes forming an organic insulating layer on a semiconductor on which metal wiring is provided, the organic insulating layer having an opening to expose part of the metal wiring, forming a seed metal covering the part of the metal wiring exposed from the opening, and an inside face and an around portion of the opening of the organic insulating layer, forming a mask covering an edge of the seed metal and exposing part of the seed metal formed in the opening, and forming a barrier metal on the seed metal exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material. | 2020-03-19 |
20200091099 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion. | 2020-03-19 |
20200091100 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness. | 2020-03-19 |
20200091101 | PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES - Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes. | 2020-03-19 |
20200091102 | ELECTRONIC APPARATUS - An electronic apparatus includes first and second packages. The first package includes a first semiconductor chip between opposing first and second surfaces of the first package, a plurality of terminals on the first semiconductor chip facing a first direction that is perpendicular to the first and second surface, the terminals including first input/output terminals and a second input/output terminal, and a plurality of bumps that are electrically connected to the plurality of first input/output terminals at positions that are directly below the first semiconductor chip in the first direction. The second package includes a second semiconductor chip provided on the second surface of the first package, a wire that electrically connects the second semiconductor chip to a conductor that is electrically connected to the second input/output terminal, and coating resin that covers the second surface of the first package, the second semiconductor chip and the wire. | 2020-03-19 |
20200091103 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps. | 2020-03-19 |
20200091104 | MULTILAYER WIRING BOARD, ELECTRONIC DEVICE AND METHOD FOR PRODUCING MULTILAYER WIRING BOARD - A multilayer wiring board includes a first insulating layer, a second insulating layer stacked on the first insulating layer, a via conductor inside each of the first insulating layer and the second insulating layer, and a conductive bonding layer that bonds the via conductors to each other. The first insulating layer is directly bonded to the second insulating layer, and a relationship a | 2020-03-19 |
20200091105 | ANISOTROPIC CONDUCTIVE FILM AND METHOD OF PRODUCING THE SAME - An anisotropic conductive film has a three-layer structure in which a first connection layer is sandwiched between a second connection layer and a third connection layer that each are formed mainly of an insulating resin. The first connection layer has a structure in which conductive particles are arranged in a single layer in the plane direction of an insulating resin layer on a side of the second connection layer, and the thickness of the insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than that of the insulating resin layer in regions in proximity to the conductive particles. | 2020-03-19 |
20200091106 | SEMICONDUCTOR CHIP PACKAGING STRUCTURE WITHOUT SOLDERING WIRE, AND PACKAGING METHOD THEREOF - A semiconductor chip packaging structure without soldering wire and a packaging method thereof are disclosed. The semiconductor chip packaging structure comprises at least one packaging structure, and each packaging structure comprises a substrate, and a semiconductor chip is arranged on the substrate. Pins of the semiconductor chip are electrically connected to the conductive circuit formed by engraving or etching metal film or alloy film. The semiconductor chip packaging structure also comprises a packaging glue layer covering the semiconductor chip and the conductive circuit. The semiconductor chip packaging method includes steps of arranging a semiconductor chip on the substrate; forming a metal film or an alloy film around the semiconductor chip; etching the metal film or alloy film, to form the conductive circuit; and covering a packaging glue layer on the semiconductor chip and the conductive circuit. As a result, the production efficiency can be improved greatly. | 2020-03-19 |
20200091107 | CAPILLARY TRANSPORT DEVICE, CAPILLARY MOUNTING DEVICE, CAPILLARY REPLACEMENT DEVICE, CAPILLARY TRANSPORT METHOD, CAPILLARY MOUNTING METHOD, AND CAPILLARY REPLACEMENT METHOD - There is provided a capillary transport device capable of inserting, without manpower, a capillary into a mounting section of an ultrasonic horn. According to an aspect of the present invention, a capillary transport device includes: a first tube | 2020-03-19 |
20200091108 | Laser reflow apparatus and method for electronic components with micron-class thickness - Provided is a laser reflow apparatus for reflowing electronic components on a substrate disposed on a stage, the apparatus including: a laser emission unit comprised of a plurality of laser modules for emitting a laser beam having a flat top output profile in at least one section of the substrate on which the electronic components are disposed; a camera unit comprising at least one camera module for capturing a reflowing process of the electronic components performed by the laser beam; and a laser output control unit configured to generate a control signal for independently controlling the respective laser modules of the laser emission unit based on a signal output from the camera unit and apply the control signal to the laser emission unit. | 2020-03-19 |
20200091109 | METHOD FOR MANUFACTURING ELECTRONIC PACKAGE - The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips. | 2020-03-19 |
20200091110 | SYSTEM AND METHOD FOR PROVIDING 3D WAFER ASSEMBLY WITH KNOWN-GOOD-DIES - Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies. | 2020-03-19 |
20200091111 | STACKED SEMICONDUCTOR SYSTEM HAVING INTERPOSER OF HALF-ETCHED AND MOLDED SHEET METAL - A semiconductor system ( | 2020-03-19 |
20200091112 | STACK PACKAGES INCLUDING STACKED SEMICONDUCTOR DIES - A stack package includes a second semiconductor die stacked on the first semiconductor die, a third semiconductor die disposed on the lifting supporter. The third semiconductor die vertically and partially overlapping with the second semiconductor die. | 2020-03-19 |
20200091113 | Packages Formed Using RDL-Last Process - A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines. | 2020-03-19 |
20200091114 | SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDCUTOR PACKAGE - A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars. | 2020-03-19 |
20200091115 | 3DIC Structure and Methods of Forming - A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other. | 2020-03-19 |
20200091116 | 3-D STACKING SEMICONDUCTOR ASSEMBLY HAVING HEAT DISSIPATION CHARACTERISTICS - A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate. These wires can also effectively compensate for the thermal expansion mismatch between the stacked chips and the interconnect substrate, thereby allowing a higher manufacturing yield and better reliability. | 2020-03-19 |
20200091117 | STACKED SEMICONDUCTOR CHIPS HAVING TRANSISTOR IN A BOUNDARY REGION - A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a first semiconductor chip which includes a first region, a second region, and a boundary region between the first region and the second region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region, wherein a first circuit element is disposed in the first region and a second circuit element is disposed in the boundary region, and wherein second circuit element stress tolerance is greater than first circuit element stress tolerance. | 2020-03-19 |
20200091118 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes a metal layer; a semiconductor chip on the metal layer and having an upper electrode and a lower electrode; a first wiring board electrically connected to the upper electrode, and includes a first, a second, a third plate-shaped portion, the first plate-shaped portion being parallel to the second plate-shaped portion, and the third plate-shaped portion being connected to the first and the second plate-shaped portion; a second wiring board electrically connected to the metal layer, and includes a fifth, a sixth, and a seventh plate-shaped portion, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to the fifth and the sixth plate-shaped portion. The first and the second plate-shaped portion are provided between the fifth and the sixth plate-shaped portion, and the semiconductor chip is positioned between the fifth and the sixth plate-shaped portion. | 2020-03-19 |
20200091119 | ALIGNED ARRANGEMENT OF LEDS - A lighting arrangement includes at least a first and a second LED lighting element arranged next to each other on a carrier surface. The spacer element has, at least in a portion thereof which is in contact with the second LED lighting element, a width which is less than 20% of a width of the first LED lighting element. The first LED lighting element comprises a spacer element projecting into a direction in parallel to the carrier surface. The second LED lighting element is arranged in contact with the spacer element such that it is arranged aligned relative to the first LED lighting element, and such that the first and second LED lighting elements are arranged at a distance forming a gap between the first and second LED lighting elements. | 2020-03-19 |
20200091120 | SEMICONDUCTOR MODULE, DISPLAY DEVICE, AND SEMICONDUCTOR MODULE MANUFACTURING METHOD - Resin covers a side surface and a back surface of a blue LED and holds the blue LED level. An electrode is disposed between a top surface of a wiring substrate and a back surface of the blue LED, extends through the resin, and electrically connects the wiring substrate and the blue LED to each other. A light-outgoing surface (top-surface) of the blue LED is exposed without being covered with the resin, and the light-outgoing surface (top-surface) is flush with a top surface of the resin. | 2020-03-19 |
20200091121 | LIGHT-EMITTING DEVICE AND BACKLIGHT INCLUDING LIGHT-EMITTING DEVICE - The light-emitting device includes a first light-emitting element having an emission peak wavelength of 430 nm or more and less than 490 nm, a second light-emitting element having an emission peak wavelength of 490 nm or more and 570 nm or less, a support body at which the first light-emitting element and the second light-emitting element are disposed, and a light-transmissive member containing a red phosphor and covering the first light-emitting element and the second light-emitting element. A content density of the red phosphor in the light-transmissive member in a space between the first and second light-emitting elements is higher in a part below an upper surface of the second light-emitting element than in a part above the upper surface thereof. | 2020-03-19 |
20200091122 | PACKAGE ON PACKAGE STRUCTURE - A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package. | 2020-03-19 |
20200091123 | SEMICONDUCTOR PACKAGES INCLUDING BRIDGE DIE - A semiconductor package includes first and second semiconductor dies, first and second redistributed line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistributed line structure. The first bridge die is disposed to provide a level difference between the first semiconductor die and the first bridge die, the first bridge die having a height that is less than a height of the first semiconductor die. The second redistributed line structure has a protrusion, laterally protruding from a side surface of the first semiconductor die when viewed from a plan view, and a bottom surface of the second redistributed line structure is in contact with a top surface of the first semiconductor die. The second semiconductor die is disposed on the second redistributed line structure. The vertical connector is disposed between the bridge die and the protrusion of the second redistributed line structure to support the protrusion. | 2020-03-19 |
20200091124 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure including a plurality of first dies and an insulating encapsulant is provided. The plurality of first dies each include a first waveguide layer having a first waveguide path of a bent pattern, wherein the first waveguide layers of the plurality of first dies are optically coupled to each other to form an optical route. The insulating encapsulant encapsulates the plurality of first dies. | 2020-03-19 |
20200091125 | LIGHT-EMITTING PACKAGE - A light-emitting apparatus package of the present invention includes (i) an electrically insulated ceramic substrate, (ii) a first concave section formed in the direction of thickness of the ceramic substrate so as to form a light exit aperture in a surface of the ceramic substrate, (iii) a second concave section formed within the first concave section in the further direction of thickness of the ceramic substrate so that one or more light-emitting devices are provided therein, (iv) a wiring pattern for supplying electricity, which is provided in the first concave section, and (v) a metalized layer having light-reflectivity, which is (a) provided between the light-emitting device and the surface of the second concave section of the substrate, and (b) electrically insulated from the wiring pattern. On the account of this, the light-emitting apparatus package in which heat is excellently discharged and light is efficiently utilized and a light-emitting apparatus in which the light-emitting apparatus package is used can be obtained. | 2020-03-19 |
20200091126 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips. | 2020-03-19 |
20200091127 | LIGHT EMITTING STRUCTURE - A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material. | 2020-03-19 |
20200091128 | MICROELECTRONIC ASSEMBLIES - Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar. | 2020-03-19 |
20200091129 | SEMICONDUCTOR DEVICE WITH IMPROVED HEAT DISSIPATION - A semiconductor device includes a substrate, a semiconductor device module, and a heat conductor. The semiconductor device module is on the substrate. The semiconductor device module includes an interposer substrate, one or more semiconductor device chips, a covering resin, and a metal film. The one or more semiconductor device chips are on a first surface of the interposer substrate. The covering resin is in contact with the first surface of the interposer substrate and the one or more semiconductor device chips and encloses the one or more semiconductor device chips. The metal film is in contact with the covering resin and covers the covering resin. The heat conductor is in thermal contact with the substrate and the metal film, and has a higher thermal conductivity than the covering resin. | 2020-03-19 |
20200091130 | SEMICONDUCTOR MODULE - A semiconductor module includes: a first circuit substrate having a conductive layer disposed on an insulating plate; a plurality of semiconductor elements on the conductive layer, a second circuit substrate disposed above the semiconductor elements, the second circuit substrate having a main current wiring layer and a control wiring layer positioned in a layer above the main current wiring layer; a first lead terminal vertically extending upwards from and in contact with the main current wiring layer; a second lead terminal vertically extending upwards from and in contact with the conductive layer of the first circuit substrate; a third lead terminal vertically extending upwards from and in contact with the control wiring layer; and a sealing material covering at least some of the elements mentioned above. | 2020-03-19 |
20200091131 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material. | 2020-03-19 |
20200091132 | INTEGRATED CIRCUIT AND LAYOUT DESIGN METHOD - According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks. | 2020-03-19 |
20200091133 | MEMORY CIRCUIT LAYOUT METHOD - A method includes placing first and second oxide diffusion (OD) layout patterns in a layout design corresponding to first, second, third, and fourth memory cells of a memory circuit. The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. The method is wholly or partially performed by using a hardware processor. | 2020-03-19 |
20200091134 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a semiconductor layer having first and second plane, a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region between the first semiconductor region and the first plane, a first conductivity-type third semiconductor region between the second semiconductor region and the first plane, a second conductivity-type fourth semiconductor region between the third semiconductor region and the first plane, a first conductivity-type fifth semiconductor region provided between the first semiconductor region and the first plane, a first electrode provided on a side of the first plane, and electrically connected to the third semiconductor region and the fourth semiconductor region, a second electrode provided on a side of the second plane, and electrically connected to the first semiconductor region, and a conductive layer provided on a side of the first plane, and electrically connecting the second and the fifth semiconductor region. | 2020-03-19 |
20200091135 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element ( | 2020-03-19 |
20200091136 | RC-TRIGGERED BRACING CIRCUIT - A protection circuit including a low-leakage electrostatic discharge (ESD) protection circuit and at least one bracing circuit, the at least one bracing circuit including an RC input stage connected between a pad and ground, a driver transistor configured to drive a plurality of components of the at least one bracing circuit, a series transistor on an input line configured to act as a high impedance element during an ESD event, and a mini-clamp configured to short the input line to ground to protect a circuit to be protected during an ESD event. | 2020-03-19 |
20200091137 | ELECTROSTATIC DISCHARGE HANDLING FOR LATERAL TRANSISTOR DEVICES - A semiconductor transistor device includes a source region, a gate region having a p-type gate region and an n-type gate region, and a drain region having a p-type drain region and an n-type drain region. The p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region are positioned to provide, in response to an electrostatic discharge (ESD) voltage, a drain-to-gate ESD current path to at least partially discharge the ESD voltage. | 2020-03-19 |
20200091138 | ESD PROTECTION DEVICE WITH BIDIRECTIONAL DIODE STRING-TRIGGERING SCR STRUCTURE - An ESD protection device for bidirectional diode string triggering SCR structure belongs to the field of electro-static discharge of an integrated circuit. A deep N well is arranged on a P substrate, and a first P well, a first N well, a second P well and a second N well are successively arranged from left to right on a surface region of the deep N well. In a second N well region, a mask preparing plate is used to insert the P wells at intervals. The circumference of each P well is isolated by the N well. Each P well is respectively provided with a pair of P+ implantation region and N+ implantation region. The metal wire is connected with the implantation region, and a positive electrode and a negative electrode are led out from the metal wire for forward conduction and reverse conduction. | 2020-03-19 |
20200091139 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of reducing a mounting area. A semiconductor device ( | 2020-03-19 |
20200091140 | SEMICONDUCTOR UNIT, SEMICONDUCTOR MODULE, AND SEMICONDUCTOR DEVICE - A semiconductor unit includes: a plurality of transistor chips arranged in a plurality of parallel rows, each transistor chip respectively having a first main electrode on one surface and a second main electrode on another surface; a first conductor layer electrically connected to the first main electrodes of the transistor chips, both corner portions on one end of the first conductor layer being drawn out in a direction in which the rows of transistor chips run; a second conductor layer arranged between the both corner portions of the first conductor layer; and a wiring substrate that is arranged on a side of the second main electrodes of the plurality of transistor chips and includes a wiring layer electrically connected to the second main electrodes of the plurality of transistor chips and to the second conductor layer. | 2020-03-19 |
20200091141 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first electrically conductive portion, a first semiconductor chip of a reverse-conducting insulated gate bipolar transistor, a second electrically conductive portion, a third electrically conductive portion, a second semiconductor chip of an insulated gate bipolar transistor, and a fourth electrically conductive portion. The first semiconductor chip includes a first electrode and a second electrode. The first electrode is electrically connected to the first electrically conductive portion. The second electrically conductive portion is electrically connected to the second electrode. The third electrically conductive portion is electrically connected to the first electrically conductive portion. The second semiconductor chip includes a third electrode and a fourth electrode. The third electrode is electrically connected to the third electrically conductive portion. The fourth electrically conductive portion is electrically connected to the fourth electrode and the second electrically conductive portion. | 2020-03-19 |
20200091142 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin. | 2020-03-19 |
20200091143 | GATE CUT STRUCTURES - The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials. | 2020-03-19 |
20200091144 | NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DISJOINED EPITAXIAL SOURCE OR DRAIN REGIONS - Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. | 2020-03-19 |
20200091145 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED SOURCE OR DRAIN UNDERCUT FOR VARIED WIDTHS - Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance. | 2020-03-19 |
20200091146 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and the substrate includes a first region and a second region. A gate structure is formed over a fin structure and a first S/D structure has a first volume. A second S/D structure has a second volume, and the second volume is lower than the first volume. A first contact structure is formed over the first S/D structure and a first conductive via is formed over the first contact structure. A power line is formed over the first conductive via, and the power line is electrically connected to the first S/D structure by the first conductive via and the first contact structure. | 2020-03-19 |
20200091147 | SILICON CARBIDE MOSFET WITH SOURCE BALLASTING - An integrated device and a method for making said integrated device. The integrated device includes a plurality of planar MOSFETs that have a first contact region formed in a first source region of a plurality of source regions and a second contact region formed in a second source region of the plurality of source regions. The first and second contact regions have respective portions of the source region doped with the second conductivity type, and the first and second contact regions are separated by a JFET region, wherein the JFET region is longer in one planar dimension than the other and the first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region. | 2020-03-19 |
20200091148 | S-Contact for SOI - Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate. | 2020-03-19 |
20200091149 | REDUCTION OF MULTI-THRESHOLD VOLTAGE PATTERNING DAMAGE IN NANOSHEET DEVICE STRUCTURE - Devices and methods are provided to fabricate nanosheet field-effect transistor devices having dummy nanosheet channel layers disposed above active nanosheet channel layers to protect the active nanosheet channel layers from oxidation during work function metal patterning processes that are implemented as part of a multi-threshold voltage process module. The dummy nanosheet channel layers have a reduced thickness so that the dummy nanosheet layers do not function as active channel layers of the nanosheet field-effect transistor devices. The dummy nanosheet channel layers serve as oxygen infusion blocking layers to protect the active nanosheet channel layers from being infused with oxygen and oxidized by a directional plasma etch process performed during a work function metal patterning process. | 2020-03-19 |
20200091150 | Semiconductor Device and Fabricating the Same - An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature. | 2020-03-19 |
20200091151 | STRUCTURE AND FORMATION METHOD OF HYBRID SEMICONDUCTOR DEVICE - A structure and a formation method of hybrid semiconductor devices are provided. The structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The structure further includes a gate stack over the nanostructures. The nanostructures are separated from each other by portions of the gate stack. | 2020-03-19 |
20200091152 | SEMICONDUCTOR DEVICES - Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure. | 2020-03-19 |
20200091153 | Semiconductor Device - A semiconductor device is disclosed. The semiconductor device includes a substrate, a well, an oxidation layer, a gate electrode and a shared source/drain electrode. The substrate has a first surface and a second surface opposite to each other. The well is formed in the substrate. The substrate and the well have a first conductivity type and a second conductivity type respectively. The oxidation layer is formed in the well. The gate electrode is formed above the first surface and has a first opening. The shared source/drain electrode is formed near the first surface in the oxidation layer and exposed from the first opening. The shared source/drain electrode has the first conductivity type. | 2020-03-19 |
20200091154 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power. | 2020-03-19 |
20200091155 | Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor - Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device. | 2020-03-19 |
20200091156 | TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORS - Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. | 2020-03-19 |
20200091157 | STATIC RANDOM ACCESS MEMORY CELL EMPLOYING N-DOPED PFET GATE ELECTRODES AND METHODS OF MANUFACTURING THE SAME - Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion. | 2020-03-19 |
20200091158 | INTEGRATED CIRCUIT DEVICES INCLUDING FIN SHAPES - Integrated circuit devices are provided. An integrated circuit device includes a substrate having first and second fin-shaped Field Effect Transistor (FinFET) bodies protruding from the substrate. The first and second FinFET bodies have different respective first and second shapes in a first region and a second region, respectively, of the integrated circuit device. | 2020-03-19 |
20200091159 | FinFET SRAM Having Discontinuous PMOS Fin Lines - An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines. | 2020-03-19 |
20200091160 | MEMORY DEVICE - A memory device according to an embodiment includes a first conductive layer, a second conductive layer, and a first layer provided between the first conductive layer and the second conductive layer and containing aluminum oxide that contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide is a ferroelectric. | 2020-03-19 |
20200091161 | ANTI-FUSE WITH REDUCED PROGRAMMING VOLTAGE - A semiconductor device having transistors and anti-fuses integrated thereon includes a transistor region having a defect free monocrystalline semiconductor layer and a device channel for a transistor. The device also has an anti-fuse region including a defective semiconductor layer formed on an oxide of a portion of the surface of an epitaxial semiconductor layer over which the transistor is formed, the oxide having a thickness extending into the epitaxial semiconductor layer. It also has gate structures formed in the transistor region and in the anti-fuse region, where the defective semiconductor layer is programmable by an applied field on the gate structures in the anti-fuse region. | 2020-03-19 |
20200091162 | ONE TRANSISTOR AND ONE FERROELECTRIC CAPACITOR MEMORY CELLS IN DIAGONAL ARRANGEMENTS - Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations. | 2020-03-19 |
20200091163 | MEMORY DEVICE AND MANUFACTURING METHOD FOR THE SAME - A memory device and a manufacturing method for the same are provided. The memory device comprises a NAND memory string. The NAND memory string includes a U-shape channel, a first inversion gate electrode and a second inversion gate electrode. The U-shape channel includes a bottom channel surface, a first outer channel sidewall and a second outer channel sidewall. The bottom channel surface is between the first outer channel sidewall and the second outer channel sidewall opposing to the first outer channel sidewall. The first inversion gate electrode is electrically coupled to the U-shape channel and is disposed under bottom channel surface. The second inversion gate electrode is electrically coupled to the U-shape channel and is disposed outside the first outer channel sidewall, and separated from the first inversion gate electrode. | 2020-03-19 |
20200091164 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME - Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device. | 2020-03-19 |
20200091165 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a channel layer and a gate electrode. A first insulating layer is between the semiconductor layer and the gate electrode. A second insulating layer is between the first insulating layer and the gate electrode. A storage region is between the first insulating layer and the second insulating layer. The storage region comprises metal or semiconductor material. A coating layer comprises silicon and nitrogen and surrounds the storage region. The coating layer is between the storage region and the second insulating layer and between the storage region and the first insulating layer. | 2020-03-19 |
20200091166 | NOVEL 3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME - In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact. | 2020-03-19 |