12th week of 2020 patent applcation highlights part 58 |
Patent application number | Title | Published |
20200090667 | METHOD AND SYSTEM FOR LOSSLESS VALUE-LOCATION ENCODING - A method of encoding samples in a digital signal is provided that includes receiving a frame of N samples of the digital signal, determining L possible distinct data values in the N samples, determining a reference data value in the L possible distinct data values and a coding order of L−1 remaining possible distinct data values, wherein each of the L−1 remaining possible distinct data values is mapped to a position in the coding order, decomposing the N samples into L−1 coding vectors based on the coding order, wherein each coding vector identifies the locations of one of the L−1 remaining possible distinct data values in the N samples, and encoding the L−1 coding vectors. | 2020-03-19 |
20200090668 | APPARATUS AND METHOD FOR GENERATING AN ENHANCED SIGNAL USING INDEPENDENT NOISE-FILLING - An apparatus for generating an enhanced signal from an input signal, wherein the enhanced signal has spectral values for an enhancement spectral region, the spectral values for the enhancement spectral regions not being contained in the input signal, includes a mapper for mapping a source spectral region of the input signal to a target region in the enhancement spectral region, the source spectral region including a noise-filling region; and a noise filler configured for generating first noise values for the noise-filling region in the source spectral region of the input signal and for generating second noise values for a noise region in the target region, wherein the second noise values are decorrelated from the first noise values or for generating second noise values for a noise region in the target region, wherein the second noise values are decorrelated from first noise values in the source region. | 2020-03-19 |
20200090669 | METHOD AND DEVICE FOR QUANTIZATION OF LINEAR PREDICTION COEFFICIENT AND METHOD AND DEVICE FOR INVERSE QUANTIZATION - A quantization apparatus comprises: a first quantization module for performing quantization without an inter-frame prediction; and a second quantization module for performing quantization with an inter-frame prediction, and the first quantization module comprises: a first quantization part for quantizing an input signal; and a third quantization part for quantizing a first quantization error signal, and the second quantization module comprises: a second quantization part for quantizing a prediction error; and a fourth quantization part for quantizing a second quantization error signal, and the first quantization part and the second quantization part comprise a trellis structured vector quantizer. | 2020-03-19 |
20200090670 | POST-PROCESSOR, PRE-PROCESSOR, AUDIO ENCODER, AUDIO DECODER AND RELATED METHODS FOR ENHANCING TRANSIENT PROCESSING - An audio post-processor for post-processing an audio signal having a time-variable high frequency gain information as side information includes: a band extractor for extracting a high frequency band of the audio signal and a low frequency band of the audio signal; a high band processor for performing a time-variable modification of the high frequency band in accordance with the time-variable high frequency gain information to obtain a processed high frequency band; and a combiner for combining the processed high frequency band and the low frequency band. Furthermore, a pre-processor is illustrated. | 2020-03-19 |
20200090671 | LOW-COMPLEXITY TONALITY-ADAPTIVE AUDIO SIGNAL QUANTIZATION - The invention provides an audio encoder for encoding an audio signal so as to produce therefrom an encoded signal, the audio encoder including: a framing device configured to extract frames from the audio signal; a quantizer configured to map spectral lines of a spectrum signal derived from the frame of the audio signal to quantization indices, wherein the quantizer has a dead-zone, in which the input spectral lines are mapped to quantization index zero; and a control device configured to modify the dead-zone; wherein the control device includes a tonality calculating device configured to calculate at least one tonality indicating value for at least one spectrum line or for at least one group of spectral lines, wherein the control device is configured to modify the dead-zone for the at least one spectrum line or the at least one group of spectrum lines depending on the respective tonality indicating value. | 2020-03-19 |
20200090672 | AUDIO SIGNAL ENCODING AND DECODING - An audio codec suitable for robust wireless transmission of high quality audio with low latency, still at a moderate bit rate. The encoding and decoding methods are based on ADPCM and in addition to the encoded output bits APM, additional data QB are included in output data blocks, namely data QB representing an internal value of the adaptive quantization ADQ of the ADPCM encoding algorithm, especially a scaling factor encoded and truncated to such as 8 bits. Further, output data blocks preferably include data CFB representing an internal value of the predictor PR of the ADPCM encoding algorithm, especially data CFB representing coefficients of a lattice prediction FIR filter which, truncated to such as 8 bits, can be sequentially included in output data blocks. These additional data QB, CFB regarding internal values of the ADPCM encoding algorithm can be utilized at the encoder side to increase robustness against loss of data blocks in wireless transmission. Especially, the decoding algorithm may comprise comparing its current internal ADPCM decoding values corresponding to the received internal values QB, CFB from the encoder, and in case there is a difference, the decoder can adapt or overwrite its internal values to the ones received QB, CFB. This helps to ensure fast recovery after lost data blocks, thereby ensuring robustness against artefacts in the reconstructed signal, e.g. clicks in case of audio. | 2020-03-19 |
20200090673 | CODING DEVICE, DECODING DEVICE, AND METHOD AND PROGRAM THEREOF - A technology of accurately coding and decoding coefficients which are convertible into linear prediction coefficients even for a frame in which the spectrum variation is great while suppressing an increase in the code amount as a whole is provided. A coding device includes: a first coding unit that obtains a first code by coding coefficients which are convertible into linear prediction coefficients of more than one order; and a second coding unit that obtains a second code by coding at least quantization errors of the first coding unit if (A−1) an index Q commensurate with how high the peak-to-valley height of a spectral envelope is, the spectral envelope corresponding to the coefficients which are convertible into the linear prediction coefficients of more than one order, is larger than or equal to a predetermined threshold value Th | 2020-03-19 |
20200090674 | COORDINATING AND MIXING VOCALS CAPTURED FROM GEOGRAPHICALLY DISTRIBUTED PERFORMERS - Despite many practical limitations imposed by mobile device platforms and application execution environments, vocal musical performances may be captured and continuously pitch-corrected for mixing and rendering with backing tracks in ways that create compelling user experiences. Based on the techniques described herein, even mere amateurs are encouraged to share with friends and family or to collaborate and contribute vocal performances as part of virtual “glee clubs.” In some implementations, these interactions are facilitated through social network- and/or eMail-mediated sharing of performances and invitations to join in a group performance. Using uploaded vocals captured at clients such as a mobile device, a content server (or service) can mediate such virtual glee clubs by manipulating and mixing the uploaded vocal performances of multiple contributing vocalists. | 2020-03-19 |
20200090675 | METHOD AND APPARATUS FOR PROCESSING SPEECH SIGNAL ADAPTIVE TO NOISE ENVIRONMENT - A voice signal processing method includes acquiring a near-end noise signal and a near-end voice signal by using at least one microphone, acquiring a far-end voice signal according to an incoming call, determining a noise control parameter and a voice signal change parameter based on at least one of information about the near-end voice signal, information about the near-end noise signal, or information about the far-end voice signal, generating an anti-phase signal of the near-end noise signal based on the noise control parameter, changing the far-end voice signal to improve articulation of the far-end voice signal based on information related to at least one of the voice signal change parameter, the near-end noise signal, or the anti-phase signal, and outputting the anti-phase signal and the changed far-end voice signal. | 2020-03-19 |
20200090676 | SYSTEM AND METHOD FOR AUDIO NOISE REDUCTION - A system is provided. The system comprises at least one artificial neural network configured to: receive an audio signal; for a time period, determine if at least one human voice audio spectrum is in the audio signal; for the time period, identify at least one human voice audio power spectrum; for the time period, extract each of the at least one identified human voice audio power spectrum; remove artifacts from each extracted human voice audio power spectrum to synthesize an estimation of an original human voice prior to its distortion; and transmit the synthesized estimation of an original human voice. | 2020-03-19 |
20200090677 | SEPARATING DESIRED AUDIO CONTENT FROM UNDESIRED CONTENT - The present disclosure provides new variants of non-negative matrix factorization suitable for separating desired audio content from undesired audio content. In certain embodiments, a multi-dimensional non-negative representation of an audio signal is decomposed into desired content and undesired content by performing convolutional non-negative matrix factorization (CNMF) on multiple layers, each layer having a respective non-negative matrix representation. In certain embodiments, the desired content is represented by a first dictionary and the undesired content is represented by a second dictionary, and sparsity is imposed on activations of basic elements of the first or the second dictionary, wherein a degree of sparsity is controlled by setting a minimum number of components with significant activations of the first or second dictionary, respectively. | 2020-03-19 |
20200090678 | AUTOMATIC DETERMINATION OF TIMING WINDOWS FOR SPEECH CAPTIONS IN AN AUDIO STREAM - The technology disclosed herein may determine timing windows for speech captions of an audio stream. In one example, the technology may involve accessing audio data comprising a plurality of segments; determining, by a processing device, that one or more of the plurality of segments comprise speech sounds; identifying a time duration for the speech sounds; and providing a user interface element corresponding to the time duration for the speech sounds, wherein the user interface element indicates an estimate of a beginning and ending of the speech sounds and is configured to receive caption text associated with the speech sounds of the audio data. | 2020-03-19 |
20200090679 | DEVICE FOR PREVENTING CABLES AGAINST EXTERNAL DAMAGE BASED ON SOUND SOURCE LOCALIZATION - A device for preventing cables against external damage based on sound source localization comprises a power supply unit, and a sound source sensor unit, a camera unit, a signal processing unit and a wireless communication unit which are electrically connected to the power supply unit. The signal processing unit is connected to the sound source sensor unit, the camera unit and the wireless communication unit. The camera unit is associated with the sound source sensor unit. When the sound source sensor unit recognizes a target signal, the signal processing unit sends a trigger signal to the camera unit, and then the camera unit is triggered to replay a surveillance video to determine whether or not a target really exists. Compared with the prior art, the device has the advantages of being good in safety, high in reliability and the like. | 2020-03-19 |
20200090680 | VOICE SYNTHESIZED PARTICIPATORY RHYMING CHAT BOT - Among other things, embodiments of the present disclosure may be used to help train speech recognizers for improving generalized voice experience quality in a chat bot system. In some embodiments, the system provides users with games to play to increase user engagement with the chat bot system. | 2020-03-19 |
20200090681 | MENTAL HEALTH DIAGNOSTICS USING AUDIO DATA - The present disclosure generally relates to a system and method for obtaining a diagnosis of a mental health condition. An exemplary system can receive an audio input; convert the audio input into a text string; identify a speaker associated with the text string; based on at least a portion of the audio input, determine a predefined audio characteristic of a plurality of predefined audio characteristics; based on the determined audio characteristic, identify an emotion corresponding to the portion of the audio input; generate a set of structured data based on the text string, the speaker, the predefined audio characteristic, and the identified emotion; and provide an output for obtaining the diagnosis of the mental disorder or condition, wherein the output is indicative of at least a portion of the set of structured data. | 2020-03-19 |
20200090682 | VOICE ACTIVITY DETECTION METHOD, METHOD FOR ESTABLISHING VOICE ACTIVITY DETECTION MODEL, COMPUTER DEVICE, AND STORAGE MEDIUM - A method for establishing a voice activity detection model includes obtaining a training audio file and a target result of the training audio file, framing the training audio file to obtain an audio frame, extracting an audio feature of the audio frame, the audio feature comprising at least two types of features, inputting the extracted audio feature as an input to a deep neural network model, performing information processing on the audio feature through a hidden layer of the deep neural network model, and outputting the processed audio feature through an output layer of the deep neural network model, to obtain a training result; determining a bias between the training result and the target result, and inputting the bias as an input to an error back propagation mechanism, and updating weights of the hidden layer until the deep neural network model reaches a preset condition. | 2020-03-19 |
20200090683 | MAGNETIC RECORDING AND REPRODUCING DEVICE - According to one embodiment, a magnetic recording and reproducing device includes a magnetic flux control layer provided between a main magnetic pole and an auxiliary magnetic pole, and a protective layer provided on an ABS of the auxiliary magnetic pole. The magnetic flux control layer includes an adjustment layer formed of a magnetic material includes one of Fe, Co or Ni and provided between a first conductive layer and a second conductive layer, and generates a spin torque and inverts a direction of magnetization in the adjustment layer, when current is supplied. A voltage Vb applied to the magnetic flux control layer is lower than a voltage Vba represented by an expression (1). | 2020-03-19 |
20200090684 | MAGNETIC DISK DEVICE CONFIGURED TO SPECIFY A RANGE OF PREVIOUSLY WRITTEN TRACK THAT IS TO BE OVERLAPPED DURING A WRITE AND VERIFY DATA PREVIOUSLY WRITTEN IN THE SPECIFIED RANGE AFTER THE WRITE - A magnetic disk device includes a magnetic disk and a control circuit. The magnetic disk includes a first area where writing is performed in a manner such that a newly written track partially overlaps a previously written adjacent track. The control circuit is configured to specify a range of a second track, which is to be overlapped as a result of writing first data to a first track, write second data written in the specified range of the second track to a saving area prior to writing the first data to the first track, write the first data to the first track, and verify the second data in the second track after writing the first data to the first track. | 2020-03-19 |
20200090685 | MAGNETIC RECORDING DEVICE - According to one embodiment, a magnetic recording device includes a magnetic head, a first electrical circuit, and a second electrical circuit. The magnetic head includes a magnetic pole, a first shield, a conductive member electrically connecting the magnetic pole and the first shield and being provided between the magnetic pole and the first shield, and a coil. The first electrical circuit is configured to supply a first current to the magnetic pole, the conductive member, and the first shield. The second electrical circuit is configured to supply a recording current to the coil. A recording magnetic field is generated from the magnetic pole. The recording magnetic field corresponds to the recording current. A rise time of the recording current is not less than 65% of a shortest bit length. | 2020-03-19 |
20200090686 | SPLIT CONTACT SENSOR FOR A HEAT-ASSISTED MAGNETIC RECORDING SLIDER - An apparatus comprises a slider having an air bearing surface (ABS), a leading edge, and a trailing edge opposing the leading edge. A writer having a write pole is situated at or near the ABS. A near-field transducer (NFT) is situated at or near the ABS and between the write pole and the leading edge of the slider. An optical waveguide is configured to couple light from a laser source to the NFT. A contact sensor is situated between the write pole and the trailing edge. The contact sensor comprises a first ABS section situated at or near the ABS, a second | 2020-03-19 |
20200090687 | ADHESIVE FOR PROCESSING A MICROELECTRONIC SUBSTRATE, AND RELATED METHODS - Described are methods for processing microelectronic device substrates by a lapping step, e.g., a final lapping step, wherein the step includes the use of an elastomeric pressure-sensitive adhesive to secure the microelectronic device substrate to a carrier that holds the substrate to a surface of the carrier during the lapping step, and wherein the pressure-sensitive adhesive can be a non-polysilicone based adhesive having mechanical properties that include a tan delta that is below about 0.2. | 2020-03-19 |
20200090688 | WIRING BOARD UNIT FOR DISK DEVICES, ACTUATOR ASSEMBLY FOR DISK DEVICES AND DISK DEVICE COMPRISING THE SAME - According to one embodiment, a wiring board unit includes a reinforcing board, a flexible printed circuit board includes a joint portion including a first plane and a second plane and attached on the reinforcing board, a relay unit extending from the first plane, a plurality of connection pad groups located on one of the first plane and the second plane and a first IC chip mounted on the first plane, and the joint portion is bent on a boundary between the first plane and the second plane. | 2020-03-19 |
20200090689 | ACTUATOR ASSEMBLY OF DISK DEVICE AND DISK DEVICE COMPRISING THE SAME - According to one embodiment, an actuator assembly includes a head actuator including an actuator block having a first surface, a second surface intersecting the first surface, and a first groove provided on the second surface, and a suspension assembly supporting a magnetic head and a wiring board including a plate arranged on the first surface, a flexible printed circuit board provided on the plate, and an IC chip provided on the flexible printed circuit board, wherein the plate comprises a first engaging portion engaging with the first groove. | 2020-03-19 |
20200090690 | MAGNETIC DISK DEVICE AND METHOD - According to one embodiment, a magnetic disk device includes a magnetic disk including a plurality of tracks, first and second actuators, and a control circuit. The magnetic disk includes the plurality of tracks. The control circuit writes, in a first track by using the first actuator, second data having a size corresponding to a first number among the first data. In addition, the control circuit writes, in a second track by using the second actuator, third data having a size corresponding to a second number among the first data. Each of the first track and the second track is a track among the plurality of tracks. The first number is a number of writable sectors included in the first track. The second number is a number of writable sectors included in the second track. The third data is data received subsequent to the second data. | 2020-03-19 |
20200090691 | MAGNETIC DISK DEVICE AND HEAD POSITION CORRECTION METHOD - According to one embodiment, a magnetic disk device includes a disk including a recording region including a servo sector, a head configured to write data to the disk and read data from the disk, and a controller configured to acquire a plurality of correction data for a repeatable runout of the recording region, the correction data respectively corresponding to a plurality of measurement positions set based on a first linearity error acquired by reading the servo sector, and to correct a position of the head based on the correction data. | 2020-03-19 |
20200090692 | MAGNETIC HEAD AND MAGNETIC DISK DEVICE INCLUDING THE SAME - According to one embodiment, a magnetic head includes a slider including an air bearing surface with a pair of side edges, a pair of side surfaces disposed along the pair of side edges of the air bearing surface, a leading-side end surface, and a trailing-side end surface, and a head portion in the slider. The slider includes a leading step at a leading-side end of the air bearing surface, a trailing step at a trailing-side end of the air bearing surface, a deep groove between the leading step and the trailing step to be opened to the air bearing surface and the side surfaces, and a shallow groove formed in a center area between the pair of side edges in a region between the deep groove and the trailing step. | 2020-03-19 |
20200090693 | MAGNETIC HEAD AND MAGNETIC DISK DEVICE INCLUDING THE SAME - According to one embodiment, a magnetic head includes a slider with an air bearing surface, and a head element in the slider. The slider includes a leading step at a leading side end of the air bearing surface, a trailing step at a trailing side end of the air bearing surface and including the head element, a deep groove formed between the leading step and the trailing step and opening to the air bearing surface, a center rail extending from a center portion of the air bearing surface to the trailing step, and a pair of pressure generators disposed between the center rail and each side edge. | 2020-03-19 |
20200090694 | MAGNETIC RECORDING MEDIUM AND MAGNETIC RECORDING AND REPRODUCING DEVICE - The magnetic recording medium includes a non-magnetic support; and a magnetic layer including a ferromagnetic powder and a binding agent on the non-magnetic support, in which a difference (S | 2020-03-19 |
20200090695 | 45 RPM Toneolascope Starspinner Adaptor - A 45-record adapter embellished with weighted and shiny chrome ball-bearings and perhaps colored metal balls with LED lights structured and arranged to allow 45 rpm records to be played on a turntable, but also help to hold the records in place while offering record-collectors and enthusiasts a unique, eye-catching novelty. | 2020-03-19 |
20200090696 | MAGNETIC DISK DEVICE, CONTROL DEVICE, AND REGULATOR DEVICE - According to one embodiment, a magnetic disk device includes a control device and a regulator device. The control device and the regulator device are connected to each other through a first interface and a second interface. The control device transmits a required voltage value to the regulator device through the first interface and transmits a correction value based on the required voltage value and an output voltage output from the regulator device to the regulator device. The regulator device outputs a voltage to the control device on the basis of the received required voltage value and corrects a value of the voltage to be output to the control device on the basis of the received correction value. | 2020-03-19 |
20200090697 | AUDIO BUFFERING FOR PROCESSING WITH VARIABLE LOOKAHEAD - An audio processing system has a buffer, a first digital signal processing module that uses a first lookahead, a second digital signal processing module that uses a second, greater lookahead, and a cross-fader. The cross-fader fades between the output of the first digital signal processing module to the output of the second digital signal processing module, based on lookahead depth of data of the audio signal in the buffer. Other aspects are also described and claimed. | 2020-03-19 |
20200090698 | MAGNETIC DISK DEVICE AND METHOD FOR OPTIMIZING RECORDING CURRENT - A magnetic disk device includes a magnetic disk that includes a plurality of zones divided in a radial direction, a plurality of tracks in each of the zones, and a plurality of sectors in each of the tracks divided in a circumferential direction, a magnetic head configured to read and write data to and from the magnetic disk, and a control unit configured to determine a setting value of a recording current to be applied to the magnetic head when writing to each of a plurality of sections of a first sector, based on error rates in data read from a second sector that is in the same zone as the first sector and to which a write was performed while changing setting values of recording currents applied to the magnetic head while writing to each of a plurality of sections of the second sector. | 2020-03-19 |
20200090699 | MAGNETIC DISK DEVICE AND CONTROL METHOD - According to an embodiment, the magnetic disk device includes a disk medium and a control circuit. The disk medium includes a first region including a first track. The control circuit controls a write operation of first data to the first track, executes error correction coding of the first data during the write operation. The control circuit makes first determination on whether the written first data is protected by an error correction code. The control circuit sets a second track in a location adjacent to the first track in accordance with a result of the first determination. | 2020-03-19 |
20200090700 | MAGNETIC DISK DEVICE AND WRITE PROCESSING METHOD - According to one embodiment, a magnetic disk device includes a disk, a head configured to write data to the disk and read data from the disk, and a controller configured to control the head to write a first track based on a first error rate read immediately after writing a second track adjacent in a radial direction of the disk to the first track. | 2020-03-19 |
20200090701 | VIDEO-LOG PRODUCTION SYSTEM - Methods, computer-readable media, and apparatuses for composing a video in accordance with a user goal and an audience preference are described. For example, a processing system having at least one processor may obtain a plurality of video clips of a user, determine at least one goal of the user for a production of a video from the plurality of video clips, determine at least one audience preference of an audience, and compose the video comprising at least one video clip of the plurality of video clips of the user in accordance with the at least one goal of the user and the at least one audience preference. The processing system may then upload the video to a network-based publishing platform. | 2020-03-19 |
20200090702 | IMMERSIVE VIRTUAL REALITY PRODUCTION AND PLAYBACK FOR STORYTELLING CONTENT - Methods for digital content production and playback of an immersive stereographic video work provide or enhance interactivity of immersive entertainment using various different playback and production techniques. “Immersive stereographic” may refer to virtual reality, augmented reality, or both. The methods may be implemented using specialized equipment for immersive stereographic playback or production. Aspects of the methods may be encoded as instructions in a computer memory, executable by one or more processors of the equipment to perform the aspects. | 2020-03-19 |
20200090703 | METHOD FOR INLAYING IMAGES OR VIDEO WITHIN ANOTHER VIDEO SEQUENCE - A method for inlaying images within another video sequence comprises: controlling the acquisition of the main sequence and recording it in a memory of mobile equipment; simultaneously controlling, at the initiative of the user, a) the display of the main sequence in a first part of the display screen of the mobile equipment; b) acquiring the secondary video sequence with at least one image sensor of the mobile equipment; c) recording the secondary video sequence in the memory of the mobile equipment; d) displaying the secondary video sequence in a second part of the display screen of the mobile equipment, in a synchronous manner with the display of the main sequence; transmitting the recordings over a server via a communication session; automatically controlling a step of inlaying the secondary video sequence ink the main sequence; controlling the recording of the merged sequence thus produced on the server; and computing an access link by an item of equipment remote from the merged sequence. | 2020-03-19 |
20200090704 | ELECTRONIC DEVICE AND SCREEN IMAGE DISPLAY METHOD FOR ELECTRONIC DEVICE - According to various embodiments of the present invention, an electronic device can comprise: a display for displaying at least a part of an image corresponding to a designated direction in image data on a screen as a partial image; a communication circuit for receiving information related to an external electronic device; and a processor for performing a control so as to display a first partial image of the image data through the display, to check information on a second partial image, being displayed on the external electronic device, of the image data from the information received through the communication circuit, and to allow the information on the second partial image the information on the second partial image to be displayed through the display while the first partial image is being displayed on the screen through the display. The various embodiments of the present invention can allow other embodiments to be possible. | 2020-03-19 |
20200090705 | SHINGLED MAGNETIC RECORDING STORAGE SYSTEM - Methods and systems that reduce off-track write retry operations in shingled magnetic recording systems. In one implementation, the method includes writing data to an initial track, determining which side of the initial track is a shingled side, calculating a percentage of position error signal (PES) at a shingled side end of the initial track (PES1) when an off-track write operation occurs, determining whether the PES1 meets a first pre-determined threshold, continue writing data to a second track responsive to determining the PES1 is below a first pre-determined threshold, calculating a percentage of PES at a shingled side end of the second track (PES2), determining whether a combined value of PES1 and PES2 is above a second predetermined threshold to determine a probability value of the initial track being erased, and continue writing to a third track if the combined value is below the second predetermined threshold. | 2020-03-19 |
20200090706 | ELECTRONIC DEVICE WITH DETACHABLE STRUCTURE AND MODULE FRAME THEREOF - An electronic device with a detachable structure is provided. The electronic device includes a bracket, a connector, a module frame and a carried unit. The bracket includes a bracket wedging portion, wherein the bracket has a receiving recess, the receiving recess has a first side and a second side, the first side is opposite to the second side, and the bracket wedging portion is located on the first side. The connector is disposed on the second side of the bracket. The module frame is detachably connected to the bracket. The module frame can be easily attached to or detached from the bracket, reducing the time and effort required for assembly. | 2020-03-19 |
20200090707 | DISK DEVICE - According to one embodiment, a disk device includes a housing including a base including a sidewall, and a first cover on a surface of the sidewall, and a discoidal recording medium in the housing. The first cover includes a first surface, a second surface on an opposite side to the first surface, and a side portion. The second surface includes a packing on a peripheral portion thereof. The side portion includes a burr on the second surface side and the packing is aligned to the burr. | 2020-03-19 |
20200090708 | LAYERED SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR - The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip. | 2020-03-19 |
20200090709 | APPARATUSES AND METHODS FOR PLATE COUPLED SENSE AMPLIFIERS - Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell. | 2020-03-19 |
20200090710 | DATA LATCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate. | 2020-03-19 |
20200090711 | TWO PIN SERIAL BUS COMMUNICATION INTERFACE AND PROCESS - A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design. | 2020-03-19 |
20200090712 | VARIABLE FILTER CAPACITANCE - Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array. | 2020-03-19 |
20200090713 | APPARATUSES AND METHODS FOR DRAM WORDLINE CONTROL WITH REVERSE TEMPERATURE COEFFICIENT DELAY - Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the timing for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures. | 2020-03-19 |
20200090714 | INTEGRATED CIRCUIT - An integrated circuit includes: a delay circuit suitable for delaying one or more input signals; a toggle sensing circuit suitable for sensing whether or not the one or more input signals toggle; and a replica delay circuit suitable for delaying one or more clock signals in a section where no toggle of the one or more input signals is sensed by the toggle sensing circuit. | 2020-03-19 |
20200090715 | DECODE CIRCUITRY COUPLED TO A MEMORY ARRAY - In an example, an apparatus includes a memory array in a first region and decode circuitry in a second region separate from a semiconductor. The decode circuitry is coupled to an access line in the memory array. | 2020-03-19 |
20200090716 | STORAGE DEVICE - A storage device includes a first memory chip including a first input pad configured to receive a first input signal, a first initializing circuit configured to generate a first initializing signal, a first input delay circuit configured to delay the first input signal by a first time to generate a first output signal, a first output pad configured to receive the first output signal and output the first output signal, a first clock delay circuit configured to delay the first initializing signal by a second time to generate a first clock signal, a second clock delay circuit configured to delay the first clock signal by a third time to generate a second clock signal, a first latch configured to store the first input signal based on the first clock signal, and a second latch configured to store the first input signal based on the second clock signal. | 2020-03-19 |
20200090717 | CONTROLLER AND METHOD OF OPERATING THE SAME - Provided is a method of operating a controller to control an operation of a semiconductor memory device. The method includes: determining a minimum pass tapped delay of the semiconductor memory device based on a first offset; determining a maximum pass tapped delay of the semiconductor memory device based on a second offset; and determining a tapped delay of the semiconductor memory device based on the determined minimum pass tapped delay and the determined maximum pass tapped delay. | 2020-03-19 |
20200090718 | MAGNETIC MEMORY DEVICE - A magnetic memory device includes a conductive member, a stacked body, and a controller. The stacked body includes a first magnetic layer, a second magnetic layer provided between the conductive member and the first magnetic layer, and a third magnetic layer stacked with the first magnetic layer and the second magnetic layer. The controller causes a current to flow in the conductive member. The controller causes a current to flow between the conductive member and the stacked body. The controller is able to identify three or more levels of an electrical resistance value of the stacked body. | 2020-03-19 |
20200090719 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - Provided is a magnetoresistance effect element in which the magnetization direction of the recording layer is perpendicular to the film surface and which has a high thermal stability factor Δ, and a magnetic memory. | 2020-03-19 |
20200090720 | MEMORY DEVICE - The present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein a diffusion barrier is formed between the magnetic tunnel junction and the capping layer. In addition, the present invention provides a memory device in which a lower electrode, a seed layer, synthetic antiferromagnetic layers, a separation layer, a magnetic tunnel junction, a capping layer, and an upper electrode are formed on a substrate in a laminated manner, wherein the seed layer is formed of a material that allows the synthetic antiferromagnetic layers to grow in the FCC ( | 2020-03-19 |
20200090721 | WORD LINE DECODER MEMORY ARCHITECTURE - A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal. | 2020-03-19 |
20200090722 | MEMORY DEVICE CONFIGURED TO PERFORM ASYMMETRIC WRITE OPERATION ACCORDING TO WRITE DIRECTION - Disclosed are memory devices including a variable resistance memory cell and a word line control circuit. A memory device including a variable resistance memory cell including a variable resistance element, a first cell transistor, and a second cell transistor, a first end of the variable resistance element connected to a bit line, a second end of the variable resistance element, a first end of the first cell transistor, and a first end of the second cell transistor connected to the common node, a second end of the first cell transistor and a second end of the second cell transistor connected to a source line, and a word line control circuit configured to separate a sub word line connected to a gate electrode of the second cell transistor from a word line connected to a gate electrode of the first cell transistor in a first write operation and to connect the word line and the sub word line to each other in a second write operation may be provided. | 2020-03-19 |
20200090723 | NONVOLATILE STORAGE DEVICE - A nonvolatile storage device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a memory cell between the first and second wirings, a reading circuit configured to read data from the memory cell during a first and a second reading period, a writing circuit configured to write reference data into the memory cell during a writing period between the first and second reading periods, and a determination circuit configured to compare a first voltage which is based on the data read during the first reading period with a second voltage which is based on the data read during the second reading period, to determine the value of the data read during the first reading period. A current is caused to flow in the memory cell during the first reading period, the writing period, and the second reading period. | 2020-03-19 |
20200090724 | MEMORY DEVICE FOR REDUCING LEAKAGE CURRENT - A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided. | 2020-03-19 |
20200090725 | MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM - A memory system including an MRAM; a memory controller; a temperature sensor; and a magnetic sensor. In the MRAM, write/erase count information, patrol read execution time information, and patrol read information defining a patrol read execution time interval for combinations of a temperature, an intensity of a magnetic field, and a write/erase count are stored. The memory controller acquires the temperature from the temperature sensor, acquires the intensity of the magnetic field from the magnetic sensor, acquires from the patrol read information the patrol read execution time interval corresponding to the combination of the temperature, the intensity of the magnetic field, and the write/erase count, and determines whether or not a patrol read shall be executed by comparing the elapsed time from the previous patrol read execution time with the acquired patrol read execution time interval. | 2020-03-19 |
20200090726 | REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY - Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells. | 2020-03-19 |
20200090727 | FERROELECTRIC MEMORY CELL SENSING - Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground. | 2020-03-19 |
20200090728 | MEMORY CELL IMPRINT AVOIDANCE - Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period. | 2020-03-19 |
20200090729 | MEMORY MODULE INCLUDING REGISTER CLOCK DRIVER DETECTING ADDRESS FREQUENTLY ACCESSED - A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices. | 2020-03-19 |
20200090730 | Signal Timing Alignment based on a Common Data Strobe in Memory Devices Configured for Stacked Arrangements - Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. | 2020-03-19 |
20200090731 | MEMORY SYSTEM TO PROCESS MULTIPLE WORD LINE FAILURES WITH LIMITED STORAGE AND METHOD OF OPERATING SUCH MEMORY SYSTEM - Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information. | 2020-03-19 |
20200090732 | SYSTEMS AND METHODS FOR IMPROVING WRITE PREAMBLES IN DDR MEMORY DEVICES - A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device. | 2020-03-19 |
20200090733 | MEMORY PERFORMING REFRESH OPERATION AND OPERATION METHOD OF THE SAME - A memory includes: first to N | 2020-03-19 |
20200090734 | Memory Device Comprising An Electrically Floating Body Transistor - A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region. | 2020-03-19 |
20200090735 | MEMORY CIRCUIT CONFIGURATION - A circuit includes a first cell in a first row of a memory array, a second cell in a second row of the memory array, and a data line perpendicular to the first row and the second row, intersecting each of the first cell and the second cell, and electrically coupled with each of the first cell and the second cell. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a read operation on the first row. | 2020-03-19 |
20200090736 | POWER AWARE PROGRAMMABLE NEGATIVE BIT LINE CONTROL - A write driver includes a first write data driver, a second write driver, and a control circuit. The first (second) write data driver provides a true (complement) write data signal to an output thereof at a high voltage when a true (complement) data signal is in a first logic state, at a ground voltage when the true (complement) data signal is in a second logic state and a negative bit line enable signal is inactive, and at a voltage below the ground voltage when the true (complement) data signal is in the second logic state and the negative bit line enable signal is active. The control circuit provides the negative bit line enable signal in an active state when a power supply voltage is below a first threshold, and in an inactive state when the power supply voltage is above a second threshold higher than the first threshold. | 2020-03-19 |
20200090737 | MEMORY DEVICE WITH ENHANCED ACCESS CAPABILITY AND ASSOCIATED METHOD - A memory array includes a first memory cell and a second memory cell. Each of the first and the second memory cells includes a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory array also includes a first word line and a second word line coupled to the first access transistor and the second access transistor, respectively, of the first memory cell, wherein the first word line and the second word line are operated independently during a read operation and activated at the same time during a write operation. The memory array further includes a first bit line coupled to the first access transistor of the first memory cell, a second bit line coupled to the second access transistor of the first memory cell, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line. | 2020-03-19 |
20200090738 | QUANTIZING LOOP MEMORY CELL SYSTEM - One example includes a memory cell system that includes a quantizing loop that conducts a quantizing current in a first direction corresponding to a first stored memory state and to conduct the quantizing current in a second direction corresponding to a second stored memory state. The system also includes a bias element configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state. The stored memory state can be read from the memory cell system in response to the substantially constant flux bias and a read current that is provided to the memory cell system. The system further includes a tunable energy element that is responsive to a write current that is provided to the memory cell system to change the state of the stored memory state between the first state and the second state. | 2020-03-19 |
20200090739 | Quantum Metrology and Quantum Memory Using Defect Sates with Spin -3/2 or Higher Half-Spin Multiplets - Devices and methods for the detection of magnetic fields, strain, and temperature using the spin states of a V | 2020-03-19 |
20200090740 | MEMORY SYSTEM - A memory system includes a storage device and a controller. The storage device includes a first string including a first memory cell transistor and a second memory cell transistor connected in series to each other, and a first select transistor, a second string including a third memory cell transistor and a second select transistor, a gate of the second select transistor being independent from a gate of the first select transistor. The controller configured to perform first writing to cause a threshold voltage of the first memory cell transistor to be lower than a first target threshold voltage, perform second writing to cause a threshold voltage of the second memory cell transistor to be higher than a second target threshold voltage after the first writing, perform third writing to cause a threshold voltage of the first memory cell transistor to be higher than the first target threshold voltage after the second writing, and perform fourth writing on the third memory cell transistor after the third writing. | 2020-03-19 |
20200090741 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a memory cell array having plural memory cells that can be set to any one of plural different threshold voltages, plural bit lines connected to the plural memory cells respectively, a word line connected to gates of the plural memory cells, a control unit configured to execute a write sequence for repetitively performing plural loops including a set of a program operation of writing data into the memory cells and a verify operation of verifying data written in the memory cells to write predetermined data in the memory cells MT, and prior to execution of the write sequence, the control unit corrects the write sequence based on a result of performing the preliminary program operation and the detection verify operation on the memory cells. | 2020-03-19 |
20200090742 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n≥3). The first circuit is configured to calculate an estimated value of each of n−m determination voltages based on values of m determination voltages (2≤m≤n−1) among the n determination voltages, and calculate a difference between a value of each of the n−m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n−m determination voltages. | 2020-03-19 |
20200090743 | SYSTEM AND METHOD FOR PERFORMING A CONCURRENT MULTIPLE PAGE READ OF A MEMORY ARRAY - A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment. | 2020-03-19 |
20200090744 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively. | 2020-03-19 |
20200090745 | MEMORY DEVICE - A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a switching element and an information storage element connected to the switching element and containing a phase-change material, a decoder unit configured to determine a selected word line and a selected bit line connected to a selected memory cell to read data, among the plurality of memory cells, and a current compensation circuit configured to remove a leakage current from the selected word line, the leakage current corresponding to a sun of off-currents flowing in unselected bit lines, excluding the selected bit line, among the plurality of bit lines, from the selected word line. | 2020-03-19 |
20200090746 | NONVOLATILE MEMORY DEVICE FOR INVALIDATING DATA STORED THEREIN, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF - A memory device includes a plurality of word lines and a plurality of bit lines intersecting the word lines, a memory cell array comprising a plurality of memory cells coupled between the word lines and the bit lines at intersections between the word lines and the bit lines, respectively, an address decoder suitable for decoding an address to access a memory cell selected among the memory cells, and a controller suitable for writing and reading data to and from the selected memory cell by applying voltages to the word lines and bit lines, wherein the controller invalidates data stored in memory cells coupled to a target word line among the word lines by applying an invalidation voltage to the target word line for a set time. | 2020-03-19 |
20200090747 | CIRCUITRY AND METHODS FOR PROGRAMMING RESISTIVE RANDOM ACCESS MEMORY DEVICES - A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value. | 2020-03-19 |
20200090748 | RANDOM BIT CELL WITH MEMORY UNITS - A random bit cell incudes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line. | 2020-03-19 |
20200090749 | ROW HAMMER REFRESH FOR CONTENT ADDRESSABLE MEMORY DEVICES - A method of operating a memory device may include receiving, during each phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content addressable memory (CAM). The method may further include storing, during each phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Moreover, the method may include refreshing each stored RHA of the CAM via a RHR during the RHR interval. Semiconductor devices and an electronic system are also described. | 2020-03-19 |
20200090750 | ROW HAMMER REFRESH FOR CONTENT-ADDRESSABLE MEMORY DEVICES - A method of operating a memory device may include receiving, during a phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content-addressable memory (CAM). The method further includes storing, during the phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Further, the method includes refreshing the stored RHA of the CAM via a RHR during the RHR interval. | 2020-03-19 |
20200090751 | SEMICONDUCTOR MEMORY DEVICE APPLYING DIFFERENT VOLTAGES TO RESPECTIVE SELECT GATE LINES - According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line. | 2020-03-19 |
20200090752 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer provided above the third conductive layer, the fifth conductive layer being spaced apart from the third conductive layer in the first direction, and the fifth conductive layer being provided parallel to the substrate plane, a sixth conductive layer provided above the fourth conductive layer, the sixth conductive layer being spaced apart from the fourth conductive layer in the first direction, and the sixth conductive layer being provided parallel to the substrate plane, an insulator provided between the first and second conductive layers, between the third and fourth conductive layers, and between the fifth and sixth conductive layers, a first signal line provided between the first, third, and fifth conductive layers and the insulator, the first signal line extending in the first direction, a second signal line provided between the second, fourth, and sixth conductive layers and the insulator, the second signal line extending in the first direction, a first memory cell provided between the first conductive layer and the first signal line, the first memory cell being configured to store first information, a second memory cell provided between the second conductive layer and the second signal line, the second memory cell being configured to store second information, a third memory cell provided between the third conductive layer and the first signal line, the third memory cell being configured to store third information, a fourth memory cell provided between the fourth conductive layer and the second signal line, the fourth memory cell being configured to store fourth information, a fifth memory cell provided between the fifth conductive layer and the first signal line, the fifth memory cell being configured to store fifth information, a sixth memory cell provided between the sixth conductive layer and the second signal line, the sixth memory cell being configured to store sixth information, and a control circuit configured to apply a second voltage to the third conductive layer, the control circuit being configured to apply a third voltage to the fifth conductive layer, the control circuit being configured to read data from the first memory cell, the second voltage being smaller than a first voltage, the first voltage being applied to the first conductive layer, and the third voltage being larger than the first voltage. | 2020-03-19 |
20200090753 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected. | 2020-03-19 |
20200090754 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address. | 2020-03-19 |
20200090755 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD - A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line. | 2020-03-19 |
20200090756 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a plurality of strings each including a select transistor and a memory cell that can be set to any one of a plurality of different threshold voltages, a select gate line that is commonly connected to the select transistors of the plurality of strings, a plurality of bit lines that are individually connected to the plurality of strings, a word line that is commonly connected to the memory cells of the plurality of strings, and a control unit configured to execute a write sequence for repeatedly performing a plurality of loops each including a set of a program operation and a verify operation, and a voltage applied to the select gate line in the program operation of a last loop is lower than a voltage applied to the select gate line in the program operation of a first loop. | 2020-03-19 |
20200090757 | METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE - A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal | 2020-03-19 |
20200090758 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended. | 2020-03-19 |
20200090759 | PRE-PROGRAM READ TO COUNTER WORDLINE FAILURES - Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline. | 2020-03-19 |
20200090760 | DATA STORAGE SYSTEMS AND METHODS FOR IMPROVED RECOVERY AFTER A WRITE ABORT EVENT - Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device. | 2020-03-19 |
20200090761 | MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY - According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a memory string including memory cells including first to third memory cells, and a selection transistor connected to the memory cells, and first to third word lines that are connected to gates of the first to third memory cells of the memory string. The memory controller reads data of the first to third memory cells by applying first to third read voltages to the first to third word lines, respectively. The memory controller reads second data by applying a fourth read voltage to the second word line in parallel to processing of decoding first data, obtains likelihood information on the basis of the first data, the second data, and at least one of the third data and the fourth data, and decodes data on the basis of the likelihood information. | 2020-03-19 |
20200090762 | MEMORY SYSTEM - According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively. | 2020-03-19 |
20200090763 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit. | 2020-03-19 |
20200090764 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND METHOD - A semiconductor memory device includes a plurality of memory cells that include one or more pairs of reference cells that store reference data, and a circuit peripheral thereto. The memory cells are commonly connected to a word line and connected to a plurality of bit lines, respectively. The circuit is configured to apply a read voltage to the word line, cause sense nodes of bit lines connected to the reference memory cells of each pair to be electrically connected to each other, determine whether or not each of the plurality of reference memory cells is ON or OFF based on a voltage at a sense node of each of the plurality of bit lines, and update the read voltage based on the number of reference memory cells determined to be ON and the number thereof determined to be OFF. | 2020-03-19 |
20200090765 | CAPACITIVE VOLTAGE MODIFIER FOR POWER MANAGEMENT - A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage. | 2020-03-19 |
20200090766 | MEMORY SYSTEM - According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data. | 2020-03-19 |