11th week of 2021 patent applcation highlights part 63 |
Patent application number | Title | Published |
20210082766 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND PLASMA PROCESSING APPARATUS - In a manufacturing process of a three-dimensional structure device such as a GAA type FET or a nanosheet fork type FET having stacked channels in which channels having a shape of a wire or a sheet are stacked in a direction vertical to a substrate, a work function control metal is separately formed without expanding a space between FETs having different threshold voltages. Therefore, a first step S | 2021-03-18 |
20210082767 | SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate. | 2021-03-18 |
20210082768 | Semiconductor Device and Method - An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas. | 2021-03-18 |
20210082769 | LEAKAGE REDUCTION METHODS AND STRUCTURES THEREOF - A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary. | 2021-03-18 |
20210082770 | MIDDLE OF THE LINE CONTACT FORMATION - Methods for forming semiconductor devices are disclosed including forming a semiconductor structure having a semiconductor substrate containing two or more fins. The method includes etching a first optical planarization layer on the semiconductor structure exposing a top surface of each of a gate spacer, a gate cap layer and a portion of a source/drain contact adjacent to the exposed gate spacer to form a first gate contact opening. The method further includes depositing a sacrificial place-holder material in the first gate contact opening. The method further includes removing the first optical planarization layer. The method further includes recessing a first conductive material. | 2021-03-18 |
20210082771 | METHOD FOR FORMING ISOLATION STRUCTURE HAVING IMPROVED GAP-FILL CAPABILITY - A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a first semiconductor fin and a second semiconductor fin, and depositing a first dielectric material on the first and second semiconductor fins. There is a trench between the first and second semiconductor fins. The method also includes depositing a semiconductor material on the first dielectric material, heating the semiconductor material to cause the semiconductor material to flow to a bottom region of the trench, filling a top region of the trench with a second dielectric material, and heating the first dielectric material, the second dielectric material, and the semiconductor material to form an isolation structure between the first and second semiconductor fins. | 2021-03-18 |
20210082772 | METAL GATE STRUCTURE OF A CMOS SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a substrate with an isolation region surrounding a P-active region and an N-active region, a first gate electrode comprising a first metal composition over the N-active region, and a second gate electrode with a center portion over the P-active region and an endcap portion over the isolation region. The endcap portion includes a first metal composition, and the center portion includes a second metal composition different from the first metal composition, and the center portion and the endcap portion do not overlap. An inner sidewall of the endcap portion is substantially aligned with a sidewall of the isolation region. | 2021-03-18 |
20210082773 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer. | 2021-03-18 |
20210082774 | EVALUATION METHOD OF METAL CONTAMINATION - A method of evaluating metal contamination by measuring the amount of metal contaminants to a silicon wafer in a rapid thermal processing apparatus includes steps of obtaining a Si single crystal grown by the Czochralski method at a pulling rate of 1.0 mm/min or lower, the crystal having oxygen concentration of 1.3×10 | 2021-03-18 |
20210082775 | Method for Forming a Connection between Two Connection Partners and Method for Monitoring a Connection Process - A method for forming a connection between two connection partners includes: forming a pre-connection layer on a first surface of a first connection partner, the pre-connection layer including a certain amount of liquid; performing a pre-connection process, thereby removing liquid from the pre-connection layer; performing photometric measurements while performing the pre-connection process, wherein performing the photometric measurements includes determining at least one photometric parameter of the pre-connection layer, wherein the at least one photometric parameter changes depending on the fluid content of the pre-connection layer; and constantly evaluating the at least one photometric parameter, wherein the pre-connection process is terminated when the at least one photometric parameter is detected to be within a desired range. | 2021-03-18 |
20210082776 | TESTING SRAM STRUCTURES - A technique relates probing a pass gate transistor in a static random access memory (SRAM) circuit. A gate probe is connected to a gate metal layer of the SRAM circuit, the gate metal layer being coupled to a gate of the pass gate transistor. A source probe is connected to a source metal layer of the SRAM circuit, the source metal layer being coupled to a source of the pass gate transistor. A drain probe is connected to a drain metal layer of the SRAM circuit, the drain metal layer being coupled to a drain of the pass gate transistor, the SRAM circuit comprising other transistors along with the pass gate transistor. The other transistors are free from connections for the probing so as not to cause the other transistors to have an unwanted effect on the pass gate transistor being probed. | 2021-03-18 |
20210082777 | FILM FORMING SYSTEM, MAGNETIZATION CHARACTERISTIC MEASURING DEVICE, AND FILM FORMING METHOD - A film forming system for forming a magnetic film is provided. The film forming system includes a processing module configured to form the magnetic film on a substrate, a magnetization characteristic measuring device configured to measure magnetization characteristics of the magnetic film formed on the substrate in the processing module, and a transfer unit configured to transfer the substrate between the processing module and the magnetization characteristic measuring device. The magnetization characteristic measuring device includes a magnetic field applying mechanism having a permanent magnet magnetic circuit configured to apply a magnetic field to the substrate and adjust the magnetic field to be applied to the substrate, and a detector configured to detect magnetization characteristics of the substrate. | 2021-03-18 |
20210082778 | POWER SEMICONDUCTOR MODULE AND POWER CONVERSION APPARATUS - A power semiconductor module includes an insulating substrate, a first conductive circuit pattern, a second conductive circuit pattern, a first semiconductor device, a second semiconductor device, a sealing member, and a first barrier layer. The sealing member seals the first semiconductor device, the second semiconductor device, the first conductive circuit pattern, and the second conductive circuit pattern. At least one of the first barrier layer and the sealing member includes a first stress relaxation portion. This configuration improves the reliability of the power semiconductor module. | 2021-03-18 |
20210082779 | SEMICONDUCTOR PACKAGES WIYH SHORTENED TALKING PATH - Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring. | 2021-03-18 |
20210082780 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating circuit substrate including an insulating plate, a first metal layer formed on a top surface of the insulating plate, and a second metal layer formed on a bottom surface of the insulating plate, a heatsink on whose top surface the insulating circuit substrate is disposed; semiconductor elements disposed on the top surface of the first metal layer through a bonding material, and a case that encloses a perimeter of the insulating circuit substrate and the semiconductor elements. The first metal layer includes circuit patterns electrically connected to the semiconductor elements and an annular pattern formed to enclose the perimeter of the circuit patterns with a gap provided with respect to the circuit patterns. The second metal layer is disposed at a spot that surfaces the annular pattern. The housing is affixed to the annular pattern through an adhesive. | 2021-03-18 |
20210082781 | SEMICONDUCTOR DEVICE - A semiconductor device of embodiments includes a first semiconductor chip; a metal plate having a first plane and a second plane facing the first plane and including a first ceramic plate provided between the first plane and the second plane; and a first insulating board provided between the first semiconductor chip and the metal plate and facing the first plane, in which the first ceramic plate does not exist between the first semiconductor chip and the second plane. | 2021-03-18 |
20210082782 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed. | 2021-03-18 |
20210082783 | SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device. | 2021-03-18 |
20210082784 | HEAT DISSIPATION STRUCTURES - The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through. | 2021-03-18 |
20210082785 | SEMICONDUCTOR POWER DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor power device includes a substrate, a power chip, and a capping layer, and the substrate has a patterned unit, and the thickness of the substrate is matched with the configuration of the power chip, and the height of the power chip is smaller than the thickness of the substrate, and the power chip is installed at a position corresponding to the patterned unit, and the capping layer is covered onto a side of the patterned unit having the substrate, and the power chip is covered by the capping layer and installed to the substrate. This invention features a simple structure and reasonable design. Since the height of the patterned unit is matched with the thickness of the power chip, therefore the height of the installed power chip is lower than the substrate to facilitate the installation of the capping layer and the dissipation of heat. | 2021-03-18 |
20210082786 | ELECTROHYDRODYNAMIC CONTROL DEVICE - A fluidic device is disclosed, comprising an enclosed passage that is adapted to convey a circulating fluid. The enclosed passage comprises a flow unit having a first electrode and a second electrode offset from the first electrode in a downstream direction of a flow of the circulating fluid. The first electrode is formed as a grid structure and arranged to allow the circulating fluid to flow through the first electrode. The fluidic device may be used for controlling or regulating the flow of the fluid circulating in the enclosed passage, and thereby act as a valve opening, reducing or even closing the passage. | 2021-03-18 |
20210082787 | ION THROUGH-SUBSTRATE VIA - Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV. | 2021-03-18 |
20210082788 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure. | 2021-03-18 |
20210082789 | SIGNAL ISOLATOR HAVING ENHANCED CREEPAGE CHARACTERISTICS - Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die. | 2021-03-18 |
20210082790 | POWER SEMICONDUCTOR PACKAGE HAVING INTEGRATED INDUCTOR AND METHOD OF MAKING THE SAME - A power semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a first metal clip, a second metal clip, an inductor assembly, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. A method for fabricating a power semiconductor package. The method comprises the steps of providing a lead frame; attaching a low side FET and a high side FET to the lead frame; mounting a first metal clip and a second metal clip; mounting an inductor; forming a molding encapsulation; and applying a singulation process. | 2021-03-18 |
20210082791 | LEAD FRAME AND METHOD FOR MANUFACTURING THE SAME - A lead frame includes a die pad having a pad top surface and a pad bottom surface opposite to the top pad surface, a plurality of leads, each having a top lead surface and a bottom lead surface opposite to the top lead surface and disposed around the die pad, and a first molding compound disposed between the die pad and each of the leads. The first molding compound exposes the top pad surface of the die pad by covering a portion of the periphery of the top pad surface of the die pad. A method for manufacturing the lead frame is also disclosed. | 2021-03-18 |
20210082792 | ELECTRICAL DEVICE WITH TERMINAL NOTCHES AND METHOD FOR MANUFACTURING THE SAME - An electric device with terminal notches includes a main body, a plurality of SMT leads and a plurality of plating layers. Each of the SMT leads is extended from the main body and ended up with a lead end surface furnished with a terminal notch, where the terminal notch has a notch peripheral surface. Each of the plating layers covers at least the notch peripheral surface of the corresponding SMT lead. In addition, a method for manufacturing the same electric device with terminal notches is also provided. | 2021-03-18 |
20210082793 | POWER SEMICONDUCTOR PACKAGE HAVING INTEGRATED INDUCTOR, RESISTOR AND CAPACITOR - A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar. | 2021-03-18 |
20210082794 | MICROELECTRONIC DEVICE WITH FLOATING PADS - A microelectronic device has a first die attached to a first die pad, and a second die attached to a second die pad. A magnetically permeable member is attached to a first coupler pad and a second coupler pad. A coupler component is attached to the magnetically permeable member. The first die pad, the second die pad, the first coupler pad, the second coupler pad, and the magnetically permeable member are electrically conductive. The first coupler pad is electrically isolated from the first die, from the second coupler pad, and from external leads of the microelectronic device. The second coupler pad is electrically isolated from the first die and from the external leads. The first die and the second die are electrically coupled to the coupler component. A package structure contains at least portions of the components of the microelectronic device and extends to the external leads. | 2021-03-18 |
20210082795 | SEMICONDUCTOR DEVICE PACKAGES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device package includes a substrate, a semiconductor device and an encapsulant. The substrate includes a passivation layer, a first conductive layer and a barrier layer. The passivation layer has a substantially vertical sidewall. The first conductive layer is disposed on the passivation layer. The barrier layer is disposed on the passivation layer and the first conductive layer. The barrier layer includes a substantially slant sidewall. | 2021-03-18 |
20210082796 | CIRCUIT BOARD AND SEMICONDUCTOR APPARATUS - The circuit board includes a plurality of bonding pads having a first bonding pad and a second bonding pad configured to supply a ground potential; a first ground wiring connected to the first bonding pad; a second ground wiring connected to the second bonding pad; and a first extension pad connected to the first ground wiring and a second extension pad connected to the second ground wiring, the first extension pad and the and second extension pad being provided in a different area from an area in which the plurality of bonding pads is provided, the first extension pad and the and second extension pad being connectable through a wire. | 2021-03-18 |
20210082797 | SEMICONDUCTOR PACKAGES WITH EMBEDDED INTERCONNECTS - A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than a second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die. | 2021-03-18 |
20210082798 | VARIED BALL BALL-GRID-ARRAY (BGA) PACKAGES - Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition. | 2021-03-18 |
20210082799 | SEMICONDUCTOR DEVICES HAVING IMPROVED ELECTRICAL CHARACTERISTICS AND METHODS OF FABRICATING THE SAME - The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer. | 2021-03-18 |
20210082800 | ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES - Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described. | 2021-03-18 |
20210082801 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure. | 2021-03-18 |
20210082802 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a metal line over a substrate, forming a first dielectric layer surrounding the metal line, selectively forming a dielectric block over the first dielectric layer without forming the dielectric block on the metal line, forming a second dielectric layer over the dielectric block and the metal line, etching the second dielectric layer to form a via hole corresponding to the metal line, and filling the via hole with a conductive material. | 2021-03-18 |
20210082803 | Barrier-Free Interconnect Structure and Manufacturing Method Thereof - Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer. | 2021-03-18 |
20210082804 | Self-Aligned Via Structures and Methods - Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via. | 2021-03-18 |
20210082805 | VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN - An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks. | 2021-03-18 |
20210082806 | Assemblies Comprising Memory Cells and Select Gates - Some embodiments include an assembly having a memory stack which includes dielectric levels and conductive levels. A select gate structure is over the memory stack. A trench extends through the select gate structure. The trench has a first side and an opposing second side, along a cross-section. The trench splits the select gate structure into a first select gate configuration and a second select gate configuration. A void is within the trench and is laterally between the first and second select gate configurations. Channel material pillars extend through the memory stack. Memory cells are along the channel material pillars. | 2021-03-18 |
20210082807 | PLACING TOP VIAS AT LINE ENDS BY SELECTIVE GROWTH OF VIA MASK FROM LINE CUT DIELECTRIC - Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end. | 2021-03-18 |
20210082808 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a substrate, a first conductive layer provided across a first region and a second region of the substrate, a second conductive layer disposed above the first conductive layer to be away from the first conductive layer, the second conductive layer being provided across the first region and the second region, a pillar passing through the first conductive layer and the second conductive layer in a first direction in the second region, the pillar including a semiconductor film, a charge storage film provided between the semiconductor film and the first conductive layer and between the semiconductor film and the second conductive layer, a first insulating layer provided between the first conductive layer and the second conductive layer in the first region, the first insulating layer containing a first insulating material, the first insulating material being silicon oxide, a second insulating layer provided between the first conductive layer and the second conductive layer in the second region, the second insulating layer containing a second insulating material having a higher dielectric constant than a dielectric constant of the silicon oxide, a dividing film configured to divide the first conductive layer, the second conductive layer, and the second insulating layer in a second direction intersecting with the first direction across the first region and the second region, and a third insulating layer provided between the dividing film and the second insulating layer, the third insulating layer containing the first insulating material, the third insulating layer being in contact with the first insulating layer. | 2021-03-18 |
20210082809 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a chip region and a scribe lane region having first edges extending in a first direction and second edges extending in a second direction, a first insulating interlayer structure on the scribe lane region and including a low-k dielectric material, first conductive structures on a portion of the scribe lane region adjacent one of the first edges and each extending through the first insulating interlayer structure in a vertical direction and extending in the first direction, a second insulating interlayer on the first insulating interlayer structure and including a material having a dielectric constant greater than that of the first insulating interlayer structure, first vias each extending in the first direction through the second insulating interlayer to contact one of the first conductive structures, and a first wiring commonly contacting upper surfaces of the first vias. | 2021-03-18 |
20210082810 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE - A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad. | 2021-03-18 |
20210082811 | FABRICATION OF INTEGRATED CIRCUIT INCLUDING PASSIVE ELECTRICAL COMPONENT - A method for fabricating an integrated circuit upon a substrate may include forming a passive electrical component in a non-final layer of the integrated circuit and forming one or more electrical contacts in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical component are positioned in a manner such that an imaginary line perpendicular to and from a surface of the substrate intersects the passive electrical component and the one or more electrical contacts. | 2021-03-18 |
20210082812 | SEMICONDUCTOR DEVICE HAVING FUSE ARRAY AND METHOD OF MAKING THE SAME - A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance. | 2021-03-18 |
20210082813 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device and a manufacturing method thereof are provided. The memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction. | 2021-03-18 |
20210082814 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a first dielectric layer over a substrate, forming a first conductive feature through the first dielectric layer, forming a first blocking layer on the first conductive feature, forming a first etching stop layer over the first dielectric layer and exposing the first blocking layer, removing at least a portion of the first blocking layer, forming a first metal bulk layer over the first etching stop layer and the first conductive feature, and etching the first metal bulk layer to form a second conductive feature electrically connected to the first conductive feature. | 2021-03-18 |
20210082815 | SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT - A semiconductor device includes a substrate, a front side circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface and including a back side power supply wiring coupled to a first potential. The front side circuit includes semiconductor fins and a first front side insulating layer covering bottom portions of the semiconductor fins, a plurality of buried power supply wirings embedded in the first front side insulating layer, the plurality of buried power supply wirings including a first buried power supply wiring and a second buried power supply wiring, and a power switch configured to electrically connect and disconnect the first buried power supply wiring and the second buried power supply wiring. The second buried power supply wiring is connected to the back side power supply wiring by a first through-silicon via passing through the substrate. | 2021-03-18 |
20210082816 | Semiconductor Device and Method of Manufacture - Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad. | 2021-03-18 |
20210082817 | SEMICONDUCTOR STRUCTURE, MEMORY DEVICE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure, a memory device, a semiconductor device and a semiconductor device manufacturing method are provided. The semiconductor structure includes a die, a power bus and a first pad assembly. The power bus is disposed on the die and extends in a predetermined direction. The first pad assembly is arranged on one side of the power bus. The first pad assembly includes at least four pads separated from one another along the predetermined direction by the first, the second and the third gaps. The first gap and the second gap both have a width larger than a width of the third gap and the first pad assembly includes a power pad coupled to the power bus and located between the first gap and the second gap. The power pad and the first and second gaps are all located between opposing ends of the power bus. | 2021-03-18 |
20210082818 | INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES - A semiconductor device comprising a substrate is provided. The device further comprises a through-substrate via (TSV) extending into the substrate, and a substantially helical conductor disposed around the TSV. The substantially helical conductor can be configured to generate a magnetic field in the TSV in response to a current passing through the helical conductor. More than one TSV can be included, and/or more than one substantially helical conductor can be provided. | 2021-03-18 |
20210082819 | PACKAGE STRUCTURE HAVING BRIDGE STRUCTURE FOR CONNECTION BETWEEN SEMICONDUCTOR DIES - A package structure including a first semiconductor die, a second semiconductor die, a molding compound, a bridge structure, through insulator vias, an insulating encapsulant, conductive bumps, a redistribution layer and seed layers is provided. The molding compound encapsulates the first and second semiconductor die. The bridge structure is disposed on the molding compound and electrically connects the first semiconductor die with the second semiconductor die. The insulating encapsulant encapsulates the bridge structure and the through insulator vias. The conductive bumps are electrically connecting the first and second semiconductor dies to the bridge structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the bridge structure. The seed layers are respectively disposed in between the through insulator vias and the redistribution layer. | 2021-03-18 |
20210082820 | Semiconductor Device and Manufacturing Method of Semiconductor Device - A semiconductor device includes: a first semiconductor element having a first electrode on a main surface side thereof and a second electrode on a back surface side thereof; a base material provided with a connection conductor connected to the first electrode; a sealing resin provided on the base material to seal the first semiconductor element; and a first via provided in the sealing resin and electrically connected to the second electrode of the first semiconductor element. | 2021-03-18 |
20210082821 | METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES HAVING RAISED VIA CONTACTS - A method of fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer over a semiconductor substrate and forming first and second via contacts in the first dielectric layer and extending below a bottom surface of the first dielectric layer. The method also includes etching back the first dielectric layer to expose upper portions of the first and second via contacts. The method further includes depositing an etch stop layer conformally on the upper portions of the first and second via contacts and on the first dielectric layer. In addition, the method includes depositing a second dielectric layer on the etch stop layer and forming first and second metal lines in the second dielectric layer to be electrically connected to the first via contact and the second via contact, respectively. | 2021-03-18 |
20210082822 | ORGANIC INTERPOSERS FOR INTEGRATED CIRCUIT PACKAGES - An electronic interposer may be formed comprising an upper section, a lower section and a middle section. The upper section and the lower section may each have between two and four layers, wherein each layer comprises an organic material layer and at least one conductive route comprising at least one conductive trace and at least one conductive via. The middle section may be formed between the upper section and the lower section, wherein the middle section comprises up to eight layers, wherein each layer comprises an organic material and at least one conductive route comprising at least one conductive trace and at least one conductive via, and wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and thinner than a thickness of any of the layers of the lower section. | 2021-03-18 |
20210082823 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad. | 2021-03-18 |
20210082824 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals. | 2021-03-18 |
20210082825 | HIGH-DENSITY INTERCONNECTS FOR INTEGRATED CIRCUIT PACKAGES - An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device. | 2021-03-18 |
20210082826 | SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DIE MOUNT - Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole. | 2021-03-18 |
20210082827 | Semiconductor Device and Method of Manufacture - A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate. | 2021-03-18 |
20210082828 | ELECTRONIC CIRCUIT DEVICE AND METHOD OF MANUFACTURING ELECTRONIC CIRCUIT DEVICE - An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface. | 2021-03-18 |
20210082829 | Graphene Barrier Layer - Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer. | 2021-03-18 |
20210082830 | CRYSTAL GRAINS COPPER COLUMNAR SHAPE PATTERN ELECTRICAL CONNECTED TO A SEMICONDUCTOR DIE - A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has conductive patterns, where each of the conductive patterns includes crystal grains, the crystal grains each are in a column shape and include a plurality of first banded structures having copper atoms oriented on a ( | 2021-03-18 |
20210082831 | ELECTRO-MIGRATION BARRIER FOR INTERCONNECT - The present disclosure relates to an integrated circuit having a conductive interconnect disposed on a dielectric over a substrate. A first liner is arranged along an upper surface of the conductive interconnect. A barrier layer is arranged along a lower surface of the conductive interconnect and contacts an upper surface of the dielectric. The barrier layer and the first liner surround the conductive interconnect. A second liner is located over the first liner and has a lower surface contacting the upper surface of the dielectric. | 2021-03-18 |
20210082832 | Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof - A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature. | 2021-03-18 |
20210082833 | ANTI-ELECTROMAGNETIC INTERFERENCE RADIO FREQUENCY MODULE AND IMPLEMENTATION METHOD THEREFOR - An anti-electromagnetic interference radio frequency module and an implementation method therefor. The anti-electromagnetic interference radio frequency module comprises a radio frequency module body, the inside of the radio frequency module body is provided with an electrical connection area ( | 2021-03-18 |
20210082834 | INTERCONNECT STRUCTURE - An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias. | 2021-03-18 |
20210082835 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR PACKAGING THE SAME - A semiconductor device package and a method for packaging the same are provided. A semiconductor device package includes a carrier, an electronic component, a buffer layer, a reinforced structure, and an encapsulant. The electronic component is disposed over the carrier and has an active area. The buffer layer is disposed on the active area of the electronic component. The reinforced structure is disposed on the buffer layer. The encapsulant encapsulates the carrier, the electronic component and the reinforced structure. | 2021-03-18 |
20210082836 | SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE - A substrate structure includes a chip attach area and an upper side rail surrounding the chip attach area. The upper side rail includes an upper stress relief structure and an upper reinforcing structure. The upper stress relief structure surrounds the upper chip attach area. The upper reinforcing structure surrounds the upper stress relief structure. A stress relieving ability of the upper stress relief structure is greater than a stress relieving ability of the upper reinforcing structure. A structural strength of the upper reinforcing structure is greater than a structural strength of the upper stress relief structure. | 2021-03-18 |
20210082837 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided. | 2021-03-18 |
20210082838 | ELECTRONIC COMPONENT COMPRISING SUBSTRATE WITH THERMAL INDICATOR - An electronic component includes a substrate comprising a die attach region and a perimeter region on a front side of the substrate; and at least one thermal indicator disposed within the perimeter region for monitoring the cumulative heat exposure of the substrate. The thermal indicator signals when the predetermined thermal budget limit that correlates with the decline in the condition of the OSP layer or the degradation of the adhesion of the die attach films is reached. | 2021-03-18 |
20210082839 | METHOD OF MANUFACTURING DIE SEAL RING - A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer. | 2021-03-18 |
20210082840 | FAN-OUT TRANSITION STRUCTURE FOR TRANSMISSION OF mm-WAVE SIGNALS FROM IC TO PCB VIA CHIP-SCALE PACKAGING - The disclosed systems, structures, and methods are directed to a mm-Wave communication structure employing a first transmission structure employing a first ring transition structure followed by a first ground structure and a second ground structure configured to carry a ground signal, a second transmission structure employing a second ring transition structure followed by a third ground structure and a fourth ground structure configured to carry the ground signal, a third transmission structure configured to carry a mm-Wave signal, wherein the third transmission structure begins at the center of the first ring transition structure and the second ring transition structure and the third transmission structure is coplanar with the second transmission structure, and a fourth transmission structure configured to operatively couple an IC and the first transmission layer, the second transmission layer, and the third transmission structure. | 2021-03-18 |
20210082841 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna. | 2021-03-18 |
20210082842 | WIRELESS TRANSMISSION MODULE AND MANUFACTURING METHOD - A wireless transmission module, chips, a passive component, and a coil are integrated into an integral structure, so that an integration level of the wireless transmission module is improved. In addition, the integral structure can effectively implement independence of the module, and the independent module can be flexibly arranged inside structural design of an electronic device, and does not need to be disposed on a mainboard of the electronic device. Only an input terminal of the wireless transmission module needs to be retained on the mainboard of the electronic device. In addition, the integral structure can further effectively increase a capability of a product for working continuously and normally in an extremely harsh scenario, and improve product reliability. In addition, in the structure of the wireless transmission module, the chips and the coil are integrated, and signal transmission paths between the chips and the coil are relatively short. | 2021-03-18 |
20210082843 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first conductive body, a second conductive body positioned separate from the first conductive body, a plurality of liners respectively correspondingly attached to a side surface of the first conductive body and a side surface of the second conductive body, and a first insulating segment positioned between the first conductive body and the second conductive body. | 2021-03-18 |
20210082844 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit (IC) device includes a lower electrode formed on a substrate, and an upper support structure disposed around the lower electrode and supporting the lower electrode. The upper support structure includes an upper support pattern surrounding the lower electrode and extending in a lateral direction parallel to the substrate, the upper support pattern having a hole through which the lower electrode passes, and an upper spacer support pattern between the upper support pattern and the lower electrode inside the hole and having an outer sidewall in contact with the upper support pattern and an inner sidewall in contact with the lower electrode, wherein a width of the upper spacer support pattern in the lateral direction decreases in a direction toward the substrate. To manufacture an IC device, an upper support pattern is formed on a substrate. An upper spacer support film is formed to cover a sidewall and a top surface of the upper support pattern. A plurality of lower electrodes are formed inside a plurality of holes formed in the upper support pattern. Portions of the upper spacer support film are removed to form a plurality of upper spacer support patterns between the upper support pattern and the lower electrodes, respectively. | 2021-03-18 |
20210082845 | Semiconductor Device and Method of Manufacture - A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated. | 2021-03-18 |
20210082846 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, a through substrate via, an insulating layer, a conductive pillar, a dummy conductive pillar, a passivation layer and a bonding pad. The interconnection structure is disposed over the semiconductor substrate. The through substrate via at least partially extends in the semiconductor substrate along a thickness direction of the semiconductor substrate, and electrically connects to the interconnection structure. The insulating layer is disposed over the interconnection structure. The conductive pillar is disposed in the insulating layer, and electrically connected to the through substrate via. The dummy conductive pillar is disposed in the insulating layer, and laterally separated from the conductive pillar. The passivation layer is disposed over the insulating layer. The bonding pad is disposed in the passivation layer, and electrically connected to the conductive pillar. | 2021-03-18 |
20210082847 | DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion. | 2021-03-18 |
20210082848 | Methods and Apparatus for Transmission Lines in Packages - Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes. | 2021-03-18 |
20210082849 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer. | 2021-03-18 |
20210082850 | SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE - A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided. | 2021-03-18 |
20210082851 | INTEGRATED CIRCUITS WITH CONDUCTIVE BUMPS HAVING A PROFILE WITH A WAVE PATTERN - An article of manufacture comprises: an integrated circuit having a contact; a conductive bump electrically coupled to the contact, the conductive bump having a profile with a wave pattern; a lead frame electrically coupled to the conductive bump; and an integrated circuit package mold, the integrated circuit package mold covering portions of the conductive bump and the lead frame. | 2021-03-18 |
20210082852 | COPPERLESS REGIONS TO CONTROL PLATING GROWTH - Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps. | 2021-03-18 |
20210082853 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed. | 2021-03-18 |
20210082854 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip including a conductive pad, an insulating layer provided on the conductive pad, and having an aperture exposing a part of the conductive pad, and a first bump layer provided on the insulating layer and connected to the conductive pad via the aperture, and a second semiconductor chip including an electrode and a second bump layer provided on the electrode. The first bump layer includes a recessed portion provided at the aperture and in contact with the second bump layer, and a raised portion provided adjacent the aperture and in contact with the second bump layer. | 2021-03-18 |
20210082855 | Chip Package Structure with Bump - A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure. | 2021-03-18 |
20210082856 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate. | 2021-03-18 |
20210082857 | Packages with Si-substrate-free Interposer and Method Forming Same - A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding. | 2021-03-18 |
20210082858 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided. | 2021-03-18 |
20210082859 | METHOD AND MATERIAL FOR ATTACHING A CHIP TO A SUBMOUNT - A die attachment material may include an ultra-violet (UV) curable resin and silver particles to attach a chip to a submount, where the silver particles are positioned within the UV curable resin. A method may include heating the die attachment material to obtain the UV curable resin on sintered silver particles, where at least a portion of the die attachment material is position between a chip and a submount. The method may further include irradiating, with UV light, the UV curable resin to obtain a polymer on the sintered silver particles. The polymer may form a layer on the sintered silver particles. | 2021-03-18 |
20210082860 | INTERCONNECT AND TUNING THEREOF - Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two. | 2021-03-18 |
20210082861 | CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT - In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper. | 2021-03-18 |
20210082862 | INTEGRATED DEVICE PACKAGE - A package is disclosed. The package can include a package substrate that has an opening, such as a through hole, extending from a top side to a bottom side opposite the top side of the package substrate. The package can also include a component at least partially disposed in the through hole. The component can be an electrical component. The component can be exposed at a bottom surface of the package. The package can include a bonding material that mechanically couples the component and the package substrate. | 2021-03-18 |
20210082863 | SUBSTRATE BONDING APPARATUS - According to one embodiment, in a substrate bonding apparatus a first chucking stage includes a first stage base, a plurality of first cylindrical members, and a plurality of first drive mechanisms. The first stage base includes a first main face facing a second chucking stage. The plurality of first cylindrical members are disposed on the first main face. The plurality of first cylindrical members are arrayed in planar directions. The plurality of first cylindrical members protrudes from the first main face in a direction toward the second chucking stage to chuck the first substrate. The plurality of first drive mechanisms are configured to drive the plurality of first cylindrical members independently of each other. The substrate bonding apparatus further comprises a first pressure control mechanism configured to control pressure states of spaces in the plurality of first cylindrical members independently of each other. | 2021-03-18 |
20210082864 | SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVING DEVICE - According to one embodiment, there is provided a semiconductor integrated circuit including a first line, a second line, a third line, a fourth line, a latch circuit, a first offset adjustment circuit, and a second offset adjustment circuit. The second line forms a differential pair with the first line. The fourth line forms a differential pair with the third line. The latch circuit has a first input node, a second input node, a first output node, and a second output node. The first input node is electrically connected to the first line. The second input node is electrically connected to the second line. The first output node is electrically connected to the third line. The second output node is electrically connected to the fourth line. The first offset adjustment circuit is electrically connected between the first line and the third line. The second offset adjustment circuit has a circuit configuration equivalent to the first offset adjustment circuit. The second offset adjustment circuit is electrically connected between the second line and the fourth line. | 2021-03-18 |
20210082865 | METHODS FOR REUSING SUBSTRATES DURING MANUFACTURE OF A BONDED ASSEMBLY INCLUDING A LOGIC DIE AND A MEMORY DIE - A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry. Substrates employed to provide the memory die and the support die can be reused by replacing one of the substrates with an alternative low-cost substrate that provides structural support to the bonded assembly. | 2021-03-18 |