11th week of 2016 patent applcation highlights part 59 |
Patent application number | Title | Published |
20160079387 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Disclosed herein is a nonvolatile semiconductor memory device containing a semiconductor layer, a block insulating layer, an organic molecular layer which is formed between the semiconductor layer and the block insulating layer, and a control gate electrode formed on the block insulating layer. The organic molecular layer contains first organic molecules and second organic molecules, such that the first organic molecule has a first alkyl chain or a first alkyl halide chain on the semiconductor layer side and a charge trapping unit on the block insulating layer side, and the second organic molecule has a second alkyl chain or a second alkyl halide chain on the semiconductor layer side and a hydroxy group, an ether group, a carboxyl group or an ester group on the block insulating layer side. | 2016-03-17 |
20160079388 | PRODUCTION OF SPACERS AT FLANKS OF A TRANSISTOR GATE - The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material. | 2016-03-17 |
20160079389 | PREPARATION METHOD OF SEMICONDUCTOR DEVICE - The invention presents a preparation method of semiconductor device, form an amorphous region in the semiconductor substrate, then form the source/drain region of the semiconductor device in the semiconductor substrate, the amorphous region can restrain the generation of end-of-range defects of the source/drain region, then can lower well the current leakage between the semiconductor device source/drain region and the semiconductor substrate; besides, after the dummy gate structure is eliminated, form a short channel inhibition region in the channel region; it can restrain the short-channel effect of the semiconductor device and satisfy the requirement of keeping narrowing the feature size of the device. | 2016-03-17 |
20160079390 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source. | 2016-03-17 |
20160079391 | METHOD OF FABRICATING A VERTICAL MOS TRANSISTOR - The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole. | 2016-03-17 |
20160079392 | Drain Extended CMOS with Counter-Doped Drain Extension - An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region. | 2016-03-17 |
20160079393 | DISPLAY APPARATUS AND MANUFACTURING METHOD OF THE SAME - Provided are a display apparatus and a manufacturing method of the same. The display apparatus includes: a counter substrate, and an active matrix substrate including a pixel area. The active matrix substrate includes, in a non-transmissive region of each pixel, a transparent substrate, a polycrystalline silicon film, a gate insulating film, a gate electrode, an interlayer insulating film, and a drain layer including patterned conductive films, and includes, in a transparent region of each pixel, the transparent substrate, the gate insulating film and the interlayer insulating film. The interlayer insulating film includes zones where the interlayer insulating film is thinner than a part of the interlayer insulating film at the middle of each transmissive region. The zones are each located so as to extend between the neighboring patterned conductive films and are further located so as not to overlap with the transmissive regions and regions laid over LDD portions of the polycrystalline silicon film. | 2016-03-17 |
20160079394 | NANOWIRE STRUCTURE WITH SELECTED STACK REMOVED FOR REDUCED GATE RESISTANCE AND METHOD OF FABRICATING SAME - Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers. | 2016-03-17 |
20160079395 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a preliminary gate insulation layer is formed on a substrate, and at least a portion of the substrate serves as a channel region. A hydrogen plasma treatment is performed on the preliminary gate insulation layer to form a gate insulation layer, and the hydrogen plasma treatment supplying a hydrogen-containing gas and an inert gas supply in a chamber via different gas supply parts to form a hydrogen plasma region and an inert gas plasma region in the chamber, respectively. A gate electrode is formed on the gate insulation layer, and impurity regions are formed at upper portions of the substrate adjacent to the gate electrode. | 2016-03-17 |
20160079396 | METHOD FOR THE SURFACE ETCHING OF A THREE-DIMENSIONAL STRUCTURE - A method for etching a dielectric layer located on the surface of a three-dimensional structure formed on a face of a substrate oriented along a plane of a substrate, which includes a step of implanting ions so as to directionally create a top layer in the dielectric layer. Such top layer is thus not formed everywhere. Then, the layer in question is removed, except on the predefined zones, such as flanks of a transistor gate. A selective etching of the dielectric layer is executed relative to the material of the residual part of the top layer and relative to the material of the face of the substrate. | 2016-03-17 |
20160079397 | PARTIAL FIN ON OXIDE FOR IMPROVED ELECTRICAL ISOLATION OF RAISED ACTIVE REGIONS - A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions. | 2016-03-17 |
20160079398 | SEMICONDUCTOR DEVICE HAVING FIN GATE, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant. | 2016-03-17 |
20160079399 | Semiconductor Device And Manufacturing Method Thereof - Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer. | 2016-03-17 |
20160079400 | A JUNCTION-MODULATED TUNNELING FIELD EFFECT TRANSISTOR AND A FABRICATION METHOD THEREOF - The present invention discloses a junction-modulated tunneling field effect transistor and a fabrication method thereof, belonging to a field of field effect transistor logic device and the circuit in connection with CMOS ultra large scale integrated circuit (ULSI). The PN junction provided by a highly-doped source region surrounding three sides of the vertical channel region of the tunneling field effect transistor can deplete effectively the channel region, so that the energy band of the surface channel under the gate is lifted, therefore the device may obtain a steeper energy band and a narrower tunneling barrier width than the conventional TFET when the band-to-band tunneling occurs, equivalently achieving the effect of a steep doping concentration gradient at the source tunneling junction, and thereby the sub-threshold characteristics are significantly improved while the turn-on current of the device is improved relative to the conventional TFET. Under the conditions that the device of the present invention is compatible with the existing CMOS process, on the one hand an ambipolar effect of the device can be inhibited effectively, while a parasitic tunneling current at a source junction corner in the small size device can be inhibited and thus can equivalently achieve an effect of a steep doping concentration gradient at the source junction. | 2016-03-17 |
20160079401 | SHORT-CIRCUIT PROTECTION CIRCUITS, SYSTEM, AND METHOD - Systems, circuits, and methods for protecting an Insulated-Gate Bipolar Transistor (IGBT) from short-circuit events are provided. A short-circuit protection circuit is described that includes a switch, a resistor, a capacitor, and an optional current buffer that provide a strong pull-down to the IGBT in response to detecting a short-circuit event and then controls a rate at which turn-off current is decreased, thereby minimizing a peak voltage for the IGBT. | 2016-03-17 |
20160079402 | TRENCH INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - A trench insulated gate bipolar transistor includes trenches formed in the front surface of a first conductivity type drift layer, a plurality of gate electrodes selectively provided inside the trenches, insulating blocks formed of an insulator, with which the insides of the trenches are filled, one between adjacent gate electrodes, and a second conductivity type collector region formed on a surface of the first conductivity type drift layer on the opposite side from the trenches. | 2016-03-17 |
20160079403 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a multilayer body, a finger source electrode, a finger drain electrode, a finger gate electrode, an insulating layer, and a source field plate. A finger gate electrode includes a bottom part. The bottom part has a first side surface and a second side surface. A source field plate includes a finger part and an interconnect part. A side surface of the finger part is provided between the second side surface of the finger gate electrode and the finger drain electrode. A source terminal electrode covers the finger source electrode and a tip part of the interconnect part. A side surface of the finger source electrode has an opening recessed from the first side surface. And the tip part is extended to a part of the insulating layer exposed in the opening. | 2016-03-17 |
20160079404 | HETEROJUNCTION FIELD EFFECT TRANSISTOR - A heterojunction field effect transistor includes a first contact portion and a second contact portion. A length of the first contact portion in a longitudinal direction is smaller than a length of source electrodes in the longitudinal direction, and a length of the second contact portion in the longitudinal direction is smaller than a length of drain electrodes in the longitudinal direction. For each drain electrode, a distance from ends of the second contact portion to ends of the drain electrode, the ends being outside of the second contact portion, is greater than a distance from ends of the first contact portion to ends of the source electrode, the ends being outside of the first contact portion. | 2016-03-17 |
20160079405 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a first insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided over the first semiconductor layer, includes a nitride semiconductor, and contains composition different from the composition of the first semiconductor layer. The first insulating film is provided over the second semiconductor layer, covers at least a part of the first electrode, and contains silicon nitride. The hydrogen concentration in the first insulating film is greater than or equal to 5.0×10 | 2016-03-17 |
20160079406 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, source and drain electrodes over the second semiconductor layer, a gate electrode, and a first field plate electrode. The second semiconductor layer includes a first semiconductor portion and a second semiconductor portion thinner than the first semiconductor portion. The source and drain electrodes are electrically connected to the second semiconductor layer. The gate electrode is provided over the second semiconductor layer between the source electrode and the drain electrode. The first field plate electrode is provided over the second semiconductor layer and includes a portion that extends from a location over the gate electrode toward the drain electrode and has an end portion that is positioned over the second semiconductor portion. | 2016-03-17 |
20160079407 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer, a first insulation layer, and a first electrode. The first electrode includes a titanium layer and a titanium nitride layer. The first insulation layer is provided on the first semiconductor layer. The first insulation layer contains silicon nitride. The titanium nitride layer is provided on the first insulation layer. The titanium layer is provided on at least a portion of the titanium nitride layer. | 2016-03-17 |
20160079408 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a silicon substrate, a multi-layered film formed on the silicon substrate, the multi-layered film including a first aluminum nitride containing layer, a second aluminum nitride containing layer, and a film stack having a super lattice structure in which, between the first aluminum nitride containing layer and the second aluminum nitride containing layer, at least two layers selected from a group of layers including an aluminum nitride containing layer, a gallium nitride containing layer and an aluminum gallium nitride containing layer are alternately disposed between the first aluminum nitride containing layer and the second aluminum nitride containing layer, and a first gallium nitride containing layer formed on the multi-layered film. | 2016-03-17 |
20160079409 | SEMICONDUCTOR DEVICE - A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In | 2016-03-17 |
20160079410 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface. | 2016-03-17 |
20160079411 | SEMICONDUCTOR DEVICE - A device that increases a value of current flowing through a whole chip until a p-n diode in a unit cell close to a termination operates and reduces a size of the chip and a cost of the chip resulting from the reduced size. The device includes a second well region located to sandwich the entirety of a plurality of first well regions therein in plan view, a third separation region located to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode provided on the third separation region. | 2016-03-17 |
20160079412 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first-conductive-type first semiconductor layer having a first surface and an opposing second surface. A first-conductive-type second semiconductor layer is on the first surface, and a second-conductive-type third semiconductor layer is on the second semiconductor layer. A first-conductive-type fourth semiconductor layer is on the third semiconductor layer. A first electrode is provided on the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via an insulating film. A second electrode is on the fourth semiconductor layer. A third electrode is separated from the second electrode in a second direction. The third electrode has a width in the second direction, and the width of the third electrode narrows from a first depth to a second depth. An angle of the side surface of the second semiconductor layer is greater than or equal to 90 degrees. | 2016-03-17 |
20160079413 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type between the first electrode and the second electrode, a plurality of second semiconductor regions of a second conductivity type selectively provided between the first semiconductor region and the second electrode, a third semiconductor region of the first conductivity type provided between each of the second semiconductor regions and the second electrode, an insulating film provided on the first semiconductor region in a location between adjacent second semiconductor regions, the second semiconductor regions, and the third semiconductor region; and a third electrode located over the insulating film, wherein a portion of the insulating film and the third electrode extend inwardly of the second semiconductor regions. | 2016-03-17 |
20160079414 | SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON - A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a dielectric disposed on top of the gate electrode, and a doped polysilicon spacer disposed on the source region and along a sidewall of the dielectric. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2016-03-17 |
20160079415 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device includes a gate and a gate dielectric film on a substrate. A first diffusion-layer of a first conductivity-type is in a surface of the substrate. A second diffusion-layer of a second conductivity-type is under the first diffusion-layer and forms a PN-junction with the bottom of the first diffusion-layer. A drain-layer of the first conductivity-type is in the substrate on one side of the gate. A source-layer of the second conductivity-type is provided in the substrate on other side of the gate. A first sidewall is on a side surface of the gate and on a top surface of the first diffusion-layer. A conductive-layer is on the source-layer at a position separated from the first sidewall. A top surface of the substrate in a separation region between the first sidewall and the conductive-layer is at a position equal to or lower than a bottom of the first diffusion-layer. | 2016-03-17 |
20160079416 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes first semiconductor layers and a second semiconductor layer disposed between adjacent first semiconductor layers. The first semiconductor layers have first end surfaces, and the second semiconductor layer has a second end surface between the adjacent first semiconductor layers. The device includes a first electrode facing each first end surface of the adjacent first semiconductor layers via an insulating film, a second electrode in contact with side surfaces of the adjacent first semiconductor layers and the second end surface, a first semiconductor region between the second electrode and the adjacent first semiconductor layers, and a second semiconductor region in the first semiconductor region between the second electrode and each of the adjacent first semiconductor layers. The first semiconductor region and the second semiconductor region face the first electrode via the insulating film, and electrically connected to the second electrode. | 2016-03-17 |
20160079417 | Semiconductor Device and Method of Manufacturing the Same - To satisfy both suppression of rise in contact resistance and improvement of breakdown voltage near the end part of a trench part. The trench part GT is provided between a source offset region and a drain offset region at least in plan view in a semiconductor layer, and is provided in a source-drain direction from the source offset region toward the drain offset region in plan view. A gate insulating film GI covers the side surface and the bottom surface of the trench part GT. A gate electrode is provided in the trench part at least in plan view, and contacts the gate insulating film GI. A contact GC contacts the gate electrode GE. The contact GC is disposed, shifted in a first direction perpendicular to the source-drain direction relative to the centerline in the trench part GT extending in the source-drain direction in plan view, and is provided in the trench part GT in plan view. | 2016-03-17 |
20160079418 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include an ion implantation process of performing ion implantation of an ion species including at least one type of atom of boron, antimony, arsenic, phosphorus, or indium into a semiconductor region at low temperature, and an electrode formation process of forming a source region and a drain region at two mutually-separated locations on the semiconductor region and forming an electrode in a region directly above the semiconductor region between the source region and the drain regions of the two locations with an insulating film interposed between the electrode and the semiconductor region. | 2016-03-17 |
20160079419 | STRAINED SEMICONDUCTOR TRAMPOLINE - A method of forming a strained trampoline including: forming a strain inducing layer on a semiconductor-on-insulator (SOI), the SOI having a semiconductor layer on an insulator layer and the insulator layer is on a handle substrate; forming a opening through the semiconductor layer and the insulator layer using a patterned hardmask; forming a trampoline support in the opening; forming a trench through the strain inducing layer and through the semiconductor layer exposing a portion of the insulator layer, a strained trampoline is a portion of the semiconductor layer with a boundary defined by the trampoline support and the trench; and removing the insulator layer through the trench, where the strained trampoline is supported by the trampoline support. | 2016-03-17 |
20160079420 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; and a stress memorization technology (SMT) sidewall spacer over a sidewall of the gate stack. The gate stack includes a gate dielectric layer over the semiconductor substrate and a gate electrode over the gate dielectric layer. The SMT sidewall spacer provides a stress for a channel region beneath the gate stack. | 2016-03-17 |
20160079421 | FIN FIELD EFFECT TRANSISTOR INCLUDING SELF-ALIGNED RAISED ACTIVE REGIONS - Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity. | 2016-03-17 |
20160079422 | NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF - A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire. | 2016-03-17 |
20160079423 | ENHANCED DISLOCATION STRESS TRANSISTOR - A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation. | 2016-03-17 |
20160079424 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region. | 2016-03-17 |
20160079425 | DEVICE HAVING EPI FILM IN SUBSTRATE TRENCH - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation. | 2016-03-17 |
20160079426 | SEMICONDUCTOR DEVICE - To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×10 | 2016-03-17 |
20160079427 | STRUCTURE AND METHOD FOR SRAM FINFET DEVICE - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer. | 2016-03-17 |
20160079428 | FINFET STRUCTURE AND MANUFACTURE METHOD - A method for forming a FinFET transistor structure includes providing a substrate with a buried oxide layer and a layer of first semiconductor material. One or more fin structures are formed on the first layer of semiconductor material using a hard mask layer. Sidewall spacers are formed on sidewalls of the fin structures and the hard mask layer. An angled oxygen ion implantation is carried out using the hard mask and side walls as the mask. Next, an annealing process is performed to form oxide diffusion regions. Then, the oxide diffusion regions are removed, and the exposed first semiconductor material layer is etched to expose portions of the buried oxide layer. The resulting fin structure has recessed regions formed on the sidewalls, and the fin structure has a bottom portion below the recessed regions that is wider than a top portion. | 2016-03-17 |
20160079429 | TOP GATE TFT WITH POLYMER INTERFACE CONTROL LAYER - A transistor includes a substrate and a polymer layer that is in contact with the substrate. The polymer layer has a first pattern defining a first area. There is an inorganic semiconductor layer over and in contact with the polymer layer that has a second pattern defining a second area. The first area is located within the second area. There is a source electrode in contact with a first portion of the semiconductor layer and a drain electrode in contact with a second portion of the semiconductor layer, and the source electrode and the drain electrode separated by a gap. A gate insulating layer is in contact with the inorganic semiconductor layer in the gap. There is a gate in contact with the gate insulating layer over the gap. | 2016-03-17 |
20160079430 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a transistor containing a semiconductor with low density of defect states, a transistor having a small subthreshold swing value, a transistor having a small short-channel effect, a transistor having normally-off electrical characteristics, a transistor having a low leakage current in an off state, a transistor having excellent electrical characteristics, a transistor having high reliability, or a transistor having excellent frequency characteristics. An insulator is formed, a layer is formed over the insulator, oxygen is added to the insulator through the layer, the layer is removed, an oxide semiconductor is formed over the insulator to which the oxygen is added, and a semiconductor element is formed using the oxide semiconductor. | 2016-03-17 |
20160079431 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer. | 2016-03-17 |
20160079432 | SEMICONDUCTOR DEVICE - To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer is surrounded by an insulating layer including an aluminum oxide film containing excess oxygen. Excess oxygen in the aluminum oxide film is supplied to the oxide semiconductor layer including a channel by heat treatment in a manufacturing process of the semiconductor device. Furthermore, the aluminum oxide film forms a barrier against oxygen and hydrogen. It is thus possible to suppress the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layer including an aluminum oxide film, and the entry of impurities such as hydrogen into the oxide semiconductor layer; as a result, the oxide semiconductor layer can be made highly intrinsic. In addition, gate electrode layers over and under the oxide semiconductor layer control the threshold voltage effectively. | 2016-03-17 |
20160079433 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and has high reliability. To provide a method for manufacturing the semiconductor device. The semiconductor device includes a gate electrode, a gate insulating film formed over the gate electrode, an oxide semiconductor film formed over the gate insulating film, a source electrode and a drain electrode formed over the oxide semiconductor film, and a protective film. The protective film includes a metal oxide film, and the metal oxide film has a film density of higher than or equal to 3.2 g/cm | 2016-03-17 |
20160079434 | SEMICONDUCTOR DEVICE - This semiconductor device comprises: a gate insulating film provided on a surface of a channel layer; a gate electrode provided on an upper surface of the gate insulating film; and a diffusion layer provided in the channel layer. Furthermore, this semiconductor device comprises: a polycrystalline silicon film provided so as to cover a surface of the gate electrode and the diffusion layer; and an inter-layer insulating film provided so as to cover the gate electrode and the polycrystalline silicon film. | 2016-03-17 |
20160079435 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented. | 2016-03-17 |
20160079436 | SEMICONDUCTOR DEVICE - According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction. | 2016-03-17 |
20160079437 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME - This thin film transistor comprises, on a substrate, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and two or more protective films. The oxide semiconductor layer comprises Sn, O and one or more elements selected from the group consisting of In, Ga and Zn. In addition, the two or more protective films are composed of at least a first protective film that is in contact with the oxide semiconductor film, and one or more second protective films other than the first protective film. The first protective film is a SiO | 2016-03-17 |
20160079438 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed. | 2016-03-17 |
20160079439 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer. | 2016-03-17 |
20160079440 | BOTTOM GATE TFT WITH MULTILAYER PASSIVATION - A transistor includes a gate in contact with a substrate. A gate insulating layer is in contact with at least the gate. An inorganic semiconductor layer is in contact with the gate insulating layer. There is a source electrode in contact with a first portion of the inorganic semiconductor layer and a drain electrode in contact with a second portion of the inorganic semiconductor layer, and the source electrode and the drain electrode are separated by a gap. There is a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap. The multilayer structure includes an inorganic dielectric layer having a first pattern defining a first area; and a polymer structure having a second pattern defining a second area. The second area is located within the first area and the polymer structure is in contact with the semiconductor layer in the gap. | 2016-03-17 |
20160079441 | High Frequency Power Diode and Method for Manufacturing the Same - High frequency power diode including a semiconductor wafer having first and second main sides, a first layer of a first conductivity type formed on the first main side, a second layer of a second conductivity type formed on the second main side and a third layer of the second conductivity type formed between the first layer and the second layer. The first layer has a dopant concentration decreasing from 10 | 2016-03-17 |
20160079442 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND PIN DIODE | 2016-03-17 |
20160079443 | JUNCTION BARRIER SCHOTTKY DIODE - A JBS diode includes a silicon substrate, a first P doped region, a metal layer, a second P doped region, and a first N doped region. The silicon substrate includes an upper surface. An NBL is provided in the bottom of the silicon substrate. An N well is provided between the upper surface and the NBL. The first P doped region is arranged in the N well, and extending downward from the upper surface. The metal layer covers the upper surface, and located on a side of the first P doped region. The second P doped region is arranged in the N well, extending downward from the upper surface, and located at the other side of the first P doped region. The first N doped region is arranged in the N well, extending downward from the upper surface, and located at the other side of the first P doped region. | 2016-03-17 |
20160079444 | COMPOUND VARACTOR - Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein. | 2016-03-17 |
20160079445 | CIRCUIT ARRANGEMENT AND METHOD OF FORMING A CIRCUIT ARRANGEMENT - A circuit arrangement may be provided. The circuit arrangement may include a semiconductor substrate including a first surface, a second surface opposite the first surface, and a first doped region of a first conductivity type extending from the first surface into the semiconductor substrate. The circuit arrangement may include at least one capacitor including a first electrode including a doped region of the first conductivity type extending from the second surface into the semiconductor substrate, a dielectric layer formed over the first electrode extending from the second surface away from the semiconductor substrate, and a second electrode formed over the dielectric layer opposite the first electrode. The circuit arrangement may further include at least one semiconductor device monolithically integrated in the semiconductor substrate. The first doped region of the first conductivity type may extend from the first surface into the semiconductor substrate to form an electrically conductive connection with the first electrode. | 2016-03-17 |
20160079446 | PUMPING CAPACITOR - A pumping capacitor is provided. The pumping capacitor includes a substrate, a P-type gate layer on the substrate, and a gate dielectric layer between the substrate and the P-type gate layer. The substrate includes an N-type well region and an N-type doping region in the N-type well region. | 2016-03-17 |
20160079447 | OPTICAL SENSOR ARRANGEMENT AND METHOD FOR GENERATING AN ANALOG OUTPUT SIGNAL - An optical sensor arrangement ( | 2016-03-17 |
20160079448 | ELECTROCOATED PHOTOVOLTAIC MODULES AND METHODS OF MAKING SAME - Photovoltaic modules are disclosed. The photovoltaic module comprises a front transparency, a front contact, a semiconductor, a back contact, an electrocoat, and a back coat. Methods of making photovoltaic modules are also disclosed. | 2016-03-17 |
20160079449 | ANTIREFLECTION SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface. | 2016-03-17 |
20160079450 | FOIL-BASED METALLIZATION OF SOLAR CELLS - Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. In an example, a solar cell includes a substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A conductive contact structure is disposed above the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal seed material regions providing a metal seed material region disposed on each of the alternating N-type and P-type semiconductor regions. A metal foil is disposed on the plurality of metal seed material regions, the metal foil having anodized portions isolating metal regions of the metal foil corresponding to the alternating N-type and P-type semiconductor regions. | 2016-03-17 |
20160079451 | PHOTODIODE STRUCTURES - Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. | 2016-03-17 |
20160079452 | PHOTODETECTOR WITH PLASMONIC STRUCTURE AND METHOD FOR FABRICATING THE SAME - A photodetector with a plasmon structure includes a semiconductor substrate, a plurality of light-receiving elements that are formed in a predetermined pattern, protruding from the semiconductor substrate, and a nanostructure that is placed in contact with a surface of the semiconductor substrate among the light-receiving elements and which induces a plasmon phenomenon thereon. | 2016-03-17 |
20160079453 | THIN REFRACTORY METAL LAYER USED AS CONTACT BARRIER TO IMPROVE THE PERFORMANCE OF THIN-FILM SOLAR CELLS - A thin film amorphous silicon solar cell may have front contact between a hydrogenated amorphous silicon layer and a transparent conductive oxide layer. The cell may include a layer of a refractory metal, chosen among the group composed of molybdenum, tungsten, tantalum and titanium, of thickness adapted to ensure a light transmittance of at least 80%, interposed therebetween, before growing by PECVD a hydrogenated amorphous silicon p-i-n light absorption layer over it. A refractory metal layer of just about 1 nm thickness may effectively shield the oxide from the reactive plasma, thereby preventing a diffused defect when forming the p.i.n. layer that would favor recombination of light-generated charge carriers. | 2016-03-17 |
20160079454 | FORMATION OF A I-III-VI2 SEMICONDUCTOR LAYER BY HEAT TREATMENT AND CHALCOGENIZATION OF AN I-III METALLIC PRECURSOR - A process for forming a semiconductor layer, especially with a view to photovoltaic applications, and more particularly to a process for forming a semiconductor layer of I-III-VI | 2016-03-17 |
20160079455 | STAINLESS STEEL SUBSTRATE FOR SOLAR CELL HAVING SUPERIOR INSULATING PROPERTIES AND LOW THERMAL EXPANSION COEFFICIENT AND METHOD OF PRODUCING THE SAME - Provided is a stainless steel substrate for a solar cell, the stainless steel substrate including, by mass %, Cr: 9% to 25%, C: 0.03% or less, Mn: 2% or less, P: 0.05% or less, S: 0.01% or less, N: 0.03% or less, Al: 0.005% to 5.0%, Si: 0.05% to 4.0%, and a remainder including Fe and unavoidable impurities, in which an oxide film containing (i) Al | 2016-03-17 |
20160079456 | REDUCED LIGHT DEGRADATION DUE TO LOW POWER DEPOSITION OF BUFFER LAYER - Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a work function that falls substantially in a middle of a barrier formed between the transparent electrode and the p-type layer to provide a greater resistance to light induced degradation. An intrinsic layer and an n-type layer are formed over the p-type layer. | 2016-03-17 |
20160079457 | THIN FILM SOLAR CELL MODULE INCLUDING SERIES CONNECTED CELLS FORMED ON A FLEXIBLE SUBSTRATE BY USING LITHOGRAPHY - Solar thin film modules are provided with reduced lateral dimensions of isolation trenches and contact trenches, which provide for a series connection of the individual solar cells. To this end lithography and etch techniques are applied to pattern the individual material layers, thereby reducing parasitic shunt leakages compared to conventional laser scribing techniques. In particular, there may be series connected solar cells formed on a flexible substrate material that are highly efficient in indoor applications. | 2016-03-17 |
20160079458 | SOLAR BATTERY RECTANGULAR CONDUCTOR, METHOD FOR FABRICATING SAME AND SOLAR BATTERY LEAD WIRE - A rectangular conductor for a solar battery and a lead wire for a solar battery, in which warping or damaging of a silicon crystal wafer is hard to occur at the time of bonding a connection lead wire even when a silicon crystal wafer is configured to have a thin sheet structure, can be provided. A conductor | 2016-03-17 |
20160079459 | SOLAR CELL MODULE - A solar cell module is provided with: a wiring material which electrically connects the light receiving surface-side electrode of the first solar cell with the rear surface-side electrode of the second solar cell; a first resin adhesive layer disposed between the wiring material and the light receiving surface-side electrode; and a second resin adhesive layer which is disposed between the wiring material and the rear surface-side electrode, and which has a smaller surface area than the first resin adhesive layer. | 2016-03-17 |
20160079460 | MANUFACTURING PROCESS OF A HYBRID SOLAR PANEL - The invention relates to a hybrid solar panel comprising: photovoltaic elements having a front face and a rear face; a heat exchanger arranged opposite the rear face of said photovoltaic elements; and a cooling fluid circulating in said exchanger in such a way as to cool the photovoltaic elements, said exchanger comprising a heat exchange region through which said fluid flows, arranged beneath said photovoltaic elements, said exchange region comprising elements that enable the flow of the fluid to be disrupted in such a way as to stimulate the heat exchanges in the exchange region. The invention is characterised in that said exchange region is formed by a lower exchange plate designed in such a way as to form built-in obstruction elements extending over the entire thickness of the strand of cooling fluid flowing through the exchange region, and in that the upper end of the obstruction elements is in contact with the rear face of the photovoltaic elements in such a way that said photovoltaic elements are cooled mainly at these contact points. | 2016-03-17 |
20160079461 | SOLAR GENERATOR WITH FOCUSING OPTICS INCLUDING TOROIDAL ARC LENSES - We disclose here a new type of solar generator using an optical concentrator in which sunlight is concentrated successively in each of two dimensions. Sunlight is first reflected toward a linear focus by a large, deeply-curved, cylindrical trough reflector of parabolic shape. Before the reflected light comes to the focus, it passes through smaller, regularly spaced toroidal arc lenses which further concentrate it in the orthogonal direction. The lenses have the two-dimensional cross section of a convex lens, extended into a toroid by rotation about an axis parallel to the line focus. The toroidal arc lenses operate to efficiently focus at very high-concentration converging rays that are incident from a wide range of directions, from the deeply curved primary reflector. The foci formed by the toroidal arc lenses are formed at regular intervals, spaced along a line parallel to and close to the primary linear trough focus. The concentrated sunlight at these foci is converted into electricity preferably by multi junction photovoltaic cells of very high efficiency, configured in short, parallel-connected linear arrays. In one embodiment, tolerance to off-axis pointing and uniformity of illumination is improved with an additional refractive element in the form of a rod lens, introduced close to and parallel to each cell array, so as to image the outline of the toroidal arc lenses onto the cells. | 2016-03-17 |
20160079462 | PACKAGE STRUCTURE OF SOLAR PHOTOVOLTAIC MODULE - A package structure of solar photovoltaic module is provided. The package structure of solar photovoltaic module includes a transparent substrate, a backsheet disposed opposite to the transparent substrate, a plurality of solar cells between the transparent substrate and the backsheet, several encapsulants sandwiched in between the transparent substrate and the backsheet, and an optical board, wherein the encapsulants encapsulate the solar cells. The optical board is adhered to an outer surface of the backsheet, wherein the optical board has an embossing surface, and the embossing surface is a serrated surface, and a vertex angle of the serrated surface is larger than 60° and less than 150°. | 2016-03-17 |
20160079463 | INTERDIGITATED BACK CONTACT HETEROJUNCTION PHOTOVOLTAIC DEVICE - A photovoltaic device includes a crystalline substrate having a first dopant conductivity, an interdigitated back contact and a front surface field structure. The front surface field structure includes a crystalline layer formed on the substrate and a noncrystalline layer formed on the crystalline layer. The crystalline layer and the noncrystalline layer are doped with dopants having a same dopant conductivity as the substrate. Methods are also disclosed. | 2016-03-17 |
20160079464 | PHOTODETECTOR - According to a photodetector includes a first light detection layer and a reflective layer. The first light detection layer has a first surface and a second surface on a side opposite to the first surface. The first light detection layer includes a first light detection area including a p-n junction of a p-type semiconductor layer containing Si and an n-type semiconductor layer containing Si. The reflective layer arranged on a second surface side of the first light detection layer so as to be opposed to the first light detection area. The reflective layer reflects at least part of light in a near-infrared range. | 2016-03-17 |
20160079465 | PHOTO CELL DEVICES FOR PHASE-SENSITIVE DETECTION OF LIGHT SIGNALS - Embodiments relate to photo cell devices. In one embodiment, a trench-based photo cells provides very fast capture of photo-generated charge carriers, particularly when compared with conventional approaches, as the trenches of the photo cells create depleted regions deep within the bulk of the substrate that avoid the time-consuming diffusion of carriers. | 2016-03-17 |
20160079466 | SOLAR CELL AND SOLAR-CELL MODULE - A solar cell wherein: an emitter layer is formed on a light-receiving-surface side of a crystalline silicon substrate, with a dopant of the opposite conductivity type from the silicon substrate added to said emitter layer; a passivation film is formed on the surface of the silicon substrate; and an extraction electrode and a collector electrode are formed. Said extraction electrode extracts photogenerated charge from the silicon substrate, and said collector electrode contacts the extraction electrode at least partially and collects the charge collected at the extraction electrode. The extraction electrode contains a first electrode that consists of a sintered conductive paste containing a dopant that makes silicon conductive. Said first electrode, at least, is formed so as to pass through the abovementioned passivation layer. The collection electrode contains a second electrode that has a higher conductivity than the aforementioned first electrode. This invention reduces contact-resistance losses between the silicon and the electrodes, resistance losses due to electrode resistance, and optical and electrical losses in the emitter layer, thereby greatly improving the characteristics of the solar cell. | 2016-03-17 |
20160079467 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR - The present invention provides a Group III nitride semiconductor light-emitting device in which the production method is simplified while migration of at least one of Ag atoms and Al atoms is suppressed, and a production method therefor. The production method comprises steps of forming a first electrode, forming a second electrode, and forming a second electrode side barrier metal layer on the second electrode. Moreover, the second electrode has an electrode layer containing at least one of Ag and Al. In forming the first electrode and the second electrode side barrier metal layer, the second electrode side barrier metal layer is formed on the second electrode while the first electrode to be electrically connected to the first semiconductor layer is formed. The first electrode and the second electrode side barrier metal layer are deposited are deposited in the same layered structure. | 2016-03-17 |
20160079468 | METHOD FOR PRODUCING OPTOELECTRONIC SEMICONDUCTOR CHIPS - The method is designed for producing optoelectronic semiconductor chips and comprises the steps:
| 2016-03-17 |
20160079469 | LIGHT EMITTING DIODE CHIP AND METHOD OF MANUFACTURING SAME - A light emitting diode (LED) chip includes a first semiconductor layer, a first light emitting layer formed on the first semiconductor layer, a second light emitting layer formed on the first light emitting layer, and a second semiconductor layer formed on the second light emitting layer. The first light emitting layer emits light having a first color. The second light emitting layer emits light having a second color different from the first color. | 2016-03-17 |
20160079470 | OPTOELECTRONIC GAN-BASED COMPONENT HAVING INCREASED ESD RESISTANCE VIA A SUPERLATTICE AND METHOD FOR THE PRODUCTION THEREOF - An optoelectronic component includes a semiconductor layer structure having a quantum film structure, and a p-doped layer arranged above the quantum film structure, wherein the p-doped layer includes at least one first partial layer and a second partial layer, and the second partial layer has a higher degree of doping than the first partial layer. | 2016-03-17 |
20160079471 | UV LIGHT EMITTING DEVICES AND SYSTEMS AND METHODS FOR PRODUCTION - A method of fabricating an ultraviolet (UV) light emitting device includes receiving a UV transmissive substrate, forming a first UV transmissive layer comprising aluminum nitride upon the UV transmissive substrate using a first deposition technique at a temperature less than about 800 degrees Celsius or greater than about 1200 degrees Celsius, forming a second UV transmissive layer comprising aluminum nitride upon the first UV transmissive layer comprising aluminum nitride using a second deposition technique that is different from the first deposition technique, at a temperature within a range of about 800 degrees Celsius to about 1200 degrees Celsius, forming an n-type layer comprising aluminum gallium nitride layer upon the second UV transmissive layer, forming one or more quantum well structures comprising aluminum gallium nitride upon the n-type layer, and forming a p-type nitride layer upon the one or more quantum well structures. | 2016-03-17 |
20160079472 | SEMICONDUCTOR DEVICES AND RELATED METHODS - Semiconductor devices and related methods are disclosed. In one aspect, a semiconductor device includes a substrate and an active area disposed over the substrate. The active area includes at least one or more corner region having a non-orthogonal angled edge. A method of providing a semiconductor device is also provided. The method includes providing a substrate and fabricating an active area over the substrate. The active area includes at least one or more corner region with a non-orthogonal angled edge. LED chips and methods herein have a reduced sensitivity to corner cracking, fracturing, or chipping. | 2016-03-17 |
20160079473 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A semiconductor light emitting element includes a first layer, a second layer, an intermediate layer, and a third layer. The first layer has a first surface having roughness including concave portions of which side surfaces are inclined and a second surface on an opposite side to the first surface. The first layer includes a first conductive-type first semiconductor layer. The second layer includes a second conductive-type second semiconductor layer. The intermediate layer is provided between the second surface and the second layer. The third layer is provided in the concave portions. | 2016-03-17 |
20160079474 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - This invention relates to a semiconductor light emitting device which has superior lateral light extraction efficiency, and to a method of manufacturing the same. The semiconductor light emitting device includes a sapphire substrate and a light emitting structure formed on an upper surface of the sapphire substrate and including a plurality of nitride epitaxial layers including an active layer which produces light, wherein at least one side surface of the light emitting structure is formed as an inclined surface which creates an acute angle relative to the upper surface of the sapphire substrate. In some embodiments, at least one modification region can be formed in a horizontal direction on at least one side surface of the sapphire substrate using laser irradiation. | 2016-03-17 |
20160079475 | LIGHT-EMITTING DEVICE - A light-emitting device of an embodiment of the present disclosure comprises a substrate; a semiconductor stack comprising a first type semiconductor layer, a second type semiconductor layer and an active layer formed between the first type semiconductor layer and the second type semiconductor layer, wherein the first type semiconductor layer comprises a non-planar roughened surface; a bonding layer formed between the substrate and the semiconductor stack; and multiple recesses each comprising a bottom surface lower than the non-planar roughened surface; and multiple buried electrodes physically buried in the first type semiconductor layer, wherein the multiple buried electrodes are formed in the multiple recesses respectively, and one of the multiple buried electrodes comprises an upper surface higher than the non-planar roughened surface of the first type semiconductor layer. | 2016-03-17 |
20160079476 | SEMICONDUCTOR COMPONENT COMPRISING AN INTERLAYER - An optoelectronic semiconductor component includes a layer sequence including a p-doped layer, an n-doped layer and an active zone that generates electromagnetic radiation arranged between the n-doped layer and the p-doped layer, wherein the n-doped layer includes at least GaN, an interlayer is arranged in the n-doped layer, wherein the interlayer includes Al | 2016-03-17 |
20160079477 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element is provided. The semiconductor light-emitting element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer, wherein the light emitting layer has a light-emitting surface facing the second semiconductor layer. The semiconductor light-emitting element further includes a first electrode pad; and a first wiring connected to the first electrode pad. The first wiring has a length and a width each substantially parallel to the light-emitting surface. The length is greater than the width, and the width changes between a first portion and a second portion. The first portion is closer to the first electrode pad than the second portion is to the first electrode pad. | 2016-03-17 |
20160079478 | SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE - A semiconductor light emitting device package may include: a package body having first and second electrode structures; and a light emitting diode chip mounted on the second electrode structure of the package body, the light emitting diode chip including: a support substrate, a light emitting structure including a second conductivity type semiconductor layer, an active layer and a first conductivity type semiconductor layer sequentially stacked on the support substrate, a transparent electrode layer disposed on the first conductivity type semiconductor layer, and an insulating layer disposed on at least a side surface of the light emitting structure. The transparent electrode layer and the first electrode structure may be connected to each other by a side electrode disposed on a side surface of the light emitting diode chip. | 2016-03-17 |
20160079479 | LIGHT-EMITTING DEVICE - A light-emitting device according to an aspect of the present disclosure includes a light transmissive first electrode layer, a light transmissive second electrode layer, an electroluminescent layer between the first electrode layer and the second electrode layer, and a reflective layer located on a side opposite to the electroluminescent layer with respect to the second electrode layer. The reflective layer includes a base material having a refractive index equal to or higher than a refractive index of the electroluminescent layer, and fillers each having a refractive index different from that of the base material. | 2016-03-17 |
20160079480 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device includes a first layer having a first surface and an opposing second surface. The first surface has a roughness including a bottom portion and a top portion. A light emitting layer is provided between the second surface and a second layer. An insulating layer is provided on the first surface. The insulating layer includes a first portion adjacent to the bottom portion and a second portion adjacent to the top portion along the first direction. The first portion has a thickness that is greater than a thickness of the second portion. | 2016-03-17 |
20160079481 | LIGHT EMITTING DEVICE - This disclosure discloses a light-emitting chip comprises: a light-emitting stack, having a side wall, comprising an active layer emitting light; and a light-absorbing layer having a first portion surrounding the side wall and being configured to absorb 50% light toward the light-absorbing layer. | 2016-03-17 |
20160079482 | VERTICAL STRUCTURE LEDS - A vertical structure light-emitting device includes a conductive support, a light-emitting semiconductor structure disposed on the conductive support structure, the semiconductor structure having a first semiconductor surface, a side semiconductor surface and a second semiconductor surface, a first electrode electrically connected to the first-type semiconductor layer, a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has a first electrode surface, a side electrode surface and a second electrode surface, wherein the first electrode surface, relative to the second electrode surface, is proximate to the semiconductor structure; and wherein the second electrode surface is opposite to the first electrode surface, and a passivation layer disposed on the side semiconductor surface and the second semiconductor surface. | 2016-03-17 |
20160079483 | LIGHT-EMITTING UNIT AND SEMICONDUCTOR LIGHT-EMITTING DEVICE - A light-emitting unit is provided including a mounting substrate and a semiconductor light-emitting device. The mounting substrate includes a first pad, a second pad, and one or more third pads provided between the first pad and the second pad. The semiconductor light-emitting device includes a plurality of light-emitting elements having a first light-emitting element and a second light-emitting element separated in a first direction. Each light-emitting element includes a first external terminal and a second external terminal separated in the first direction. A first external terminal of the first light-emitting element is bonded to the first pad. A second external terminal of the first light-emitting element and a first external terminal of the second light-emitting element are each bonded to one of the one or more third pads. A second external terminal of the second light-emitting element is bonded to the second pad. | 2016-03-17 |
20160079484 | LIGHT EMITTING DEVICE INCLUDING LIGHT EMITTING ELEMENT WITH PHOSPHOR - A light emitting device includes a light emitting element, a molded member, and a sealing member. The light emitting element is arranged on or above the molded member. The sealing member covers the light emitting element. The sealing member contains a phosphor, and a filler material. The phosphor can be excited by light of the light emitting element, and emit luminescent radiation. The filler material contains neodymium hydroxide, neodymium aluminate or neodymium silicate. The filler material absorbs a part of the spectrum of the mixed light of the light emitting element and the phosphor so that the other parts of the spectrum of this mixed light are extracted from the light emitting device. | 2016-03-17 |
20160079485 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, a semiconductor light-emitting device includes a light-emitting element including a light-emitting layer; a first transparent body provided on the light-emitting element; a phosphor scattered in the first transparent body and emitting a light of a different wavelength from a radiated light of the light-emitting layer; and a second transparent body including a first transparent portion and a second transparent portion. The first transparent portion is surrounded by the first transparent body in an area on the light-emitting element. The second transparent portion is provided on the first transparent body and the first transparent portion. The second transparent portion includes an inclined portion provided on the first transparent portion. The inclined portion is inclined with respect to a first direction orthogonal to the light-emitting layer. | 2016-03-17 |
20160079486 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting element whose upper surface is a light extraction surface, and a light-transmissive member that has an upper surface and a lower surface, and covers the light extraction surface of the light emitting element. The light-transmissive member contains a phosphor. The upper surface and the lower surface of the light-transmissive member are both flat surfaces and parallel to each other. A side surface of the light-transmissive member has a protruding portion that protrudes to the side and has contact with the lower surface. | 2016-03-17 |