11th week of 2016 patent applcation highlights part 57 |
Patent application number | Title | Published |
20160079187 | METHODS TO CONTROL WAFER WARPAGE UPON COMPRESSION MOLDING THEREOF AND ARTICLES USEFUL THEREFOR - Provided herein are multilayer structures having a reduced propensity to warp upon curing of certain components thereof. In one aspect, there are provided multilayer assemblies comprising a plurality of the above-described multilayer structures. In another aspect, there are provided methods for reducing wafer warpage upon cure of molding compositions applied thereto. In yet another aspect, there are provided methods for preparing wafers having substantially no warpage upon cure thereof. | 2016-03-17 |
20160079188 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND MOUNTING METHOD OF SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film. | 2016-03-17 |
20160079189 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape. | 2016-03-17 |
20160079190 | Package with UBM and Methods of Forming - Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer. | 2016-03-17 |
20160079191 | PACKAGE WITH UBM AND METHODS OF FORMING - Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. | 2016-03-17 |
20160079192 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 2016-03-17 |
20160079193 | USE OF ELECTROLYTIC PLATING TO CONTROL SOLDER WETTING - A method including forming a copper pillar, electroplating a metal layer on a top surface and a sidewall of the copper pillar, and electroplating a metal cap above the top surface of the copper pillar in direct contact with the metal layer. The method further including forming an intermetallic by heating the metal layer and the copper pillar in a non-reducing environment, the intermetallic including elements of both the copper pillar and the metal layer, where molten solder will wet to the metal cap and will not wet to the intermetallic. | 2016-03-17 |
20160079194 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps. | 2016-03-17 |
20160079195 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first substrate and a second substrate facing the first substrate, each substrate having conductive pads disposed thereon, an insulating adhesive layer sealing the space between the first substrate and the second substrate, and a plurality of bumps penetrating the insulating adhesive layer and electrically connecting the plurality of first conductive pads and the plurality of second conductive pads. The plurality of bumps include at least a first bump having a first height and a second bump that is provided in a position closer to a geometric center of the second substrate than the first bump and has a second height greater than the first height. | 2016-03-17 |
20160079196 | HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE - Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads. | 2016-03-17 |
20160079197 | SEMICONDUCTOR DEVICE HAVING A DIE AND THROUGH-SUBSTRATE VIA - Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die. | 2016-03-17 |
20160079198 | WIRE BONDING DEVICE AND METHOD OF ELIMINATING DEFECTIVE BONDING WIRE - A method of eliminating a defective bonding wire is provided, including moving a bonding member from a first region of a carrier to a second region of the carrier if the bonding wire of the bonding member is defective, and cooperatively operating a movement member and the bonding member so as to cause the defective bonding wire to be removed from the bonding member and bonded to the second region of the carrier, thereby auto-debugging the bonding member and improving the production efficiency. | 2016-03-17 |
20160079199 | APPARATUS FOR BONDING SEMICONDUCTOR CHIPS - A semiconductor chip bonding apparatus includes a bonding head to adsorptively pick up a semiconductor chip, a bonding stage supporting a substrate, the semiconductor chip to be bonded to the substrate on the bonding stage, a first camera to capture an image of the semiconductor chip and to obtain positional information regarding the semiconductor chip, a second camera to capture an image of the substrate and to obtain positional information regarding the substrate, a correction device structure at a first side surface of the bonding stage, the correction device structure including a correction substrate and at least one correction chip, and a bonding controller to control pick up of the at least one correction chip by the bonding head, mounting of the at least one correction chip on the correction substrate, and correcting of a bonding position. | 2016-03-17 |
20160079200 | APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing apparatus of a semiconductor device includes a stage, a head unit configured to face the stage, a driving unit configured to move the head unit towards and away from the stage, a heating unit configured to heat the head unit, and a control unit configured to control the driving unit to move the head unit away from the stage when the heating unit heats the head unit. | 2016-03-17 |
20160079201 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, for example formed utilizing component stacking. As non-limiting examples, various aspects of this disclosure provide a method for reducing warpage and/or stress in stacked semiconductor devices. | 2016-03-17 |
20160079202 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. | 2016-03-17 |
20160079203 | WAFER PROCESS FOR MOLDED CHIP SCALE PACKAGE (MCSP) WITH THICK BACKSIDE METALLIZATION - A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer at a bottom surface of the wafer in the recessed space; cutting off an edge portion of the wafer; flipping and mounting the wafer on a substrate; depositing a metal layer covering the metal seed layer; removing the substrate from the wafer; and separating individual chips from the wafer by cutting through the first packaging layer, the wafer, the metal seed layers and the metal layers along the scribe lines. | 2016-03-17 |
20160079204 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness. | 2016-03-17 |
20160079205 | SEMICONDUCTOR PACKAGE ASSEMBLY - The invention provides a semiconductor package, a semiconductor package assembly and a method for fabricating a semiconductor package. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. Conductive pillar structures are disposed on a surface of the first RDL structure away from the first semiconductor die, wherein the conductive pillar structures are coupled to the first RDL structure. | 2016-03-17 |
20160079206 | SEMICONDUCTOR PACKAGE, PACKAGE-ON-PACKAGE DEVICE INCLUDING THE SAME, AND MOBILE DEVICE INCLUDING THE SAME - A semiconductor package includes a substrate; a first semiconductor chip arranged on the substrate; a second semiconductor chip arranged on the first semiconductor chip; a lead attached to the second semiconductor chip on a side of the second semiconductor chip opposite a side of the second semiconductor chip facing the first semiconductor chip; and a molding member covering an upper surface of the substrate and side surfaces of the lead and sealing the first semiconductor chip and the second semiconductor chip. | 2016-03-17 |
20160079207 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - [Problem] To provide a semiconductor device suitable for use as an upper-side package of a semiconductor device having a PoP structure. [Solution] This invention is provided with a semiconductor chip ( | 2016-03-17 |
20160079208 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip. | 2016-03-17 |
20160079209 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE DEVICE - Disclosed herein is a semiconductor device including: a first substrate provided with a first surface layer including a first electrode; an expanded second substrate provided with a second surface layer including a second electrode and directly bonded to the first substrate so that the second surface layer contacts with the first surface layer; and a through electrode running through the first or second substrate. The second surface layer is provided over an expanded second principal surface defined by a second substrate and a resin portion. The second substrate has a smaller planar size than the first substrate. The first and second electrodes are connected together and in contact with each other. | 2016-03-17 |
20160079210 | SEMICONDUCTOR PACKAGES INCLUDING THROUGH ELECTRODES AND METHODS OF MANUFACTURING THE SAME - A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided. | 2016-03-17 |
20160079211 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE - A method for manufacturing a light-emitting device of the present invention includes a step in which solid-state sealing resin ( | 2016-03-17 |
20160079212 | STRESS RELIEF FOR ARRAY-BASED ELECTRONIC DEVICES - In accordance with certain embodiments, an electric device includes a flexible substrate having first and second conductive traces on a first surface thereof and separated by a gap therebetween, an electronic component spanning the gap, and a stiffener configured to substantially prevent flexing of the substrate proximate the gap during flexing of the substrate. | 2016-03-17 |
20160079213 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package including a first printed circuit board and a second printed circuit board is provided. The first printed circuit board may include a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached. The first printed circuit board may further include at least one thermal via and a heat sink and the at least one thermal via and the heat sink may be disposed under the first semiconductor chip with the heat sink being disposed between the first surface and the second surface. The second printed circuit board may include a third surface upon which a second semiconductor chip is mounted. The second printed circuit board may be disposed under the first printed circuit board with the at least one connecting structure connecting the first printed circuit board to the second printed circuit board. | 2016-03-17 |
20160079214 | BVA INTERPOSER - A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds. | 2016-03-17 |
20160079215 | BATCH PROCESS FABRICATION OF PACKAGE-ON-PACKAGE MICROELECTRONIC ASSEMBLIES - A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies. | 2016-03-17 |
20160079216 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including a first semiconductor chip and a second semiconductor chip. The second semiconductor chip is mounted on a back surface of the first semiconductor chip. The first semiconductor chip includes a substrate, a back surface wiring, a multi-layer wiring, a through silicon via, and a front surface electrode. The back surface wiring is arranged on a back surface of the substrate. The back surface wiring is electrically connected to a terminal of the second semiconductor chip. The multi-layer wiring is arranged on a front surface of the substrate. The through silicon via is configured to electrically connect the back surface wiring and the multi-layer wiring through the substrate. The front surface electrode is arranged on the multi-layer wiring and electrically connected to the multi-layer wiring. | 2016-03-17 |
20160079217 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LEAD FRAME - According to one embodiment, a semiconductor light emitting device includes a lead frame; a chip mounted on the lead frame, the chip including a substrate and a light emitting element provided on the substrate; a wall section including an inner wall facing to a side portion of the chip, and an outer wall on an opposite side to the inner wall; and a phosphor layer provided on at least the chip. A distance between the side portion of the chip and the inner wall of the wall section is smaller than a thickness of the chip. An angle between an upper surface of the lead frame and the inner wall is smaller than an angle between the upper surface of the lead frame and the outer wall. | 2016-03-17 |
20160079218 | ELECTROSTATIC PROTECTION DEVICE AND LIGHT-EMITTING MODULE - An electrostatic protection device includes a base member formed of a high-resistance semiconductor material. External connecting lands are formed on a first principal surface of the base member along a first direction with a space therebetween. A diode section is formed in the first principal surface of the base member through a semiconductor forming process. The diode section is formed between formation regions of the external connecting lands along the first direction. A high concentration region is a region that has the same polarity as the base member and contains larger amounts of impurities than the base member. The high concentration region is formed in a ring shape enclosing the diode section in a plan view of the base member. | 2016-03-17 |
20160079219 | SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including an interposer, a logic chip, a memory chip, and a package substrate. In the interposer, first via is configured to electrically connect a signal terminal of the logic chip and a signal terminal of the memory chip to each other through a substrate. Multi-layer wiring is disposed on first principal surface side of the substrate. Power supply terminal of the logic chip is electrically connected to the multi-layer wiring. Power supply pad is disposed on the first principal surface side of the substrate and configured to be electrically connected to the power supply terminal of the logic chip through the multi-layer wiring. A metal wire is connected to power supply pad. The package substrate includes a power supply wiring. The power supply pad and the power supply wiring are electrically connected to each other through the metal wire. | 2016-03-17 |
20160079220 | SEMICONDUCTOR PACKAGE ASSEMBLY - The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die. | 2016-03-17 |
20160079221 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included. | 2016-03-17 |
20160079222 | SEMICONDUCTOR DEVICE HAVING TERMINALS FORMED ON A CHIP PACKAGE INCLUDING A PLURALITY OF SEMICONDUCTOR CHIPS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a chip package including plurality of stacked semiconductor chips, a sealing layer covering at least an upper surface of the chip package, a plurality of first conductive elements disposed on the chip package and exposed on an upper surface of the sealing layer, and a plurality of second conductive elements, each being disposed on one of the exposed surfaces of the first conductive elements. | 2016-03-17 |
20160079223 | SEMICONDUCTOR POWER MODULES AND DEVICES - An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion. | 2016-03-17 |
20160079224 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal. | 2016-03-17 |
20160079225 | ELECTROSTATIC PROTECTION CIRCUIT AND INTEGRATED CIRCUIT - An electrostatic protection circuit includes a first transistor connected to an external terminal, a second transistor that is connected in series to the first transistor and that is in a normally OFF state. The electrostatic protection circuit includes a third transistor that is connected between a power source line and a gate of the first transistor, and a fourth transistor that is connected between the power source line and the gate of the first transistor in the opposite direction to the third transistor. | 2016-03-17 |
20160079226 | ELECTRONIC DEVICE INCLUDING A DIODE - An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein. | 2016-03-17 |
20160079227 | ESD PROTECTION CIRCUIT WITH PLURAL AVALANCHE DIODES - An electrostatic discharge (ESD) protection circuit ( | 2016-03-17 |
20160079228 | ESD PROTECTION CIRCUIT WITH PLURAL AVALANCHE DIODES - An electrostatic discharge (ESD) protection circuit (FIG. | 2016-03-17 |
20160079229 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second transistor on a second side of the STI region. The first transistor includes a first conductive portion having a second conductivity type formed within a well having a first conductivity type, a first nanowire connected to the first conductive portion and a first active area, and a first gate surrounding the first nanowire. The second transistor includes a second conductive portion having the second conductivity type formed within the well, a second nanowire connected to the second conductive portion and a second active area, and a second gate surrounding the second nanowire. Excess current from an ESD event travels through the first conductive portion through the well to the second conductive portion bypassing the first nanowire and the second nanowire. | 2016-03-17 |
20160079230 | FAST AND STABLE ULTRA LOW DROP-OUT (LDO) VOLTAGE CLAMP DEVICE - In one general aspect, an apparatus can include a junction-less, gate-controlled voltage clamp device having a gate terminal coupled to a voltage reference device. | 2016-03-17 |
20160079231 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region. | 2016-03-17 |
20160079232 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a first semiconductor layer of a first dopant type on the first electrode. A first region of the semiconductor device includes a second semiconductor layer of the second dopant type on the first semiconductor layer, a third semiconductor layer of the first dopant type on the second semiconductor layer, and a second electrode extending though the second and third semiconductor layers and inwardly of the first semiconductor layer. A second region of the semiconductor device includes an insulating layer over the first semiconductor layer, a fourth semiconductor layer of the first or second dopant type on the insulating layer, a fifth semiconductor layer of a different dopant type on the insulating layer and surrounding the fourth semiconductor layer, and a sixth semiconductor layer of the same dopant type on the insulation layer and surrounding the fifth semiconductor layer. | 2016-03-17 |
20160079233 | III-V SEMICONDUCTOR MATERIAL BASED AC SWITCH - A power circuit is described that includes a semiconductor die and a coupling structure. The semiconductor die includes a common substrate and a III-V semiconductor layer formed atop the common substrate. At least one bidirectional switch device is formed at least partially within the III-V semiconductor layer. The at least one bidirectional switch has at least a first load terminal and a second load terminal. The coupling structure is configured to dynamically couple the common substrate of the semiconductor die to a lowest potential out of a first potential of the first load terminal and a second potential of the second load terminal. | 2016-03-17 |
20160079234 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated from the first well; a Schottky barrier diode formed in the first well; and a PN junction diode formed in the second well, with an impurity concentration of the PN junction thereof set higher than an impurity concentration of the Schottky junction of the Schottky barrier diode, and being connected antiparallel with the Schottky barrier diode. | 2016-03-17 |
20160079235 | SEMICONDUCTOR DEVICE - A semiconductor device includes first electrode, first semiconductor layer of first conductivity type on the first electrode, second semiconductor layer of second conductivity type on the first semiconductor layer, third semiconductor layer of the first conductivity type on second semiconductor layer, fourth semiconductor layer of the second conductivity type selectively located on the third semiconductor layer, gate electrode through the third and fourth semiconductor layers and into the second semiconductor layer and insulated therefrom, second electrode on the fourth semiconductor layer, fifth semiconductor layer of the second conductivity type between the first electrode and the second semiconductor layer, sixth semiconductor layer of the first conductivity type on the second semiconductor layer contacting the second electrode, and seventh semiconductor layer of the first conductivity type in the second and sixth semiconductor layers, such that the bottom thereof is closer to the first electrode than the bottom of the gate insulating film. | 2016-03-17 |
20160079236 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the first conductivity type provided on the third semiconductor region and the fourth semiconductor region, and a sixth semiconductor region of the second conductivity type. The third semiconductor region is provided on the first semiconductor region and has a dopant concentration that is lower than a dopant concentration of the first semiconductor region. The fourth semiconductor region is provided on the second semiconductor region adjacent to the third semiconductor region. A dopant contained in the fourth semiconductor region extends to a level that is deeper than a level of a dopant contained in the third semiconductor region. | 2016-03-17 |
20160079237 | High Voltage Semiconductor Power Switching Device - A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected together serving as the collector terminal. The base of the first high voltage bipolar transistor serves as the base terminal. The emitter of the first high voltage bipolar transistor connects to the base of the second high voltage bipolar transistor (inner base), and the emitter of the second high voltage bipolar transistor serves as the emitter terminal. A diode has its anode connected to the inner base (emitter of the first high voltage bipolar transistor, or base of the second high voltage bipolar transistor), and its cathode connected to the base terminal. Similarly, a three terminal hybrid MOSFET/bipolar high voltage switching device can be formed by replacing the first high voltage bipolar transistor of the previous switching device by a high voltage MOSFET. | 2016-03-17 |
20160079238 | Semiconductor Device with Field Electrode Structures, Gate Structures and Auxiliary Diode Structures - A semiconductor device includes field electrode structures extending in a direction vertical to a first surface in a semiconductor body. Cell mesas are formed from portions of the semiconductor body between the field electrode structures and include body zones that form first pn junctions with a drift zone. Gate structures between the field electrode structures control a current flow through the body zones. Auxiliary diode structures with a forward voltage lower than the first pn junctions are electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas. | 2016-03-17 |
20160079239 | SERIES-CONNECTED TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other. | 2016-03-17 |
20160079240 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, an isolation region, a first electrode, a second electrode, and a third electrode. The plurality of second semiconductor regions is selectively provided on the first semiconductor region. The second semiconductor region has a first conductivity type. The plurality of third semiconductor regions is selectively provided on the first semiconductor region. Each of the third semiconductor regions is adjacent to each of the second semiconductor regions. The third semiconductor region has a second conductivity type. The isolation region is provided in the first semiconductor region. The isolation region is positioned between the adjacent second semiconductor regions and the adjacent third semiconductor regions. The first electrode is connected to the second semiconductor region and the third semiconductor region which are adjacent to the isolation region. | 2016-03-17 |
20160079241 | INTEGRATED CIRCUIT DEVICE INCLUDING BLOCKING INSULATING LAYER - An integrated circuit device includes an active area, a gate line extending in a direction across the active area and having a gate uppermost surface of a first level, a source/drain regions, an inter-gate insulating film covering opposite sidewalls of the gate line, a blocking insulating film comprising a first part covering the gate uppermost surface and a second part covering the inter-gate insulating film at a level different from the first level, and a contact plug penetrating the blocking insulating film and the inter-gate insulating film and connected to the source/drain regions. | 2016-03-17 |
20160079242 | PATTERNING MULTIPLE, DENSE FEATURES IN A SEMICONDUCTOR DEVICE USING A MEMORIZATION LAYER - Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures. | 2016-03-17 |
20160079243 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern along side and bottom surfaces of the trench, forming a second metal gate film on the first metal gate film pattern and the insulation film, and forming a second metal gate film pattern positioned on the first metal gate film pattern by removing the second metal gate film to expose at least a portion of the insulation film and forming a blocking layer pattern on the second metal gate film pattern by oxidizing an exposed surface of the second metal gate film pattern. | 2016-03-17 |
20160079244 | MONOLITHIC BI-DIRECTIONAL CURRENT CONDUCTING DEVICE AND METHOD OF MAKING THE SAME - A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor. | 2016-03-17 |
20160079245 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10 | 2016-03-17 |
20160079246 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a device isolation trench; forming a device isolation layer defining active regions by sequentially stacking a first insulating layer, a second insulating layer, and a third insulating layer on an inner surface of the device isolation trench; forming word lines buried in the substrate of the first region, the word lines extending in a first direction to intersect the active region of the first region, the word lines being spaced apart from each other; forming a first mask layer covering the word lines on the substrate of the first region, the first mask layer exposing the substrate of the second region; forming a channel layer on the substrate of the second region; and forming a gate electrode on the channel layer. | 2016-03-17 |
20160079247 | Semiconductor Device - A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer. | 2016-03-17 |
20160079248 | METHOD AND STRUCTURE FOR PREVENTING EPI MERGING IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY - After forming a plurality of first semiconductor fins having a first spacing in a logic device region and a plurality of second semiconductor fins having a second spacing in a memory device region, sacrificial spacers are formed on sidewalls of the plurality of the first semiconductor fins and the plurality of the second semiconductor fins to completely fill spaces between the plurality of first semiconductor fins, but only partially fill spaces between second semiconductor fins. Next, dielectric barrier layer portions are formed in gaps between the sacrificial spacers. After removal of the sacrificial spacers, an entirety of the plurality of first semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layers, while each of the plurality of second semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layer portions. | 2016-03-17 |
20160079249 | PITCH-HALVING INTEGRATED CIRCUIT PROCESS - A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns. | 2016-03-17 |
20160079250 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer. | 2016-03-17 |
20160079251 | SINGLE-POLY NONVOLATILE MEMORY CELL - A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer. | 2016-03-17 |
20160079252 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor pillar extending in a first direction, a first insulating film, a second insulating film, a third insulating film, a first portion of a first electrode provided to be in contact with an outer surface of the first insulating film, a second portion of the first electrode provided to be in contact with an outer surface of the first insulating film, a third portion of the first electrode provided to be in contact with the first insulating film, a forth insulating film provided on an outer surface of the first electrode, and a second electrode provided on an outer surface of the forth insulating film. An outer diameter of the first portion is larger than an outer diameter of the third portion. | 2016-03-17 |
20160079253 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars. | 2016-03-17 |
20160079254 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and a charge storage film. The stacked body includes a plurality of electrode layers crosswise extending in a first direction and second direction crossing the first direction, the plurality of electrode layers separately stacked each other in a third direction crossing the first direction and second direction. The semiconductor body extends in the third direction and provided in the stacked body. The charge storage film is provided between the semiconductor body and the plurality of electrode layers. | 2016-03-17 |
20160079255 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FORMANUFACTURING SAME - According to one embodiment, a stacked body includes electrode layers and first insulating layers alternately stacked. An isolation region extends in the stacked body, the isolation region dividing the stacked body into first regions. First semiconductor members extend in one of the first regions in a stacked direction of the stacked body. A memory film is provided between one of the first semiconductor members and one of the electrode layers. A insulating region extends in the one of the first regions in the stacked direction. A composition of a second region of the one of the electrode layers is different from a composition of a third region of the one of the electrode layers. The second region is in contact with the insulating region, the third region being in contact with the isolation region. | 2016-03-17 |
20160079256 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate and a multilayer body provided on the substrate. The multilayer body has electrode films and insulating films. The electrode films contain silicon, the insulating films contain silicon oxide. Each of the electrode films and each of the insulating films are alternately stacked. A hole is formed in the multilayer body, and the hole vertically extends in the multilayer body. The electrode films include a first electrode film and a second electrode film located below the first electrode film. Carbon concentration of the first electrode film is higher than carbon concentration of the second electrode film. | 2016-03-17 |
20160079257 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded. | 2016-03-17 |
20160079258 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing. | 2016-03-17 |
20160079259 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory cell array and a peripheral circuit. The peripheral circuit is connected to the memory cell array through conductive lines and includes transistors. Each of the transistors is formed on the substrate and includes first and second regions and a gate electrode. In at least one of the transistors, the first region is connected to at least one of the conductive lines through first contact plugs extending in the direction perpendicular to the substrate, and second contact plugs extending in the direction perpendicular to the substrate. A contact area of each of the first contact plugs is different from a contact area of each of the second contact plugs. | 2016-03-17 |
20160079260 | Methods of Fabricating Semiconductor Devices - A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed. | 2016-03-17 |
20160079261 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers respectively provided between the plurality of electrode layers; a columnar part penetrating through the stacked body and extending in stacking direction of the stacked body; a conductive film provided on the columnar part and containing a metal; and a contact part provided on the conductive film and being in contact with the conductive film. The columnar part includes a channel body extending in the stacking direction; a charge accumulation film provided between the channel body and each of the electrode layers; and a semiconductor film provided below the conductive film, being in contact with the channel body and the conductive film, and having a higher impurity concentration than the channel body. | 2016-03-17 |
20160079262 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a conductive layer; a stacked body provided on the conductive layer and including a plurality of electrode layers separately stacked each other; a semiconductor body provided in the stacked body and extending in a stacking direction in the stacking body and including a lower end portion provided in the conductive layer; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. As viewed in the stacking direction, a maximum width of the lower end portion is larger than a maximum width of the semiconductor body provided inside a bottom surface of the charge storage film. | 2016-03-17 |
20160079263 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member. | 2016-03-17 |
20160079264 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a stacked body including electrode layers and first insulating layers; first semiconductor members extending in the stacked body; a second semiconductor member including first portions and a second portion, the second semiconductor member being connected commonly to lower ends of the first semiconductor members; a memory film provided between a first electrode layer of the first electrode layers and one of the first semiconductor members; and an insulating film provided between the second semiconductor member and the stacked body. A second electrode layer of the electrode layers is provided on the second portion of the second semiconductor member via the insulating film. A third electrode layer of the electrode layers is provided under the second portion of the second semiconductor member via the insulating film. One of the first insulating layers is provided between the second electrode layer and the third electrode layer. | 2016-03-17 |
20160079265 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - This nonvolatile semiconductor memory device includes a semiconductor substrate and a first semiconductor layer formed on a surface of the semiconductor substrate. A memory cell array is formed by coupling a plurality of memory cells in series, and includes a memory string formed to extend in a first direction vertical to the surface of the semiconductor substrate. A contact extends in a direction vertical to the semiconductor substrate, and has one end coupled to the first semiconductor layer. The contact includes: a second semiconductor layer that is formed in the first semiconductor layer and has a higher impurity concentration than that of the first semiconductor layer; a silicide film that has one end coupled to the second semiconductor layer and extends in the first direction; and a metal film formed on an inner wall of the silicide film. | 2016-03-17 |
20160079266 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body, a selection gate electrode, a semiconductor pillar, a first insulating member, a second insulating member, a third insulating member. The stacked body is provided on the substrate. The selection gate electrode is provided on the stacked body. The first insulating member divides the stacked body in a first direction. The second insulating member is provided in an area directly above the first insulating member and dividing the selection gate electrode in the first direction. The third insulating member is provided in a region other than the area directly above the first insulating member and dividing the selection gate electrode in the first direction. An average width of the second insulating member in the first direction is larger than an average width of the third insulating member in the first direction. | 2016-03-17 |
20160079267 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a first layer; a stacked body provided above the first layer and including a plurality of electrode layers separately stacked each other; a second layer provided between the first layer and the stacked body; an intermediate layer provided between the first layer and the second layer; a semiconductor body provided in the stacked body, the second layer, the intermediate layer and the first layer, the semiconductor body extending in a stacking direction of the stacked body; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The semiconductor body includes a side surface connected with the intermediate layer in the vicinity of a boundary between the first layer and the second layer. At least one of the first layer and the second layer has conductivity and is connected with the intermediate layer. | 2016-03-17 |
20160079268 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . . . an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction perpendicular to a surface of a semiconductor substrate, where n is a natural number, an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction, a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges, and a area provided in the oxide semiconductor layer. | 2016-03-17 |
20160079269 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer. | 2016-03-17 |
20160079270 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - An integrated circuit device according to one embodiment includes a plurality of first electrode films stacked spaced from each other, a plurality of second electrode films stacked spaced from each other on the plurality of first electrode films and extending in one direction, a semiconductor pillar penetrating the first electrode films and the second electrode films, a memory film provided between the first electrode films and the semiconductor pillar and capable of storing charge, a gate insulating film provided between the second electrode films and the semiconductor pillar, and a spacer film electrically connecting width-direction edges of the plurality of second electrode films to each other. | 2016-03-17 |
20160079271 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film comprises a first insulating film having SiO | 2016-03-17 |
20160079272 | DOUBLE-SOURCE SEMICONDUCTOR DEVICE - A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The semiconductor device may include first channel layers passing through the first stacked structure and the first insulating layer. The semiconductor device may include a second source layer including a first region interposed between the first source layer and the first insulating layer and a second region interposed between the first channel layers and the first insulating layer. | 2016-03-17 |
20160079273 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a plurality of pillar columns, each of the plurality of pillar columns including a plurality of pillars arranged in one direction to be offset from each other, wherein an mth pillar and an (m+1)th pillar, among the plurality of pillars included in each pillar column, are aligned with each other (m is an integer of 0 or more). | 2016-03-17 |
20160079274 | Transistors, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string. | 2016-03-17 |
20160079275 | THREE-DIMENSIONAL (3D) SEMICONDUCTOR DEVICE - A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions. | 2016-03-17 |
20160079276 | Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same - A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration. | 2016-03-17 |
20160079277 | FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS - A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage. | 2016-03-17 |
20160079278 | METHOD FOR FABRICATING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE - A method for fabricating an array substrate, an array substrate and a display device are provided. The method for fabricating the array substrate includes: forming a spacer layer on the array substrate, the spacer layer is disposed under a planarized layer and corresponds to a location of a via hole in the planarized layer, wherein the planarized layer is formed of a hot melt material. | 2016-03-17 |
20160079279 | LIQUID CRYSTAL DISPLAY AND ELEMENT SUBSTRATE THEREOF - An element substrate is provided, including a substrate, a metal layer, a planarization layer and a first conductive layer. The metal layer is disposed on the substrate. The planarization layer is located on the metal layer, wherein the planarization layer includes a contact hole, the contact hole has a continuous wall and a bottom, the bottom exposes the metal layer, and the bottom of the contact hole has a first width. The first conductive layer is located on the planarization layer, wherein the first conductive layer includes an opening, the opening exposes the contact hole, and the opening has a second width above the contact hole, wherein the relationship of the first width and the second width is modified to decrease illumination loss and to prevent problems of shot-circuiting and insufficient capacitance. | 2016-03-17 |
20160079280 | DISPLAY APPARATUS - A display apparatus including a display area on a substrate, the display area including at least a display device; and a non-display area adjacent to the display area, wherein the non-display area includes a pull-in area, the pull-in area includes a wiring unit that includes a plurality of wires electrically connected to the display device of the display area, and a conductive pattern unit that is electrically connected to the display device and that includes at least one area separated from and overlapping the wiring unit, and the plurality of wires of the wiring unit are not arranged in parallel such that respective angles between an edge of the display area and at least two of the plurality of wires are different. | 2016-03-17 |
20160079281 | Flexible Display With Bent Edge Regions - An electronic device may have a flexible display with portions that are bent along a bend axis. The display may have display circuitry such as an array of display pixels in an active area. Contact pads may be formed in an inactive area of the display. Signal lines may couple the display pixels to the contact pads. The signal lines may overlap the bend axis in the inactive area of the display. During fabrication, an etch stop may be formed on the display that overlaps the bend axis. The etch stop may prevent over etching of dielectric such as a buffer layer on a polymer flexible display substrate. A layer of polymer that serves as a neutral stress plane adjustment layer may be formed over the signal lines in the inactive area of the display. Upon bending, the neutral stress plane adjustment layer helps prevent stress in the signal lines. | 2016-03-17 |
20160079282 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH AN ISOLATION REGION AND A DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures | 2016-03-17 |
20160079283 | SEMICONDUCTOR DEVICE AND PEELING OFF METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer | 2016-03-17 |
20160079284 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND FRABRICATING METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY - A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided. | 2016-03-17 |
20160079285 | DOUBLE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A double thin film transistor includes a first semiconductor layer, a gate, a second semiconductor layer, a first insulating layer, a second insulating layer, a first source, a first drain, a second source and a second drain. The first semiconductor layer is disposed over a substrate. The gate is disposed over the first semiconductor layer. The second semiconductor layer is disposed over the gate, and the first and second semiconductor layers are the same conductive type. The first insulating layer is disposed between the first semiconductor layer and the gate. The second insulating layer is disposed between the gate and the second semiconductor layer. The first source and the first drain are disposed between the substrate and the second insulating layer. The second source and the second drain are disposed over the second insulating layer. | 2016-03-17 |
20160079286 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - A thin-film transistor (TFT) array substrate including at least one TFT, the at least one TFT including a semiconductor layer including a source region and a drain region having a first doping concentration on a substrate, a channel region between the source and drain regions and having a second doping concentration, the second doping concentration being lower than the first doping concentration, and a non-doping region extending from the source and drain regions; a gate insulating layer on the semiconductor layer; a gate electrode on the gate insulating layer and at least partially overlapping the channel region; and a source electrode and a drain electrode insulated from the gate electrode and electrically connected to the source region and the drain region, respectively. | 2016-03-17 |