11th week of 2012 patent applcation highlights part 16 |
Patent application number | Title | Published |
20120061752 | SINGLE TRANSISTOR FLOATING-BODY DRAM DEVICES HAVING VERTICAL CHANNEL TRANSISTOR STRUCTURES - Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided. | 2012-03-15 |
20120061753 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a drain layer; a drift layer provided on the drain layer; a base region provided on the drift layer; a source region selectively provided on a surface of the base region; a first gate; a field-plate; a second gate; a drain electrode; and a source electrode. The first gate electrode is provided in each of a plurality of first trenches via a first insulating film. The first trenches penetrate from a surface of the source region through the base region and contact the drift layer. The field-plate electrode is provided in the first trench under the first gate electrode via a second insulating film. The second gate electrode is provided in a second trench via a third insulating film. The second trench penetrates from the surface of the source region through the base region and contacts the drift layer between the first trenches. | 2012-03-15 |
20120061754 | SUPER-JUNCTION TRENCH MOSFET WITH RESURF STEPPED OXIDES AND SPLIT GATE ELECTRODES - A super-junction trench MOSFET with Resurf Stepped Oxide and split gate electrodes is disclosed. The inventive structure can apply additional freedom for better optimization of device performance and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. Furthermore, the fabrication method can be implemented more reliably with lower cost. | 2012-03-15 |
20120061755 | Checkerboarded high-voltage vertical transistor layout - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 2012-03-15 |
20120061756 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a channel formation region of first conductivity type, a first offset region of second conductivity type, a first insulating region, a first liner layer, a first semiconductor region of second conductivity type, a second semiconductor region of second conductivity type, a gate insulating film, and a gate electrode. The first liner layer is provided between the first offset region and the first insulating region. The first semiconductor region of second conductivity type is provided on the side opposite to the channel formation region sandwiching the first insulating region therebetween and having impurity concentration higher than that of the first offset region. The second semiconductor region of second conductivity type is provided on the side opposite to the first semiconductor region sandwiching the channel formation region therebetween and having impurity concentration higher than that of the first offset region. | 2012-03-15 |
20120061757 | SEMICONDUCTOR DEVICE - An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate. | 2012-03-15 |
20120061758 | SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD - A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type. | 2012-03-15 |
20120061759 | Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same - A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided. | 2012-03-15 |
20120061760 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises including a insulating pattern and a silicon film over a SOI substrate, thereby increasing a reduced volume of a floating body after forming a floating body fin transistor so as to secure a data storage space. The method comprises: forming a insulating pattern and a first silicon film over an upper silicon film of a SOI substrate; and forming a fin structure in the first silicon film. | 2012-03-15 |
20120061761 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES - Logic transistors (MOSFETs, MISFETs) in core portions of integrated circuits can be microminiaturized by scaling operating voltage as their generation advances. However, since transistors (MOSFETs, MISFETs) in high-breakdown voltage portions operate on relatively high power supply voltage, it is difficult to reduce their size. Similarly, electrostatic discharge (ESD) protection circuits in power supply cells protect the elements in a semiconductor integrated circuit against static electricity (foreign surge); therefore, they are indispensably required to be high in breakdown voltage and call for a large area for dissipating electric charges. To microminiaturize integrated circuits, therefore, a transistor structure that enables microminiaturization is indispensable. To solve the above problem, a semiconductor integrated circuit device having in its ESD protection circuit portion a CMIS inverter made up of a pair of MISFETs having a source/drain asymmetric structure and including a halo region only on the source side is provided. | 2012-03-15 |
20120061762 | Asymmetric FinFET devices - Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin. | 2012-03-15 |
20120061763 | METHODS OF FORMING NON-VOLATILE MEMORY DEVICES INCLUDING LOW-K DIELECTRIC GAPS IN SUBSTRATES AND DEVICES SO FORMED - A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer. | 2012-03-15 |
20120061764 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas. | 2012-03-15 |
20120061765 | ANTI-FUSE BASED PROGRAMMABLE SERIAL NUMBER GENERATOR - An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage. | 2012-03-15 |
20120061766 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In the device, first and second transistors have first and second gates and first and second source/drain regions, respectively. First and second contacts are electrically connected to the first and the second source/drain regions, respectively. A width of a first bottom surface if the first contacts in a gate width direction of the first-gate is wider than a width of the first bottom in a gate length direction of the first-gate. Widths of a second bottom surface of the second-contact are narrower than the longitudinal direction width of the first bottom. The high-concentration region is formed between the first source/drain regions and the first-contact. Extending widths of an outline of the high-concentration region extending from an outline of the first bottom in the longitudinal direction is larger than extending widths of an outline of the high-concentration region extending from an outline thereof in the short direction. | 2012-03-15 |
20120061767 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor. | 2012-03-15 |
20120061768 | POWER AMPLIFIER - According to an embodiment, a power amplifier is provided with at least one first growth ring gate structure and multiple second growth ring gate structures. The first growth ring gate structure is bounded by a semiconductor layer and performs a power amplification operation. The multiple second growth ring gate structures are bounded by the semiconductor layer and are arranged adjacently around the first growth ring gate structure in a surrounding manner. When the first growth ring gate structure performs a power amplification operation, the multiple second growth ring gate structures are depleted by applying a reverse bias to the multiple second growth ring gate structures whereby the depleted multiple second growth ring gate structures isolate the first growth ring gate structure from a surrounding portion. | 2012-03-15 |
20120061769 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - For constituting a pre-metal interlayer insulating film, such a method is considered as forming a CVD silicon oxide-based insulating film having good filling properties by ozone TEOS, reflowing the film to planarize it, stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and further planarizing by CMP. However, in forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects. In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, a plasma TEOS film is formed over the remaining ozone TEOS film, and the plasma TEOS film is planarized by CMP. | 2012-03-15 |
20120061770 | Nonvolatile Memory Device and Method of Manufacturing the Same - A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed. | 2012-03-15 |
20120061771 | MOSFET LAYOUT AND STRUCTURE - A MOSFET layout is disclosed. The MOSFET comprises a drain region, a gate region, a source region and a body region. The gate region is disposed outside the drain region and adjacent to the drain region. The source region has a plurality of source sections, which are disposed outside of the gate region and adjacent to the gate region. Each of two adjacent source sections has a source blank zone there between. The body region has at least two body portions, which are disposed at the source blank zones and adjacent to the gate region. | 2012-03-15 |
20120061772 | Transistor having replacement metal gate and process for fabricating the same - A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor. | 2012-03-15 |
20120061773 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×10 | 2012-03-15 |
20120061774 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape. | 2012-03-15 |
20120061775 | DEVICE FOR USE AS DUAL-SIDED SENSOR PACKAGE - A sensor package, and in one embodiment a sensor package for surface mount applications, that comprises a leadframe with an upper and lower surface for receiving a device thereon. Embodiments of the sensor package comprise a first device secured to the upper surface, and a second device secured to the lower surface so as to place connective pads from each of the first device and the second device proximate to one side of the leadframe. The sensor package further comprises a lead that is positioned in the sensor package in a manner that prevents electrical connection with circuitry that is external of the housing. The lead has an end proximate the side of the lead frame where the connective pads are positioned on the upper and lower surfaces. The end configured to receive connections, e.g., wirebonds, from the connective pads in a manner connecting the first device and the second device independent of any external connections of the sensor package. | 2012-03-15 |
20120061776 | WAFER LEVEL PACKAGING - A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer. | 2012-03-15 |
20120061777 | INTEGRALLY FABRICATED MICROMACHINE AND LOGIC ELEMENTS - Embodiments relate to micromachine structures. In one embodiment, a micromachine structure includes a first electrode, a second electrode, and a sensing element. The sensing element is mechanically movable and is disposed intermediate the first and second electrodes and adapted to oscillate between the first and second electrodes. Further, the sensing element includes a FinFET structure having a height and a width, the height being greater than the width. | 2012-03-15 |
20120061778 | Method and Apparatus for Producing Chip Devices, and Chip Device Produced by Means of the Method - A chip device is produced providing at least one wafer having a plurality of chip components. The wafer or wafers are separated into the individual chip components and/or into groups of chip components. The individual chip components and/or the groups of chip components are applied to a carrier element, in such a way that interspaces having a predetermined width are formed between the individual chip components and/or the groups of chip components. A polymer is introduced into the interspaces in order to form a composite element composed of the chip components and a polymer matrix. The composite element is separated in such a way that chip devices composed of in each case one of the chip components and at least one section of the polymer matrix are formed. The invention furthermore relates to a chip device produced by means of the method. | 2012-03-15 |
20120061779 | MEMORY ELEMENT AND MEMORY - There is provided a memory element including a magnetic layer that includes at least one kind of element selected from a group consisting of Fe, Co, and Ni, and carbon, has a content of carbon that is equal to or greater than 3 atomic % and less than 70 atomic % with respect to a total content of Fe, Co, and Ni, and has magnetic anisotropy in a direction perpendicular to a film face; and an oxide layer that is formed of an oxide having a sodium chloride structure or a spinel structure and that comes into contact with the magnetic layer. | 2012-03-15 |
20120061780 | STORAGE ELEMENT AND MEMORY DEVICE - Disclosed herein is a storage element, including: a storage layer which has magnetization vertical to a film surface and in which a direction of the magnetization is changed in correspondence to information; a magnetization fixing layer which has magnetization vertical to a film surface becoming a reference of the information stored in the storage layer, which is composed of plural magnetic layers, and which has a multilayered ferri-pin structure into which the plural magnetic layers are laminated one upon another through a non-magnetic layer(s); and an insulating layer made of a non-magnetic material and provided between the storage layer and the magnetization fixing layer. | 2012-03-15 |
20120061781 | MEMORY ELEMENT AND MEMORY - There is provided a memory element including a magnetic layer that includes Fe | 2012-03-15 |
20120061782 | SPIN WAVE DEVICE - A spin wave device comprises a metal layer, a pinned layer, a nonmagnetic layer, a free layer, an antiferromagnetic layer, a first electrode, a first insulator layer, and a second electrode. The pinned layer has a magnetization whose direction is fixed. The free layer has a magnetization whose direction is variable. | 2012-03-15 |
20120061783 | MEMORY CELL WITH RADIAL BARRIER - Magnetic tunnel junction cells and methods of making magnetic tunnel junction cells that include a radially protective layer extending proximate at least the ferromagnetic free layer of the cell. The radially protective layer can be specifically chosen in thickness, deposition method, material composition, and/or extent along the cell layers to enhance the effective magnetic properties of the free layer, including the effective coercivity, effective magnetic anisotropy, effective dispersion in magnetic moment, or effective spin polarization. | 2012-03-15 |
20120061784 | MAGNETIC RECORDING DEVICE AND MAGNETIC RECORDING APPARATUS - An example magnetic recording device includes a laminated body. The laminated body includes a first ferromagnetic layer with a magnetization substantially fixed in a first direction; a second ferromagnetic layer with a variable magnetization direction; a first nonmagnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic layer; a third ferromagnetic layer with a variable magnetization direction; and a fourth ferromagnetic layer with a magnetization substantially fixed in a second direction, wherein at least one of the first and second direction is generally perpendicular to the film plane. The magnetization direction of the second ferromagnetic layer is determinable in response to the orientation of a current, by passing the current in a direction generally perpendicular to the film plane of the layers of the laminated body and the magnetization of the third ferromagnetic layer is able to undergo precession by passing the current. | 2012-03-15 |
20120061785 | SEMICONDUCTOR LIGHT DETECTING ELEMENT AND MANUFACTURING METHOD THEREFOR - A photodiode PD | 2012-03-15 |
20120061786 | ISOLATED BOND PAD WITH CONDUCTIVE VIA INTERCONNECT - An integrated circuit for use, for example, in a backside illuminated imager device includes circuitry provided on a first side of a substrate, a first conductive pad connected to the circuitry and spaced from the first side of the substrate, a second conductive pad spaced from a second side of the substrate, an electrically conductive interconnect formed through the substrate to interconnect the first and second conductive pads, and a dielectric surrounding the second conductive pad and at least a portion of the interconnect. Methods of forming the integrated circuit are also described. | 2012-03-15 |
20120061787 | LIQUID ELECTRICAL INTERCONNECT AND DEVICES USING SAME - Various embodiments include interconnects for semiconductor structures that can include a first conductive structure, a second conductive structure and a non-hardening liquid conductive material in contact with the first and second structure. Other embodiments include semiconductor components and imager devices using the interconnects. Further embodiments include methods of forming a semiconductor structure and focusing methods for an imager device. | 2012-03-15 |
20120061788 | PHOTODIODES WITH PN-JUNCTION ON BOTH FRONT AND BACK SIDES - The present invention is directed toward a dual junction photodiode semiconductor device. The photodiode has a semiconductor substrate of a first conductivity type, a first impurity region of a second conductivity type shallowly diffused on the front side of the semiconductor substrate, a second impurity region of the second conductivity type shallowly diffused on the back side of the semiconductor substrate, a first PN junction formed between the first impurity region and the semiconductor substrate, and a second PN junction formed between the second impurity region and the semiconductor substrate. Since light beams of a shorter wavelength are absorbed near the surface of a semiconductor, while light beams of a longer wavelength reach deeper sections, the two PN junctions at front and back sides of the photodiode allow the device to be used as an adjustable low pass or high pass wavelength filter detector. | 2012-03-15 |
20120061789 | IMAGE SENSOR WITH IMPROVED NOISE SHIELDING - An image sensor includes a device wafer including a pixel array for capturing image data bonded to a carrier wafer. Signal lines are disposed adjacent to a side of the carrier wafer opposite the device wafer and a metal noise shielding layer is disposed beneath the pixel array within at least one of the device wafer or the carrier wafer to shield the pixel array from noise emanating from the signal lines. A through-silicon-via (“TSV”) extends through the carrier wafer and the metal noise shielding layer and extends into the device wafer to couple to circuitry within the device wafer. Further noising shielding may be provided by highly doping the carrier wafer and/or overlaying the bottom side of the carrier wafer with a low-K dielectric material. | 2012-03-15 |
20120061790 | Structure and Method of Fabricating a CZTS Photovoltaic Device by Electrodeposition - Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided. | 2012-03-15 |
20120061791 | INFRARED DETECTION DEVICE - According to one embodiment, an infrared detection device includes a detection element. The detection element includes a semiconductor substrate, a signal interconnect section, a detection cell and a support section. The semiconductor substrate is provided with a cavity on a surface of the semiconductor substrate. The signal interconnect section is provided in a region surrounding the cavity of the semiconductor substrate. The detection cell spaced from the semiconductor substrate above the cavity includes a thermoelectric conversion layer, and an absorption layer. The absorption layer is laminated with the thermoelectric conversion layer, and provided with a plurality of holes each having a shape whose upper portion is widened. The support section holds the detection cell above the cavity and connects the signal interconnect section and the detection cell. | 2012-03-15 |
20120061792 | BIDIRECTIONAL VOLTAGE-REGULATOR DIODE - In one embodiment, a bidirectional voltage-regulator diode includes first to fifth semiconductor layers formed on an inner surface of a first recess formed in a semiconductor substrate of an N-type in the order. The first semiconductor layer of the N-type has a first impurity concentration lower than an impurity concentration of the semiconductor substrate. The second semiconductor layer of a P-type has a second impurity concentration. The third semiconductor layer of the P-type has a third impurity concentration higher than the second impurity concentration. The fourth semiconductor layer of the P-type has a fourth impurity concentration lower than the third impurity concentration. The fifth semiconductor layer of the N-type has a fifth impurity concentration. | 2012-03-15 |
20120061793 | PARASITIC PNP BIPOLAR TRANSISTOR IN A SILICON-GERMANIUM BICMOS PROCESS - A parasitic PNP bipolar transistor, wherein a base region includes a first and a second region; the first region is formed in an active area, has a depth larger than shallow trench field oxides, and has its bottom laterally extended into the bottom of the shallow trench field oxides on both sides of an active area; the second region is formed in an upper part of the first region and has a higher doping concentration; an N-type and a P-type pseudo buried layer is respectively formed at the bottom of the shallow trench field oxides; a deep hole contact is formed on top of the N-type pseudo buried layer to pick up the base; the P-type pseudo buried layer forms a collector region separated from the active area by a lateral distance; an emitter region is formed by a P-type SiGe epitaxial layer formed on top of the active area. | 2012-03-15 |
20120061794 | METHODS OF FORMING THROUGH WAFER INTERCONNECTS IN SEMICONDUCTOR STRUCTURES USING SACRIFICIAL MATERIAL, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of fabricating semiconductor structures include providing a sacrificial material within a via recess, forming a first portion of a through wafer interconnect in the semiconductor structure, and replacing the sacrificial material with conductive material to form a second portion of the through wafer interconnect. Semiconductor structures are formed by such methods. For example, a semiconductor structure may include a sacrificial material within a via recess, and a first portion of a through wafer interconnect that is aligned with the via recess. Semiconductor structures include through wafer interconnects comprising two or more portions having a boundary therebetween. | 2012-03-15 |
20120061795 | Through-Substrate Via Waveguides - A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate. | 2012-03-15 |
20120061796 | Programmable anti-fuse wire bond pads - A mechanically programmable anti-fuse is configured in a thick, top metallic layer of a semiconductor. The metallic layer is selected of a material that possesses malleable properties. The metal anti-fuse programming pad is surrounded, either wholly or in part, by a pad segment. An intervening space between the anti-fuse pad and the pad segment is selected from a predetermined value such that capillary pressure, exerted when a ball-bond is placed atop the anti-fuse pad and the pad segment, causes the pads to deform and shorts to the anti-fuse pad to the pad segment. The shorting, created during the wire bonding process, programs the anti-fuse. | 2012-03-15 |
20120061797 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device including a substrate, and an anti-fuse element including a first insulator formed on the substrate, a conductive film formed on the first insulator, the conductive film including a silicide film, a contact formed on the substrate, the contact being disposed adjacent to the conductive film with a second insulator interposed between the contact and the conductive film, the contact being short-circuited to the silicide film. | 2012-03-15 |
20120061798 | HIGH CAPACITANCE TRENCH CAPACITOR - A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers. | 2012-03-15 |
20120061799 | Yttrium and Titanium High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions. | 2012-03-15 |
20120061800 | CAPACITOR ELEMENT, MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first capacitive insulating film, a first electrode, and a first barrier film. The first electrode has a first surface containing nitrogen. The first barrier film is between the first capacitive insulating film and the first electrode. The first barrier film faces the first surface of the first electrode. The first barrier film includes zinc oxide. The first barrier film is conductive. | 2012-03-15 |
20120061801 | STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING A STRUCTURE HAVING VIAS AND HIGH DENSITY CAPACITORS - A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate. | 2012-03-15 |
20120061802 | BIPOLAR JUNCTION TRANSISTOR - A bipolar junction transistor includes a semiconductor island on an insulating substrate; an emitter and at least one of a collector and sub collector within the semiconductor island, the emitter and the at least one of the collector and the sub collector being of a first conductivity type; a base within the semiconductor island separating the emitter and the at least one of the collector and the sub collector, the base being of a second conductivity type; a base contact region within the semiconductor island, the base contact region being of the second conductivity type; and a connecting base region adjacent the base within the semiconductor island and connecting the base to the base contact region while not directly contacting the emitter, the connecting base region being of the second conductivity type with a doping concentration less than a doping concentration of the base contact region. | 2012-03-15 |
20120061803 | ASYMMETRICAL BIDIRECTIONAL PROTECTION COMPONENT - An asymmetrical bidirectional protection component formed in a semiconductor substrate of a first conductivity type, including: a first implanted area of the first conductivity type; a first epitaxial layer of the second conductivity type on the substrate and the first implanted area; a second epitaxial layer of the second conductivity type on the first epitaxial layer, the second layer having a doping level different from that of the first layer; a second area of the first conductivity type on the outer surface of the epitaxial layer, opposite to the first to area; a first metallization covering the entire lower surface of the substrate; and a second metallization covering the second area. | 2012-03-15 |
20120061804 | Systems and Methods for Enabling Esd Protection on 3-D Stacked Devices - An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry. | 2012-03-15 |
20120061805 | DICING DIE BOND FILM - The present invention provides a dicing die bond film in which peeling electrification hardly occurs and which has good tackiness and workability. The dicing die bond film of the present invention is a dicing die bond film including a dicing film and a thermosetting type die bond film provided thereon, wherein the thermosetting type die bond film contains conductive particles, the volume resistivity of the thermosetting type die bond film is 1×10 | 2012-03-15 |
20120061806 | SYSTEMS AND METHODS FOR DRYING A ROTATING SUBSTRATE - A method of drying a surface of a substrate is provided. The method includes supporting a substrate; rotating the substrate about a rotational center point; applying a liquid to the substrate via a liquid dispenser; applying a drying fluid to the substrate via a drying fluid dispenser; moving the drying fluid dispenser and the liquid dispenser in a direction toward an edge region of the substrate, the drying fluid being applied closer to the rotational center point than the fluid; upon the liquid being applied to the edge region of the substrate, discontinuing application of the liquid while continuing the manipulation of the drying fluid dispenser; and upon the drying fluid being applied to the edge region of the substrate, continuing to apply the drying fluid for a predetermined period of time. | 2012-03-15 |
20120061807 | PITCH MULTIPLIED MASK PATTERNS FOR ISOLATED FEATURES - Crisscrossing spacers formed by pitch multiplication are used to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with conductive material to form conductive contacts. | 2012-03-15 |
20120061808 | SEMICONDUCTOR PACKAGES HAVING INCREASED INPUT/OUTPUT CAPACITY AND RELATED METHODS - A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided. | 2012-03-15 |
20120061809 | METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a substrate for a semiconductor element, the manufacturing method including the steps of: providing a first photosensitive resin layer at a first surface of a metal plate; providing a second photosensitive resin layer at a second surface of the metal plate different from the first surface; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring post on the second surface of the metal plate; forming the connection post by performing an etching on the first surface of the metal plate from a first surface side to a midway of the metal plate; applying a premold resin in liquid form to the first surface of the metal plate which underwent the etching on the first surface; forming a premold resin layer by solidifying the premold resin in liquid form being applied; and forming a wiring pattern by performing an etching on the second surface of the metal plate from a second surface side. | 2012-03-15 |
20120061810 | LED LEAD FRAME HAVING DIFFERENT MOUNTING SURFACES - An LED lead frame comprises an insulative housing including a top surface, a bottom surface, and four side surfaces connected the top surface and the bottom surface, and a cavity recessed from the top surface. A pair of conductive leads each has a portion embedded into the insulative housing and another portion exposed out of the insulative housing. The another portion includes an end portion extending downwardly along one of the side surface, a bottom soldering portion extending continuously from the end portion along the bottom surface, and a pair of side soldering portions extending upwardly from two ends of the bottom soldering portion along another two opposite side surfaces. The bottom soldering portion and the side soldering portions can be used as an alternative mounting surface. | 2012-03-15 |
20120061811 | APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES - An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a heat sink plate and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the heat sink plate. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. | 2012-03-15 |
20120061812 | Power Semiconductor Chip Package - A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad. | 2012-03-15 |
20120061813 | Package Structure for DC-DC Converter - A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package. | 2012-03-15 |
20120061814 | Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads. | 2012-03-15 |
20120061815 | POWER SEMICONDUCTOR MODULE HAVING SINTERED METAL CONNECTIONS, PREFERABLY SINTERED SILVER CONNECTIONS, AND PRODUCTION METHOD - A power semiconductor module having a substrate ( | 2012-03-15 |
20120061816 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor package and method of fabricating the same. The package includes an interconnection substrate, a semiconductor chip mounted on the interconnection substrate, a lateral wire bonded on the interconnection substrate and configured to enclose a side surface of the semiconductor chip, and a metal layer disposed on the semiconductor chip and electrically connected to the lateral wire. | 2012-03-15 |
20120061817 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board. | 2012-03-15 |
20120061818 | 3-D Integrated Semiconductor Device Comprising Intermediate Heat Spreading Capabilites - In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips. | 2012-03-15 |
20120061819 | Semiconductor Module and Method for Production Thereof - This invention relates to a module including a semiconductor chip, at least two contact elements and an insulating material between the two contact elements. Furthermore, the invention relates to a method for production of such a module. | 2012-03-15 |
20120061820 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT, AND ELECTRONIC COMPONENT - Provided is a method for manufacturing an electronic component by using a solder joining method for bonding a first electronic component having a metal electrode with a second electronic component having a solder electrode, the method comprising; (i) forming a resin layer containing a thermosetting resin on at least one of the solder joint surfaces of said first electronic component and said second electronic component; (ii) positioning said metal electrode of said first electronic component and said solder electrode of said second electronic component to face each other, heating said positioned electrodes and applying pressure, and thereby bringing said metal electrode and said solder electrode into contact; (iii) heating electronic components while applying pressure thereby fusion bonding said solder to said metal electrode; and (iv) heating said resin layer. | 2012-03-15 |
20120061821 | SEMICONDUCTOR CHIP WITH REDUNDANT THRU-SILICON-VIAS - A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias. | 2012-03-15 |
20120061822 | Semiconductor Device and Method of Forming Base Substrate With Cavities Formed Through Etch-Resistant Conductive Layer for Bump Locking - A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers. | 2012-03-15 |
20120061823 | SEMICONDUCTOR DEVICE HAVING PAD STRUCTURE WITH STRESS BUFFER LAYER - A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring. | 2012-03-15 |
20120061824 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING BOND-ON-LEAD INTERCONNECTION FOR MOUNTING SEMICONDUCTOR DIE IN FO-WLCSP - A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer. | 2012-03-15 |
20120061825 | CHIP SCALE PACKAGE AND METHOD OF FABRICATING THE SAME - A chip scale package and a method of fabricating the chip scale package. The chip scale package includes a encapsulant having a first surface and a second surface opposing the first surface; a conductive pillar formed in the encapsulant and exposed from the first surface and the second surface; a chip embedded in the encapsulant while exposed from the first surface; a dielectric layer formed on the first surface, the conductive pillar and the chip; a circuit layer formed on the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer electrically connecting the circuit layer, electrode pads and the conductive pillar; and a solder mask layer formed on the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. | 2012-03-15 |
20120061826 | SEMICONDUCTOR DEVICE - A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad. | 2012-03-15 |
20120061827 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a first surface, a through silicon via (TSV) that is formed so that at least a part thereof penetrates through the semiconductor substrate, and an insulation ring. The insulation ring is formed so as to penetrate through the semiconductor substrate and so as to surround the TSV. The insulation ring includes a tapered portion and a vertical portion. The tapered portion has a sectional area which is gradually decreased from the first surface toward a thickness direction of the semiconductor substrate. The vertical portion has a constant sectional area smaller than the tapered portion. | 2012-03-15 |
20120061828 | SEMICONDUCTOR DEVICE AND LAYOUT METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate. | 2012-03-15 |
20120061829 | METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - A manufacturing method of a substrate for a semiconductor element, wherein a first step includes: forming a first and second photosensitive resin layer on a first and second surface of a metal plate, respectively; forming a first and second resist pattern on the first and second surface, for forming a connection post and a wiring pattern, respectively. A second step includes: forming the connection post and wiring pattern; filling in a premold liquid resin to the first surface which was etched; forming a premold resin layer by hardening the premold liquid resin; performing a grinding operation on the first surface, and exposing an upper bottom surface of the connection post from the premold resin layer. A groove structure is formed by the first and second steps, wherein a depth of the groove is up to an intermediate part in a thickness direction of the metal plate. | 2012-03-15 |
20120061830 | BACK SIDE PROTECTIVE STRUCTURE FOR A SEMICONDUCTOR PACKAGE - A back side protective structure for a semiconductor package provided with a conductive layer, which is elastic and contains conductive material, formed between a protection substrate and an adhesive layer for having the protection substrate more stably fixed on the semiconductor package and protecting the back side of the semiconductor package. | 2012-03-15 |
20120061831 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring. | 2012-03-15 |
20120061832 | COLLAR STRUCTURE AROUND SOLDER BALLS THAT CONNECT SEMICONDUCTOR DIE TO SEMICONDUCTOR CHIP PACKAGE SUBSTRATE - In one embodiment, a collar structure includes a non-conductive layer that relieves stress around the perimeter of each of the solder balls that connect the semiconductor die to the semiconductor chip package substrate, and another non-conductive layer placed underneath to passivate the entire surface of the die. | 2012-03-15 |
20120061833 | EMBEDDED BALL GRID ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad. | 2012-03-15 |
20120061834 | SEMICONDUCTOR CHIP, STACKED CHIP SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND FABRICATING METHOD THEREOF - A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole. | 2012-03-15 |
20120061835 | DIE STRUCTURE, DIE ARRANGEMENT AND METHOD OF PROCESSING A DIE - A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded. | 2012-03-15 |
20120061836 | SPRAY PYROLYSIS OF Y-DOPED ZnO - One example embodiment includes a method for applying a transparent conducting oxide. The method includes providing a solution, where the solution includes a solvent, a zinc precursor and an yttrium precursor. The method also includes spraying the solution on a heated substrate, where the heated substrate turns the solution into an yttrium-doped zinc oxide film. The method further includes annealing the film on the substrate in a controlled environment. | 2012-03-15 |
20120061837 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device according to an embodiment, an etching stopper, an oxide film and a mask material are formed. A trench pattern is formed in the mask material. The oxide film is etched to form the trench pattern therein by using the mask material having the trench pattern formed therein as a mask. The etching stopper is etched until the etching stopper is penetrated to form the trench pattern therein, by using the oxide film having the trench pattern formed therein as a mask. A Cu film is formed to be filled in the trench pattern formed in the etching stopper and the oxide film and to cover the top surface of the oxide film. CMP is performed on the Cu film and the oxide film until the top surface of the etching stopper serving as a stopper is exposed. | 2012-03-15 |
20120061838 | BARRIER LAYER FORMATION FOR METAL INTERCONNECTS THROUGH ENHANCED IMPURITY DIFFUSION - A method of forming a barrier layer for metal interconnects of an integrated circuit device includes forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line. | 2012-03-15 |
20120061839 | METAL CAP LAYER WITH ENHANCED ETCH RESISTIVITY FOR COPPER-BASED METAL REGIONS IN SEMICONDUCTOR DEVICES - During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. Hence, well-established wet chemical etch chemistries may be used while not unduly contributing to process complexity. | 2012-03-15 |
20120061840 | DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF - A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer. | 2012-03-15 |
20120061841 | SEMICONDUCTOR INTEGRATED CIRCUIT, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING SEMICONDUCTOR INTEGRATED CIRCUIT - A step of forming a through hole in a semiconductor substrate, or a step of polishing the semiconductor substrate from its back surface requires a very long time and causes decrease of productivity. In addition, when semiconductor substrates are stacked, a semiconductor integrated circuit which is formed of the stack is thick and has poor mechanical flexibility. A release layer is formed over each of a plurality of substrates, layers each having a semiconductor element and an opening for forming a through wiring are formed over each of the release layers. Then, layers each having the semiconductor element are peeled off from the substrates, and then overlapped and stacked, a conductive layer is formed in the opening, and the through wiring is formed; thus, a semiconductor integrated circuit is formed. | 2012-03-15 |
20120061842 | STACK PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stack package includes a substrate, a lower semiconductor chip stacked on the substrate and electrically connected to the substrate through a lower via, a plurality of upper semiconductor chips stacked on the lower semiconductor chip and electrically connected to the lower via through an upper via, wherein the upper semiconductor chips are larger in size than the lower semiconductor chip, and an edge guide electrically connecting edge vias of the upper semiconductor chips and the substrate. | 2012-03-15 |
20120061843 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having a first surface, on which an electrode pad is arranged, and a second surface which is the other side of the semiconductor chip, an insulation member formed on the second surface of the semiconductor chip, and comprising a via hole at a position spaced apart from the semiconductor chip, and a conductive filler filling the via hole. | 2012-03-15 |
20120061844 | COPPER ALLOY FOR WIRING, SEMICONDUCTOR DEVICE, METHOD FOR FORMING WIRING, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries composing the Cu polycrystal and in vicinities of the crystal grain boundaries, higher than that of the inside of the crystal grains. The additional element is preferably at least one element selected from a group consisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag. This Cu wiring is formed by forming a Cu polycrystalline film, forming an additional element layer on this Cu film, and diffusing this additional element from the additional element layer into the Cu film. This copper alloy for wiring is preferred as metal wiring formed for a semiconductor device. | 2012-03-15 |
20120061845 | Methods for filling a contact hole in a chip package arrangement and chip package arrangements - In various embodiments, a method for filling a contact hole in a chip package arrangement is provided. The method may include introducing electrically conductive discrete particles into a contact hole of a chip package; and forming an electrical contact between the electrically conductive particles and a contact terminal of the front side and/or the back side of the chip. | 2012-03-15 |
20120061846 | COMPLIANT PRINTED CIRCUIT AREA ARRAY SEMICONDUCTOR DEVICE PACKAGE - An integrated circuit (IC) package for an IC device, and a method of making the same. The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members. The compliant layer is positioned to bias at least the first contact members against terminals on the IC device. Packaging substantially surrounds the IC device and the interconnect assembly. The second contact members are accessible from outside the packaging. | 2012-03-15 |
20120061847 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed. | 2012-03-15 |
20120061848 | CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHESIVE LAYER - A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffner. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffner can be tailored so that the thermal coefficient of expansion of the stiffner provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon. | 2012-03-15 |
20120061849 | SEMICONDUCTOR COMPONENT AND DEVICE PROVIDED WITH HEAT DISSIPATION MEANS - A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components. | 2012-03-15 |
20120061850 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA). | 2012-03-15 |
20120061851 | SIMULATED WIREBOND SEMICONDUCTOR PACKAGE - A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds | 2012-03-15 |