11th week of 2014 patent applcation highlights part 64 |
Patent application number | Title | Published |
20140075139 | MODIFYING MEMORY SPACE ALLOCATION FOR INACTIVE TASKS - Provided are a computer program product, system, and method for modifying memory space allocation for inactive tasks. Information is maintained on computational resources consumed by tasks running in the computer system allocated memory space in the memory. The information on the computational resources consumed by the tasks is used to determine inactive tasks of the tasks. The allocation of the memory space allocated to at least one of the determined inactive tasks is modified. | 2014-03-13 |
20140075140 | SELECTIVE CONTROL FOR COMMIT LINES FOR SHADOWING DATA IN STORAGE ELEMENTS - Systems and methods to selectively apply commit and rollback operations between a backup memory and a primary memory are implemented. For each entry in the primary memory, a monitor may be implemented to track the state of the entry. The state may indicate that the entry has changed upon execution of a write command for the entry. The state may be reset upon execution of a commit or rollback command. The primary memory may be a storage array coupled to a backup memory. The backup memory may be a shadow storage element. | 2014-03-13 |
20140075141 | CONCURRENT VIRTUAL MACHINE SNAPSHOTS AND RESTORE - Various mechanisms are disclosed herein for the saving and restoring of virtual machine environment state. For example, virtual machine state can be either be saved or (multiple) snapshots can be taken of the virtual machine state. In the latter case, virtual processors can be allowed to run while the memory of the virtual machine state is being saved. In either case, virtual devices associated with the virtual machine environment can be quiesced such that these devices can prepare themselves to be saved. Once such virtual devices and memory are saved, they can also be restored. For example, restoration of memory can occur while virtual processors are running at the same time. And, moreover, restoration can occur in batches of pages, thus optimizing the response time for restoring saved data. | 2014-03-13 |
20140075142 | MANAGING BACKING OF VIRTUAL MEMORY - A computer system includes memory and a processor configured to manage memory allocation. The processor is configured to execute a memory allocation request to allocate a portion of the memory to an application by determining whether a size of the memory allocation request is less than a first pre-defined size. The processor searches virtual memory for a free allocated memory area corresponding at least to the size of the memory allocation request based on determining that the size of the memory allocation request is less than the first pre-defined size. | 2014-03-13 |
20140075143 | MANAGEMENT APPARATUS AND MANAGEMENT METHOD - Proposed are a management apparatus and a management method capable of improving the stability of the overall computer system. In a computer system which manages a storage area provided by each of a plurality of mutually connected storage apparatuses as a logical pool, provides to a host computer a virtual volume associated with the logical pool, and assigns a real storage area from the logical pool to the virtual volume when the host computer writes [data] into the virtual volume, when a storage apparatus is added to the plurality of storage apparatuses, the host computer is controlled to switch the access path to the added storage apparatus. | 2014-03-13 |
20140075144 | DYNAMICALLY RESIZABLE CIRCULAR BUFFERS - Methods and apparatus for dynamically resizing circular buffers are described wherein circular buffers are dynamically allocated arrays from a pool of arrays. The method comprises receiving either a request to add data to a circular buffer or to remove data from a circular buffer. If the request is an addition request and the circular buffer is full, an array from the pool is allocated to the circular buffer. If, however, the request is a removal request and removal of the data creates an empty array, an array is de-allocated from the circular buffer and returned to the pool. Any arrays that are not allocated to a circular buffer may be disabled to conserve power. | 2014-03-13 |
20140075145 | MODIFYING MEMORY SPACE ALLOCATION FOR INACTIVE TASKS - Provided are a computer program product, system, and method for modifying memory space allocation for inactive tasks. Information is maintained on computational resources consumed by tasks running in the computer system allocated memory space in the memory. The information on the computational resources consumed by the tasks is used to determine inactive tasks of the tasks. The allocation of the memory space allocated to at least one of the determined inactive tasks is modified. | 2014-03-13 |
20140075146 | METHODS FOR OPERATING A MEMORY INTERFACE CIRCUIT INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES - A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes. | 2014-03-13 |
20140075147 | TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC LOOK-UP, ADD AND LOCK OPERATION - A transactional memory (TM) receives an Atomic Look-up, Add and Lock (ALAL) command across a bus from a client. The command includes a first value. The TM pulls a second value. The TM uses the first value to read a set of memory locations, and determines if any of the locations contains the second value. If no location contains the second value, then the TM locks a vacant location, adds the second value to the vacant location, and sends a result to the client. If a location contains the second value and it is not locked, then the TM locks the location and returns a result to the client. If a location contains the second value and it is locked, then the TM returns a result to the client. Each location has an associated data structure. Setting the lock field of a location locks access to its associated data structure. | 2014-03-13 |
20140075148 | MEMORY UTILIZATION OF SPARSE PAGES - A method, system, and computer program product for improving memory utilization of sparse pages are provided in the illustrative embodiments. A set of virtual pages is identified. Each virtual page in the set of virtual pages is a sparse virtual page. The set of virtual pages includes a first sparse virtual page and a second sparse virtual page. At least a portion of data of the first sparse virtual page in the set of virtual pages is stored in a first physical page. The first physical page belongs to a set of consolidation physical pages, and the first physical page also stores at least a portion of the data of the second sparse virtual page. The first and the second sparse pages are mapped to the first physical page. | 2014-03-13 |
20140075149 | Storage Mechanism with Variable Block Size - A file system may access a logical unit by addressing storage space using a constant block size, but the underlying logical unit may physically store information using different block sizes for different types of files. Certain file types may be stored using large blocks sizes for performance, while other file types may be stored using smaller block sizes for storage efficiency. A storage management system may create the logical unit from different block extents on various storage devices, where each block extent may be created with different block sizes. The system may place a file in a block extent that may be appropriate for the file type, and may perform a translation between the file system's request for a specific block and the manner in which the block is stored on the media. | 2014-03-13 |
20140075150 | METHOD FOR GENERATING A DELTA FOR COMPRESSED DATA - A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content. | 2014-03-13 |
20140075151 | DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS - There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages. | 2014-03-13 |
20140075152 | METHOD FOR GENERATING A DELTA FOR COMPRESSED DATA - A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content. | 2014-03-13 |
20140075153 | REDUCING ISSUE-TO-ISSUE LATENCY BY REVERSING PROCESSING ORDER IN HALF-PUMPED SIMD EXECUTION UNITS - Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction. | 2014-03-13 |
20140075154 | Task Switching and Inter-task Communications for Multi-core Processors - The invention provides hardware based techniques for switching processing tasks of software programs for execution on a multi-core processor. Invented techniques involve a hardware logic based controller for assigning, adaptive to program processing loads, tasks for processing by cores of a multi-core fabric as well as configuring a set of multiplexers to appropriately interconnect cores of the fabric and program task specific segments at fabric memories, to arrange efficient inter-task communication as well as transferring of activating and de-activating task memory images among the multi-core fabric. The invention thereby provides an efficient, hardware-automated runtime operating system for multi-core processors, minimizing any need to use processing capacity of the cores for traditional operating system software functions. Additionally, such low overhead hardware based operating system for multi-core processors provides significant cost-efficiency and performance advantages, including data processing throughput maximization across all programs dynamically sharing a given multi-core processor, and hardware based security. | 2014-03-13 |
20140075155 | OPERATING METHOD FOR A COMPUTER SYSTEM - A method for operating a computer system, in which a plurality of processes run, within the scope of which a multiplicity of objects are accessed. The method initially predefines, for the subsequent continued operation, which of the processes can be used to access which of the objects. The processes may be distributed among a plurality of processors of a multiprocessor system, and it is initially predefined which of the processors can address which objects. | 2014-03-13 |
20140075156 | FETCH WIDTH PREDICTOR - Various techniques for predicting instruction fetch widths. In one embodiment, a fetch prediction unit in a processor is configured to generate a fetch width that specifies a number of bits to be retrieved in a subsequent fetch from an instruction cache. The fetch prediction unit may also generate a fetch prediction that includes the fetch width in response to a current fetch request. A number of bits corresponding to the fetch width may be fetched from the instruction cache. The fetch width may correspond to a location of a predicted-taken control transfer instruction. This fetch width prediction may lead to power savings in instruction cache accesses. | 2014-03-13 |
20140075157 | Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type - Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements. | 2014-03-13 |
20140075158 | IDENTIFYING LOAD-HIT-STORE CONFLICTS - A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter. | 2014-03-13 |
20140075159 | Multithreaded processor architecture with operational latency hiding - A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue. | 2014-03-13 |
20140075160 | SYSTEM AND METHOD FOR SYNCHRONIZING THREADS IN A DIVERGENT REGION OF CODE - A system and method are provided for synchronizing threads in a divergent region of code within a multi-threaded parallel processing system. The method includes, prior to any thread entering a divergent region, generating a count that represents a number of threads that will enter the divergent region. The method also includes using the count within the divergent region to synchronize the threads in the divergent region. | 2014-03-13 |
20140075161 | Data-Parallel Computation Management - Data-parallel computation programs may be improved by, for example, determining the functional properties user defined functions (UDFs), eliminating unnecessary data-shuffling stages, and/or changing data-partition properties to cause desired data properties to appear after one or more user defined functions are applied. | 2014-03-13 |
20140075162 | DIGITAL PROCESSOR HAVING INSTRUCTION SET WITH COMPLEX EXPONENTIAL NON-LINEAR FUNCTION - A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to θ; and computing a fine corrective value using a polynomial approximation. | 2014-03-13 |
20140075163 | LOAD-MONITOR MWAIT - Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction. | 2014-03-13 |
20140075164 | TEMPORAL LOCALITY AWARE INSTRUCTION SAMPLING - A method and system are disclosed for sampling instructions executing on a computer processor. A computer processor determines a number of times a specified event has occurred within a specified temporal window. The computer processor determines to mark an instruction to be executed for monitoring based on the number of times the specified event has occurred within the temporal window, and in response, the computer processor marks the instruction. | 2014-03-13 |
20140075165 | EXECUTING SUBROUTINES IN A MULTI-THREADED PROCESSING SYSTEM - This disclosure is directed to techniques for executing subroutines in a single instruction, multiple data (SIMD) processing system that is subject to divergent thread conditions. In particular, a resume counter-based approach for managing divergent thread state is described that utilizes program module-specific minimum resume counters (MINRCs) for the efficient processing of control flow instructions. In some examples, the techniques of this disclosure may include using a main program MINRC to control the execution of a main program module and subroutine-specific MINRCs to control the execution of subroutine program modules. Techniques are also described for managing the main program MINRC and subroutine-specific MINRCs when subroutine call and return instructions are executed. Techniques are also described for updating a subroutine-specific MINRC to ensure that the updated MINRC value for the subroutine-specific MINRC is within the program space allocated for the subroutine. | 2014-03-13 |
20140075166 | Swapping Branch Direction History(ies) in Response to a Branch Prediction Table Swap Instruction(s), and Related Systems and Methods - Swapping branch direction history(ies) in response to a branch prediction table swap instruction(s), and related systems and methods are disclosed. In one embodiment, a branch history management circuit is configured to process a branch prediction table swap instruction. In response to the branch prediction table swap instruction, the branch history management circuit is configured to swap a prior branch direction history set assigned to a current software code region from cache memory, into a branch prediction table (BPT) for use in branch prediction. The current branch direction history set is swapped out of the BPT and stored in cache memory to avoid being overwritten. In this manner, branch direction history sets assigned to particular software code regions are used for branch prediction when processing the particular software code regions. Therefore, branch prediction accuracy and instruction processing throughput of an instruction processing system are increased. | 2014-03-13 |
20140075167 | BRANCH HISTORY CACHE AND METHOD - A branch history table cache is a write cache that stores values of branch history counters written to a branch history table. An update to a branch history table counter is reflected in both the branch history table cache and the branch history table. Before a branch history table counter is updated, a check is made to see if the branch history table counter is in the cache. If not, the branch history table counter is updated based on a value of the branch history table counter that was saved during fetch of the branch history table counter. If, however, the branch history table counter value is in the cache, the value in the cache is used to update the branch history table counter. All branches that use the branch history table counter update the correct counter value, improving processor performance by providing more accurate predictions of branches taken. | 2014-03-13 |
20140075168 | INSTRUCTION SEQUENCE BUFFER TO STORE BRANCHES HAVING RELIABLY PREDICTABLE INSTRUCTION SEQUENCES - A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer. | 2014-03-13 |
20140075169 | ACCESSORY BOOTING OVER USB - Methods, systems, and apparatuses for booting an accessory with an accessory firmware image received from a host device are described. When the host device detects a connection between the accessory and the host device, the host device may send a request for an accessory identifier to the accessory. The accessory may send an accessory identifier to the host device in response. The host device may select an accessory firmware image that is suitable for the accessory, and may transmit the accessory firmware image to the accessory. The accessory firmware image may include information that the accessory can use to enable the accessory to exchange application data with the host device. | 2014-03-13 |
20140075170 | AUTOMATED FIRMWARE VOTING TO ENABLE MULTI-ENCLOSURE FEDERATED SYSTEMS - One embodiment provides a method of initializing a federated computer system from a fabric of nodes connected by a federated interface. Each node casts a vote to the federated interface for a candidate firmware version supported by the node casting the vote. The candidate firmware version having received the greatest number of votes is identified, and the computer system is initialized as a federated system of the nodes that support the firmware version identified as having received the greatest number of votes. A process of iterative voting may be used to identify a greater number of nodes supporting a compatible firmware version. | 2014-03-13 |
20140075171 | MULTI-PURPOSE POWER CONTROLLER AND METHOD - The present invention provides a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex mid-size complex programmable logic devices (CPLD) or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. | 2014-03-13 |
20140075172 | Operating System Hardware Configuration State Specialization - In one or more embodiments, hardware configuration state data for specialization of a portable installation of an operating system may be stored on a per hardware configuration basis. Specializations may include designation of boot start drivers, driver settings, device settings, and other state data that may vary based on hardware configurations of different machines on which the portable operating system is loaded. In a pre-boot environment, an identity of the current computing device is resolved and used to look-up corresponding hardware configuration state data that is available. When booting of the operating system on a new computing device is detected, the operating system is loaded using default state settings. An optimization routine may then be performed to create and store hardware specific hardware configuration state data for the computing device that defines specializations for subsequent boots of the operating system on the computing device. | 2014-03-13 |
20140075173 | AUTOMATED FIRMWARE VOTING TO ENABLE A MULTI-ENCLOSURE FEDERATED SYSTEM - A method initializes a federated computer system from a fabric of nodes connected by a federated interface. Each node casts a vote to the federated interface for a candidate firmware version supported by the node casting the vote. The candidate firmware version having received the greatest number of votes is identified, and the computer system is initialized as a federated system of the nodes that support the firmware version identified as having received the greatest number of votes. A process of iterative voting may be used to identify a greater number of nodes supporting a compatible firmware version. | 2014-03-13 |
20140075174 | Boot State Restore from Nonvolatile Bitcell Array - A processing device using a plurality of volatile storage elements to execute a boot process for and stores in a plurality of non-volatile logic element arrays a boot state representing a state of the processing device after a given amount of the boot process is completed. When it is determined that the processing device needs to restart from a boot state, energy can be saved by restoring the machine state at that boot state instead of re-booting. The stored boot state will not change, and given the nature of certain non-volatile storage elements, the data read from the NVL storage elements needs to be re-written to the elements after read out. Accordingly, a round-trip data restoration operation is executed that automatically writes back data to an individual non-volatile logic element after reading data from the individual non-volatile logic element without completing separate read and write operations. | 2014-03-13 |
20140075175 | Control of Dedicated Non-Volatile Arrays for Specific Function Availability - A device's configuration is controlled through control of its pre-boot process. Protected non-volatile logic element arrays store a machine state configuration of a processing device configured to backup data from volatile storage elements in a plurality of non-volatile logic element arrays. The machine state configuration is read in response to the processing device's entering a pre-boot process. The processing device's configuration is then set to the machine state configuration. This setting of the device configuration can be done by receiving instructions from the protected non-volatile logic element arrays to direct an order in which data for individual device functions are restored from non-volatile logic element arrays in response to the processing device's entering a wakeup or recovery mode. In one approach, the instructions arrange configuration bits that direct operation of a non-volatile logic controller during the wakeup or recovery mode to control the order of data restoration. | 2014-03-13 |
20140075176 | INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a processor that executes an instruction stored in a fixed address area in a storage part; the storage part that stores a first startup program and a second startup program, contents of the second startup program being different at least partially from those of the first startup program; and an address conversion part that, when the processor carries out a predetermined startup different from an ordinary startup that is carried out at a time of starting power supply to the information processing apparatus, converts an address included in a read instruction issued by the processor indicating a storage area that stores the first startup program into an address indicating an other storage area that stores the second startup program, and sends the converted address to the storage part. | 2014-03-13 |
20140075177 | ELECTRONIC CONTROL APPARATUS - An electronic control apparatus as one of nodes connected to a communication line includes a microcomputer, a power integrated circuit for controlling power supply to the microcomputer, and a timer adjuster. The power integrated circuit has a timer for measuring a time period during which no data flows through a communication line. The timer is reset, when no data flows through the communication line and then data flows through the communication line. The power integrated circuit starts power supply to the microcomputer, when data flows through the communication line. The power integrated circuit stops the power supply when the timer reaches a threshold value. The timer adjuster prevents the timer from reaching the threshold value until the microcomputer completes a shutdown process. | 2014-03-13 |
20140075178 | Providing Support for Device States - A method of providing support for power-management of a device. The method may include gathering contextual data from a sensor communicatively coupled to a sensor controller. The method may also include receiving power-management data including an operational state of a main processor of the device. The method may also include modifying the operation of the device based on the contextual data and the power management data. | 2014-03-13 |
20140075179 | Techniques for Managing or Controlling Computing Devices - Examples are disclosed for receiving or gathering asset information associated with computing devices housed in respective decentralized locations. The gathered or received asset information may be stored. A portion of the computing devices may be grouped based on the stored asset information to create a virtual rack. An operating parameter of at least some of the computing devices included in the virtual rack may then be managed or controlled. | 2014-03-13 |
20140075180 | Media Storage Structures for Storing Content, Devices for Using Such Structures, Systems for Distributing Such Structures - Some embodiments of the invention provide a content-distribution system. In some embodiments, the content-distribution system distributes device-restricted content and device-unrestricted content. Device-restricted content is content that can only be played on devices that the system associates with the particular user. Device-unrestricted content is content that can be played on any device without any restrictions. However, for at least one operation or service other than playback, device-unrestricted content has to be authenticated before this operation or service can be performed on the content. In some embodiments, the system facilitates this authentication by specifying a verification parameter for a piece of device-unrestricted content. The content-distribution system of some embodiments has a set of servers that supply (1) media storage structures that store content, (2) cryptographic keys that are needed to decrypt device-restricted content, and (3) verification parameters that are needed to verify device-unrestricted content. | 2014-03-13 |
20140075181 | SYSTEMS AND METHODS FOR PROVIDING CONDITIONAL ACCESS TO TRANSMITTED INFORMATION - Systems, methods and computer program products for controlling access to position information at a receiver based on various considerations, including a requested service type, a user type, a device type, a software application type, and/or other characteristics associated with a particular software application at the receiver from which the position information was requested | 2014-03-13 |
20140075182 | METHOD FOR PROVIDING DATA TO A PERSONAL PORTABLE DEVICE VIA NETWORK AND A SYSTEM THEREOF - Disclosed are a method and a system for synchronizing and providing data requiring digital rights protection, to a portable device, wherein a contents providing server is connected with a contents synchronization server to which the portable device is connected. | 2014-03-13 |
20140075183 | SECURE AND SCALABLE MAPPING OF HUMAN SEQUENCING READS ON HYBRID CLOUDS - System and methods are provided for performing privacy-preserving, high-performance, and scalable DNA read mapping on hybrid clouds including a public cloud and a private cloud. The systems and methods offer strong privacy protection and have the capacity to process millions of reads and allocate most of the workload to the public cloud at a small overall cost. The systems and methods perform seeding on the public cloud using keyed hash values of individual sequencing reads' seeds and then extend matched seeds on the private cloud. The systems and methods are designed to move the workload of read mapping from the extension stage to the seeding stage, thereby ensuring that the dominant portion of the overhead is shouldered by the public cloud. | 2014-03-13 |
20140075184 | TRUST SERVICES FOR SECURING DATA IN THE CLOUD - Embodiments are directed to securing data in the cloud, securely encrypting data that is to be stored in the cloud and to securely decrypting data accessed from the cloud. In one scenario, an instantiated trust service receives information indicating that a trust server is to be instantiated. The trust service instantiates the trust server, which is configured to store key references and encrypted keys. The trust service receives the public key portion of a digital certificate for each publisher and subscriber that is to have access to various specified portions of encrypted data. A data access policy is then defined that specifies which encrypted data portions can be accessed by which subscribers. | 2014-03-13 |
20140075185 | SECURELY HANDLING SERVER CERTIFICATE ERRORS IN SYNCHRONIZATION COMMUNICATION - An invalid digital certificate can be saved and subsequently compared to an incoming digital certificate when performing a security check. If a subsequently provided digital certificate does not match the saved digital certificate, an error condition can be generated. Because a digital certificate can be invalid for non-malicious reasons, such technologies can be useful for improving software security. | 2014-03-13 |
20140075186 | Multiple Access Key Fob - The invention relates to a portable device with access to several instances such that each of the instances performs an operation in response to a wireless data exchange with the portable device. The portable device comprises a data processing unit and a memory that stores a public key, a private key and a certificate. The portable device is further configured to transfer the certificate and the public key to a first instance. The first instance is configured to receive the first public key and the first certificate from the first portable device. The first instance is further configured to receive a signature from the first portable device, to decrypt the signature with the copy of the first public key so as receive a code, to compare the code with the random challenge and to perform the operation only if the code and random challenge match. | 2014-03-13 |
20140075187 | SELECTIVE AUTHORIZATION OF THE LOADING OF DEPENDENT CODE MODULES BY RUNNING PROCESSES - Systems and methods for selective authorization of dependent code modules are provided. According to one embodiment, responsive to a monitored file system or operating system event initiated by an active process, a real-time authentication process is performed or bypassed on a code module to which the monitored event relates with reference to a whitelist that includes cryptographic hash values of approved code modules, which are known not to contain viruses or malicious code. The active process is allowed to load the code module when the authentication process is bypassed or when the cryptographic hash value of the code module matches one of the cryptographic hash values of approved code modules within the whitelist. | 2014-03-13 |
20140075188 | TRUSTED THIRD PARTY CLIENT AUTHENTICATION - A method includes receiving, at a video service provider system, a request for an online video session from a third party device with a security markup assertion language (SAML) token as an input, decrypting a SAML assertion in the SAML token with a private key associated with the video service provider system, validating the SAML assertion based on a third party public key associated with the third party STS, and retrieving a third party account user identifier and a device type. The method also includes identifying a link time based on the third party account user identifier, identifying a password change time (PCT) stamp associated with the service provider user account, and providing the online video session to the third party device in response to determining that the PCT stamp is not later than the link time. | 2014-03-13 |
20140075189 | SYSTEMS, APPARATUS, AND METHODS FOR ASSOCIATION IN MULTI-HOP NETWORKS - Systems, methods, and devices for communicating data in a wireless communications network are described herein. One innovative aspect of the present disclosure includes a method of communicating in a wireless network. The method includes encrypting a message based, at least in part, on an original source address, and a final destination address. The method further includes transmitting the encrypted message to a relay for delivery to the final destination address. | 2014-03-13 |
20140075190 | AUTHENTICATOR, AUTHENTICATEE AND AUTHENTICATION METHOD - According to one embodiment, an authenticatee includes, a memory configured to store secret information XY, secret information XY which is created by multiply duplicating, at least twice, the secret information XY, and secret information XY | 2014-03-13 |
20140075191 | SYSTEM AND METHOD FOR TRANSMITTING AND UTILIZING ATTACHMENTS - A method of handling cryptographic information in a communication comprising body elements and attachment elements to a mobile device includes the steps of determining if the communication includes an attachment element comprising cryptographic information and converting the attachment element into a body element upon determining that the communication includes an attachment element comprising cryptographic information. | 2014-03-13 |
20140075192 | INFORMATION PROCESSING APPARATUS AND METHOD - To limit use of content, when a source receives a request for transmitting content from a sink, the source performs an authentication process. When the authentication is successful, the source transmits to the sink key information necessary for decrypting the encryption applied to the content. The sink can receive the content by receiving the key information and by decrypting the encryption applied to the content by using the key information. | 2014-03-13 |
20140075193 | STORAGE METHOD - The present invention discloses a storage method. When User A uploads data X to a server which has not been stored in the server, the method includes: calculating a storage encryption key ekS and corresponding decryption key dkS based on data X and a pre-determined algorithm; encrypting the data X with ekS to obtain encrypted data Y, and uploading the data Y to a server; encrypting dkS with ekA which is an encryption key ekA for User A to obtain User A's personal key kA and submitting the kA to the server. | 2014-03-13 |
20140075194 | SYSTEM AND METHOD FOR SECURE AUTHENTICATION OF A "SMART" BATTERY BY A HOST - Systems and methods for providing a battery module | 2014-03-13 |
20140075195 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - To realize a configuration to output content to a medium and to use the content stored in the medium under control of the use of content. | 2014-03-13 |
20140075196 | SECURELY FILTERING TRUST SERVICES RECORDS - Embodiments are directed to securely filtering trust services records. In one scenario, a client computer system receives at least one of the following trust services records: a trust services certificate, a principal certificate, a group certificate and a trust services policy. The client computer system performs a time validity check to validate the trust services record's timestamp, performs an integrity check to validate the integrity of the trust services record and performs a signature validity check to ensure that the entity claiming to have created the trust services record is the actual creator of the trust services record. The client computer system then, based on the time validity check, the integrity check and the signature validity check, determines that the trust services record is valid and allows a client computer system user to perform a specified task using the validated trust services record. | 2014-03-13 |
20140075197 | METHOD FOR SELECTIVE SOFTWARE ROLLBACK - A system and method for validating a software file to be installed into a controller. The method includes preparing the software file including assigning a software version code to the software file, assigning a security version code to the software file, and signing the software file with the software file version code and the security version code. The signed software file is presented to the controller for installing on the controller and the controller verifies the software file signature to determine if the software file is valid and the security version code is valid. The controller allows the software file to be installed in the controller if both the signed software file is valid and the security version code is valid. | 2014-03-13 |
20140075198 | FULLY AUTHENTICATED CONTENT TRANSMISSION FROM A PROVIDER TO A RECIPIENT DEVICE VIA AN INTERMEDIARY DEVICE - A method, system, and computer readable medium containing programming for handling fully authenticated transmission of video or other data (content) from a provider to a recipient device via an intermediary device. An inner envelope containing the content and/or security features is prepared and digitally signed using a private cryptographic key. The signed inner envelope is then included in a second, outer envelope which may also include some or all of the content. The outer envelope is also digitally signed, thereby forming a data package which may be sent from the provider to the intermediary device. If the signature of the outer envelope is authenticated at the intermediary device, then the inner envelope is sent to the recipient device which then uses the inner signature to verify its authenticity. Authenticated content may then be presented or otherwise used at the recipient device. | 2014-03-13 |
20140075199 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM - There is provided an information processing apparatus including a key selection section configured to select one out of a plurality of different secret keys, in a public key authentication scheme or a digital signature scheme in which each of the plurality of secret keys exists for one public key registered in a verifier, and a process execution section configured to execute, by using the secret key selected by the key selection section, an authentication process with the verifier by the public key authentication scheme or a digital signature generation process to the verifier by the digital signature scheme. | 2014-03-13 |
20140075200 | METHOD FOR MANAGING ELECTRONIC FILE AND ELECTRONIC FILE MANAGEMENT APPARATUS - In accordance with one embodiment, a method for managing an electronic file include creating an electronic signature of a user who is generating an electronic file by encrypting the electronic file using a private key of the user, and embedding the created electronic signature of the user and a public key certificate of the user, in the electronic file. The public key certificate of the user certifying a public key of the user corresponding to the private key of the user and including a link to a certificate list that shows whether or not the public key certificate of the user is valid. | 2014-03-13 |
20140075201 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - There is provided an information processing device including a distribution control unit configured to cause one or two external devices to distributively perform a repetitive process in a process for signature or authentication in which the repetitive process is included, and a processing unit configured to perform the process for signature or authentication using a processing result of each of the external devices. | 2014-03-13 |
20140075202 | METHOD AND SYSTEM FOR SECURELY ACCESSING DIFFERENT SERVICES BASED ON SINGLE SIGN ON - An embodiment for securely accessing services of a service provider based on single sign on. The user device is authenticated by an authentication server if the computed hash of the first random number r is same as the received hash of the first random number r sent by a user device. Thereafter, the second random number y, the user id and an element Q are encrypted using a service provider password and send to the service provider. The user device computes a first discrete exponential function Z using the element Q and the second random number y and sends along with the user id to the service provider. The service provider computes a second discrete exponential function Z′ using the element Q and the second random number y received from the authentication server and provides the user device access to the services if Z is equal to Z′. | 2014-03-13 |
20140075203 | METHOD FOR TESTING THE SECURITY OF AN ELECTRONIC DEVICE AGAINST AN ATTACK, AND ELECTRONIC DEVICE IMPLEMENTING COUNTERMEASURES - A method of testing security of an electronic device against a combination of a side-channel attack and a fault-injection attack implemented during a method of cryptographic processing that includes: delivering a message signature based on a secret parameter and implementing a recombination of at least two intermediate values according to the Chinese remainder theorem; and verifying the signature on the basis of at least one public exponent. The method of testing includes: transmitting a plurality of messages to be signed by said electronic device; disturbing each message, including modifying the message by inserting an identical error for each message, before executing a step of determining one of the intermediate values; and analyzing physical measurements, obtained during the step of verifying the signature as a function of the message to be signed, the identical error for each message, and an assumption of a value of part of the secret parameter. | 2014-03-13 |
20140075204 | REMOVABLE DEVICES - An embodiment of a method of operating a storage system includes combining a password, a first number, and a number of iterations to produce a first key, encrypting the first key, receiving a second number, and encrypting the second number with the first key to produce an encrypted second key. | 2014-03-13 |
20140075205 | METHOD OF PROCESSING DATA TO ENABLE EXTERNAL STORAGE THEREOF WITH MINIMIZED RISK OF INFORMATION LEAKAGE - A method is provided to process data so that the data can be externally stored with minimized risk of information leakage. A framework (virtual execution framework) based on virtual machines (VMs) is utilized as a substitute for a trusted institution. Encryption of consolidated data can reduce risk of information leakage and enhance security. Since the virtual execution framework can control connection and direction of communication, financial institutions are allowed to apply encryption to data on their own, which makes the data further appropriate for external storage. By allowing financial institutions to apply their own decryption, it is possible to prevent one of two financial institutions from retrieving externally stored data into the external execution framework without intervention of the other. Additionally, associated acting subjects can be provided with freedom depending on the degree of information leakage risk. | 2014-03-13 |
20140075206 | METHODS AND SYSTEMS FOR PROVIDING ACCESS CONTROL TO SECURED DATA - In a system for providing access control management to electronic data, techniques to secure the electronic data and keep the electronic data secured at all times are disclosed. According to one embodiment, a secured file or secured document includes two parts: an attachment, referred to as a header, and an encrypted document or data portion. The header includes security information that points to or includes the access rules and a file key. The access rules facilitate restrictive access to the secured document and essentially determine who/when/how/where the secured document can be accessed. The file key is used to encrypt/decrypt the encrypted data portion. Only those who have the proper access privileges are permitted to retrieve the file key to encrypt/decrypt the encrypted data portion. | 2014-03-13 |
20140075207 | APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING INFORMATION - An information processing apparatus performs mutual authentication with another information processing apparatus storing key management information and at least one of apparatus secret keys, the key management information containing encrypted secret keys each being a secret key encrypted with a different one of the apparatus secret keys respectively assigned to information processing apparatuses. The apparatus transmits, to the other apparatus, designation information specifying one of the encrypted secret keys decryptable with the apparatus secret key, out of the encrypted secret keys contained in the key management information usable by the apparatus, receives the encrypted secret key specified by the designation information out of the encrypted secret keys contained in the key management information stored in the other apparatus from the other apparatus, obtains the secret key by decrypting the encrypted secret key with the apparatus secret key, and performs authentication with the other apparatus based on the secret key. | 2014-03-13 |
20140075208 | DATA WHITENING FOR WRITING AND READING DATA TO AND FROM A NON-VOLATILE MEMORY - Systems, apparatuses, and methods are provided for whitening and managing data for storage in non-volatile memories, such as Flash memory. In some embodiments, an electronic device such as media player is provided, which may include a system-on-a-chip (SoC) and a non-volatile memory. The SoC may include SoC control circuitry and a memory interface that acts as an interface between the SoC control circuitry and the non-volatile memory. The SoC can also include an encryption module, such as a block cipher based on the Advanced Encryption Standard (AES). The memory interface can direct the encryption module to whiten all types of data prior to storage in the non-volatile memory, including sensitive data, non-sensitive data, and memory management data. This can, for example, prevent or reduce program-disturb problems or other read/write/erase reliability issues. | 2014-03-13 |
20140075209 | METHOD FOR CONTENT USE, DEVICE FOR CONTENT USE, MOBILE TERMINAL, AND RECORDING MEDIUM - The present invention relates to a content service technology, and more particularly to an apparatus and a method for content use, a device for content use, a mobile terminal and a recording medium capable of providing a streaming service while preventing the unauthorized use, illegal reproduction, and illegal falsification of content. | 2014-03-13 |
20140075210 | ADAPTER FOR USE WITH A PORTABLE ELECTRONIC DEVICE - An adapter for enabling connection of a portable electronic device with an accessory includes two connectors, an identification device, a power control device, and power clamping circuitry. All of these components may be included in a single integrated housing. Another adapter may have a cable with two connectors connected to either end of the cable. One of the connectors may house the identification device and the power control device. Optionally, the adapter may also house the power clamp circuitry. | 2014-03-13 |
20140075211 | CASCADING POWER CONSUMPTION - A method and system for cascading power consumption is described herein. The method may include providing power to a first sensor and a second sensor, wherein the first sensor consumes more power than the second sensor. The method may also include detecting the first sensor does not capture a sample of data. In addition, the method may include stopping the flow of power to the first sensor. Furthermore, the method may include monitoring an operating environment with the second sensor. The method may also include providing power to the first sensor in response to the second sensor detecting a sample of data. | 2014-03-13 |
20140075212 | MANAGING AND REVOKING POWER ALLOCATED THROUGH BUS INTERFACES - The disclosed embodiments provide a system that manages power allocated through a set of bus interfaces on a computer system. During operation, the system obtains a first request for revocable current beyond a reserved current for a first bus interface from the set of bus interfaces, wherein the request is associated with a first device connected to the first bus interface. Next, the system allocates the revocable current to the first bus interface from an extra-current budget for the set of bus interfaces. Upon detecting a connection of a second device that requires non-revocable current over the extra-current budget to a second bus interface from the set of bus interfaces, the system transmits a first notification to the first device to relinquish the revocable current. Finally, the system allocates the non-revocable current to the second device from the relinquished revocable current. | 2014-03-13 |
20140075213 | MANAGED CENTRALIZED POWER SUPPLY AND FIBER SPLITTER FOR FTTP DEPLOYMENT - A network connection apparatus and system are described. The network connection apparatus includes a network interface for connection to a communication network, at least one power interface for connection to a powered network device, and at least one communication interface for connection to the powered network device. The communication interface is communicatively coupled to the network interface through a splitter. The network connection apparatus includes a bus connected to the at least one power interface, and a power supply electrically connected to the bus to supply power to the at least one power interface. The network connection apparatus may also include a communication terminal connected to the bus and to the splitter. | 2014-03-13 |
20140075214 | CONFIGURATION DETECTION FOR AN INPUT DEVICE - In certain embodiments, a protective cover includes a housing having a surface, and a latch mechanism hingeably coupled to the housing. The latch can include a top side and a bottom side, the bottom side configured to couple to and secure an input device to the surface of the housing. The latch can be configured to rotate, via the hinge coupling, between a first configuration and second configuration. In the first configuration, the top side of the latch can be flush with the surface of the housing and the bottom side embedded within the housing such that the latch does not protrude from the housing. In the second configuration, the latch can be rotated relative to the first configuration and protrude from the housing. The latch can be operable to be rotated open from the first configuration to the second configuration via the hinge coupling. | 2014-03-13 |
20140075215 | LAUNDRY TREATING APPARATUS - The present invention provides a laundry treating apparatus including a cabinet, a control panel having a power key and a display panel provided to one side of the cabinet, a display MICOM for controlling a frame to be displayed on a display of the display panel, a main MICOM for putting a load into operation according to a washing stroke applied thereto, and a standby power MICOM for generating a power supply signal to supply power to the display MICOM and the main MICOM in response to a power key applied signal generated as the power key is operated. | 2014-03-13 |
20140075216 | ELECTRONIC DEVICE FOR DETECTING CONSUMPTION OF POWER - An electronic device includes a current detection module, two path switches, a processing unit, and two control circuits. Two terminals of the current detection module are connected to an external power port and a battery. The two path switches are connected to the two terminals. A first control circuit is connected to the processing unit and to one path switch. A second control circuit is connected to the processing unit and to another path switch. When the electronic device is powered on, whether using power from the battery or from the external power port, the device can analyze the power consumed by the functioning parts of the device, including (when power is taken from the external power port) the amount of current taken in charging the battery. | 2014-03-13 |
20140075217 | Power Saving Network Controller - A method and system are provided for reducing power usage in a telecommunications network. An intelligent network manager within a network operations center determines whether to change the power usage of the network, such as reducing power usage at limes of low network activity. The network operations center is in communication with the network elements of the network, and using the communication channels between the network operations center and the network elements the intelligent network manager instructs various ones of the network elements to operate at a lower capacity or even not at all. | 2014-03-13 |
20140075218 | Nonvolatile Logic Array And Power Domain Segmentation In Processing Device - A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device. | 2014-03-13 |
20140075219 | Run-Time Task-Level Dynamic Energy Management - A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator. | 2014-03-13 |
20140075220 | METHOD AND DEVICE OF CONTROLLING POWER SAVING - Disclosed in the present invention are a method and a device for controlling power saving. The method comprises: monitoring an amount of remaining charge in a battery of a mobile device; and automatically adjusting a operation of the mobile device according to the monitored amount of remaining charge of the battery, the automatic adjusting comprising at least one of: changing a current value of a device parameter of the mobile device according to the monitored amount of remaining charge, and determining whether to turn off a user application and/or a device function that is currently active on the mobile device according to the monitored amount of remaining charge, so as to reduce the consumption of electricity from the battery. | 2014-03-13 |
20140075221 | Power Management Method and Apparatus, and Power Supply Method - A power management method and apparatus, and a power supply system are provided. The method includes: obtaining a power demand value of each module and a rated output power of each power supply unit (PSU) in a communication equipment; calculating the obtained power demand value of each module to acquire a total power demand value of the modules; and adjusting, according to the calculated total power demand value of the modules and the obtained rated output power of each PSU, the current number of the PSUs actually turned on in the communication equipment. | 2014-03-13 |
20140075222 | System and Method for Managing Energy Consumption in a Compute Environment - Disclosed are systems and methods of performing a power cap processing in a compute environment. The method includes determining of one of committed resources and dedicated resources in a compute environment exceed a threshold value for a job. If a determination is yes that the threshold value is exceeded, then the method includes preempting processing of the job in the compute environment by performing one of migrating the job to a new compute resources and performing a power reduction action associated with the job, such as slowing down a processor associated with a job or cancelling the job. When such a power state reduction action is taken, reservations associated with other jobs may also be adjusted. | 2014-03-13 |
20140075223 | ELECTRONIC DEVICE WITH POWER MANAGEMENT MECHANISM AND POWER MANAGEMENT METHOD THEREOF - An electronic device with a power management mechanism and a power management method thereof are disclosed. The electronic device includes a multi-core processor and a temperature sensor. The multi-core processor has a plurality of processor cores. The temperature sensor is coupled to the multi-core processor. The temperature sensor detects the temperature of the multi-core processor and determines whether the electronic device enters an underclocking mode from a performance priority mode according to the detected temperature. When the temperature of the multi-core processor is greater than a first temperature threshold, the multi-core processor controls the electronic device to enter a first underclocking mode and dynamically adjusts an enabled core number. When the temperature of the multi-core processor is greater than a second temperature threshold, the multi-core processor controls the electronic device to enter a second underclocking mode. The first temperature threshold is smaller than the second temperature threshold. | 2014-03-13 |
20140075224 | METHOD OF PERFORMING DYNAMIC VOLTAGE AND FREQUENCY SCALING OPERATION, APPLICATION PROCESSOR PERFORMING METHOD, AND MOBILE DEVICE COMPRISING APPLICATION PROCESSOR - A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor, and controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit. | 2014-03-13 |
20140075225 | Non-Volatile Array Wakeup and Backup Sequencing Control - Individual first ones of a plurality of non-volatile logic element arrays are designated to restore first in response to entering a wakeup or restoration mode. These non-volatile logic element arrays include instructions for an order in which other non-volatile logic element arrays are to be restored next. So configured, the processing device can be set to have one or more NVL arrays restored first, which arrays are pre-configured to guide further wakeup of the device through directed restoration from particular NVL arrays. Certain NVL arrays can be skipped if the functions stored therein are not needed, and the order of restoration of others can be tailored to a particular wakeup time and power concern through restoration in parallel, serial, or combinations thereof. | 2014-03-13 |
20140075226 | ULTRA LOW POWER APPARATUS AND METHOD TO WAKE UP A MAIN PROCESSOR - An apparatus and method for waking up a main processor (MP) in a low power or ultra-low power device preferably includes the MP, and a sub-processor (SP) that utilizes less power than the MP to monitor ambient conditions than the MP, and may be internalized in the MP. The MP and SP can remain in a sleep mode while an interrupt sensor monitors for changes in the ambient environment. A sensor is preferably an interrupt-type sensor, as opposed to polling-type sensors conventionally used to detect ambient changes. The MP and SP may remain in sleep mode, as a low-power or an ultra-low power interrupt sensor operates with the SP being in sleep mode, and awakens the SP via an interrupt indicating a detected change. The SP then wakes the MP after comparing data from the interrupt sensor with values in storage or with another sensor. | 2014-03-13 |
20140075227 | CONTROL DEVICE, DATA PROCESSING DEVICE, CONTROLLER, METHOD OF CONTROLLING THEREOF AND COMPUTER-READABLE MEDIUM - A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power. | 2014-03-13 |
20140075228 | PROCESSING DEVICE AND METHOD THEREOF - According to some embodiments, there is provided a communication device including: a processing unit and a notifying unit. The processing unit receives an acquisition request of first information from a requester and determines based on a predetermined condition whether or not the first information needs to be acquired from an acquisition destination of the first information. The notifying unit notifies a first response to the requester when the processing unit determines that the first information needs to be acquired, the first response containing an instruction of transitioning to a low power consumption status. | 2014-03-13 |
20140075229 | LOWEST POWER MODE FOR A MOBILE DRIVE - A hard disk drive enters a low power mode to reduce power consumption. To maintain communication with a host device, a communication interface remains energized along with a circuit portion storing configuration data for the communication interface. To energize the communication interface and the circuit portion, low power voltage regulators provide suitable reference voltages. One low power voltage regulator is dedicated to this purpose. Another voltage regulator is converted from an active, switching mode to a low power, linear mode to provide the necessary reference voltage. Also, unique handshaking signals are used to control entry and exit from the low power mode by the hard disk drive. | 2014-03-13 |
20140075230 | Waking An Electronic Device - Implementations disclosed herein relate to waking an electronic device 107. In one embodiment, an electronic device 107 detects a person within a particular proximity of the electronic device 107 and wakes the electronic device 107 while suppressing an outward indication of the operation of the electronic device 107. The electronic device 107 may then detect a person intending to use the electronic device 107 and therefore exhibit the outward indication of the operation of the electronic device 107. | 2014-03-13 |
20140075231 | MICROCONTROLLER INPUT/OUTPUT CONNECTOR STATE RETENTION IN LOW-POWER MODES - A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode. | 2014-03-13 |
20140075232 | Nonvolatile Logic Array Based Computing Over Inconsistent Power Supply - Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply. | 2014-03-13 |
20140075233 | Customizable Backup And Restore From Nonvolatile Logic Array - Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics. | 2014-03-13 |
20140075234 | ESTIMATING REMAINING USE TIME OF MOBILE COMPUTING DEVICES - Methods, systems, apparatus, and computer programs encoded on computer storage medium, for receiving a set of expected activities, each expected activity in the set of expected activities including an activity that is expected to be performed by a computing device, determining one or more time periods based on the set of expected activities, determining one or more expected rates of change of state of charge (SOC) of a battery of the mobile computing device by, for each time period of the one or more time periods, determining an expected rate of change of SOC based on a base rate of change of SOC and one or more expected activities associated with the time period, and determining an estimated remaining time based on the one or more expected rates of change of SOC, the remaining time corresponding to a time at which an expected SOC is less than a threshold SOC. | 2014-03-13 |
20140075235 | Switch for Clock Synchronization Over A Switched Fabric - Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay, and stores the in-switch delay. Another switch receives a packet from a first device, forwards the packet to a second device, determines an in-switch delay of the packet, and stores the in-switch delay. Storing of in-switch delays may include adding an in-switch delay to values in one or more transaction delay fields of a packet. Storing of in-switch delays may include storing the delays in a storage element of a switch. In-switch delay may be determined as a difference between a receiving time corresponding to reception of a packet and a forwarding or transmittal time corresponding to forwarding or transmitting of a packet. | 2014-03-13 |
20140075236 | MEMORY INTERFACE CIRCUITS INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES - A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes. | 2014-03-13 |
20140075237 | MEMORY SYSTEM USING ASYMMETRIC SOURCE-SYNCHRONOUS CLOCKING - The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant. | 2014-03-13 |
20140075238 | SYSTEM AND METHOD FOR INTELLIGENT TIMER SERVICES - A method is provided for efficiently scheduling timer events within an operating system by allocating a plurality of timers, each of which has an expiry time, to a set of available timer slots. The method defines a timer spread value that denotes the allowed variance of the expiry times of each of the timers, calculates a set of available timer slots for each of the timers based on the timer spread value, and adjusts the expiry times of the timers so as to insert and evenly spread the timers across the set of available timer slots. In one implementation, the set of available timer slots is located in a timer wheel existing within the operating system, and the timer wheel uses a plurality of timer vectors arranged into successively increasing levels, beginning with level zero. | 2014-03-13 |