11th week of 2014 patent applcation highlights part 43 |
Patent application number | Title | Published |
20140073031 | STAR-WORM LUCIFERASE - The present invention relates to a luciferase derived from a star-worm belonging to genus | 2014-03-13 |
20140073032 | BATCHES OF RECOMBINANT ADENOVIRUS WITH ALTERED TERMINAL ENDS - Described is a composition comprising a plurality of recombinant adenovirus particles, being a recombinant human adenovirus of serotype 5, 26, 34, 35, 48, 49 or 50, or a recombinant simian adenovirus, characterized in that the genomes of essentially all adenovirus particles in the composition comprise as the 5′ terminal nucleotides the nucleotide sequence: CTATCTAT (nucleotides 1-8 of SEQ ID NO:7). Also described are methods to produce such compositions. | 2014-03-13 |
20140073033 | METHOD FOR ORTHOPOXVIRUS PRODUCTION AND PURIFICATION - The present invention relates to a method for producing and purifying a wild type, an attenuated and/or a recombinant | 2014-03-13 |
20140073034 | Liquid to Liquid Biological Particle Concentrator with Disposable Fluid Path - Highly efficient and rapid filtration-based concentration devices, systems and methods are disclosed with sample fluidic lines and a filter packaged in a disposable tip which concentrate biological particles that are suspended in liquid from a dilute feed suspension. A sample concentrate or retentate suspension is retained while eliminating the separated fluid in a separate flow stream. The concentrate is then dispensed from the disposable tip in a set volume of elution fluid. Suspended biological particles include such materials as proteins/toxins, viruses, DNA, and/or bacteria in the size range of approximately 0.001 micron to 20 microns diameter. Concentration of these particles is advantageous for detection of target particles in a dilute suspension, because concentrating them into a small volume makes them easier to detect. All conduits by which the disposable tip attaches to the instrument are combined into a single connection point on the upper end of the tip. | 2014-03-13 |
20140073035 | PHOTOBIOREACTOR IN A CLOSED ENVIRONMENT FOR THE CULTURE OF PHOTOSYNTHETIC MICROORGANISMS - The present invention relates to a photobioreactor intended for the notably continuous culture of photosynthetic microorganisms, preferably microalgae, comprising at least one culture enclosure ( | 2014-03-13 |
20140073036 | STABLE LIQUID MANUAL DISHWASHING COMPOSITIONS CONTAINING ENZYMES - Liquid stable enzyme compositions and methods of employing the same for cleaning, including warewashing and dishwashing, are disclosed. The stable enzyme compositions preferably employ an amphoteric surfactant stabilizing agent, such as disodium camphodiacetate (CADA), to stabilize a mixture of traditionally unstable enzymes, such as proteases and lipases. | 2014-03-13 |
20140073037 | METHOD FOR EXTRACTING SQUALENE FROM MICROALGAE - The invention relates to a method for extracting, without using an organic solvent, squalene produced by fermenting microalgae belonging to the Thraustochytriales sp. family, characterised in that it includes the following steps: 1) preparing a biomass of microalgae belonging to the Thraustochytriales family so as to reduce the concentration of interstitial soluble matter, and to thereby achieve a purity of 30 to 99% expressed as the dry weight of biomass over the total dry weight of the fermentation medium; 2) treating the resulting biomass using a protease enzyme selected from the group of neutral or basic proteases, so as to break the cell wall of said microalgae while preventing the formation of the emulsion produced by said enzyme treatment; 3) centrifuging the resulting reaction mixture in order to separate the oil from the aqueous phase; and 4) recovering the thus-produced crude oil rich in squalene. | 2014-03-13 |
20140073038 | METHOD AND SYSTEMS FOR ENHANCING OIL RECOVERY FROM ETHANOL PRODUCTION BYPRODUCTS - In one aspect of the invention, a method recovers oil from a concentrated byproduct, such as evaporated thin stillage formed during a dry milling process used for producing ethanol. The method includes forming a concentrate from the byproduct and recovering oil from the concentrate. The step of forming the concentrate may comprise evaporating the byproduct. Further, the step of separating the oil from the concentrate may comprise using a centrifuge and, in particular, a disk stack centrifuge. Other aspects of the invention include related methods and subsystems for recovering oil from thin stillage. | 2014-03-13 |
20140073039 | DIRECT SENSING BIOFETS AND METHODS OF MANUFACTURE - The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a plurality of micro wells having a sensing gate bottom and a number of stacked well portions. A bottom surface area of a well portion is different from a top surface area of a well portion directly below. The micro wells are formed by multiple etching operations through different materials, including a sacrificial plug, to expose the sensing gate without plasma induced damage. | 2014-03-13 |
20140073040 | System And Method For Interfacing Sensors To A Sterile Flow Stream - A system and method for interfacing non-sterile sensors to a sterile flow stream is disclosed. Typically, sensors cannot be sterilized in the same manner as other components of the flow stream. This results in complex processes to incorporate a sterilized sensor into a sterilized flow stream. By introducing a separation membrane, the desired sensor can be interfaced to the sterile flow stream. By doing so, the sensor need not be sterile, only sufficiently clean. The membrane separates the sterile environment within the flow stream from the sensor, while still permitting the sensor to function. | 2014-03-13 |
20140073041 | ANALYZING DEVICE - A feature of an analyzing device is that a peeling portion ( | 2014-03-13 |
20140073042 | FLUIDIC DEVICE, CHEMICAL REACTION SYSTEM, AND NUCLEIC-ACID ANALYZING SYSTEM - A fluidic device in which a first member and a second member are connected by an expanding member is provided. The fluidic device includes a first member having a fluid channel communicating with an opening; and a second member having a supply channel supplying a fluid to the fluid channel through the opening. An expanding member having a through-hole is fit into the opening, the fluid channel and the supply channel communicate with each other through the through-hole in the expanding member, and the first member and the second member are connected to each other with at least the expanding member being in an expanded state. | 2014-03-13 |
20140073043 | SYSTEMS AND METHODS FOR MULTI-ANALYSIS - Systems and methods are provided for sample processing. A device may be provided, capable of receiving the sample, and performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing multiple assays. The device may comprise one or more modules that may be capable of performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing the steps using a small volume of sample. | 2014-03-13 |
20140073044 | STRIPPING ABSORPTION MODULE - In a process, a portion of a liquid mixture flow is vaporized to produce a vapor and a depleted flow of liquid. The vapor is introduced to a brine which is adapted to exothermically absorb one or more components therefrom, and heat is withdrawn, to produce at least a flow of heat and a flow of brine which is enriched in the one or more components. The heat previously withdrawn is transferred, to drive the vaporization. This transfer can be associated with the change of a working fluid from a gaseous into a liquid state. In this case, the heat withdrawal involves the change of the working fluid from the liquid to the gaseous state. In the liquid state, the working fluid flows only by one or more of gravity, convection and wicking. In the gaseous state, the working fluid flows only by one or more of diffusion and convection. | 2014-03-13 |
20140073045 | MUCIN ANTIGEN VACCINE - Provided are expression vectors for generating an immune response to a mucin. The vectors comprise a transcription unit encoding a secretable polypeptide, the polypeptide comprising a secretory signal, a mucin antigen and CD40 ligand. Also provided are methods of generating an immune response against cells expressing a mucin by administering an effective amount of the vector. Further provided are methods of generating an immune response against cancer cells expressing a mucin in an individual by administering an effective amount of the vector. Still further provided are methods of overcoming anergy to a mucin self antigen by administering an effective amount of the vector. | 2014-03-13 |
20140073046 | Cell Populations Which Co-Express CD49C and CD90 - Substantially homogenous cells populations which co-express CD49c, CD90 and telomerase are made. In one embodiment, humans suffering from a degenerative, traumatic, acute injury, cardiac or neurological condition are treated with the substantially homogenous cells populations which co-express CD49c, CD90 and telomerase. In another embodiment, committed progenitor cells are made are made by selecting from a cultured source of a cell population which co-express CD49c and CD90 and modifying the cell population. The committed progenitor cells can be employed to treat a human suffering from a degenerative, traumatic, acute injury, cardiac or neurological condition and formulate pharmaceutical compositions. | 2014-03-13 |
20140073047 | Connective Tissue Growth Factor Antibodies - The present invention relates to antibodies that bind to CTGF. The antibodies are particularly directed to regions of CTGF involved in biological activities associated with fibrosis. The invention also relates to methods of using the antibodies to treat disorders associated with CTGF including localized and systemic fibrotic disorders including those of the lung, liver, heart, skin, and kidney. | 2014-03-13 |
20140073048 | LOW MOLECULAR WEIGHT BRANCHED POLYAMINES FOR DELIVERY OF BIOLOGICALLY ACTIVE MATERIALS - A branched polyamine comprises about 8 to about 12 backbone tertiary amine groups, about 18 to about 24 backbone secondary amine groups, a positive number n′ greater than 0 of backbone terminating primary amine groups, and a positive number q greater than 0 of backbone terminating carbamate groups of formula (2): | 2014-03-13 |
20140073049 | INDUCED PLURIPOTENT STEM CELLS PREPARED FROM HUMAN KIDNEY-DERIVED CELLS - We have disclosed an induced pluripotent stem cell and the method of preparing the induced pluripotent stem cell from a human kidney-derived cell. More particularly, we have disclosed a human kidney-derived iPS cell which may be differentiated into cells of ectoderm, mesoderm, and endoderm lineages. | 2014-03-13 |
20140073050 | METHOD FOR ACTIVATION TREATMENT OF ANTIGEN-PRESENTING CELL - Activated antigen-presenting cells that can induce immunocytes including disease antigen-specific CD8+ CTLs and/or γδ T cells efficiently in vivo and/or in vitro, a medical composition comprising the activated antigen-presenting cells, a treatment and prevention method using the activated antigen-presenting cells, and an induction method of immunocytes including disease antigen-specific CTLs and/or γδ T cells induced using the activated antigen-presenting cell, immunocytes induced by the above-noted method, a medical composition comprising the immunocytes, and a treatment and prevention method using the immunocytes are provided. By co-pulsing antigen-presenting cells with bisphosphonate in addition to the pulse with a disease antigen, the ratio of disease antigen-specific CD8+ CTLs and/or γδ T cells and the number of the disease antigen-specific CD8+ CTLs and the γδ T cells can be increased, compared with the case where the co-pulse with bisphosphonate is not carried out. | 2014-03-13 |
20140073051 | METHOD FOR PRODUCING SHEET-LIKE PANCREATIC ISLET - The present invention provides a method of producing a sheet-like pancreatic islet, comprising culturing an isolated pancreatic islet in a culture vessel, wherein a polypeptide comprising an EC1 domain of E-cadherin and having a binding ability to said E-cadherin is fixed on or applied to a surface of a solid phase, while being adhered to the solid phase surface for a period sufficient for the pancreatic islet to take a sheet-like form. | 2014-03-13 |
20140073052 | MODULATION OF GRANULOSA CELL APOPTOSIS - The present invention relates to a method of modulating apoptosis of a granulosa cell. The method includes one or more of the following steps: (i) modulating the concentration and/or activity of BMP-15 and/or BMP-6 that the granulosa cell is exposed to; (ii) modulating activity of a BMP-15 dependent signalling pathway in the granulosa cell; and (iii) modulating activity of a BMP-6 dependent signalling pathway in a granulosa cell. | 2014-03-13 |
20140073053 | METHODS FOR TRANSFECTING CELLS WITH NUCLEIC ACIDS - The present disclosure provides culture media and methods of using culture media for efficient transfection of a target cell with nucleic acid molecules. The media is capable of supporting cells in culture that are differentiating, transdifferentiating, and/or dedifferentiating. | 2014-03-13 |
20140073054 | RECOMBINANT THERMOTOLERANT YEAST WITH A SUBSTITUTE HEAT SHOCK PROTEIN 104 PROMOTER - The invention provides a yeast strain and a method for making the same. The method has the step of replacing the regulation region upstream of the hsp104 gene in the genome of the yeast, so as to accelerate and prolong the expression span of hsp104 gene and enhance the capability of the yeast to ferment and produce ethanol in a high-temperature environment. The yeast is capable of fermenting glucose at a temperature higher than 42° C. to produce ethanol, or biomass ethanol, wherein the ethanol production ratio based on fermentation of glucose is higher than 97%. Being able to synchronize the degradation/hydrolysis stage and fermentation stage of biomass ethanol producing process, the yeast in accordance with the present invention is able to lower the production cost of biomass ethanol and further raise the productivity with its high ethanol production ratio. | 2014-03-13 |
20140073055 | NANOVOLUME MICROCAPILLARY CRYSTALLIZATION SYSTEM - A nanovolume microcapillary crystallization system allows nanoliter-volume screening of crystallization conditions in a crystal card that allows crystals to either be removed for traditional cryoprotection or in situ X-ray diffraction studies on protein crystals that grow within. The system integrates formulation of crystallization cocktails with preparation of the crystallization experiments. The system allows the researcher to select either gradient screening in crystallization experiments for efficient exploration of crystallization phase space or a combination of sparse matrix with gradient screening to execute one comprehensive hybrid crystallization trial. | 2014-03-13 |
20140073056 | METHOD FOR IDENTIFYING GAMBIERED GUANGDONG SILK - A method for identifying gambiered Guangdong silk includes the steps of: detecting the surface state of fiber by microscope; detecting the pyrolysis fragments of fabrics by pyrolysis gas chromatography; determining the crude protein content in the fiber by Kjeldahl determination; and detecting the dye component of the fabrics by high performance liquid chromatography. The method of the present invention can accurately identify the true and fake, good and bad of the gambiered Guangdong silk, and then make an accurate evaluation on the gambiered Guangdong silk; and the present invention is simple, useful, environmental and has low cost. | 2014-03-13 |
20140073057 | PROCESS AND MARKERS FOR THE DIAGNOSIS OF KIDNEY DISEASES - A process for the diagnosis of kidney diseases comprising the step of determining the presence or absence or amplitude of at least three polypeptide markers in a urine sample, the polypeptide markers being selected from the markers characterized in Table 1 by values for the molecular masses and migration times. | 2014-03-13 |
20140073058 | Methods of Using Dyes in Association with Nucleic Acid Staining or Detection and Associated Technology - Methods of using dyes and associated technology are provided. A dye, such as a monomeric dye or a dimeric dye, may be used in a nucleic acid gel staining application and/or a nucleic acid detection application. Such a dye and a salt that comprises an anion that is associated with a strong acid and a cation that is associated with a strong base may be used in such an application. A dimeric dye, such as a dimeric dye capable of forming a hairpin-like structure, may be used to stain and/or detect nucleic acids via a release-on-demand mechanism. A dimeric dye having low background fluorescence in the absence of nucleic acids and high fluorescence in the presence of nucleic acids, upon binding therewith, may be used to stain and/or detect nucleic acids. | 2014-03-13 |
20140073059 | Azide Substituted Naphthylene or Rylene Imide Derivatives and their Use as Reagents in Click-Reactions - Novel mono-azide substituted rylene-imide derivatives, their use in methods for the detection of analytes and reagents kits for the detection of analytes comprising said novel mono-azide substituted rylene-imide derivatives. | 2014-03-13 |
20140073060 | CONTROL OVER HYDROGEN FLUORIDE LEVELS IN OXIDE ETCHANT - The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe. | 2014-03-13 |
20140073061 | URINE GENDER TEST KIT - A kit and methods for determining the gender of an unborn fetus. The kit comprises a container holding a solid composition therein, the solid composition including a basic salt and a transition metal separated by a filler and in which an atmosphere in the container is substantially free of water. | 2014-03-13 |
20140073062 | SPECIMEN SOLUTION ASSAY DEVICE, SPECIMEN SOLUTION ASSAY METHOD, AND IMMUNOCHROMATOGRAPHIC SENSOR DEVICE - A specimen solution assay device includes a specimen solution dropping device which drops a specimen solution sequentially onto each of sample pads of immunochromatographic sensors positioned adjacent to each other in a transverse direction of each of the immunochromatographic sensors, and an image information acquisition device which acquires image information of a test area of each of the immunochromatographic sensors onto which the specimen solution is dropped by the specimen solution dropping device. | 2014-03-13 |
20140073063 | METHODS AND SYSTEMS FOR SCAFFOLDS COMPRISING NANOELECTRONIC COMPONENTS - The present invention generally relates to nanoscale wires and tissue engineering. Systems and methods are provided in various embodiments for preparing cell scaffolds that can be used for growing cells or tissues, where the cell scaffolds comprise nanoscale wires. In some cases, the nanoscale wires can be connected to electronic circuits extending externally of the cell scaffold. Such cell scaffolds can be used to grow cells or tissues which can be determined and/or controlled at very high resolutions, due to the presence of the nanoscale wires, and such cell scaffolds will find use in a wide variety of novel applications, including applications in tissue engineering, prosthetics, pacemakers, implants, or the like. This approach thus allows for the creation of fundamentally new types of functionalized cells and tissues, due to the high degree of electronic control offered by the nanoscale wires and electronic circuits. | 2014-03-13 |
20140073064 | MAGNETIC TUNNEL JUNCTION (MTJ) ON PLANARIZED ELECTRODE - A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ. | 2014-03-13 |
20140073065 | MICROWAVE ANNEALING APPARATUS AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to one embodiment, a microwave annealing apparatus is provided, including a housing shielding electromagnetic waves, a first electromagnetic wave source configured to apply a first electromagnetic wave into the housing, a second electromagnetic wave source configured to apply, into the housing, a second electromagnetic wave having a higher frequency than the first electromagnetic wave, a susceptor configured to hold a semiconductor substrate, made of a material transparent to the first electromagnetic wave and provided in the housing, a temperature measuring device configured to measure the temperature of the semiconductor substrate, and a control unit configured to control the power of each of the first and second electromagnetic wave sources in accordance with the temperature measured by the temperature measuring device. | 2014-03-13 |
20140073066 | PLASMA ETCHING APPARATUS AND CONTROL METHOD - In a control method, a first processing is performed on an object to be processed by controlling a temperature of a base to a first temperature and controlling a temperature of an electrostatic chuck that is disposed on a mounting surface of the base so as to mount thereon the object to be processed and has a heater installed therein to a second temperature. A second processing is performed on the object by controlling a temperature of the base to a third temperature and controlling a temperature of the electrostatic chuck to a fourth temperature by a heater. In the control method, a difference between the first temperature and the second temperature and a difference between the third temperature and the fourth temperature are within a tolerable temperature of the junction layer for bonding the base and the electrostatic chuck. | 2014-03-13 |
20140073067 | WAFER PROCESSING METHOD - A wafer processing method divides a wafer along a plurality of crossing streets formed on the front side of the wafer to thereby partition a plurality of regions where a plurality of devices are respectively formed. The method includes a division groove forming step of cutting the back side of the wafer along each street by using a cutting blade to thereby form a division groove along each street with a predetermined thickness left between the bottom of the division groove and the front side of the wafer, a wafer supporting step of attaching the back side of the wafer to a dicing tape supported by an annular frame, and a wafer dividing step of applying an external force to the wafer attached to the dicing tape to thereby divide the wafer into the individual devices along the streets where the division grooves are respectively formed. | 2014-03-13 |
20140073068 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition. | 2014-03-13 |
20140073069 | ETCHING METHOD, ETCHING APPARATUS AND CHEMICAL SOLUTION - An etching method according to an embodiment, includes performing etching on a material having tungsten (W) as a main component by using as an etchant a chemical solution having hydrogen peroxide as a main component. The chemical solution contains 12 ppm or more and 100,000 ppm or less of W. | 2014-03-13 |
20140073070 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SUPPORTING SUBSTRATE, AND SEMICONDUCTOR MANUFACTURING APPARATUS - A method for fabricating a semiconductor device comprising: a first process for attaching a first supporting substrate having a plurality of through holes to a semiconductor substrate having a first surface and a second surface, so that each of the through holes is opposed to a semiconductor device formed in the semiconductor substrate; a second process for contacting probes of an electric characteristic inspection apparatus with a first electrode formed on the first surface, and a second electrode formed on the second surface via the through hole; and a third process for measuring electric characteristic of the semiconductor device. | 2014-03-13 |
20140073071 | RFID INTEGRATED CIRCUITS WITH ANTENNA CONTACTS ON MULTIPLE SURFACES - Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other. | 2014-03-13 |
20140073072 | METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY - A method of manufacturing an organic light emitting diode (OLED) display according to an exemplary embodiment includes: forming a diplay unit displaying an image and a driver positioned near the display unit to drive a light emitting element of the display unit in a lower mother substrate; forming a sealant and a plurality of bumps in an upper mother substrate; aligning the lower mother substrate and the upper mother substrate to face each other; melting and hardening the sealant to combine the lower mother substrate and the upper mother substrate; cutting the upper mother substrate; and cutting the lower mother substrate, wherein the cutting of the upper mother substrate is performed according to a first cutting line between the sealant and the bumps and a second cutting line corresponding to the bumps. | 2014-03-13 |
20140073073 | MOLD FOR NANO-IMPRINTING, METHOD FOR FORMING DIFFRACTION GRATING, AND METHOD FOR PRODUCING OPTICAL DEVICE INCLUDING DIFFRACTION GRATING - A method for forming a diffraction grating includes the steps of preparing a mold including a pattern portion having a pattern for forming a diffraction grating; forming a first semiconductor layer on a substrate; forming a resin layer on the first semiconductor layer; pressing the pattern portion of the mold against the resin layer; forming the pattern for the diffraction grating in the resin layer by curing the resin layer; and forming the diffraction grating in the first semiconductor layer by etching the first semiconductor layer using the patterned resin layer. The mold includes a first base and a plurality of second bases disposed on the first base. The first base is made of a flexible material. The second base is made of a rigid material. The plurality of second bases each include the pattern portion and are spaced apart from each other with a predetermined distance. | 2014-03-13 |
20140073074 | DISTORTION TOLERANT PIXEL DESIGN - A method of manufacturing a flexible display is provided, which includes depositing a first layer comprising a plurality of thin film transistors (TFTs) on a flexible substrate and depositing a second layer comprising a plurality of pixel electrodes above the first layer with each pixel electrode connected to a respective TFT via a respective via connector between the first and second layers. A display medium responsive to signals on the pixel electrode can be deposited on the second layer for displaying an image on the second layer. A third layer comprising colour filters for filtering an image displayed on the display medium can be aligned to the second layer. The third layer can be deposited and aligned on the second layer such that each colour filter is substantially aligned to a respective pixel electrode to compensate for distortions in the first layer caused by distortions in the flexible substrate. | 2014-03-13 |
20140073075 | METHOD FOR SEPARATING LIGHT-EMITTING DIODE FROM A SUBSTRATE - A method for separating a light-emitting diode (LED) from a substrate comprises the following steps. First, a substrate is provided which includes a junction surface and a bottom surface far away from the junction surface. Then a plurality holes are formed on the junction surface. An LED structure is further grown on the junction surface, and includes a junction portion bonded to the junction surface. The bottom surface is then polished to be shrunk to communicate with the holes. Finally, the junction portion is etched by an etching liquid via the holes to separate the LED structure from the substrate. Accordingly, by forming the holes, the LED structure and the substrate can be separated through polishing and etching processes, thereby providing a high yield rate as well as reduced production costs. | 2014-03-13 |
20140073076 | STABLE BLUE PHOSPHORESCENT ORGANIC LIGHT EMITTING DEVICES - Novel combination of materials and device architectures for organic light emitting devices are provided. In some aspects, specific charge carriers and solid state considerations are features that may result in a device having an unexpectedly long lifetime. In some aspects, emitter purity is a feature that may result in devices having unexpectedly long lifetime. In some aspects, structural and optical considerations are features that may result in a device having an unexpectedly long lifetime. In some aspects, an emissive layer including an organic phosphorescent emissive dopant and an organic carbazole host material results in devices having an unexpectedly long lifetime. | 2014-03-13 |
20140073077 | METHOD FOR EPITAXIAL GROWTH OF LIGHT EMITTING DIODE - A method for epitaxial growth of a light emitting diode, includes following steps: providing a substrate; forming a buffer layer on the substrate; forming a first epitaxial layer on the buffer layer in a first temperature; forming a second epitaxial layer on the first epitaxial layer in a second temperature lower than the first temperature, thereby forming a first rough surface on the second epitaxial layer; etching the second epitaxial layer and the first epitaxial layer until a second rough surface is formed on the first epitaxial layer; forming a mask layer on the rough surface of the first epitaxial layer; partly etching the mask layer to form a plurality of protrusions with the first epitaxial layer exposed thereamong; and forming an N-type epitaxial layer, an active layer and a P-type epitaxial layer on the first epitaxial layer in sequence. | 2014-03-13 |
20140073078 | DEVICE FOR CONVERTING ENERGY AND METHOD FOR MANUFACTURING THE DEVICE, AND ELECTRONIC APPARATUS WITH THE DEVICE - The present invention provides an energy converting device, which includes: a base substrate; and a plurality of thermoelectric element structures which are sequentially stacked on the base substrate and electrically interconnected in parallel to one another. | 2014-03-13 |
20140073079 | CAMERA MODULE AND METHOD OF MANUFACTURING THE CAMERA MODULE - A camera module includes an image sensor chip including a substrate having first and second opposite surfaces and a ground pad on the first surface, a housing surrounding the sides of the image sensor chip but which leaves the second surface of the image sensor chip exposed, an electromagnetic wave-shielding film united with the housing, and an electrical conductor electrically connected to the ground pad. The camera module also has an optical unit disposed on the first surface of the image sensor chip in the housing to guide light from an object to the image sensor chip. The electrical conductor extends through a side of the housing. The conductor also contacts the electromagnetic wave-shielding film to electrically connect the ground pad and the electromagnetic wave-shielding film. | 2014-03-13 |
20140073080 | Back Side Defect Reduction for Back Side Illuminated Image Sensor - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystallized silicon layer is formed on the back side of the substrate. The recrystallized silicon layer has different photoluminescence intensity than the substrate. | 2014-03-13 |
20140073081 | Solar Cell Having Selective Emitter - The present invention provides a solar cell having a selective emitter structure on a doped silicon substrate. The silicon substrate is mono-crystalline or multi-crystalline. A plurality of trenches are formed at the illuminated side of the silicon substrate. After one-time diffusion doping, the silicon substrate is processed through selective etching. The region outside the trenches obtains a lower doping concentration, while the region of the trenches remains to be highly doped. Thus, a selective emitter structure is formed. | 2014-03-13 |
20140073082 | METHOD OF MANUFACTURING LIGHT - ABSORBTION LAYER OF SOLAR CELL THROUGH SELENIZATION PROCESS UNDER ELEMENTAL SELENIUM VAPOR ATMOSPHERE AND THERMAL PROCESSING APPARATUS FOR MANUFACTURING LIGHT - ABSORBING LAYER - The method of manufacturing a light absorbing layer for a solar cell by performing thermal treatment on a specimen configured to include thin films of one or more of copper, indium, and gallium on a substrate and element selenium, includes steps of: (a) heating a wall of a chamber up to a predefined thin film formation temperature in order to maintain a selenium vapor pressure; (b) mounting the specimen and the element selenium on the susceptor at the room temperature and loading the susceptor in the chamber; and (c) heating the specimen in the lower portion of the susceptor and, at the same time, heating the element selenium in the upper portion of the susceptor, wherein, in the step (c), in order for liquefied selenium not to be condensed on the specimen which is loaded at the room temperature and is not yet heated, the temperature of the element selenium and the specimen loaded in the chamber are individually controlled, so that the selenium vapor pressure of an inner space of the chamber does not exceed a saturation vapor pressure corresponding to the temperature of the specimen. | 2014-03-13 |
20140073083 | MANUFACTURING METHOD FOR SOLAR CELL - A manufacturing method for a solar cell having improved output characteristics is provided. After forming a p-side transparent conductive oxide layer ( | 2014-03-13 |
20140073084 | Methods of Forming Phase Change Materials and Methods of Forming Phase Change Memory Circuitry - A method of forming a phase change material which having germanium and tellurium therein includes depositing a germanium-containing material over a substrate. Such material includes elemental-form germanium. A gaseous tellurium-comprising precursor is flowed to the germanium-comprising material and tellurium is removed from the gaseous precursor to react with the elemental-form germanium in the germanium-comprising material to form a germanium and tellurium-comprising compound of a phase change material over the substrate. Other implementations are disclosed. | 2014-03-13 |
20140073085 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region using an oxide semiconductor layer, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer. | 2014-03-13 |
20140073086 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to −40° C., still preferably lower than or equal to −50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured. | 2014-03-13 |
20140073087 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: providing a substrate having opposite first and second surfaces and a plurality of conductive through holes penetrating the first and second surfaces, disposing the substrate on a first carrier through the second surface thereof, and keeping the first carrier flat and free of warpage; attaching at least a first semiconductor chip to the first surface of the substrate and electrically connecting the first semiconductor chip and the substrate; removing the first carrier; and attaching the substrate to a packaging substrate through the second surface thereof and electrically connecting the substrate and the packaging substrate, thereby preventing the semiconductor package from warpage, increasing product yield, reducing fabrication cost, and improving thermal dissipation. | 2014-03-13 |
20140073088 | ELECTRONIC COMPONENT MOUNTING LINE AND ELECTRONIC COMPONENT MOUNTING METHOD - Disclosed is an electronic component mounting line on which a substrate undergoes solder paste printing, electronic component placements, and then reflow, while being moved from upstream to downstream. The line includes: a substrate feeding machine; a printing machine for applying solder paste to a first placement area of the substrate; a first electronic component placement machine for placing a first electronic component on the first placement area; a second electronic component placement machine for dispensing a thermosetting resin onto a reinforcement position on a peripheral edge portion of a second placement area of the substrate, and for placing on the area the second electronic component having solder bumps; and a reflow machine for bonding the electronic components to the substrate, by heating and cooling the resultant. The second electronic component is placed after the resin is dispensed, such that a peripheral edge portion thereof comes in contact with the resin. | 2014-03-13 |
20140073089 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip. | 2014-03-13 |
20140073090 | SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC INSULATING FILM AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film. | 2014-03-13 |
20140073091 | Packages with Passive Devices and Methods of Forming the Same - A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM. | 2014-03-13 |
20140073092 | RECESSED SINGLE CRYSTALLINE SOURCE AND DRAIN FOR SEMICONDUCTOR-ON-INSULATOR DEVICES - After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer. | 2014-03-13 |
20140073093 | SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION - Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer. | 2014-03-13 |
20140073094 | METHOD OF FORMING LOW-RESISTANCE WIRE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE SAME - This document relates to a method of forming low-resistance metal gate and data wirings and a method of manufacturing a thin film transistor using the same. The method of the wiring includes depositing a metal layer on a base layer; exposing a portion of the base layer by removing a portion of the metal layer; forming grooves in the base layer; forming a seed layer in the grooves of the base layer; and forming a wire consisting of the seed layer and a plated layer by plating a plating material on the seed layer formed in the grooves of the base layer. | 2014-03-13 |
20140073095 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one of lower crystallinity and relaxed crystal structure as compared to the second compound semiconductor layer. The gate electrode is disposed over the third compound semiconductor layer. Source and drain electrodes are disposed over the second compound semiconductor layer. The two-dimensional carrier gas layer is generated in the first compound semiconductor layer. The two-dimensional carrier gas layer is adjacent to the first interface. The two-dimensional carrier gas layer either is absent under the third compound semiconductor layer or is reduced in at least one of thickness and carrier gas concentration under the third compound semiconductor layer. | 2014-03-13 |
20140073096 | METHOD OF DUAL EPI PROCESS FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material. | 2014-03-13 |
20140073097 | METHOD OF DUAL EPI PROCESS FOR SEMICONDCUTOR DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material. | 2014-03-13 |
20140073098 | METHOD FOR FORMING A SCHOTTKY BARRIER DIODE INTEGRATED WITH A TRENCH MOSFET - A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode. | 2014-03-13 |
20140073099 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a vertical channel and includes a first tunnel insulating layer adjacent to a blocking insulating layer, a third tunnel insulating layer adjacent to a channel pillar, and a second tunnel insulating layer between the first and third tunnel insulating layers. The energy band gap of the third tunnel insulating layer is smaller than that of the first tunnel insulating layer and is larger than that of the second tunnel insulating layer. | 2014-03-13 |
20140073100 | Methods Of Forming A Vertical Transistor, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 2014-03-13 |
20140073101 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall. | 2014-03-13 |
20140073102 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench. | 2014-03-13 |
20140073103 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes providing a dummy gate insulation film formed on a substrate, the dummy gate insulation film including a first material and providing a spacer formed at least one side of the gate insulation film, the spacer including the first material, removing the first material included in the dummy gate insulation film by a first process, removing the dummy gate insulation film from which the first material has been removed by a second process different from the first process, and sequentially forming a gate insulation film and a gate electrode structure on the substrate. | 2014-03-13 |
20140073104 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole. | 2014-03-13 |
20140073105 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH ION IRRADIATION - According to one embodiment, a method of manufacturing a semiconductor device is provided. An impurity layer containing impurity atoms is formed on a semiconductor layer. The impurity layer is then irradiated with first ions having a first energy. Further, the impurity layer is irradiated with second ions having a second energy larger than the first energy. | 2014-03-13 |
20140073106 | LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY - A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process. | 2014-03-13 |
20140073107 | Atomic Layer Deposition of Metal Oxide Materials for Memory Applications - Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells. | 2014-03-13 |
20140073108 | METHODS FOR FORMING RESISTANCE RANDOM ACCESS MEMORY STRUCTURE - A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other. | 2014-03-13 |
20140073109 | FABRICATING METHOD OF SHALLOW TRENCH ISOLATION STRUCTURE - A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure. | 2014-03-13 |
20140073110 | METHOD FOR FABRICATING A TRENCH STRUCTURE, AND A SEMICONDUCTOR ARRANGEMENT COMPRISING A TRENCH STRUCTURE - A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure. | 2014-03-13 |
20140073111 | Method of Forming Isolation Structure - The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench. | 2014-03-13 |
20140073112 | METHOD FOR PERMANENTLY BONDING WAFERS - A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate. The method comprises:
| 2014-03-13 |
20140073113 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS - A plasma etching method deposits a silicon-containing deposit by a plasma processing using a Si-containing gas on an object to be processed that includes a film to be processed, an organic film formed in a plurality of narrow linear portions on the film to be processed, and a rigid film that covers both the film to be processed which is exposed between the linear portions and the linear portions. In the plasma etching method, each of the plurality of narrow linear portions of the organic film and the film to be processed between the linear portions are exposed by etching the silicon-containing deposit by plasma of CF-based gas and CHF-based gas after the silicon-containing deposit is deposited. | 2014-03-13 |
20140073114 | IN-SITU ACTIVE WAFER CHARGE SCREENING BY CONFORMAL GROUNDING - Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material. | 2014-03-13 |
20140073115 | METHOD OF MANUFACTURING LARGE AREA GALLIUM NITRIDE SUBSTRATE - A method of manufacturing a large area gallium nitride (GaN) substrate includes forming a buffer layer on a silicon substrate, forming an insulation layer pattern on a rim of a top surface of the buffer layer, growing a GaN layer on the buffer layer, and removing the insulation layer pattern and a portion of the GaN layer and the silicon substrate. | 2014-03-13 |
20140073116 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate including a first layer having first conductivity type, a second layer having second conductivity type, and a third layer having the first conductivity type is formed. A trench provided with an inner surface having a side wall surface and a bottom surface is formed, the side wall surface extending through the third layer and the second layer and reaching the first layer, the bottom surface being formed of the first layer. A silicon film is formed to cover the bottom surface. A gate oxide film is formed on the inner surface by oxidation in the trench. The gate oxide film includes a first portion formed by oxidation of the silicon carbide substrate, and a second portion formed by oxidation of the silicon film on the bottom surface. Accordingly, a method for manufacturing a silicon carbide semiconductor device having a high breakdown voltage is provided. | 2014-03-13 |
20140073117 | GROWTH REACTOR SYSTEMS AND METHODS FOR LOW-TEMPERATURE SYNTHESIS OF NANOWIRES - A method for synthesis of silicon nanowires provides a growth reactor having a decomposition zone and a deposition zone. A precursor gas introduced into the decomposition zone is disassociated to form an activated species that reacts with catalyst materials located in the deposition zone to deposit nano-structured materials on a low melting point temperature substrate in the deposition zone. A decomposition temperature in the decomposition zone is greater than a melting point temperature of the low melting point temperature substrate. The silicon nanowire are grown directly on the low melting point temperature substrate in the deposition zone to prevent the higher temperatures in the decomposition zone from damaging the molecular structure and/or integrity of the lower melting point temperature substrate located in the deposition zone. | 2014-03-13 |
20140073118 | NITRIDE SEMICONDUCTOR - To provide a high-quality nitride semiconductor ensuring high emission efficiency of a light-emitting element fabricated. In the present invention, when obtaining a nitride semiconductor by sequentially stacking a one conductivity type nitride semiconductor part, a quantum well active layer structure part, and a another conductivity type nitride semiconductor part opposite the one conductivity type, the crystal is grown on a base having a nonpolar principal nitride surface, the one conductivity type nitride semiconductor part is formed by sequentially stacking a first nitride semiconductor layer and a second nitride semiconductor layer, and the second nitride semiconductor layer has a thickness of 400 nm to 20 μm and has a nonpolar outermost surface. By virtue of selecting the above-described base for crystal growth, an electron and a hole, which are contributing to light emission, can be prevented from spatial separation based on the QCSE effect and efficient radiation is realized. Also, by setting the thickness of the second nitride semiconductor layer to an appropriate range, the nitride semiconductor surface can avoid having extremely severe unevenness. | 2014-03-13 |
20140073119 | DEFECT FREE STRAINED SILICON ON INSULATOR (SSOI) SUBSTRATES - A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer. | 2014-03-13 |
20140073120 | METHOD OF FABRICATING GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICE - Exemplary embodiments of the present invention disclose a method of fabricating a gallium nitride (GaN) based semiconductor device. The method includes growing GaN based semiconductor layers on a first surface of a GaN substrate to form a semiconductor stack, and separating at least a first portion of the GaN substrate from the semiconductor stack using a wire cutting technique. | 2014-03-13 |
20140073121 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection. | 2014-03-13 |
20140073122 | METHOD FOR FORMING ULTRA-SHALLOW BORON DOPING REGIONS BY SOLID PHASE DIFFUSION - A method for forming an ultra-shallow boron dopant region in a substrate is provided. In one embodiment, the method includes depositing, by atomic layer deposition (ALD), a boron dopant layer in direct contact with the substrate, where the boron dopant layer contains an oxide, a nitride, or an oxynitride formed by alternating gaseous exposures of a boron amide precursor and a reactant gas. The method further includes patterning the dopant layer and forming an ultra-shallow dopant region in the substrate by diffusing boron from the boron dopant layer into the substrate by a thermal treatment. | 2014-03-13 |
20140073123 | Method for Producing a Controllable Semiconductor Component - Disclosed is a method for producing a controllable semiconductor component. In a semiconductor body with a top side and a bottom side, a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body are formed in a common etching process. The first trench has a first width and the second trench has a second width greater than the first width. Then, in a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. Subsequently, the oxide layer is removed from the first trench completely or at least partly such that the semiconductor body comprises an exposed first surface area arranged in the first trench. | 2014-03-13 |
20140073124 | EDGE DEVICES LAYOUT FOR IMPROVED PERFORMANCE - A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate. | 2014-03-13 |
20140073125 | METHOD OF MANUFACTURING FOR SEMICONDUCTOR DEVICE USING EXPANDABLE MATERIAL - A semiconductor device is manufactured using an expandable material. The method includes forming a first gate insulating layer on a substrate, forming first and second gate structures on the first gate insulating layer, the first and second gate structures being spaced apart from each other at a distance, forming an expandable material on sidewalls and upper surfaces of the first and second gate structures, forming a gap-fill layer on the expandable material between the first and second gate structures, and performing a heat-treatment process to increase the volume of the expandable material. | 2014-03-13 |
20140073126 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY - A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness. | 2014-03-13 |
20140073127 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure. | 2014-03-13 |
20140073128 | MANUFACTURING METHOD FOR METAL LINE - A method for manufacturing metal lines in a semiconductor device is provided. The method includes steps of: providing a substrate; forming a first barrier layer on the substrate; forming a sacrificial layer on the first barrier layer; forming an opening penetrating through the sacrificial layer to expose a portion of the first barrier layer; depositing a metal material on the exposed first barrier layer to form a metal line in the opening; removing the sacrificial layer and forming a second barrier layer over the resulting structure; etching the second barrier layer and the first barrier layer while remaining a barrier spacer on a sidewall of the metal line; and forming an insulating layer on the substrate and the barrier spacer. A semiconductor device having the metal lines produced by the method is also provided. | 2014-03-13 |
20140073129 | SEMICONDUCTOR DEVICE INCLUDING BOTTOM SURFACE WIRING AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal. | 2014-03-13 |
20140073130 | FORMING NICKEL-PLATINUM ALLOY SELF-ALIGNED SILICIDE CONTACTS - A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO | 2014-03-13 |