11th week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140070328 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Semiconductor devices and methods of fabricating semiconductor devices are provided. Two or more layers can be formed on a silicon substrate, wherein one or more of the layers are used for controlling an isolation recess. A first layer can comprise a first material and a second layer can comprise a second material. | 2014-03-13 |
20140070329 | WIRELESS MODULE WITH ACTIVE AND PASSIVE COMPONENTS - A wireless multichip module has a leadframe structure | 2014-03-13 |
20140070330 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR HAVING A GATE STRUCTURE WITH A FIRST SECTION HAVING A FIRST EFFECTIVE WORK FUNCTION ABOVE A CENTER PORTION OF THE CHANNEL REGION AND WITH SECOND SECTIONS HAVING A SECOND EFFECTIVE WORK FUNCTION ABOVE OPPOSING SIDEWALLS OF THE CHANNEL REGION - In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated. | 2014-03-13 |
20140070331 | METAL OXIDE SEMICONDUCTOR (MOS) DEVICE WITH LOCALLY THICKENED GATE OXIDE - A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure. | 2014-03-13 |
20140070332 | SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES - A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures. | 2014-03-13 |
20140070333 | SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS - A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor. | 2014-03-13 |
20140070334 | SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region. | 2014-03-13 |
20140070335 | ELECTRONIC DEVICE - According to one embodiment, an electronic device includes a drive circuit on a semiconductor substrate, an insulating region including a first insulating part provided on the semiconductor substrate and formed of interlayer insulating films, and a second insulating part provided on the first insulating part, and covering the drive circuit, an element for high-frequency, which is provided on the insulating region, is driven by the drive circuit, an interconnect including a first conductive part in the first insulating part, and a second conductive part in the second insulating part, and transmitting a drive signal from the drive circuit to the element for high-frequency, and a resistive element between the second conductive part and the element for high-frequency. | 2014-03-13 |
20140070336 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity. | 2014-03-13 |
20140070337 | INTEGRATED CIRCUIT INCLUDING AN ENVIRONMENTAL SENSOR - An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate including at least one environmental sensor. The integrated circuit also includes a cap layer located on a major surface of the substrate. The integrated circuit further includes at least one elongate channel for allowing access of said sensor to an environment surrounding the integrated circuit. | 2014-03-13 |
20140070338 | Taxel-addressable matrix of vertical nanowire piezotronic transistors - A tactile sensing matrix includes a substrate, a first plurality of elongated electrode structures, a plurality of vertically aligned piezoelectric members, an insulating layer infused into the piezoelectric members and a second plurality of elongated electrode structures. The first plurality of elongated electrode structures is disposed on the substrate along a first orientation. The vertically aligned piezoelectric members is disposed on the first plurality of elongated electrode structures and form a matrix having columns of piezoelectric members disposed along the first orientation and rows of piezoelectric members disposed along a second orientation that is transverse to the first orientation. The second plurality of elongated electrode structures is disposed on the insulating layer along the second orientation. The elongated electrode structures form a Schottky contact with the piezoelectric members. When pressure is applied to the piezoelectric members, current flow therethrough is modulated. | 2014-03-13 |
20140070339 | THROUGH SILICON VIA INCLUDING MULTI-MATERIAL FILL - An apparatus includes a substrate having at least one via disposed in the substrate, wherein the substrate includes a trench having a substantially trapezoidal cross-section, the trench extending through the substrate between a lower surface of the substrate and an upper surface of the substrate, wherein the top of the trench opens to a top opening, and the bottom of the trench opens to a bottom opening, the top opening being larger than the bottom opening. The apparatus can include a mouth surrounding the top opening and extending between the upper surface and the top opening, wherein a mouth opening in the upper surface is larger than the top opening of the trench, wherein the via includes a dielectric layer disposed on an inside surface of a trench. The apparatus includes and a fill disposed in the trench, with the dielectric layer sandwiched between the fill and the substrate. | 2014-03-13 |
20140070340 | NORMALLY CLOSED MICROELECTROMECHANICAL SWITCHES (MEMS), METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Normally closed (shut) micro-electro-mechanical switches (MEMS), methods of manufacture and design structures are provided. A structure includes a beam structure that includes a first end hinged on a first electrode and in electrical contact with a second electrode, in its natural state when not actuated. | 2014-03-13 |
20140070341 | Minimal Thickness Synthetic Antiferromagnetic (SAF) Structure with Perpendicular Magnetic Anisotropy for STT-MRAM - A synthetic antiferromagnetic (SAF) structure for a spintronic device is disclosed and has an AP2/antiferromagnetic (AF) coupling/CoFeB configuration. The SAF structure is thinned to reduce the fringing (Ho) field while maintaining high coercivity. The AP2 reference layer has intrinsic perpendicular magnetic anisotropy (PMA) and induces PMA in a thin CoFeB layer through AF coupling. In one embodiment, AF coupling is improved by inserting a Co dusting layer on top and bottom surfaces of a Ru AF coupling layer. When AP2 is (Co/Ni) | 2014-03-13 |
20140070342 | METHODS OF FORMING MEMORY CELLS AND ARRAYS OF MAGNETIC MEMORY CELL STRUCTURES, AND RELATED MEMORY CELLS AND MEMORY CELL STRUCTURES - Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more unifoimity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed. | 2014-03-13 |
20140070343 | MAGNETORESISTIVE EFFECT ELEMENT - A magnetoresistive effect element in one or more embodiments of the present invention is provided with a memory layer with a variable magnetization direction having a magnetic anisotropy in a direction perpendicular to a film surface, a reference layer with an invariable magnetization direction having the magnetic anisotropy in a direction perpendicular to the film surface, and a tunnel barrier layer formed between the memory layer and the reference layer. The tunnel barrier layer has a first portion at the central part in the film surface and a second portion at a peripheral part. The second portion contains at least boron and oxygen. | 2014-03-13 |
20140070344 | SYSTEMS AND METHODS FOR IMPLEMENTING MAGNETOELECTRIC JUNCTIONS - Embodiments of the invention implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between said fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series. | 2014-03-13 |
20140070345 | INTEGRATED ELECTRONIC DEVICE WITH TRANSCEIVING ANTENNA AND MAGNETIC INTERCONNECTION - An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna. | 2014-03-13 |
20140070346 | RADIO-FREQUENCY DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole. | 2014-03-13 |
20140070347 | METHODS FOR PRODUCING CHALCOPYRITE COMPOUND THIN FILMS FOR SOLAR CELLS USING MULTI-STAGE PASTE COATING - Disclosed are methods for producing chalcopyrite compound (e.g., copper indium selenide (CIS), copper indium gallium selenide (CIGS), copper indium sulfide (CIS) or copper indium gallium sulfide (CIGS)) thin films. The methods are based on solution processes, such as printing, particularly, multi-stage coating of pastes or inks of precursors having different physical properties. Chalcopyrite compound thin films produced by the methods can be used as light-absorbing layers for thin-film solar cells. The use of the chalcopyrite compound thin films enables the fabrication of thin-film solar cells with improved efficiency at low costs. | 2014-03-13 |
20140070348 | Methods and Apparatus for Sensor Module - Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB. | 2014-03-13 |
20140070349 | Low Profile Image Sensor Package And Method - An image sensor package, and method of making same, that includes a printed circuit board having a first substrate with an aperture extending therethrough, one or more circuit layers, and a plurality of first contact pads electrically coupled to the one or more circuit layers. A sensor chip mounted to the printed circuit board and disposed at least partially in the aperture. The sensor chip includes a second substrate, a plurality of photo detectors formed on or in the second substrate, and a plurality of second contact pads formed at the surface of the second substrate which are electrically coupled to the photo detectors. Electrical connectors each electrically connect one of the first contact pads and one of the second contact pads. A lens module is mounted to the printed circuit board and has one or more lenses disposed for focusing light onto the photo detectors. | 2014-03-13 |
20140070350 | SENSOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND SENSING DISPLAY PANEL HAVING THE SAME - A sensor substrate includes a blocking pattern disposed on a base substrate, a first electrode disposed on the base substrate and overlapping the blocking pattern , the first electrode including a plurality of first unit parts arranged in a first direction, each of the first unit parts including a plurality of lines connected to each other in a mesh-type arrangement, a color filter layer disposed on the base substrate, a plurality of contact holes defined in the color filter layer and exposing the first unit parts, and a bridge line between and connected to first unit parts adjacent to each other in the first direction, through the contact holes. | 2014-03-13 |
20140070351 | METHOD FOR MANUFACTURING OPTICAL WAVEGUIDE RECEIVER AND OPTICAL WAVEGUIDE RECEIVER - A method for manufacturing an optical waveguide receiver includes the steps of growing first and second stacked semiconductor layer sections, the second stacked semiconductor layer section including a core layer and a cladding layer; forming a first mask including first and second portions; etching the first and second stacked semiconductor layer sections by using the first mask, the first and second stacked semiconductor layer sections covered with the first portion being etched in a mesa structure, the second stacked semiconductor layer section covered with the second portion being etched in a terrace-shaped structure; removing the second portion from the first mask with the first portion left; selectively etching the cladding layer until exposing a surface of the core layer; and sequentially forming a first metal layer, an insulating film, and a second metal layer on the core layer exposed in the step of selectively etching the cladding layer. | 2014-03-13 |
20140070352 | Stress Release Layout and Associated Methods and Devices - An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines. | 2014-03-13 |
20140070353 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor substrate which includes a first connection terminal electrically connected to a wiring for signal transfer. The semiconductor package may include a semiconductor support substrate which may be bonded to the semiconductor substrate such that a second connection terminal and the first connection terminal are connected to face each other, and has a through via exposing the second connection terminal. | 2014-03-13 |
20140070354 | MANUFACTURE OF N-TYPE CHALCOGENIDE COMPOSITIONS AND THEIR USES IN PHOTOVOLTAIC DEVICES - A layer of an n-type chalcogenide compositions provided on a substrate in the presence of an oxidizing gas in an amount sufficient to provide a resistivity to the layer that is less than the resistivity a layer deposited under identical conditions but in the substantial absence of oxygen. | 2014-03-13 |
20140070355 | ELECTRONIC DEVICE INCLUDING THERMAL SENSOR AND PELTIER COOLER AND RELATED METHODS - An electronic device may include a temperature sensing semiconductor substrate, that may include a thermal sensor at an upper surface thereof, and a cooling semiconductor substrate having an upper surface coupled to a lower surface of the temperature sensing semiconductor substrate. The cooling semiconductor substrate may include a Peltier cooler. At least one of the temperature sensing semiconductor substrate and the cooling semiconductor substrate may have a cavity therein beneath the thermopile and aligned therewith. | 2014-03-13 |
20140070356 | Method for Protecting a Semiconductor Device Against Degradation and a Method for Manufacturing a Semiconductor Device Protected Against Hot Charge Carriers - A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided. | 2014-03-13 |
20140070357 | SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS - A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned. | 2014-03-13 |
20140070358 | METHOD OF TAILORING SILICON TRENCH PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR - A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C. | 2014-03-13 |
20140070359 | SEMICONDUCTOR MEMORY ARRAY STRUCTURE - A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3. | 2014-03-13 |
20140070360 | FinFETs with Vertical Fins and Methods for Forming the Same - In a method for forming a device, a ( | 2014-03-13 |
20140070361 | DIFFUSION RESISTOR WITH REDUCED VOLTAGE COEFFICIENT OF RESISTANCE AND INCREASED BREAKDOWN VOLTAGE USING CMOS WELLS - Integrated circuits and manufacturing methods are presented for creating diffusion resistors ( | 2014-03-13 |
20140070362 | E-FUSE STRUCTURES AND METHODS OF MANUFACTURE - E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure. | 2014-03-13 |
20140070363 | ELECTRONIC ANTI-FUSE - An electronic anti-fuse structure, the structure including an M | 2014-03-13 |
20140070364 | ANTI-FUSE DEVICE - An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate. | 2014-03-13 |
20140070365 | SEMICONDUCTOR DEVICES WITH IMPEDANCE MATCHING-CIRCUITS, AND METHODS OF MANUFACTURE THEREOF - Embodiments of semiconductor devices (e.g., RF devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit and/or an impedance matching circuit. Embodiments also include method of manufacturing such semiconductor devices. | 2014-03-13 |
20140070366 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided. | 2014-03-13 |
20140070367 | SEMICONDUCTOR DEVICE - According to one embodiment, the semiconductor device according to the embodiment of the present disclosure is provided with a first semiconductor layer, a second semiconductor layer, a ninth semiconductor layer formed on the second semiconductor layer, a third semiconductor layer, a first region enclosed with the third semiconductor layer, a fourth semiconductor layer, a second region on the second semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer, a first terminal connected to the first semiconductor layer, and a second terminal connected to the fifth semiconductor layer and the sixth semiconductor layer. | 2014-03-13 |
20140070368 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board. | 2014-03-13 |
20140070369 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n | 2014-03-13 |
20140070370 | GROUP III NITRIDE SEMICONDUCTOR SINGLE CRYSTAL, METHOD FOR PRODUCING THE SAME, SELF-STANDING SUBSTRATE, AND SEMICONDUCTOR DEVICE - Objects of the present invention are to provide a method for producing a Group III nitride semiconductor single crystal, which method enables production of a Group III nitride semiconductor single crystal having a flat surface by means of a crucible having any inside diameter; to provide a self-standing substrate obtained from the Group III nitride semiconductor single crystal; and to provide a semiconductor device employing the self-standing substrate. The production method includes adding the template, a flux, and semiconductor raw materials to a crucible and growing a Group III nitride semiconductor single crystal while the crucible is rotated. In the growth of the semiconductor single crystal, the crucible having an inside diameter R (mm) is rotated at a maximum rotation speed ω (rpm) satisfying the following conditions: | 2014-03-13 |
20140070371 | GROUP III NITRIDE SEMICONDUCTOR CRYSTAL, GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE, GROUP III NITRIDE SEMICONDUCTOR FREESTANDING SUBSTRATE, NITRIDE SEMICONDUCTOR DEVICE, AND RECTIFIER DIODE - There is provided a group III nitride semiconductor crystal, containing a donor-type impurity and having a hydrogen concentration of 2.0E+16 cm | 2014-03-13 |
20140070372 | SEMICONDUCTOR THIN FILM STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor thin film structure and a semiconductor thin film structure formed using the same is provided. A sacrificial layer is formed on a substrate and then patterned through various methods, an inorganic thin film is formed on the sacrificial layer and then the sacrificial layer is selectively removed to form a cavity defined by the substrate and the inorganic thin film on the substrate. | 2014-03-13 |
20140070373 | SEMICONDUCTOR HOLE STRUCTURE - A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer. | 2014-03-13 |
20140070374 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines. | 2014-03-13 |
20140070375 | ELECTRONIC DEVICE INCLUDING A VIA AND A CONDUCTIVE STRUCTURE, A PROCESS OF FORMING THE SAME, AND AN INTERPOSER - An electronic device can include a substrate including a first region having a first thickness, and a second region having a second thickness different from the first thickness. The electronic device can include a via within the first region. The electronic device can include a conductive structure adjacent to the first region and connected to the via, wherein a combined thickness of the first thickness and a thickness of the conductive structure is thicker than the second thickness. In another embodiment, an interposer may have a similar structure, with laterally offset conductive structures that allow for lateral routing of electronic signals. A process of forming an electronic device can include forming a via and removing a portion of the substrate. The process can include forming a conductive structure connected to the via, wherein the conductive structure is adjacent to a region where the portion of the substrate has been removed. | 2014-03-13 |
20140070376 | Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements - A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall. | 2014-03-13 |
20140070377 | COMPOUND SEMICONDUCTOR EPITAXIAL STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer. | 2014-03-13 |
20140070378 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND APPARATUS FOR FABRICATING A SEMICONDUCTOR DEVICE - An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device, including measuring a physical amount related to an impurity concentration of a semiconductor wafer having a first thickness, deciding a second thickness of the semiconductor wafer based on a measurement value of the physical amount, the second thickness being thinner than the first thickness, and reducing the first thickness of the semiconductor wafer to approximately the same thickness as the second thickness. | 2014-03-13 |
20140070379 | Diode and Power Conversion System - A diode includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of a second conductive type arranged adjoining to the first semiconductor layer; a third semiconductor layer of the first conductive type arranged on a side, opposite to the second semiconductor layer, of the first semiconductor layer, and contains a dopant of the first conductive type at a higher concentration than the first semiconductor layer; a first electrode ohmically connected to the second semiconductor layer; a second electrode ohmically connected to the third semiconductor layer; and a fourth semiconductor layer arranged at a position adjoining to the third semiconductor layer between the first and third semiconductor layers, contains a dopant of a type being the same as a type of the dopant of the first conductive type contained in the third semiconductor layer, and has a carrier lifetime shorter than the third semiconductor layer. | 2014-03-13 |
20140070380 | BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY - Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed. | 2014-03-13 |
20140070381 | SEMICONDUCTOR MEMORY CARD - A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals. | 2014-03-13 |
20140070382 | Pre-Molded MEMS Device Package - A MEMS lead frame package body encloses a MEMS device enclosed in an internal cavity formed by the mold body and cover. To accommodate a MEMS microphone, an acoustic aperture extends through the mold body. In some embodiments, a conductive column extends through the pre-molded body to allow electrical connection from a partially encapsulated lead frame to the conductive cover. Some embodiments may include a multi-tiered cavity within the mold body for mounting an integrated circuit separated by a gap above the MEMS device. | 2014-03-13 |
20140070383 | Pre-Molded MEMS Device Package with Conductive Shell - A MEMS lead frame package body encloses a MEMS device enclosed in an internal cavity formed by the mold body and cover. A conductive internal shell with a connection window sits in the cavity. The MEMS device is mounted in the shell and electrically coupled to the lead frame through wire bonds directed through the connection window. To accommodate a MEMS microphone, an acoustic aperture extends through the mold body aligned with a hole in the internal shell. | 2014-03-13 |
20140070384 | STACKED SEMICONDUCTOR DEVICE AND PRINTED CIRCUIT BOARD - An interposer of a first semiconductor package includes a power supply wiring for a second semiconductor element, the power supply wiring including a land provided in one surface layer, and a power supply pattern provided in an inner layer and electrically connected to the land, the power supply wiring further including a larger number of lands than the land, which are provided in another surface layer and electrically connected in parallel to the power supply pattern. In a stacked semiconductor device, this configuration can improve the quality of power supply to the second semiconductor element to secure signal processing operation while preventing an increase in inductance caused by the bending of a power supply path in a power supply wiring of a printed wiring board or by a deviation of connection intervals. | 2014-03-13 |
20140070385 | FLIP-CHIP PACKAGE STRUCTURE AND METHOD FOR AN INTEGRATED SWITCHING POWER SUPPLY - Disclosed are flip-chip package structures and methods for an integrated switching power supply. In one embodiment, a flip-chip package structure can include: (i) a die with an integrated switching power supply, where a first surface of the die includes first bumps with different polarities; (ii) a redistribution layer including redistribution layer units, each having a first surface to connect bumps with a same polarity from the first bumps, the redistribution layer having a second surface including second bumps to redistribute polarities; (iii) a lead frame having pins, where a first surface of the lead frame can connect bumps with a same polarity from the second bumps; and (iv) a flip-chip package configured to package the die, the redistribution layer, the first and second bumps, and the lead frame, where a second surface of the lead frame provides electrical connectivity between the integrated switching power supply and a PCB. | 2014-03-13 |
20140070386 | Semiconductor Package with Connecting Plate for Internal Connection - A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding. | 2014-03-13 |
20140070387 | COUPLING ASSEMBLY OF POWER SEMICONDUCTOR DEVICE AND PCB AND METHOD FOR MANUFACTURING THE SAME - Provided is a coupling assembly of a power semiconductor device and a printed circuit board (PCB). The coupling assembly of the power semiconductor device and the printed circuit board (PCB) includes a PCB, a power semiconductor device comprising a plurality of legs electrically connected to a circuit pattern disposed on the PCB, a connection member disposed above the power semiconductor device, the connection member being formed of an electrically conductive material, a main fixing unit fixing the power semiconductor device to the PCB, and a housing disposed outside the PCB. Thus, a coupling force between the power semiconductor device and the PCB and electric efficiency may be improved to a heat generation amount. In addition, heat may be more quickly dissipated through the connection member to improve a cooling effect. | 2014-03-13 |
20140070388 | SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME - A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package. | 2014-03-13 |
20140070389 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - To enhance the reliability of a semiconductor device. The semiconductor device includes die pads, over which a first semiconductor chip and a second semiconductor chip are mounted respectively, a plurality of support pins that support each of the die pads, a plurality of inner leads and outer leads arranged around the die pads, a plurality of wires that electrically couple the semiconductor chips to the inner leads, and a sealing body that seals the semiconductor chips, the inner leads, and the wires. Each of the die pads is supported by three support pins integrally formed together with the die pad, and each of second support pins of each pair of the three support pins is arranged between the inner leads adjacent to each other. | 2014-03-13 |
20140070390 | MULTI-CHIP PACKAGING STRUCTURE AND METHOD - Disclosed are multi-chip packaging structures and methods. In one embodiment, a multi-chip packaging structure can include: (i) N chips, where N is an integer of at least two, and where an upper surface of each chip comprises a plurality of pads; (ii) a lead frame with a chip carrier and a plurality of pins, where the N chips are stacked in layers on the chip carrier, and where a chip in an upper layer partially covers a chip in a lower layer such that the plurality of pads of the lower layer chip are exposed; (iii) a plurality of first bonding leads configured to connect pads on one chip to pads on another chip; and (iv) a plurality of second bonding leads configured to connect pads on at least one chip to the plurality of pins for external connection to the multi-chip packaging structure. | 2014-03-13 |
20140070391 | LEAD CARRIER WITH PRINT-FORMED TERMINAL PADS - A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a plurality of terminal pads surrounding a die attach region. The pads are formed of sintered electrically conductive material. A chip is placed at the die attach region and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronic system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package. | 2014-03-13 |
20140070392 | COMMON DRAIN POWER CLIP FOR BATTERY PACK PROTECTION MOSFET - A first embodiment is a common drain+clip | 2014-03-13 |
20140070393 | HORIZONTALLY AND VERTICALLY ALIGNED GRAPHITE NANOFIBERS THERMAL INTERFACE MATERIAL FOR USE IN CHIP STACKS - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip | 2014-03-13 |
20140070394 | SEMICONDUCTOR DEVICE - In a semiconductor device including a semiconductor element that produces heat and a substrate on which the semiconductor element is mounted, functions of the substrate are divided between a heat dissipating substrate and a wiring substrate. The heat dissipating substrate has a relatively high thermal conductivity, and includes principal surfaces defined by electric insulators, one of which is provided with an outer conductor located thereon. The wiring substrate is mounted on the upper principal surface of the heat dissipating substrate, has a thermal conductivity lower than that of the heat dissipating substrate, and includes a wiring conductor made mainly of silver or copper and located inside the wiring substrate, the wiring conductor being electrically connected to the outer conductor. The semiconductor element is mounted on the upper principal surface of the heat dissipating substrate and disposed in a through hole of the wiring substrate. | 2014-03-13 |
20140070395 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device and the manufacturing method thereof are provided. The method comprises providing a module, in which the module includes a substrate, at least one component mounted on the substrate and a molding, and the molding encapsulates the component and a portion of the substrate; forming a first hole to expose a ground pad of the component; forming a first conductive layer which covers the module and is electrically connected to the ground pad. | 2014-03-13 |
20140070396 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD - A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip. | 2014-03-13 |
20140070397 | HIGH POWER SEMICONDUCTOR PACKAGE SUBSYSTEMS - A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect. | 2014-03-13 |
20140070398 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A power semiconductor element, a high-voltage electrode electrically connected to the power semiconductor element, a heat radiating plate connected to the power semiconductor element and having heat radiation property, a cooling element connected to the heat radiating plate with an insulating film being interposed, and a seal covering the power semiconductor element, a part of the high-voltage electrode, the heat radiating plate, the insulating film, and a part of the cooling element are included. The cooling element includes a base portion of which part is embedded in the seal and a cooling member connected to the base portion. The base portion and the cooling member are separate from each other, and the cooling member is fixed to the base portion exposed through the seal. | 2014-03-13 |
20140070399 | ELECTROCHEMICALLY DEPOSITED INDIUM COMPOSITES - Electrochemically deposited indium composites are disclosed. The indium composites include indium metal or an alloy of indium with one or more ceramic materials. The indium composites have high bulk thermal conductivities. Articles containing the indium composites also are disclosed. | 2014-03-13 |
20140070400 | SEMICONDUCTOR DEVICE - In a semiconductor device including semiconductor modules, it is possible to average the temperatures of the semiconductor modules. At least two semiconductor modules, wherein a plurality of semiconductor circuits, on which are mounted one or more semiconductor chips having a gate terminal and gate resistors connected to the gate terminals, are disposed in parallel, are disposed above a cooling body so that an array direction of the semiconductor circuits is a direction intersecting a refrigerant flow. At least one temperature detecting resistor is disposed in each semiconductor module, a gate signal is supplied to a gate signal input terminal of one semiconductor module of the at least two semiconductor modules via the temperature detecting resistor of the other semiconductor module, and a gate signal is supplied to a gate signal input terminal of the other semiconductor module via the temperature detecting resistor of the one semiconductor module. | 2014-03-13 |
20140070401 | EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING - Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal. | 2014-03-13 |
20140070402 | Stress Reduction Apparatus - A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of the first semiconductor die and the plurality of connectors, wherein an edge of the first dummy conductive plane and a first distance to neutral point (DNP) direction form a first angle, and wherein the first angle is less than or equal to 45 degrees. | 2014-03-13 |
20140070403 | Packaging Methods and Packaged Devices - Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die. | 2014-03-13 |
20140070404 | SEMICONDUCTOR PACKAGE STRUCTURE AND INTERPOSER THEREFOR - An interposer for a semiconductor package structure includes a base substrate, a plurality of passive devices formed on the base substrate, and an identification (ID) code. The base substrate includes a first surface and an opposite second surface. The ID code is formed on the first surface or the second surface of the base substrate. | 2014-03-13 |
20140070405 | STACKED SEMICONDUCTOR DEVICES WITH A GLASS WINDOW WAFER HAVING AN ENGINEERED COEFFICIENT OF THERMAL EXPANSION AND METHODS OF MAKING SAME - One illustrative device disclosed herein includes a device substrate having a plurality of first die formed adjacent a front side of the device substrate, a glass window wafer attached to a back side of the device substrate, wherein the glass window wafer has a plurality of openings formed therein and a coefficient of thermal expansion that is within plus or minus 200-500% of the coefficient of thermal expansion of the device wafer, and a plurality of second die, each of which is positioned in one of the openings in the glass window wafer and electrically coupled to one of the first die. | 2014-03-13 |
20140070406 | Devices and Methods for 2.5D Interposers - Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages can be reduced or eliminated by using different diameter micro-bumps, different height copper pillars, or a multi-tiered interposer to lower taller semiconductor dies in relation to shorter semiconductor dies. | 2014-03-13 |
20140070407 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and lower semiconductor chip, the upper semiconductor chip having upper chip pads on a top surface and at areas close to third and the fourth sides of the upper semiconductor chip, and a connecting structure on the lower molding element and the upper semiconductor chip and electrically connecting each of the lower chip pads and upper chip pads to a corresponding conductive pillar. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip. | 2014-03-13 |
20140070408 | Plating Structure For Wafer Level Packages - A plating structure for wafer level packages are disclosed and may include a semiconductor wafer comprising a plurality of semiconductor die and a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die. The plating structure may comprise a plating connection line around a periphery of the semiconductor wafer, and a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die. The plating traces may be electrically coupled to the redistribution layers on the plurality of semiconductor die. The semiconductor wafer may comprise a reconstituted wafer of said semiconductor die. The semiconductor wafer may comprise a wafer prior to singulating the plurality of semiconductor die. The plating bar may be located in a sawing line for the singulating of the plurality of semiconductor die. A passivation layer may cover the redistribution layer and the plating traces. | 2014-03-13 |
20140070409 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ASSEMBLY WITH LEAD-FREE SOLDER - A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag. | 2014-03-13 |
20140070410 | Semiconductor Device and Method of Forming Multi-Layered UBM with Intermediate Insulating Buffer Layer to Reduce Stress for Semiconductor Wafer - A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers. | 2014-03-13 |
20140070411 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which a semiconductor element mounted on a wiring substrate is placed in a hollow portion, the hollow portion being formed by the wiring substrate, a protective member, and a wall member, with the wiring substrate, the protective member, and the wall member being a bottom surface, a top surface, and side surfaces thereof, respectively. The wall member has a vent hole provided therein, which communicates the hollow portion to/from the outside, and the vent hole includes a pillar member formed of a material having a linear expansion coefficient which is smaller than that of the wall member. Therefore, airtightness of the hollow portion is maintained to prevent entry of foreign matters at ordinary temperature, and vapor pressure in the hollow portion is relieved when heated. | 2014-03-13 |
20140070412 | Semiconductor Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor device includes forming a lower electrode pattern on a substrate, forming a first insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first insulating layer, forming an etch blocking spacer at a side of the upper electrode pattern, forming a second insulating layer on the upper electrode pattern, etching the second insulating layer to form a cavity which exposes the etch blocking spacer, and forming a contact ball in the cavity. | 2014-03-13 |
20140070413 | SEMICONDUCTOR DEVICE WITH FRONT AND BACK SIDE RESIN LAYERS HAVING DIFFERENT THERMAL EXPANSION COEFFICIENT AND ELASTICITY MODULUS - Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer. | 2014-03-13 |
20140070414 | Semiconductor plural gate lengths - Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask. | 2014-03-13 |
20140070415 | MICROELECTRONIC PACKAGES HAVING TRENCH VIAS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads. | 2014-03-13 |
20140070416 | GUARD RING STRUCTURE AND METHOD FOR FORMING THE SAME - A guard ring structure is provided, including a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively includes a plurality of separated first doping regions formed in a top portion of the semiconductor substrate, having a second dopant type opposite to the first conductivity type, and an interconnect element formed over the semiconductor substrate, covering the first doping regions. | 2014-03-13 |
20140070417 | SEMICONDUCTOR DEVICE HAVING BARRIER METAL LAYER - According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer. | 2014-03-13 |
20140070418 | SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY - An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed. | 2014-03-13 |
20140070419 | Platinum-Containing Constructions, and Methods of Forming Platinum-Containing Constructions - Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide. Chemical-mechanical polishing is utilized to form a planarized surface extending across the platinum-containing material and the metal oxide. | 2014-03-13 |
20140070420 | Chip To Package Interface - In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil. | 2014-03-13 |
20140070421 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive backside. Conductive pathways extend between the front and back sides of the integrated circuit. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive pathways and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side. | 2014-03-13 |
20140070422 | Semiconductor Device with Discrete Blocks - A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers. | 2014-03-13 |
20140070423 | TUNABLE COMPOSITE INTERPOSER - A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure. | 2014-03-13 |
20140070424 | SEMICONDUCTOR PACKAGE, METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE, AND INTERPOSER STRUCTURE OF THE SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers. | 2014-03-13 |
20140070425 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate including semiconductor elements formed thereon, a graphene wiring structure stuck on the substrate with a connection insulating film disposed therebetween and including graphene wires, and through vias each formed through the graphene wiring structure and connection insulating film to connect part of the semiconductor elements to the graphene wires. | 2014-03-13 |
20140070426 | INTEGRATED CIRCUIT DEVICES INCLUDING A VIA STRUCTURE AND METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING A VIA STRUCTURE - Integrated circuit devices are provided. The integrated circuit devices may include a via structure including a conductive plug, a conductive barrier layer spaced apart from the conductive plug, and an insulating layer between the conductive plug and conductive barrier layer. Related methods of forming integrated circuit devices are also provided. | 2014-03-13 |
20140070427 | Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding - A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers. | 2014-03-13 |